1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_OHCID_H 28 #define _SYS_USB_OHCID_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Open Host Controller Driver (OHCI) 38 * 39 * The USB Open Host Controller driver is a software driver which interfaces 40 * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 41 * The interface to USB Open Host Controller is defined by the OpenHCI Host 42 * Controller Interface. 43 * 44 * This header file describes the data structures required for the USB Open 45 * Host Controller Driver to maintain state of USB Open Host Controller, to 46 * perform different USB transfers and for the bandwidth allocations. 47 */ 48 49 #include <sys/usb/hcd/openhci/ohci.h> 50 #include <sys/usb/hcd/openhci/ohci_hub.h> 51 52 /* 53 * OpenHCI interrupt status information structure 54 * 55 * The Host Controller Driver (HCD) has to maintain two different sets of 56 * Host Controller (HC) state information that includes HC registers, the 57 * interrupt tables etc.. for the normal and polled modes. In addition, 58 * suppose if we switched to polled mode while ohci interrupt handler is 59 * executing in the normal mode then we need to save the interrupt status 60 * information that includes interrupts for which ohci interrupt handler 61 * is called and HCCA done head list in the polled mode. This infromation 62 * will be used later in normal mode to service those missed interrupts. 63 * This will avoid race conditions like missing of normal mode's ohci SOF 64 * and WriteDoneHead interrupts because of this polled switch. 65 */ 66 typedef struct ohci_save_intr_sts { 67 /* 68 * The following field has set of flags & these flags will be set 69 * in the ohci interrupt handler to indicate that currently ohci 70 * interrupt handler is in execution and also while critical code 71 * execution within the ohci interrupt handler. These flags will 72 * be verified in polled mode while saving the normal mode's ohci 73 * interrupt status information. 74 */ 75 uint_t ohci_intr_flag; /* Intr handler flags */ 76 77 /* 78 * The following fields will be used to save the interrupt status 79 * and the HCCA done head list that the ohci interrupt handler is 80 * currently handling. 81 */ 82 uint_t ohci_curr_intr_sts; /* Current interrupts */ 83 ohci_td_t *ohci_curr_done_lst; /* Current done head */ 84 85 /* 86 * The following fields will be used to save the interrupt status 87 * and the HCCA done list currently being handled by the critical 88 * section of the ohci interrupt handler.. 89 */ 90 uint_t ohci_critical_intr_sts; /* Critical interrupts */ 91 ohci_td_t *ohci_critical_done_lst; /* Critical done head */ 92 93 /* 94 * The following fields will be used to save the interrupt status 95 * and HCCA done head list by the polled code if an interrupt is 96 * pending when polled code is entered. These missed interrupts & 97 * done list will be serviced either in current normal mode ohci 98 * interrupt handler execution or during the next ohci interrupt 99 * handler execution. 100 */ 101 uint_t ohci_missed_intr_sts; /* Missed interrupts */ 102 ohci_td_t *ohci_missed_done_lst; /* Missed done head */ 103 } ohci_save_intr_sts_t; 104 105 /* 106 * These flags will be set in the the normal mode ohci interrupt handler 107 * to indicate that currently ohci interrupt handler is in execution and 108 * also while critical code execution within the ohci interrupt handler. 109 * These flags will be verified in the polled mode while saving the normal 110 * mode's ohci interrupt status infromation. 111 */ 112 #define OHCI_INTR_HANDLING 0x01 /* Handling ohci intrs */ 113 #define OHCI_INTR_CRITICAL 0x02 /* Critical intr code */ 114 115 116 /* 117 * OpenHCI Host Controller state structure 118 * 119 * The Host Controller Driver (HCD) maintains the state of Host Controller 120 * (HC). There is an ohci_state structure per instance of the OpenHCI 121 * host controller. 122 */ 123 124 typedef struct ohci_state { 125 dev_info_t *ohci_dip; /* Dip of HC */ 126 uint_t ohci_instance; 127 usba_hcdi_ops_t *ohci_hcdi_ops; /* HCDI structure */ 128 uint_t ohci_flags; /* Used for cleanup */ 129 uint16_t ohci_vendor_id; /* chip vendor */ 130 uint16_t ohci_device_id; /* chip device */ 131 uint8_t ohci_rev_id; /* chip revison */ 132 133 ohci_regs_t *ohci_regsp; /* Host ctlr regs */ 134 ddi_acc_handle_t ohci_regs_handle; /* Reg handle */ 135 136 ddi_acc_handle_t ohci_config_handle; /* Config space hndle */ 137 uint_t ohci_frame_interval; /* Frme inter reg */ 138 ddi_dma_attr_t ohci_dma_attr; /* DMA attributes */ 139 140 ddi_intr_handle_t *ohci_htable; /* intr handle */ 141 int ohci_intr_type; /* intr type used */ 142 int ohci_intr_cnt; /* # of intrs inuse */ 143 uint_t ohci_intr_pri; /* intr priority */ 144 int ohci_intr_cap; /* intr capabilities */ 145 kmutex_t ohci_int_mutex; /* Mutex for struct */ 146 147 /* HCCA area */ 148 ohci_hcca_t *ohci_hccap; /* Virtual HCCA ptr */ 149 ddi_dma_cookie_t ohci_hcca_cookie; /* DMA cookie */ 150 ddi_dma_handle_t ohci_hcca_dma_handle; /* DMA handle */ 151 ddi_acc_handle_t ohci_hcca_mem_handle; /* Memory handle */ 152 153 /* 154 * There are two pools of memory. One pool contains the memory for 155 * the transfer descriptors and other pool contains the memory for 156 * the endpoint descriptors. The advantage of the pools is that it's 157 * easy to go back and forth between the iommu and the cpu addresses. 158 * 159 * The pools are protected by the ohci_int_mutex because the memory 160 * in the pools may be accessed by either the host controller or the 161 * host controller driver. 162 */ 163 164 /* General transfer descriptor pool */ 165 ohci_td_t *ohci_td_pool_addr; /* Start of the pool */ 166 ddi_dma_cookie_t ohci_td_pool_cookie; /* DMA cookie */ 167 ddi_dma_handle_t ohci_td_pool_dma_handle; /* DMA hndle */ 168 ddi_acc_handle_t ohci_td_pool_mem_handle; /* Mem hndle */ 169 170 /* Endpoint descriptor pool */ 171 ohci_ed_t *ohci_ed_pool_addr; /* Start of the pool */ 172 ddi_dma_cookie_t ohci_ed_pool_cookie; /* DMA cookie */ 173 ddi_dma_handle_t ohci_ed_pool_dma_handle; /* DMA handle */ 174 ddi_acc_handle_t ohci_ed_pool_mem_handle; /* Mem handle */ 175 uint_t ohci_dma_addr_bind_flag; /* DMA flag */ 176 177 /* Condition variables */ 178 kcondvar_t ohci_SOF_cv; /* SOF variable */ 179 180 /* Semaphore to serialize opens and closes */ 181 ksema_t ohci_ocsem; 182 183 /* 184 * Bandwidth fields 185 * 186 * The ohci_bandwidth array keeps track of the allocated bandwidth 187 * for this host controller. The total bandwidth allocated for least 188 * allocated list out of the 32 periodic lists is represented by the 189 * ohci_periodic_minimum_bandwidth field. 190 */ 191 uint_t ohci_periodic_minimum_bandwidth; 192 uint_t ohci_periodic_bandwidth[NUM_INTR_ED_LISTS]; 193 194 /* Different transfer open pipe counts */ 195 uint_t ohci_open_pipe_count; 196 uint_t ohci_open_ctrl_pipe_count; 197 uint_t ohci_open_bulk_pipe_count; 198 uint_t ohci_open_periodic_pipe_count; 199 uint_t ohci_open_isoch_pipe_count; 200 /* 201 * Endpoint Reclamation List 202 * 203 * The interrupt or isochronous list processing cannot be stopped 204 * when a periodic endpoint is removed from the list. The endpoints 205 * are detached from the interrupt lattice tree and put on to the 206 * reclaimation list. On next SOF interrupt all those endpoints, 207 * which are on the reclaimation list will be deallocated. 208 */ 209 ohci_ed_t *ohci_reclaim_list; /* Reclaimation list */ 210 211 ohci_root_hub_t ohci_root_hub; /* Root hub info */ 212 213 /* 214 * Global transfer timeout handling & this transfer timeout handling 215 * will be per USB Host Controller. 216 */ 217 struct ohci_trans_wrapper *ohci_timeout_list; /* Timeout List */ 218 timeout_id_t ohci_timer_id; /* Timer id */ 219 220 /* Frame number overflow information */ 221 usb_frame_number_t ohci_fno; 222 223 /* For Schedule Overrun error counter */ 224 uint_t ohci_so_error; 225 226 /* For host controller error counter */ 227 uint_t ohci_hc_error; 228 229 /* For SOF interrupt event */ 230 boolean_t ohci_sof_flag; 231 232 /* Openhci Host Controller Software State information */ 233 uint_t ohci_hc_soft_state; 234 235 /* 236 * ohci_save_intr_stats is used to save the normal mode interrupt 237 * status information while executing interrupt handler & also by 238 * the polled code if an interrupt is pending for the normal mode 239 * when polled code is entered. 240 */ 241 ohci_save_intr_sts_t ohci_save_intr_sts; 242 243 /* 244 * Saved copy of the ohci registers of the normal mode & change 245 * required ohci registers values for the polled mode operation. 246 * Before returning from the polled mode to normal mode replace 247 * the required current registers with this saved ohci registers 248 * copy. 249 */ 250 ohci_regs_t ohci_polled_save_regs; 251 252 /* 253 * Saved copy of the interrupt table used in normal ohci mode and 254 * replace this table by another interrupt table that used in the 255 * POLLED mode. 256 */ 257 ohci_ed_t *ohci_polled_save_IntTble[NUM_INTR_ED_LISTS]; 258 259 /* ohci polled mode enter counter for the input devices */ 260 uint_t ohci_polled_enter_count; 261 262 /* 263 * Counter for polled mode and used in suspend mode to see if 264 * there is a input device connected. 265 */ 266 uint_t ohci_polled_kbd_count; 267 268 /* Done list for the Polled mode */ 269 ohci_td_t *ohci_polled_done_list; 270 271 /* Log handle for debug, console, log messages */ 272 usb_log_handle_t ohci_log_hdl; 273 274 /* Kstat structures */ 275 kstat_t *ohci_intrs_stats; 276 kstat_t *ohci_total_stats; 277 kstat_t *ohci_count_stats[USB_N_COUNT_KSTATS]; 278 } ohci_state_t; 279 280 typedef struct ohci_intrs_stats { 281 struct kstat_named ohci_hcr_intr_so; 282 struct kstat_named ohci_hcr_intr_wdh; 283 struct kstat_named ohci_hcr_intr_sof; 284 struct kstat_named ohci_hcr_intr_rd; 285 struct kstat_named ohci_hcr_intr_ue; 286 struct kstat_named ohci_hcr_intr_fno; 287 struct kstat_named ohci_hcr_intr_rhsc; 288 struct kstat_named ohci_hcr_intr_oc; 289 struct kstat_named ohci_hcr_intr_not_claimed; 290 struct kstat_named ohci_hcr_intr_total; 291 } ohci_intrs_stats_t; 292 293 /* 294 * ohci kstat defines 295 */ 296 #define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats) 297 #define OHCI_INTRS_STATS_DATA(ohci) \ 298 ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data) 299 300 #define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats) 301 #define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats)) 302 #define OHCI_CTRL_STATS(ohci) \ 303 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL])) 304 #define OHCI_BULK_STATS(ohci) \ 305 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK])) 306 #define OHCI_INTR_STATS(ohci) \ 307 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR])) 308 #define OHCI_ISOC_STATS(ohci) \ 309 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH])) 310 311 /* warlock directives, stable data */ 312 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t)) 313 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri)) 314 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip)) 315 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp)) 316 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance)) 317 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id)) 318 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id)) 319 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id)) 320 321 /* this may not be stable data in the future */ 322 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr)) 323 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle)) 324 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr)) 325 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle)) 326 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie)) 327 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie)) 328 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle)) 329 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap)) 330 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag)) 331 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl)) 332 333 _NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \ 334 usba_pipe_handle_data::p_mutex \ 335 usba_device::usb_mutex \ 336 usba_ph_impl::usba_ph_mutex)) 337 338 /* 339 * Host Contoller Software States 340 * 341 * OHCI_CTLR_INIT_STATE: 342 * The host controller soft state will be set to this during the 343 * ohci_attach. 344 * 345 * OHCI_CTLR_SUSPEND_STATE: 346 * The host controller soft state will be set to this during the 347 * ohci_cpr_suspend. 348 * 349 * OHCI_CTLR_OPERATIONAL_STATE: 350 * The host controller soft state will be set to this after moving 351 * host controller to operational state and host controller start 352 * generating SOF successfully. 353 * 354 * OHCI_CTLR_ERROR_STATE: 355 * The host controller soft state will be set to this during the 356 * no SOF or UE error conditions. 357 * 358 * Under this state or condition, only pipe stop polling, pipe reset 359 * and pipe close are allowed. But all other entry points like pipe 360 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 361 * isoch send/receive, start polling etc. will fail. 362 * 363 * State Diagram for the host controller software state 364 * 365 * 366 * ohci_attach->[INIT_STATE] 367 * | 368 * | -------->----[ERROR_STATE]--<-----------<--- 369 * | | Failure (UE/no SOF condition) | 370 * | ^ ^ 371 * V | Success | 372 * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling 373 * ^ | 374 * | | 375 * | V 376 * -<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend 377 */ 378 #define OHCI_CTLR_INIT_STATE 0 /* Initilization state */ 379 #define OHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 380 #define OHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 381 #define OHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 382 383 /* 384 * Define all ohci's Vendor-id and Device-id Here 385 */ 386 #define RIO_VENDOR 0x108e 387 #define RIO_DEVICE 0x1103 388 #define OHCI_IS_RIO(ohcip) (ohcip->ohci_vendor_id == RIO_VENDOR) 389 390 /* 391 * Periodic and non-periodic macros 392 */ 393 #define OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 394 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 395 ((endpoint->bmAttributes &\ 396 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 397 398 #define OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 399 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 400 ((endpoint->bmAttributes &\ 401 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 402 403 /* 404 * OHCI ED and TD Pool sizes. 405 */ 406 #define OHCI_ED_POOL_SIZE 100 407 #define OHCI_TD_POOL_SIZE 200 408 409 /* 410 * ohci_dma_addr_bind_flag values 411 * 412 * This flag indicates if the various DMA addresses allocated by the OHCI 413 * have been bound to their respective handles. This is needed to recover 414 * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle() 415 */ 416 #define OHCI_TD_POOL_BOUND 0x01 /* For TD pools */ 417 #define OHCI_ED_POOL_BOUND 0x02 /* For ED pools */ 418 #define OHCI_HCCA_DMA_BOUND 0x04 /* For HCCA area */ 419 420 /* 421 * Maximum SOF wait count 422 */ 423 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 424 425 426 /* 427 * Pipe private structure 428 * 429 * There is an instance of this structure per pipe. This structure holds 430 * HCD specific pipe information. A pointer to this structure is kept in 431 * the USBA pipe handle (usba_pipe_handle_data_t). 432 */ 433 typedef struct ohci_pipe_private { 434 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 435 ohci_ed_t *pp_ept; /* Pipe's ept */ 436 437 /* State of the pipe */ 438 uint_t pp_state; /* See below */ 439 440 /* Local copy of the pipe policy */ 441 usb_pipe_policy_t pp_policy; 442 443 /* For Periodic Pipes Only */ 444 uint_t pp_node; /* Node in lattice */ 445 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 446 uint_t pp_max_periodic_req_cnt; /* Max req count */ 447 448 /* For isochronous pipe only */ 449 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 450 451 /* 452 * Each pipe may have multiple transfer wrappers. Each transfer 453 * wrapper represents a USB transfer on the bus. A transfer is 454 * made up of one or more transactions. 455 */ 456 struct ohci_trans_wrapper *pp_tw_head; /* Head of the list */ 457 struct ohci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 458 459 /* Done td count */ 460 uint_t pp_count_done_tds; /* Done td count */ 461 462 /* Errors */ 463 usb_cr_t pp_error; /* Pipe error */ 464 465 /* Flags */ 466 uint_t pp_flag; /* Flags */ 467 468 /* Condition variable for transfers completion event */ 469 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 470 471 /* 472 * HCD gets Interrupt/Isochronous IN polling request only once and 473 * it has to insert next polling requests after completion of first 474 * request until either stop polling/pipe close is called. So HCD 475 * has to take copy of the original Interrupt/Isochronous IN request. 476 */ 477 usb_opaque_t pp_client_periodic_in_reqp; 478 } ohci_pipe_private_t; 479 480 /* warlock directives, stable data */ 481 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t)) 482 483 /* 484 * Pipe states 485 * 486 * ohci pipe states will be similar to usba. Refer usbai.h. 487 */ 488 #define OHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 489 #define OHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 490 #define OHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 491 492 /* Additional ohci pipe states for the ohci_pipe_cleanup */ 493 #define OHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 494 #define OHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 495 #define OHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 496 497 /* 498 * Pipe specific Flags 499 */ 500 #define OHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 501 502 /* 503 * The maximum allowable usb isochronous data transfer size or maximum 504 * number of isochronous data packets. 505 * 506 * Each usb isochronous request must not exceed multiples of isochronous 507 * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER. 508 * 509 * Ex: usb isochronous endpoint maximum packet size is 64 bytes 510 * maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER 511 * * 64 bytes 512 */ 513 #define OHCI_MAX_ISOC_PKTS_PER_XFER 256 /* Max pkts per req */ 514 515 /* 516 * The ohci supports maximum of eight isochronous data packets per transfer 517 * descriptor. 518 */ 519 #define OHCI_ISOC_PKTS_PER_TD 8 /* Packets per TD */ 520 521 /* 522 * USB frame offset 523 * 524 * Add appropriate frame offset to the current usb frame number and use it 525 * as a starting frame number for a given usb isochronous request. 526 */ 527 #define OHCI_FRAME_OFFSET 2 /* Frame offset */ 528 529 /* 530 * Default usb isochronous receive packets per request before ohci will do 531 * callback. 532 */ 533 #define OHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 534 535 /* 536 * Different interrupt polling intervals supported 537 */ 538 #define INTR_1MS_POLL 1 539 #define INTR_2MS_POLL 2 540 #define INTR_4MS_POLL 4 541 #define INTR_8MS_POLL 8 542 #define INTR_16MS_POLL 16 543 #define INTR_32MS_POLL 32 544 545 /* 546 * Number of interrupt/isochronous transfer requests that should 547 * be maintained on the interrupt/isochronous endpoint corresponding 548 * to different polling intervals supported. 549 */ 550 #define INTR_1MS_REQS 4 /* 1ms polling interval */ 551 #define INTR_2MS_REQS 2 /* 2ms polling interval */ 552 #define INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 553 554 /* Function prototype */ 555 typedef void (*ohci_handler_function_t)( 556 ohci_state_t *ohcip, 557 ohci_pipe_private_t *pp, 558 struct ohci_trans_wrapper *tw, 559 ohci_td_t *td, 560 void *ohci_handle_callback_value); 561 562 563 /* 564 * Transfer wrapper 565 * 566 * The transfer wrapper represents a USB transfer on the bus and there 567 * is one instance per USB transfer. A transfer is made up of one or 568 * more transactions. 569 * 570 * Control and bulk pipes will have one transfer wrapper per transfer 571 * and where as Isochronous and Interrupt pipes will only have one 572 * transfer wrapper. The transfers wrapper are continually reused for 573 * the Interrupt and Isochronous pipes as those pipes are polled. 574 */ 575 typedef struct ohci_trans_wrapper { 576 struct ohci_trans_wrapper *tw_next; /* Next wrapper */ 577 ohci_pipe_private_t *tw_pipe_private; /* Back ptr */ 578 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 579 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 580 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 581 uint32_t tw_id; /* 32bit ID */ 582 size_t tw_length; /* Txfer length */ 583 char *tw_buf; /* Buffer for Xfer */ 584 usb_flags_t tw_flags; /* Flags */ 585 uint_t tw_num_tds; /* Number of TDs */ 586 ohci_td_t *tw_hctd_head; /* Head TD */ 587 ohci_td_t *tw_hctd_tail; /* Tail TD */ 588 uint_t tw_direction; /* Direction of TD */ 589 590 /* We preallocate all the td's for each tw and place them here */ 591 ohci_td_t *tw_hctd_free_list; 592 593 /* Current transfer request pointer */ 594 usb_opaque_t tw_curr_xfer_reqp; 595 596 /* Current isochronous packet descriptor pointer */ 597 usb_isoc_pkt_descr_t *tw_curr_isoc_pktp; 598 599 /* Transfer timeout information */ 600 uint_t tw_timeout; /* Timeout value */ 601 struct ohci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 602 603 /* 604 * This is the function to call when this td is done. This way 605 * we don't have to look in the td to figure out what kind it is. 606 */ 607 ohci_handler_function_t tw_handle_td; 608 609 /* 610 * This is the callback value used when processing a done td. 611 */ 612 usb_opaque_t tw_handle_callback_value; 613 } ohci_trans_wrapper_t; 614 615 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper)) 616 617 618 /* 619 * Time waits for the different OHCI specific operations. 620 * These timeout values are specified in terms of microseconds. 621 */ 622 #define OHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 623 #define OHCI_RESUME_TIMEWAIT 40000 /* HC resume waiting time */ 624 #define OHCI_TIMEWAIT 10000 /* HC any other waiting time */ 625 626 /* These timeout values are specified in seconds */ 627 #define OHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 628 #define OHCI_MAX_SOF_TIMEWAIT 3 /* Maximum SOF waiting time */ 629 #define OHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 630 631 /* OHCI flags for general use */ 632 #define OHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 633 #define OHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 634 #define OHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 635 636 /* 637 * Maximum allowable data transfer size per transaction as supported 638 * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a) 639 */ 640 #define OHCI_MAX_TD_XFER_SIZE 0x2000 /* Maxmum data per transaction */ 641 642 /* 643 * The maximum allowable bulk data transfer size. It can be different 644 * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will 645 * take care of breaking a bulk data request into multiples of ohci 646 * OHCI_MAX_TD_XFER_SIZE until request is satisfied. Currently this 647 * value is set to 256k bytes. 648 */ 649 #define OHCI_MAX_BULK_XFER_SIZE 0x40000 /* Maximum bulk transfer size */ 650 651 /* 652 * Timeout flags 653 * 654 * These flags will be used to stop the timer before timeout handler 655 * gets executed. 656 */ 657 #define OHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last TD */ 658 #define OHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 659 660 661 /* 662 * Bandwidth allocation 663 * 664 * The following definitions are used during bandwidth calculations 665 * for a given endpoint maximum packet size. 666 */ 667 #define MAX_USB_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 668 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 669 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 670 #define SOF 6 /* Length in bytes of SOF */ 671 #define EOF 4 /* Length in bytes of EOF */ 672 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 673 674 /* 675 * Minimum polling interval for low speed endpoint 676 * 677 * According USB Specifications, a full-speed endpoint can specify 678 * a desired polling interval 1ms to 255ms and a low speed endpoints 679 * are limited to specifying only 10ms to 255ms. But some old keyboards 680 * and mice uses polling interval of 8ms. For compatibility purpose, 681 * we are using polling interval between 8ms and 255ms for low speed 682 * endpoints. But ohci driver will reject any low speed endpoints which 683 * request polling interval less than 8ms. 684 */ 685 #define MIN_LOW_SPEED_POLL_INTERVAL 8 686 687 /* 688 * For non-periodic transfers, reserve atleast for one low-speed device 689 * transaction. According to USB Bandwidth Analysis white paper and also 690 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 691 * transaction takes 0x628h full speed bits (197 bytes), which comes to 692 * around 13% of USB frame time. 693 * 694 * The periodic transfers will get around 87% of USB frame time. 695 */ 696 #define MAX_NON_PERIODIC_BANDWIDTH 197 697 #define MAX_PERIODIC_BANDWIDTH (MAX_USB_BUS_BANDWIDTH - SOF - \ 698 EOF - MAX_NON_PERIODIC_BANDWIDTH) 699 700 /* 701 * The USB periodic transfers like interrupt and isochronous transfers 702 * after completion of SOF and USB non-periodic transfers. 703 */ 704 #define PERIODIC_XFER_STARTS (MAX_USB_BUS_BANDWIDTH - \ 705 SOF - MAX_NON_PERIODIC_BANDWIDTH) 706 707 /* Number of Bits Per Byte */ 708 #define BITS_PER_BYTE 8 709 710 /* 711 * The following are the protocol overheads in terms of Bytes for the 712 * different transfer types. All these protocol overhead values are 713 * derived from the 5.9.3 section of USB Specification and with the 714 * help of Bandwidth Analysis white paper which is posted on the USB 715 * developer forum. 716 */ 717 #define FS_NON_ISOC_PROTO_OVERHEAD 14 718 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 719 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 720 #define LOW_SPEED_PROTO_OVERHEAD 97 721 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 722 723 /* 724 * The Host Controller (HC) delays are the USB host controller specific 725 * delays. The value shown below is the host controller delay for the 726 * RIO USB host controller. This value was calculated and given by the 727 * Sun USB hardware people. 728 */ 729 #define HOST_CONTROLLER_DELAY 18 730 731 /* 732 * The low speed clock below represents that to transmit one low-speed 733 * bit takes eight times more than one full speed bit time. 734 */ 735 #define LOW_SPEED_CLOCK 8 736 737 738 /* 739 * Macros for setting/getting information 740 */ 741 #define Get_ED(addr) ddi_get32(ohcip->ohci_ed_pool_mem_handle, \ 742 (uint32_t *)&addr) 743 744 #define Set_ED(addr, val) ddi_put32(ohcip->ohci_ed_pool_mem_handle, \ 745 ((uint32_t *)&addr), \ 746 ((int32_t)(val))) 747 748 #define Get_TD(addr) ddi_get32(ohcip->ohci_td_pool_mem_handle, \ 749 (uint32_t *)&addr) 750 751 #define Set_TD(addr, val) ddi_put32(ohcip->ohci_td_pool_mem_handle, \ 752 ((uint32_t *)&addr), \ 753 ((uint32_t)(uintptr_t)(val))) 754 755 #define Get_HCCA(addr) ddi_get32(ohcip->ohci_hcca_mem_handle, \ 756 (uint32_t *)&addr) 757 758 #define Set_HCCA(addr, val) ddi_put32(ohcip->ohci_hcca_mem_handle, \ 759 ((uint32_t *)&addr), \ 760 ((int32_t)(val))) 761 762 #define Get_OpReg(addr) ddi_get32(ohcip->ohci_regs_handle, \ 763 (uint32_t *)&ohcip->ohci_regsp->addr) 764 765 #define Set_OpReg(addr, val) ddi_put32(ohcip->ohci_regs_handle, \ 766 ((uint32_t *)&ohcip->ohci_regsp->addr), \ 767 ((int32_t)(val))) 768 769 #define Sync_HCCA(ohcip) (void) ddi_dma_sync( \ 770 ohcip->ohci_hcca_dma_handle, \ 771 0, sizeof (ohci_hcca_t), \ 772 DDI_DMA_SYNC_FORCPU); 773 774 #define Sync_ED_TD_Pool(ohcip) (void) ddi_dma_sync( \ 775 ohcip->ohci_ed_pool_dma_handle, \ 776 0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \ 777 DDI_DMA_SYNC_FORCPU); \ 778 (void) ddi_dma_sync( \ 779 ohcip->ohci_td_pool_dma_handle, \ 780 0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \ 781 DDI_DMA_SYNC_FORCPU); 782 783 #define Sync_IO_Buffer(dma_handle, length) \ 784 (void) ddi_dma_sync(dma_handle, \ 785 0, length, DDI_DMA_SYNC_FORCPU); 786 787 /* 788 * Macros to speed handling of 32bit IDs 789 */ 790 #define OHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 791 #define OHCI_LOOKUP_ID(x) id32_lookup((x)) 792 #define OHCI_FREE_ID(x) id32_free((x)) 793 794 795 /* 796 * Miscellaneous definitions. 797 */ 798 799 /* Data toggle bits */ 800 #define DATA0 0 801 #define DATA1 1 802 803 /* sKip bit actions */ 804 #define CLEAR_sKip 0 805 #define SET_sKip 1 806 807 typedef uint_t skip_bit_t; 808 809 /* 810 * Setup Packet 811 */ 812 typedef struct setup_pkt { 813 uchar_t bmRequestType; 814 uchar_t bRequest; 815 ushort_t wValue; 816 ushort_t wIndex; 817 ushort_t wLength; 818 }setup_pkt_t; 819 820 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 821 822 #define REQUEST_TYPE_OFFSET 0 823 #define REQUEST_OFFSET 1 824 #define VALUE_OFFSET 2 825 #define INDEX_OFFSET 4 826 #define LENGTH_OFFSET 6 827 828 #define TYPE_DEV_TO_HOST 0x80000000 829 #define DEVICE 0x00000001 830 #define CONFIGURATION 0x00000002 831 832 /* 833 * The following are used in attach to indicate 834 * what has been succesfully allocated, so detach 835 * can remove them. 836 */ 837 #define OHCI_ATTACH 0x01 /* ohci driver initilization */ 838 #define OHCI_ZALLOC 0x02 /* Memory for ohci state structure */ 839 #define OHCI_INTR 0x04 /* Interrupt handler registered */ 840 #define OHCI_USBAREG 0x08 /* USBA registered */ 841 #define OHCI_RHREG 0x10 /* Root hub driver loaded */ 842 843 #define OHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 844 845 /* 846 * Debug printing 847 * Masks 848 */ 849 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 850 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 851 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 852 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 853 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 854 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 855 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 856 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 857 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ohci info */ 858 #define PRINT_MASK_ALL 0xFFFFFFFF 859 860 861 /* Polling support */ 862 int ohci_hcdi_polled_input_init( 863 usba_pipe_handle_data_t *ph, 864 uchar_t **polled_buf, 865 usb_console_info_impl_t *info); 866 int ohci_hcdi_polled_input_enter( 867 usb_console_info_impl_t *info); 868 int ohci_hcdi_polled_read( 869 usb_console_info_impl_t *info, 870 uint_t *num_characters); 871 int ohci_hcdi_polled_input_exit( 872 usb_console_info_impl_t *info); 873 int ohci_hcdi_polled_input_fini( 874 usb_console_info_impl_t *info); 875 876 /* Root hub related functions */ 877 int ohci_init_root_hub( 878 ohci_state_t *ohcip); 879 int ohci_load_root_hub_driver( 880 ohci_state_t *ohcip); 881 int ohci_unload_root_hub_driver( 882 ohci_state_t *ohcip); 883 int ohci_handle_root_hub_pipe_open( 884 usba_pipe_handle_data_t *ph, 885 usb_flags_t flags); 886 int ohci_handle_root_hub_pipe_close( 887 usba_pipe_handle_data_t *ph); 888 int ohci_handle_root_hub_pipe_reset( 889 usba_pipe_handle_data_t *ph, 890 usb_flags_t flags); 891 int ohci_handle_root_hub_request( 892 ohci_state_t *ohcip, 893 usba_pipe_handle_data_t *ph, 894 usb_ctrl_req_t *ctrl_reqp); 895 int ohci_handle_root_hub_pipe_start_intr_polling( 896 usba_pipe_handle_data_t *ph, 897 usb_intr_req_t *intr_reqp, 898 usb_flags_t flags); 899 void ohci_handle_root_hub_pipe_stop_intr_polling( 900 usba_pipe_handle_data_t *ph, 901 usb_flags_t flags); 902 void ohci_handle_root_hub_status_change(void *arg); 903 904 /* Endpoint Descriptor (ED) related functions */ 905 ohci_ed_t *ohci_alloc_hc_ed( 906 ohci_state_t *ohcip, 907 usba_pipe_handle_data_t *ph); 908 void ohci_deallocate_ed( 909 ohci_state_t *ohcip, 910 ohci_ed_t *old_ed); 911 uint32_t ohci_ed_cpu_to_iommu( 912 ohci_state_t *ohcip, 913 ohci_ed_t *addr); 914 915 /* Transfer Descriptor (TD) related functions */ 916 int ohci_start_periodic_pipe_polling( 917 ohci_state_t *ohcip, 918 usba_pipe_handle_data_t *ph, 919 usb_opaque_t periodic_in_reqp, 920 usb_flags_t flags); 921 void ohci_traverse_tds( 922 ohci_state_t *ohcip, 923 usba_pipe_handle_data_t *ph); 924 void ohci_deallocate_td( 925 ohci_state_t *ohcip, 926 ohci_td_t *old_td); 927 uint32_t ohci_td_cpu_to_iommu( 928 ohci_state_t *ohcip, 929 ohci_td_t *addr); 930 ohci_td_t *ohci_td_iommu_to_cpu( 931 ohci_state_t *ohcip, 932 uintptr_t addr); 933 934 /* Transfer Wrapper (TW) functions */ 935 void ohci_deallocate_tw_resources( 936 ohci_state_t *ohcip, 937 ohci_pipe_private_t *pp, 938 ohci_trans_wrapper_t *tw); 939 940 /* Interrupt Handling functions */ 941 void ohci_handle_frame_number_overflow( 942 ohci_state_t *ohcip); 943 944 /* Miscillaneous functions */ 945 ohci_state_t *ohci_obtain_state( 946 dev_info_t *dip); 947 int ohci_state_is_operational( 948 ohci_state_t *ohcip); 949 int ohci_do_soft_reset( 950 ohci_state_t *ohcip); 951 usb_frame_number_t ohci_get_current_frame_number( 952 ohci_state_t *ohcip); 953 void ohci_handle_outstanding_requests( 954 ohci_state_t *ohcip, 955 ohci_pipe_private_t *pp); 956 957 #ifdef __cplusplus 958 } 959 #endif 960 961 #endif /* _SYS_USB_OHCID_H */ 962