1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_OHCID_H 28 #define _SYS_USB_OHCID_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Open Host Controller Driver (OHCI) 38 * 39 * The USB Open Host Controller driver is a software driver which interfaces 40 * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 41 * The interface to USB Open Host Controller is defined by the OpenHCI Host 42 * Controller Interface. 43 * 44 * This header file describes the data structures required for the USB Open 45 * Host Controller Driver to maintain state of USB Open Host Controller, to 46 * perform different USB transfers and for the bandwidth allocations. 47 */ 48 49 #include <sys/usb/hcd/openhci/ohci.h> 50 #include <sys/usb/hcd/openhci/ohci_hub.h> 51 52 /* 53 * OpenHCI interrupt status information structure 54 * 55 * The Host Controller Driver (HCD) has to maintain two different sets of 56 * Host Controller (HC) state information that includes HC registers, the 57 * interrupt tables etc.. for the normal and polled modes. In addition, 58 * suppose if we switched to polled mode while ohci interrupt handler is 59 * executing in the normal mode then we need to save the interrupt status 60 * information that includes interrupts for which ohci interrupt handler 61 * is called and HCCA done head list in the polled mode. This infromation 62 * will be used later in normal mode to service those missed interrupts. 63 * This will avoid race conditions like missing of normal mode's ohci SOF 64 * and WriteDoneHead interrupts because of this polled switch. 65 */ 66 typedef struct ohci_save_intr_sts { 67 /* 68 * The following field has set of flags & these flags will be set 69 * in the ohci interrupt handler to indicate that currently ohci 70 * interrupt handler is in execution and also while critical code 71 * execution within the ohci interrupt handler. These flags will 72 * be verified in polled mode while saving the normal mode's ohci 73 * interrupt status information. 74 */ 75 uint_t ohci_intr_flag; /* Intr handler flags */ 76 77 /* 78 * The following fields will be used to save the interrupt status 79 * and the HCCA done head list that the ohci interrupt handler is 80 * currently handling. 81 */ 82 uint_t ohci_curr_intr_sts; /* Current interrupts */ 83 ohci_td_t *ohci_curr_done_lst; /* Current done head */ 84 85 /* 86 * The following fields will be used to save the interrupt status 87 * and the HCCA done list currently being handled by the critical 88 * section of the ohci interrupt handler.. 89 */ 90 uint_t ohci_critical_intr_sts; /* Critical interrupts */ 91 ohci_td_t *ohci_critical_done_lst; /* Critical done head */ 92 93 /* 94 * The following fields will be used to save the interrupt status 95 * and HCCA done head list by the polled code if an interrupt is 96 * pending when polled code is entered. These missed interrupts & 97 * done list will be serviced either in current normal mode ohci 98 * interrupt handler execution or during the next ohci interrupt 99 * handler execution. 100 */ 101 uint_t ohci_missed_intr_sts; /* Missed interrupts */ 102 ohci_td_t *ohci_missed_done_lst; /* Missed done head */ 103 } ohci_save_intr_sts_t; 104 105 /* 106 * These flags will be set in the the normal mode ohci interrupt handler 107 * to indicate that currently ohci interrupt handler is in execution and 108 * also while critical code execution within the ohci interrupt handler. 109 * These flags will be verified in the polled mode while saving the normal 110 * mode's ohci interrupt status infromation. 111 */ 112 #define OHCI_INTR_HANDLING 0x01 /* Handling ohci intrs */ 113 #define OHCI_INTR_CRITICAL 0x02 /* Critical intr code */ 114 115 116 /* 117 * OpenHCI Host Controller state structure 118 * 119 * The Host Controller Driver (HCD) maintains the state of Host Controller 120 * (HC). There is an ohci_state structure per instance of the OpenHCI 121 * host controller. 122 */ 123 124 typedef struct ohci_state { 125 dev_info_t *ohci_dip; /* Dip of HC */ 126 uint_t ohci_instance; 127 usba_hcdi_ops_t *ohci_hcdi_ops; /* HCDI structure */ 128 uint_t ohci_flags; /* Used for cleanup */ 129 uint16_t ohci_vendor_id; /* chip vendor */ 130 uint16_t ohci_device_id; /* chip device */ 131 uint8_t ohci_rev_id; /* chip revison */ 132 133 ohci_regs_t *ohci_regsp; /* Host ctlr regs */ 134 ddi_acc_handle_t ohci_regs_handle; /* Reg handle */ 135 136 ddi_acc_handle_t ohci_config_handle; /* Config space hndle */ 137 uint_t ohci_frame_interval; /* Frme inter reg */ 138 ddi_dma_attr_t ohci_dma_attr; /* DMA attributes */ 139 140 ddi_intr_handle_t *ohci_htable; /* intr handle */ 141 uint_t ohci_intr_pri; /* intr priority */ 142 kmutex_t ohci_int_mutex; /* Mutex for struct */ 143 144 /* HCCA area */ 145 ohci_hcca_t *ohci_hccap; /* Virtual HCCA ptr */ 146 ddi_dma_cookie_t ohci_hcca_cookie; /* DMA cookie */ 147 ddi_dma_handle_t ohci_hcca_dma_handle; /* DMA handle */ 148 ddi_acc_handle_t ohci_hcca_mem_handle; /* Memory handle */ 149 150 /* 151 * There are two pools of memory. One pool contains the memory for 152 * the transfer descriptors and other pool contains the memory for 153 * the endpoint descriptors. The advantage of the pools is that it's 154 * easy to go back and forth between the iommu and the cpu addresses. 155 * 156 * The pools are protected by the ohci_int_mutex because the memory 157 * in the pools may be accessed by either the host controller or the 158 * host controller driver. 159 */ 160 161 /* General transfer descriptor pool */ 162 ohci_td_t *ohci_td_pool_addr; /* Start of the pool */ 163 ddi_dma_cookie_t ohci_td_pool_cookie; /* DMA cookie */ 164 ddi_dma_handle_t ohci_td_pool_dma_handle; /* DMA hndle */ 165 ddi_acc_handle_t ohci_td_pool_mem_handle; /* Mem hndle */ 166 167 /* Endpoint descriptor pool */ 168 ohci_ed_t *ohci_ed_pool_addr; /* Start of the pool */ 169 ddi_dma_cookie_t ohci_ed_pool_cookie; /* DMA cookie */ 170 ddi_dma_handle_t ohci_ed_pool_dma_handle; /* DMA handle */ 171 ddi_acc_handle_t ohci_ed_pool_mem_handle; /* Mem handle */ 172 uint_t ohci_dma_addr_bind_flag; /* DMA flag */ 173 174 /* Condition variables */ 175 kcondvar_t ohci_SOF_cv; /* SOF variable */ 176 177 /* Semaphore to serialize opens and closes */ 178 ksema_t ohci_ocsem; 179 180 /* 181 * Bandwidth fields 182 * 183 * The ohci_bandwidth array keeps track of the allocated bandwidth 184 * for this host controller. The total bandwidth allocated for least 185 * allocated list out of the 32 periodic lists is represented by the 186 * ohci_periodic_minimum_bandwidth field. 187 */ 188 uint_t ohci_periodic_minimum_bandwidth; 189 uint_t ohci_periodic_bandwidth[NUM_INTR_ED_LISTS]; 190 191 /* Different transfer open pipe counts */ 192 uint_t ohci_open_pipe_count; 193 uint_t ohci_open_ctrl_pipe_count; 194 uint_t ohci_open_bulk_pipe_count; 195 uint_t ohci_open_periodic_pipe_count; 196 uint_t ohci_open_isoch_pipe_count; 197 /* 198 * Endpoint Reclamation List 199 * 200 * The interrupt or isochronous list processing cannot be stopped 201 * when a periodic endpoint is removed from the list. The endpoints 202 * are detached from the interrupt lattice tree and put on to the 203 * reclaimation list. On next SOF interrupt all those endpoints, 204 * which are on the reclaimation list will be deallocated. 205 */ 206 ohci_ed_t *ohci_reclaim_list; /* Reclaimation list */ 207 208 ohci_root_hub_t ohci_root_hub; /* Root hub info */ 209 210 /* 211 * Global transfer timeout handling & this transfer timeout handling 212 * will be per USB Host Controller. 213 */ 214 struct ohci_trans_wrapper *ohci_timeout_list; /* Timeout List */ 215 timeout_id_t ohci_timer_id; /* Timer id */ 216 217 /* Frame number overflow information */ 218 usb_frame_number_t ohci_fno; 219 220 /* For Schedule Overrun error counter */ 221 uint_t ohci_so_error; 222 223 /* For host controller error counter */ 224 uint_t ohci_hc_error; 225 226 /* For SOF interrupt event */ 227 boolean_t ohci_sof_flag; 228 229 /* Openhci Host Controller Software State information */ 230 uint_t ohci_hc_soft_state; 231 232 /* 233 * ohci_save_intr_stats is used to save the normal mode interrupt 234 * status information while executing interrupt handler & also by 235 * the polled code if an interrupt is pending for the normal mode 236 * when polled code is entered. 237 */ 238 ohci_save_intr_sts_t ohci_save_intr_sts; 239 240 /* 241 * Saved copy of the ohci registers of the normal mode & change 242 * required ohci registers values for the polled mode operation. 243 * Before returning from the polled mode to normal mode replace 244 * the required current registers with this saved ohci registers 245 * copy. 246 */ 247 ohci_regs_t ohci_polled_save_regs; 248 249 /* 250 * Saved copy of the interrupt table used in normal ohci mode and 251 * replace this table by another interrupt table that used in the 252 * POLLED mode. 253 */ 254 ohci_ed_t *ohci_polled_save_IntTble[NUM_INTR_ED_LISTS]; 255 256 /* ohci polled mode enter counter for the input devices */ 257 uint_t ohci_polled_enter_count; 258 259 /* 260 * Counter for polled mode and used in suspend mode to see if 261 * there is a input device connected. 262 */ 263 uint_t ohci_polled_kbd_count; 264 265 /* Done list for the Polled mode */ 266 ohci_td_t *ohci_polled_done_list; 267 268 /* Log handle for debug, console, log messages */ 269 usb_log_handle_t ohci_log_hdl; 270 271 /* Kstat structures */ 272 kstat_t *ohci_intrs_stats; 273 kstat_t *ohci_total_stats; 274 kstat_t *ohci_count_stats[USB_N_COUNT_KSTATS]; 275 } ohci_state_t; 276 277 typedef struct ohci_intrs_stats { 278 struct kstat_named ohci_hcr_intr_so; 279 struct kstat_named ohci_hcr_intr_wdh; 280 struct kstat_named ohci_hcr_intr_sof; 281 struct kstat_named ohci_hcr_intr_rd; 282 struct kstat_named ohci_hcr_intr_ue; 283 struct kstat_named ohci_hcr_intr_fno; 284 struct kstat_named ohci_hcr_intr_rhsc; 285 struct kstat_named ohci_hcr_intr_oc; 286 struct kstat_named ohci_hcr_intr_not_claimed; 287 struct kstat_named ohci_hcr_intr_total; 288 } ohci_intrs_stats_t; 289 290 /* 291 * ohci kstat defines 292 */ 293 #define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats) 294 #define OHCI_INTRS_STATS_DATA(ohci) \ 295 ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data) 296 297 #define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats) 298 #define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats)) 299 #define OHCI_CTRL_STATS(ohci) \ 300 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL])) 301 #define OHCI_BULK_STATS(ohci) \ 302 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK])) 303 #define OHCI_INTR_STATS(ohci) \ 304 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR])) 305 #define OHCI_ISOC_STATS(ohci) \ 306 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH])) 307 308 /* warlock directives, stable data */ 309 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t)) 310 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri)) 311 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip)) 312 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp)) 313 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance)) 314 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id)) 315 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id)) 316 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id)) 317 318 /* this may not be stable data in the future */ 319 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr)) 320 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle)) 321 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr)) 322 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle)) 323 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie)) 324 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie)) 325 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle)) 326 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap)) 327 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag)) 328 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl)) 329 330 _NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \ 331 usba_pipe_handle_data::p_mutex \ 332 usba_device::usb_mutex \ 333 usba_ph_impl::usba_ph_mutex)) 334 335 /* 336 * Host Contoller Software States 337 * 338 * OHCI_CTLR_INIT_STATE: 339 * The host controller soft state will be set to this during the 340 * ohci_attach. 341 * 342 * OHCI_CTLR_SUSPEND_STATE: 343 * The host controller soft state will be set to this during the 344 * ohci_cpr_suspend. 345 * 346 * OHCI_CTLR_OPERATIONAL_STATE: 347 * The host controller soft state will be set to this after moving 348 * host controller to operational state and host controller start 349 * generating SOF successfully. 350 * 351 * OHCI_CTLR_ERROR_STATE: 352 * The host controller soft state will be set to this during the 353 * no SOF or UE error conditions. 354 * 355 * Under this state or condition, only pipe stop polling, pipe reset 356 * and pipe close are allowed. But all other entry points like pipe 357 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 358 * isoch send/receive, start polling etc. will fail. 359 * 360 * State Diagram for the host controller software state 361 * 362 * 363 * ohci_attach->[INIT_STATE] 364 * | 365 * | -------->----[ERROR_STATE]--<-----------<--- 366 * | | Failure (UE/no SOF condition) | 367 * | ^ ^ 368 * V | Success | 369 * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling 370 * ^ | 371 * | | 372 * | V 373 * -<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend 374 */ 375 #define OHCI_CTLR_INIT_STATE 0 /* Initilization state */ 376 #define OHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 377 #define OHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 378 #define OHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 379 380 /* 381 * Define all ohci's Vendor-id and Device-id Here 382 */ 383 #define RIO_VENDOR 0x108e 384 #define RIO_DEVICE 0x1103 385 #define OHCI_IS_RIO(ohcip) (ohcip->ohci_vendor_id == RIO_VENDOR) 386 387 /* 388 * Periodic and non-periodic macros 389 */ 390 #define OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 391 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 392 ((endpoint->bmAttributes &\ 393 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 394 395 #define OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 396 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 397 ((endpoint->bmAttributes &\ 398 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 399 400 /* 401 * OHCI ED and TD Pool sizes. 402 */ 403 #define OHCI_ED_POOL_SIZE 100 404 #define OHCI_TD_POOL_SIZE 200 405 406 /* 407 * ohci_dma_addr_bind_flag values 408 * 409 * This flag indicates if the various DMA addresses allocated by the OHCI 410 * have been bound to their respective handles. This is needed to recover 411 * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle() 412 */ 413 #define OHCI_TD_POOL_BOUND 0x01 /* For TD pools */ 414 #define OHCI_ED_POOL_BOUND 0x02 /* For ED pools */ 415 #define OHCI_HCCA_DMA_BOUND 0x04 /* For HCCA area */ 416 417 /* 418 * Maximum SOF wait count 419 */ 420 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 421 422 423 /* 424 * Pipe private structure 425 * 426 * There is an instance of this structure per pipe. This structure holds 427 * HCD specific pipe information. A pointer to this structure is kept in 428 * the USBA pipe handle (usba_pipe_handle_data_t). 429 */ 430 typedef struct ohci_pipe_private { 431 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 432 ohci_ed_t *pp_ept; /* Pipe's ept */ 433 434 /* State of the pipe */ 435 uint_t pp_state; /* See below */ 436 437 /* Local copy of the pipe policy */ 438 usb_pipe_policy_t pp_policy; 439 440 /* For Periodic Pipes Only */ 441 uint_t pp_node; /* Node in lattice */ 442 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 443 uint_t pp_max_periodic_req_cnt; /* Max req count */ 444 445 /* For isochronous pipe only */ 446 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 447 448 /* 449 * Each pipe may have multiple transfer wrappers. Each transfer 450 * wrapper represents a USB transfer on the bus. A transfer is 451 * made up of one or more transactions. 452 */ 453 struct ohci_trans_wrapper *pp_tw_head; /* Head of the list */ 454 struct ohci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 455 456 /* Done td count */ 457 uint_t pp_count_done_tds; /* Done td count */ 458 459 /* Errors */ 460 usb_cr_t pp_error; /* Pipe error */ 461 462 /* Flags */ 463 uint_t pp_flag; /* Flags */ 464 465 /* Condition variable for transfers completion event */ 466 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 467 468 /* 469 * HCD gets Interrupt/Isochronous IN polling request only once and 470 * it has to insert next polling requests after completion of first 471 * request until either stop polling/pipe close is called. So HCD 472 * has to take copy of the original Interrupt/Isochronous IN request. 473 */ 474 usb_opaque_t pp_client_periodic_in_reqp; 475 } ohci_pipe_private_t; 476 477 /* warlock directives, stable data */ 478 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t)) 479 480 /* 481 * Pipe states 482 * 483 * ohci pipe states will be similar to usba. Refer usbai.h. 484 */ 485 #define OHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 486 #define OHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 487 #define OHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 488 489 /* Additional ohci pipe states for the ohci_pipe_cleanup */ 490 #define OHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 491 #define OHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 492 #define OHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 493 494 /* 495 * Pipe specific Flags 496 */ 497 #define OHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 498 499 /* 500 * The maximum allowable usb isochronous data transfer size or maximum 501 * number of isochronous data packets. 502 * 503 * Each usb isochronous request must not exceed multiples of isochronous 504 * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER. 505 * 506 * Ex: usb isochronous endpoint maximum packet size is 64 bytes 507 * maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER 508 * * 64 bytes 509 */ 510 #define OHCI_MAX_ISOC_PKTS_PER_XFER 256 /* Max pkts per req */ 511 512 /* 513 * The ohci supports maximum of eight isochronous data packets per transfer 514 * descriptor. 515 */ 516 #define OHCI_ISOC_PKTS_PER_TD 8 /* Packets per TD */ 517 518 /* 519 * USB frame offset 520 * 521 * Add appropriate frame offset to the current usb frame number and use it 522 * as a starting frame number for a given usb isochronous request. 523 */ 524 #define OHCI_FRAME_OFFSET 2 /* Frame offset */ 525 526 /* 527 * Default usb isochronous receive packets per request before ohci will do 528 * callback. 529 */ 530 #define OHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 531 532 /* 533 * Different interrupt polling intervals supported 534 */ 535 #define INTR_1MS_POLL 1 536 #define INTR_2MS_POLL 2 537 #define INTR_4MS_POLL 4 538 #define INTR_8MS_POLL 8 539 #define INTR_16MS_POLL 16 540 #define INTR_32MS_POLL 32 541 542 /* 543 * Number of interrupt/isochronous transfer requests that should 544 * be maintained on the interrupt/isochronous endpoint corresponding 545 * to different polling intervals supported. 546 */ 547 #define INTR_1MS_REQS 4 /* 1ms polling interval */ 548 #define INTR_2MS_REQS 2 /* 2ms polling interval */ 549 #define INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 550 551 /* Function prototype */ 552 typedef void (*ohci_handler_function_t)( 553 ohci_state_t *ohcip, 554 ohci_pipe_private_t *pp, 555 struct ohci_trans_wrapper *tw, 556 ohci_td_t *td, 557 void *ohci_handle_callback_value); 558 559 560 /* 561 * Transfer wrapper 562 * 563 * The transfer wrapper represents a USB transfer on the bus and there 564 * is one instance per USB transfer. A transfer is made up of one or 565 * more transactions. 566 * 567 * Control and bulk pipes will have one transfer wrapper per transfer 568 * and where as Isochronous and Interrupt pipes will only have one 569 * transfer wrapper. The transfers wrapper are continually reused for 570 * the Interrupt and Isochronous pipes as those pipes are polled. 571 */ 572 typedef struct ohci_trans_wrapper { 573 struct ohci_trans_wrapper *tw_next; /* Next wrapper */ 574 ohci_pipe_private_t *tw_pipe_private; /* Back ptr */ 575 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 576 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 577 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 578 uint32_t tw_id; /* 32bit ID */ 579 size_t tw_length; /* Txfer length */ 580 char *tw_buf; /* Buffer for Xfer */ 581 usb_flags_t tw_flags; /* Flags */ 582 uint_t tw_num_tds; /* Number of TDs */ 583 ohci_td_t *tw_hctd_head; /* Head TD */ 584 ohci_td_t *tw_hctd_tail; /* Tail TD */ 585 uint_t tw_direction; /* Direction of TD */ 586 587 /* We preallocate all the td's for each tw and place them here */ 588 ohci_td_t *tw_hctd_free_list; 589 590 /* Current transfer request pointer */ 591 usb_opaque_t tw_curr_xfer_reqp; 592 593 /* Current isochronous packet descriptor pointer */ 594 usb_isoc_pkt_descr_t *tw_curr_isoc_pktp; 595 596 /* Transfer timeout information */ 597 uint_t tw_timeout; /* Timeout value */ 598 struct ohci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 599 600 /* 601 * This is the function to call when this td is done. This way 602 * we don't have to look in the td to figure out what kind it is. 603 */ 604 ohci_handler_function_t tw_handle_td; 605 606 /* 607 * This is the callback value used when processing a done td. 608 */ 609 usb_opaque_t tw_handle_callback_value; 610 } ohci_trans_wrapper_t; 611 612 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper)) 613 614 615 /* 616 * Time waits for the different OHCI specific operations. 617 * These timeout values are specified in terms of microseconds. 618 */ 619 #define OHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 620 #define OHCI_RESUME_TIMEWAIT 40000 /* HC resume waiting time */ 621 #define OHCI_TIMEWAIT 10000 /* HC any other waiting time */ 622 623 /* These timeout values are specified in seconds */ 624 #define OHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 625 #define OHCI_MAX_SOF_TIMEWAIT 3 /* Maximum SOF waiting time */ 626 #define OHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 627 628 /* OHCI flags for general use */ 629 #define OHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 630 #define OHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 631 #define OHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 632 633 /* 634 * Maximum allowable data transfer size per transaction as supported 635 * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a) 636 */ 637 #define OHCI_MAX_TD_XFER_SIZE 0x2000 /* Maxmum data per transaction */ 638 639 /* 640 * The maximum allowable bulk data transfer size. It can be different 641 * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will 642 * take care of breaking a bulk data request into multiples of ohci 643 * OHCI_MAX_TD_XFER_SIZE until request is satisfied. Currently this 644 * value is set to 256k bytes. 645 */ 646 #define OHCI_MAX_BULK_XFER_SIZE 0x40000 /* Maximum bulk transfer size */ 647 648 /* 649 * Timeout flags 650 * 651 * These flags will be used to stop the timer before timeout handler 652 * gets executed. 653 */ 654 #define OHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last TD */ 655 #define OHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 656 657 658 /* 659 * Bandwidth allocation 660 * 661 * The following definitions are used during bandwidth calculations 662 * for a given endpoint maximum packet size. 663 */ 664 #define MAX_USB_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 665 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 666 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 667 #define SOF 6 /* Length in bytes of SOF */ 668 #define EOF 4 /* Length in bytes of EOF */ 669 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 670 671 /* 672 * Minimum polling interval for low speed endpoint 673 * 674 * According USB Specifications, a full-speed endpoint can specify 675 * a desired polling interval 1ms to 255ms and a low speed endpoints 676 * are limited to specifying only 10ms to 255ms. But some old keyboards 677 * and mice uses polling interval of 8ms. For compatibility purpose, 678 * we are using polling interval between 8ms and 255ms for low speed 679 * endpoints. But ohci driver will reject any low speed endpoints which 680 * request polling interval less than 8ms. 681 */ 682 #define MIN_LOW_SPEED_POLL_INTERVAL 8 683 684 /* 685 * For non-periodic transfers, reserve atleast for one low-speed device 686 * transaction. According to USB Bandwidth Analysis white paper and also 687 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 688 * transaction takes 0x628h full speed bits (197 bytes), which comes to 689 * around 13% of USB frame time. 690 * 691 * The periodic transfers will get around 87% of USB frame time. 692 */ 693 #define MAX_NON_PERIODIC_BANDWIDTH 197 694 #define MAX_PERIODIC_BANDWIDTH (MAX_USB_BUS_BANDWIDTH - SOF - \ 695 EOF - MAX_NON_PERIODIC_BANDWIDTH) 696 697 /* 698 * The USB periodic transfers like interrupt and isochronous transfers 699 * after completion of SOF and USB non-periodic transfers. 700 */ 701 #define PERIODIC_XFER_STARTS (MAX_USB_BUS_BANDWIDTH - \ 702 SOF - MAX_NON_PERIODIC_BANDWIDTH) 703 704 /* Number of Bits Per Byte */ 705 #define BITS_PER_BYTE 8 706 707 /* 708 * The following are the protocol overheads in terms of Bytes for the 709 * different transfer types. All these protocol overhead values are 710 * derived from the 5.9.3 section of USB Specification and with the 711 * help of Bandwidth Analysis white paper which is posted on the USB 712 * developer forum. 713 */ 714 #define FS_NON_ISOC_PROTO_OVERHEAD 14 715 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 716 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 717 #define LOW_SPEED_PROTO_OVERHEAD 97 718 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 719 720 /* 721 * The Host Controller (HC) delays are the USB host controller specific 722 * delays. The value shown below is the host controller delay for the 723 * RIO USB host controller. This value was calculated and given by the 724 * Sun USB hardware people. 725 */ 726 #define HOST_CONTROLLER_DELAY 18 727 728 /* 729 * The low speed clock below represents that to transmit one low-speed 730 * bit takes eight times more than one full speed bit time. 731 */ 732 #define LOW_SPEED_CLOCK 8 733 734 735 /* 736 * Macros for setting/getting information 737 */ 738 #define Get_ED(addr) ddi_get32(ohcip->ohci_ed_pool_mem_handle, \ 739 (uint32_t *)&addr) 740 741 #define Set_ED(addr, val) ddi_put32(ohcip->ohci_ed_pool_mem_handle, \ 742 ((uint32_t *)&addr), \ 743 ((int32_t)(val))) 744 745 #define Get_TD(addr) ddi_get32(ohcip->ohci_td_pool_mem_handle, \ 746 (uint32_t *)&addr) 747 748 #define Set_TD(addr, val) ddi_put32(ohcip->ohci_td_pool_mem_handle, \ 749 ((uint32_t *)&addr), \ 750 ((uint32_t)(uintptr_t)(val))) 751 752 #define Get_HCCA(addr) ddi_get32(ohcip->ohci_hcca_mem_handle, \ 753 (uint32_t *)&addr) 754 755 #define Set_HCCA(addr, val) ddi_put32(ohcip->ohci_hcca_mem_handle, \ 756 ((uint32_t *)&addr), \ 757 ((int32_t)(val))) 758 759 #define Get_OpReg(addr) ddi_get32(ohcip->ohci_regs_handle, \ 760 (uint32_t *)&ohcip->ohci_regsp->addr) 761 762 #define Set_OpReg(addr, val) ddi_put32(ohcip->ohci_regs_handle, \ 763 ((uint32_t *)&ohcip->ohci_regsp->addr), \ 764 ((int32_t)(val))) 765 766 #define Sync_HCCA(ohcip) (void) ddi_dma_sync( \ 767 ohcip->ohci_hcca_dma_handle, \ 768 0, sizeof (ohci_hcca_t), \ 769 DDI_DMA_SYNC_FORCPU); 770 771 #define Sync_ED_TD_Pool(ohcip) (void) ddi_dma_sync( \ 772 ohcip->ohci_ed_pool_dma_handle, \ 773 0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \ 774 DDI_DMA_SYNC_FORCPU); \ 775 (void) ddi_dma_sync( \ 776 ohcip->ohci_td_pool_dma_handle, \ 777 0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \ 778 DDI_DMA_SYNC_FORCPU); 779 780 #define Sync_IO_Buffer(dma_handle, length) \ 781 (void) ddi_dma_sync(dma_handle, \ 782 0, length, DDI_DMA_SYNC_FORCPU); 783 784 /* 785 * Macros to speed handling of 32bit IDs 786 */ 787 #define OHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 788 #define OHCI_LOOKUP_ID(x) id32_lookup((x)) 789 #define OHCI_FREE_ID(x) id32_free((x)) 790 791 792 /* 793 * Miscellaneous definitions. 794 */ 795 796 /* Data toggle bits */ 797 #define DATA0 0 798 #define DATA1 1 799 800 /* sKip bit actions */ 801 #define CLEAR_sKip 0 802 #define SET_sKip 1 803 804 typedef uint_t skip_bit_t; 805 806 /* 807 * Setup Packet 808 */ 809 typedef struct setup_pkt { 810 uchar_t bmRequestType; 811 uchar_t bRequest; 812 ushort_t wValue; 813 ushort_t wIndex; 814 ushort_t wLength; 815 }setup_pkt_t; 816 817 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 818 819 #define REQUEST_TYPE_OFFSET 0 820 #define REQUEST_OFFSET 1 821 #define VALUE_OFFSET 2 822 #define INDEX_OFFSET 4 823 #define LENGTH_OFFSET 6 824 825 #define TYPE_DEV_TO_HOST 0x80000000 826 #define DEVICE 0x00000001 827 #define CONFIGURATION 0x00000002 828 829 /* 830 * The following are used in attach to indicate 831 * what has been succesfully allocated, so detach 832 * can remove them. 833 */ 834 #define OHCI_ATTACH 0x01 /* ohci driver initilization */ 835 #define OHCI_ZALLOC 0x02 /* Memory for ohci state structure */ 836 #define OHCI_INTR 0x04 /* Interrupt handler registered */ 837 #define OHCI_USBAREG 0x08 /* USBA registered */ 838 #define OHCI_RHREG 0x10 /* Root hub driver loaded */ 839 840 #define OHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 841 842 /* 843 * Debug printing 844 * Masks 845 */ 846 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 847 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 848 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 849 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 850 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 851 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 852 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 853 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 854 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ohci info */ 855 #define PRINT_MASK_ALL 0xFFFFFFFF 856 857 858 /* Polling support */ 859 int ohci_hcdi_polled_input_init( 860 usba_pipe_handle_data_t *ph, 861 uchar_t **polled_buf, 862 usb_console_info_impl_t *info); 863 int ohci_hcdi_polled_input_enter( 864 usb_console_info_impl_t *info); 865 int ohci_hcdi_polled_read( 866 usb_console_info_impl_t *info, 867 uint_t *num_characters); 868 int ohci_hcdi_polled_input_exit( 869 usb_console_info_impl_t *info); 870 int ohci_hcdi_polled_input_fini( 871 usb_console_info_impl_t *info); 872 873 /* Root hub related functions */ 874 int ohci_init_root_hub( 875 ohci_state_t *ohcip); 876 int ohci_load_root_hub_driver( 877 ohci_state_t *ohcip); 878 int ohci_unload_root_hub_driver( 879 ohci_state_t *ohcip); 880 int ohci_handle_root_hub_pipe_open( 881 usba_pipe_handle_data_t *ph, 882 usb_flags_t flags); 883 int ohci_handle_root_hub_pipe_close( 884 usba_pipe_handle_data_t *ph); 885 int ohci_handle_root_hub_pipe_reset( 886 usba_pipe_handle_data_t *ph, 887 usb_flags_t flags); 888 int ohci_handle_root_hub_request( 889 ohci_state_t *ohcip, 890 usba_pipe_handle_data_t *ph, 891 usb_ctrl_req_t *ctrl_reqp); 892 int ohci_handle_root_hub_pipe_start_intr_polling( 893 usba_pipe_handle_data_t *ph, 894 usb_intr_req_t *intr_reqp, 895 usb_flags_t flags); 896 void ohci_handle_root_hub_pipe_stop_intr_polling( 897 usba_pipe_handle_data_t *ph, 898 usb_flags_t flags); 899 void ohci_handle_root_hub_status_change(void *arg); 900 901 /* Endpoint Descriptor (ED) related functions */ 902 ohci_ed_t *ohci_alloc_hc_ed( 903 ohci_state_t *ohcip, 904 usba_pipe_handle_data_t *ph); 905 void ohci_deallocate_ed( 906 ohci_state_t *ohcip, 907 ohci_ed_t *old_ed); 908 uint32_t ohci_ed_cpu_to_iommu( 909 ohci_state_t *ohcip, 910 ohci_ed_t *addr); 911 912 /* Transfer Descriptor (TD) related functions */ 913 int ohci_start_periodic_pipe_polling( 914 ohci_state_t *ohcip, 915 usba_pipe_handle_data_t *ph, 916 usb_opaque_t periodic_in_reqp, 917 usb_flags_t flags); 918 void ohci_traverse_tds( 919 ohci_state_t *ohcip, 920 usba_pipe_handle_data_t *ph); 921 void ohci_deallocate_td( 922 ohci_state_t *ohcip, 923 ohci_td_t *old_td); 924 uint32_t ohci_td_cpu_to_iommu( 925 ohci_state_t *ohcip, 926 ohci_td_t *addr); 927 ohci_td_t *ohci_td_iommu_to_cpu( 928 ohci_state_t *ohcip, 929 uintptr_t addr); 930 931 /* Transfer Wrapper (TW) functions */ 932 void ohci_deallocate_tw_resources( 933 ohci_state_t *ohcip, 934 ohci_pipe_private_t *pp, 935 ohci_trans_wrapper_t *tw); 936 937 /* Interrupt Handling functions */ 938 void ohci_handle_frame_number_overflow( 939 ohci_state_t *ohcip); 940 941 /* Miscillaneous functions */ 942 ohci_state_t *ohci_obtain_state( 943 dev_info_t *dip); 944 int ohci_state_is_operational( 945 ohci_state_t *ohcip); 946 int ohci_do_soft_reset( 947 ohci_state_t *ohcip); 948 usb_frame_number_t ohci_get_current_frame_number( 949 ohci_state_t *ohcip); 950 void ohci_handle_outstanding_requests( 951 ohci_state_t *ohcip, 952 ohci_pipe_private_t *pp); 953 954 #ifdef __cplusplus 955 } 956 #endif 957 958 #endif /* _SYS_USB_OHCID_H */ 959