1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_OHCID_H 27 #define _SYS_USB_OHCID_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Open Host Controller Driver (OHCI) 35 * 36 * The USB Open Host Controller driver is a software driver which interfaces 37 * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 38 * The interface to USB Open Host Controller is defined by the OpenHCI Host 39 * Controller Interface. 40 * 41 * This header file describes the data structures required for the USB Open 42 * Host Controller Driver to maintain state of USB Open Host Controller, to 43 * perform different USB transfers and for the bandwidth allocations. 44 */ 45 46 #include <sys/usb/hcd/openhci/ohci.h> 47 #include <sys/usb/hcd/openhci/ohci_hub.h> 48 49 /* 50 * OpenHCI interrupt status information structure 51 * 52 * The Host Controller Driver (HCD) has to maintain two different sets of 53 * Host Controller (HC) state information that includes HC registers, the 54 * interrupt tables etc.. for the normal and polled modes. In addition, 55 * suppose if we switched to polled mode while ohci interrupt handler is 56 * executing in the normal mode then we need to save the interrupt status 57 * information that includes interrupts for which ohci interrupt handler 58 * is called and HCCA done head list in the polled mode. This infromation 59 * will be used later in normal mode to service those missed interrupts. 60 * This will avoid race conditions like missing of normal mode's ohci SOF 61 * and WriteDoneHead interrupts because of this polled switch. 62 */ 63 typedef struct ohci_save_intr_sts { 64 /* 65 * The following field has set of flags & these flags will be set 66 * in the ohci interrupt handler to indicate that currently ohci 67 * interrupt handler is in execution and also while critical code 68 * execution within the ohci interrupt handler. These flags will 69 * be verified in polled mode while saving the normal mode's ohci 70 * interrupt status information. 71 */ 72 uint_t ohci_intr_flag; /* Intr handler flags */ 73 74 /* 75 * The following fields will be used to save the interrupt status 76 * and the HCCA done head list that the ohci interrupt handler is 77 * currently handling. 78 */ 79 uint_t ohci_curr_intr_sts; /* Current interrupts */ 80 ohci_td_t *ohci_curr_done_lst; /* Current done head */ 81 82 /* 83 * The following fields will be used to save the interrupt status 84 * and the HCCA done list currently being handled by the critical 85 * section of the ohci interrupt handler.. 86 */ 87 uint_t ohci_critical_intr_sts; /* Critical interrupts */ 88 ohci_td_t *ohci_critical_done_lst; /* Critical done head */ 89 90 /* 91 * The following fields will be used to save the interrupt status 92 * and HCCA done head list by the polled code if an interrupt is 93 * pending when polled code is entered. These missed interrupts & 94 * done list will be serviced either in current normal mode ohci 95 * interrupt handler execution or during the next ohci interrupt 96 * handler execution. 97 */ 98 uint_t ohci_missed_intr_sts; /* Missed interrupts */ 99 ohci_td_t *ohci_missed_done_lst; /* Missed done head */ 100 } ohci_save_intr_sts_t; 101 102 /* 103 * These flags will be set in the the normal mode ohci interrupt handler 104 * to indicate that currently ohci interrupt handler is in execution and 105 * also while critical code execution within the ohci interrupt handler. 106 * These flags will be verified in the polled mode while saving the normal 107 * mode's ohci interrupt status infromation. 108 */ 109 #define OHCI_INTR_HANDLING 0x01 /* Handling ohci intrs */ 110 #define OHCI_INTR_CRITICAL 0x02 /* Critical intr code */ 111 112 113 /* 114 * OpenHCI Host Controller state structure 115 * 116 * The Host Controller Driver (HCD) maintains the state of Host Controller 117 * (HC). There is an ohci_state structure per instance of the OpenHCI 118 * host controller. 119 */ 120 121 typedef struct ohci_state { 122 dev_info_t *ohci_dip; /* Dip of HC */ 123 uint_t ohci_instance; 124 usba_hcdi_ops_t *ohci_hcdi_ops; /* HCDI structure */ 125 uint_t ohci_flags; /* Used for cleanup */ 126 uint16_t ohci_vendor_id; /* chip vendor */ 127 uint16_t ohci_device_id; /* chip device */ 128 uint8_t ohci_rev_id; /* chip revison */ 129 130 ohci_regs_t *ohci_regsp; /* Host ctlr regs */ 131 ddi_acc_handle_t ohci_regs_handle; /* Reg handle */ 132 133 ddi_acc_handle_t ohci_config_handle; /* Config space hndle */ 134 uint_t ohci_frame_interval; /* Frme inter reg */ 135 ddi_dma_attr_t ohci_dma_attr; /* DMA attributes */ 136 137 ddi_intr_handle_t *ohci_htable; /* intr handle */ 138 int ohci_intr_type; /* intr type used */ 139 int ohci_intr_cnt; /* # of intrs inuse */ 140 uint_t ohci_intr_pri; /* intr priority */ 141 int ohci_intr_cap; /* intr capabilities */ 142 boolean_t ohci_msi_enabled; /* default to true */ 143 kmutex_t ohci_int_mutex; /* Mutex for struct */ 144 145 /* HCCA area */ 146 ohci_hcca_t *ohci_hccap; /* Virtual HCCA ptr */ 147 ddi_dma_cookie_t ohci_hcca_cookie; /* DMA cookie */ 148 ddi_dma_handle_t ohci_hcca_dma_handle; /* DMA handle */ 149 ddi_acc_handle_t ohci_hcca_mem_handle; /* Memory handle */ 150 151 /* 152 * There are two pools of memory. One pool contains the memory for 153 * the transfer descriptors and other pool contains the memory for 154 * the endpoint descriptors. The advantage of the pools is that it's 155 * easy to go back and forth between the iommu and the cpu addresses. 156 * 157 * The pools are protected by the ohci_int_mutex because the memory 158 * in the pools may be accessed by either the host controller or the 159 * host controller driver. 160 */ 161 162 /* General transfer descriptor pool */ 163 ohci_td_t *ohci_td_pool_addr; /* Start of the pool */ 164 ddi_dma_cookie_t ohci_td_pool_cookie; /* DMA cookie */ 165 ddi_dma_handle_t ohci_td_pool_dma_handle; /* DMA hndle */ 166 ddi_acc_handle_t ohci_td_pool_mem_handle; /* Mem hndle */ 167 168 /* Endpoint descriptor pool */ 169 ohci_ed_t *ohci_ed_pool_addr; /* Start of the pool */ 170 ddi_dma_cookie_t ohci_ed_pool_cookie; /* DMA cookie */ 171 ddi_dma_handle_t ohci_ed_pool_dma_handle; /* DMA handle */ 172 ddi_acc_handle_t ohci_ed_pool_mem_handle; /* Mem handle */ 173 uint_t ohci_dma_addr_bind_flag; /* DMA flag */ 174 175 /* Condition variables */ 176 kcondvar_t ohci_SOF_cv; /* SOF variable */ 177 178 /* Semaphore to serialize opens and closes */ 179 ksema_t ohci_ocsem; 180 181 /* 182 * Bandwidth fields 183 * 184 * The ohci_bandwidth array keeps track of the allocated bandwidth 185 * for this host controller. The total bandwidth allocated for least 186 * allocated list out of the 32 periodic lists is represented by the 187 * ohci_periodic_minimum_bandwidth field. 188 */ 189 uint_t ohci_periodic_minimum_bandwidth; 190 uint_t ohci_periodic_bandwidth[NUM_INTR_ED_LISTS]; 191 192 /* Different transfer open pipe counts */ 193 uint_t ohci_open_pipe_count; 194 uint_t ohci_open_ctrl_pipe_count; 195 uint_t ohci_open_bulk_pipe_count; 196 uint_t ohci_open_periodic_pipe_count; 197 uint_t ohci_open_isoch_pipe_count; 198 /* 199 * Endpoint Reclamation List 200 * 201 * The interrupt or isochronous list processing cannot be stopped 202 * when a periodic endpoint is removed from the list. The endpoints 203 * are detached from the interrupt lattice tree and put on to the 204 * reclaimation list. On next SOF interrupt all those endpoints, 205 * which are on the reclaimation list will be deallocated. 206 */ 207 ohci_ed_t *ohci_reclaim_list; /* Reclaimation list */ 208 209 ohci_root_hub_t ohci_root_hub; /* Root hub info */ 210 211 /* 212 * Global transfer timeout handling & this transfer timeout handling 213 * will be per USB Host Controller. 214 */ 215 struct ohci_trans_wrapper *ohci_timeout_list; /* Timeout List */ 216 timeout_id_t ohci_timer_id; /* Timer id */ 217 218 /* Frame number overflow information */ 219 usb_frame_number_t ohci_fno; 220 221 /* For Schedule Overrun error counter */ 222 uint_t ohci_so_error; 223 224 /* For host controller error counter */ 225 uint_t ohci_hc_error; 226 227 /* For SOF interrupt event */ 228 boolean_t ohci_sof_flag; 229 230 /* Openhci Host Controller Software State information */ 231 uint_t ohci_hc_soft_state; 232 233 /* 234 * ohci_save_intr_stats is used to save the normal mode interrupt 235 * status information while executing interrupt handler & also by 236 * the polled code if an interrupt is pending for the normal mode 237 * when polled code is entered. 238 */ 239 ohci_save_intr_sts_t ohci_save_intr_sts; 240 241 /* 242 * Saved copy of the ohci registers of the normal mode & change 243 * required ohci registers values for the polled mode operation. 244 * Before returning from the polled mode to normal mode replace 245 * the required current registers with this saved ohci registers 246 * copy. 247 */ 248 ohci_regs_t ohci_polled_save_regs; 249 250 /* 251 * Saved copy of the interrupt table used in normal ohci mode and 252 * replace this table by another interrupt table that used in the 253 * POLLED mode. 254 */ 255 ohci_ed_t *ohci_polled_save_IntTble[NUM_INTR_ED_LISTS]; 256 257 /* ohci polled mode enter counter for the input devices */ 258 uint_t ohci_polled_enter_count; 259 260 /* 261 * Counter for polled mode and used in suspend mode to see if 262 * there is a input device connected. 263 */ 264 uint_t ohci_polled_kbd_count; 265 266 /* Done list for the Polled mode */ 267 ohci_td_t *ohci_polled_done_list; 268 269 /* Log handle for debug, console, log messages */ 270 usb_log_handle_t ohci_log_hdl; 271 272 /* Kstat structures */ 273 kstat_t *ohci_intrs_stats; 274 kstat_t *ohci_total_stats; 275 kstat_t *ohci_count_stats[USB_N_COUNT_KSTATS]; 276 } ohci_state_t; 277 278 typedef struct ohci_intrs_stats { 279 struct kstat_named ohci_hcr_intr_so; 280 struct kstat_named ohci_hcr_intr_wdh; 281 struct kstat_named ohci_hcr_intr_sof; 282 struct kstat_named ohci_hcr_intr_rd; 283 struct kstat_named ohci_hcr_intr_ue; 284 struct kstat_named ohci_hcr_intr_fno; 285 struct kstat_named ohci_hcr_intr_rhsc; 286 struct kstat_named ohci_hcr_intr_oc; 287 struct kstat_named ohci_hcr_intr_not_claimed; 288 struct kstat_named ohci_hcr_intr_total; 289 } ohci_intrs_stats_t; 290 291 /* 292 * ohci kstat defines 293 */ 294 #define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats) 295 #define OHCI_INTRS_STATS_DATA(ohci) \ 296 ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data) 297 298 #define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats) 299 #define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats)) 300 #define OHCI_CTRL_STATS(ohci) \ 301 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL])) 302 #define OHCI_BULK_STATS(ohci) \ 303 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK])) 304 #define OHCI_INTR_STATS(ohci) \ 305 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR])) 306 #define OHCI_ISOC_STATS(ohci) \ 307 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH])) 308 309 /* warlock directives, stable data */ 310 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t)) 311 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri)) 312 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip)) 313 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp)) 314 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance)) 315 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id)) 316 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id)) 317 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id)) 318 319 /* this may not be stable data in the future */ 320 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr)) 321 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle)) 322 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr)) 323 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle)) 324 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie)) 325 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie)) 326 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle)) 327 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap)) 328 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag)) 329 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl)) 330 331 _NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \ 332 usba_pipe_handle_data::p_mutex \ 333 usba_device::usb_mutex \ 334 usba_ph_impl::usba_ph_mutex)) 335 336 /* 337 * Host Contoller Software States 338 * 339 * OHCI_CTLR_INIT_STATE: 340 * The host controller soft state will be set to this during the 341 * ohci_attach. 342 * 343 * OHCI_CTLR_SUSPEND_STATE: 344 * The host controller soft state will be set to this during the 345 * ohci_cpr_suspend. 346 * 347 * OHCI_CTLR_OPERATIONAL_STATE: 348 * The host controller soft state will be set to this after moving 349 * host controller to operational state and host controller start 350 * generating SOF successfully. 351 * 352 * OHCI_CTLR_ERROR_STATE: 353 * The host controller soft state will be set to this during the 354 * no SOF or UE error conditions. 355 * 356 * Under this state or condition, only pipe stop polling, pipe reset 357 * and pipe close are allowed. But all other entry points like pipe 358 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 359 * isoch send/receive, start polling etc. will fail. 360 * 361 * State Diagram for the host controller software state 362 * 363 * 364 * ohci_attach->[INIT_STATE] 365 * | 366 * | -------->----[ERROR_STATE]--<-----------<--- 367 * | | Failure (UE/no SOF condition) | 368 * | ^ ^ 369 * V | Success | 370 * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling 371 * ^ | 372 * | | 373 * | V 374 * -<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend 375 */ 376 #define OHCI_CTLR_INIT_STATE 0 /* Initilization state */ 377 #define OHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 378 #define OHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 379 #define OHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 380 381 /* 382 * Define all ohci's Vendor-id and Device-id Here 383 */ 384 #define RIO_VENDOR 0x108e 385 #define RIO_DEVICE 0x1103 386 #define OHCI_IS_RIO(ohcip) (ohcip->ohci_vendor_id == RIO_VENDOR) 387 388 /* 389 * Periodic and non-periodic macros 390 */ 391 #define OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 392 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 393 ((endpoint->bmAttributes &\ 394 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 395 396 #define OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 397 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 398 ((endpoint->bmAttributes &\ 399 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 400 401 /* 402 * OHCI ED and TD Pool sizes. 403 */ 404 #define OHCI_ED_POOL_SIZE 100 405 #define OHCI_TD_POOL_SIZE 200 406 407 /* 408 * ohci_dma_addr_bind_flag values 409 * 410 * This flag indicates if the various DMA addresses allocated by the OHCI 411 * have been bound to their respective handles. This is needed to recover 412 * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle() 413 */ 414 #define OHCI_TD_POOL_BOUND 0x01 /* For TD pools */ 415 #define OHCI_ED_POOL_BOUND 0x02 /* For ED pools */ 416 #define OHCI_HCCA_DMA_BOUND 0x04 /* For HCCA area */ 417 418 /* 419 * Maximum SOF wait count 420 */ 421 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 422 423 424 /* 425 * Pipe private structure 426 * 427 * There is an instance of this structure per pipe. This structure holds 428 * HCD specific pipe information. A pointer to this structure is kept in 429 * the USBA pipe handle (usba_pipe_handle_data_t). 430 */ 431 typedef struct ohci_pipe_private { 432 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 433 ohci_ed_t *pp_ept; /* Pipe's ept */ 434 435 /* State of the pipe */ 436 uint_t pp_state; /* See below */ 437 438 /* Local copy of the pipe policy */ 439 usb_pipe_policy_t pp_policy; 440 441 /* For Periodic Pipes Only */ 442 uint_t pp_node; /* Node in lattice */ 443 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 444 uint_t pp_max_periodic_req_cnt; /* Max req count */ 445 446 /* For isochronous pipe only */ 447 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 448 449 /* 450 * Each pipe may have multiple transfer wrappers. Each transfer 451 * wrapper represents a USB transfer on the bus. A transfer is 452 * made up of one or more transactions. 453 */ 454 struct ohci_trans_wrapper *pp_tw_head; /* Head of the list */ 455 struct ohci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 456 457 /* Done td count */ 458 uint_t pp_count_done_tds; /* Done td count */ 459 460 /* Errors */ 461 usb_cr_t pp_error; /* Pipe error */ 462 463 /* Flags */ 464 uint_t pp_flag; /* Flags */ 465 466 /* Condition variable for transfers completion event */ 467 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 468 469 /* 470 * HCD gets Interrupt/Isochronous IN polling request only once and 471 * it has to insert next polling requests after completion of first 472 * request until either stop polling/pipe close is called. So HCD 473 * has to take copy of the original Interrupt/Isochronous IN request. 474 */ 475 usb_opaque_t pp_client_periodic_in_reqp; 476 } ohci_pipe_private_t; 477 478 /* warlock directives, stable data */ 479 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t)) 480 481 /* 482 * Pipe states 483 * 484 * ohci pipe states will be similar to usba. Refer usbai.h. 485 */ 486 #define OHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 487 #define OHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 488 #define OHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 489 490 /* Additional ohci pipe states for the ohci_pipe_cleanup */ 491 #define OHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 492 #define OHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 493 #define OHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 494 495 /* 496 * Pipe specific Flags 497 */ 498 #define OHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 499 500 /* 501 * The maximum allowable usb isochronous data transfer size or maximum 502 * number of isochronous data packets. 503 * 504 * Each usb isochronous request must not exceed multiples of isochronous 505 * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER. 506 * 507 * Ex: usb isochronous endpoint maximum packet size is 64 bytes 508 * maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER 509 * * 64 bytes 510 */ 511 #define OHCI_MAX_ISOC_PKTS_PER_XFER 256 /* Max pkts per req */ 512 513 /* 514 * The ohci supports maximum of eight isochronous data packets per transfer 515 * descriptor. 516 */ 517 #define OHCI_ISOC_PKTS_PER_TD 8 /* Packets per TD */ 518 519 /* 520 * USB frame offset 521 * 522 * Add appropriate frame offset to the current usb frame number and use it 523 * as a starting frame number for a given usb isochronous request. 524 */ 525 #define OHCI_FRAME_OFFSET 2 /* Frame offset */ 526 527 /* 528 * Default usb isochronous receive packets per request before ohci will do 529 * callback. 530 */ 531 #define OHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 532 533 /* 534 * Different interrupt polling intervals supported 535 */ 536 #define INTR_1MS_POLL 1 537 #define INTR_2MS_POLL 2 538 #define INTR_4MS_POLL 4 539 #define INTR_8MS_POLL 8 540 #define INTR_16MS_POLL 16 541 #define INTR_32MS_POLL 32 542 543 /* 544 * Number of interrupt/isochronous transfer requests that should 545 * be maintained on the interrupt/isochronous endpoint corresponding 546 * to different polling intervals supported. 547 */ 548 #define INTR_1MS_REQS 4 /* 1ms polling interval */ 549 #define INTR_2MS_REQS 2 /* 2ms polling interval */ 550 #define INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 551 552 /* Function prototype */ 553 typedef void (*ohci_handler_function_t)( 554 ohci_state_t *ohcip, 555 ohci_pipe_private_t *pp, 556 struct ohci_trans_wrapper *tw, 557 ohci_td_t *td, 558 void *ohci_handle_callback_value); 559 560 561 /* 562 * Transfer wrapper 563 * 564 * The transfer wrapper represents a USB transfer on the bus and there 565 * is one instance per USB transfer. A transfer is made up of one or 566 * more transactions. OHCI uses one TD for one transaction. So one 567 * transfer wrapper may have one or more TDs associated. 568 * 569 * Control and bulk pipes will have one transfer wrapper per transfer 570 * and where as Isochronous and Interrupt pipes will only have one 571 * transfer wrapper. The transfers wrapper are continually reused for 572 * the Interrupt and Isochronous pipes as those pipes are polled. 573 * 574 * Control, bulk and interrupt transfers will have one DMA buffer per 575 * transfer. The data to be transferred are contained in the DMA buffer 576 * which is virtually contiguous but physically discontiguous. When 577 * preparing the TDs for a USB transfer, the DMA cookies contained in 578 * the buffer need to be walked through to retrieve the DMA addresses. 579 * 580 * Isochronous transfers may have multiple DMA buffers per transfer 581 * with each isoc TD having a DMA buffer. And one isoc TD may hold up to 582 * eight isoc packets, but two cookies at most. 583 */ 584 typedef struct ohci_trans_wrapper { 585 struct ohci_trans_wrapper *tw_next; /* Next wrapper */ 586 ohci_pipe_private_t *tw_pipe_private; /* Back ptr */ 587 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 588 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 589 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 590 uint32_t tw_id; /* 32bit ID */ 591 size_t tw_length; /* Txfer length */ 592 char *tw_buf; /* Buffer for Xfer */ 593 uint_t tw_ncookies; /* DMA cookie count */ 594 uint_t tw_cookie_idx; /* DMA cookie index */ 595 size_t tw_dma_offs; /* DMA buffer offset */ 596 usb_flags_t tw_flags; /* Flags */ 597 uint_t tw_num_tds; /* Number of TDs */ 598 ohci_td_t *tw_hctd_head; /* Head TD */ 599 ohci_td_t *tw_hctd_tail; /* Tail TD */ 600 uint_t tw_direction; /* Direction of TD */ 601 uint_t tw_pkt_idx; /* packet index */ 602 603 /* We preallocate all the td's for each tw and place them here */ 604 ohci_td_t *tw_hctd_free_list; 605 606 /* Current transfer request pointer */ 607 usb_opaque_t tw_curr_xfer_reqp; 608 609 /* Current isochronous packet descriptor pointer */ 610 usb_isoc_pkt_descr_t *tw_curr_isoc_pktp; 611 612 /* Isochronous DMA handlers and buffer pointers are stored here */ 613 ohci_isoc_buf_t *tw_isoc_bufs; 614 size_t tw_isoc_strtlen; 615 616 /* Transfer timeout information */ 617 uint_t tw_timeout; /* Timeout value */ 618 struct ohci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 619 620 /* 621 * This is the function to call when this td is done. This way 622 * we don't have to look in the td to figure out what kind it is. 623 */ 624 ohci_handler_function_t tw_handle_td; 625 626 /* 627 * This is the callback value used when processing a done td. 628 */ 629 usb_opaque_t tw_handle_callback_value; 630 } ohci_trans_wrapper_t; 631 632 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper)) 633 634 635 /* 636 * Time waits for the different OHCI specific operations. 637 * These timeout values are specified in terms of microseconds. 638 */ 639 #define OHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 640 #define OHCI_RESUME_TIMEWAIT 40000 /* HC resume waiting time */ 641 #define OHCI_TIMEWAIT 10000 /* HC any other waiting time */ 642 643 /* These timeout values are specified in seconds */ 644 #define OHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 645 #define OHCI_MAX_SOF_TIMEWAIT 3 /* Maximum SOF waiting time */ 646 #define OHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 647 648 /* OHCI flags for general use */ 649 #define OHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 650 #define OHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 651 #define OHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 652 653 /* 654 * Maximum allowable data transfer size per transaction as supported 655 * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a) 656 */ 657 #define OHCI_MAX_TD_XFER_SIZE 0x2000 /* Maxmum data per transaction */ 658 659 /* 660 * One OHCI TD allows two physically discontiguous pages. The page size 661 * is 4k. 662 */ 663 #define OHCI_MAX_TD_BUF_SIZE 0x1000 664 665 /* 666 * The maximum allowable bulk data transfer size. It can be different 667 * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will 668 * take care of breaking a bulk data request into multiples of ohci 669 * OHCI_MAX_TD_XFER_SIZE until request is satisfied. Currently this 670 * value is set to 256k bytes. 671 */ 672 #define OHCI_MAX_BULK_XFER_SIZE 0x40000 /* Maximum bulk transfer size */ 673 674 /* 675 * Timeout flags 676 * 677 * These flags will be used to stop the timer before timeout handler 678 * gets executed. 679 */ 680 #define OHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last TD */ 681 #define OHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 682 683 684 /* 685 * Bandwidth allocation 686 * 687 * The following definitions are used during bandwidth calculations 688 * for a given endpoint maximum packet size. 689 */ 690 #define MAX_USB_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 691 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 692 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 693 #define SOF 6 /* Length in bytes of SOF */ 694 #define EOF 4 /* Length in bytes of EOF */ 695 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 696 697 /* 698 * Minimum polling interval for low speed endpoint 699 * 700 * According USB Specifications, a full-speed endpoint can specify 701 * a desired polling interval 1ms to 255ms and a low speed endpoints 702 * are limited to specifying only 10ms to 255ms. But some old keyboards 703 * and mice uses polling interval of 8ms. For compatibility purpose, 704 * we are using polling interval between 8ms and 255ms for low speed 705 * endpoints. But ohci driver will reject any low speed endpoints which 706 * request polling interval less than 8ms. 707 */ 708 #define MIN_LOW_SPEED_POLL_INTERVAL 8 709 710 /* 711 * For non-periodic transfers, reserve atleast for one low-speed device 712 * transaction. According to USB Bandwidth Analysis white paper and also 713 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 714 * transaction takes 0x628h full speed bits (197 bytes), which comes to 715 * around 13% of USB frame time. 716 * 717 * The periodic transfers will get around 87% of USB frame time. 718 */ 719 #define MAX_NON_PERIODIC_BANDWIDTH 197 720 #define MAX_PERIODIC_BANDWIDTH (MAX_USB_BUS_BANDWIDTH - SOF - \ 721 EOF - MAX_NON_PERIODIC_BANDWIDTH) 722 723 /* 724 * The USB periodic transfers like interrupt and isochronous transfers 725 * after completion of SOF and USB non-periodic transfers. 726 */ 727 #define PERIODIC_XFER_STARTS (MAX_USB_BUS_BANDWIDTH - \ 728 SOF - MAX_NON_PERIODIC_BANDWIDTH) 729 730 /* Number of Bits Per Byte */ 731 #define BITS_PER_BYTE 8 732 733 /* 734 * The following are the protocol overheads in terms of Bytes for the 735 * different transfer types. All these protocol overhead values are 736 * derived from the 5.9.3 section of USB Specification and with the 737 * help of Bandwidth Analysis white paper which is posted on the USB 738 * developer forum. 739 */ 740 #define FS_NON_ISOC_PROTO_OVERHEAD 14 741 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 742 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 743 #define LOW_SPEED_PROTO_OVERHEAD 97 744 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 745 746 /* 747 * The Host Controller (HC) delays are the USB host controller specific 748 * delays. The value shown below is the host controller delay for the 749 * RIO USB host controller. This value was calculated and given by the 750 * Sun USB hardware people. 751 */ 752 #define HOST_CONTROLLER_DELAY 18 753 754 /* 755 * The low speed clock below represents that to transmit one low-speed 756 * bit takes eight times more than one full speed bit time. 757 */ 758 #define LOW_SPEED_CLOCK 8 759 760 761 /* 762 * Macros for setting/getting information 763 */ 764 #define Get_ED(addr) ddi_get32(ohcip->ohci_ed_pool_mem_handle, \ 765 (uint32_t *)&addr) 766 767 #define Set_ED(addr, val) ddi_put32(ohcip->ohci_ed_pool_mem_handle, \ 768 ((uint32_t *)&addr), \ 769 ((int32_t)(val))) 770 771 #define Get_TD(addr) ddi_get32(ohcip->ohci_td_pool_mem_handle, \ 772 (uint32_t *)&addr) 773 774 #define Set_TD(addr, val) ddi_put32(ohcip->ohci_td_pool_mem_handle, \ 775 ((uint32_t *)&addr), \ 776 ((uint32_t)(uintptr_t)(val))) 777 778 #define Get_HCCA(addr) ddi_get32(ohcip->ohci_hcca_mem_handle, \ 779 (uint32_t *)&addr) 780 781 #define Set_HCCA(addr, val) ddi_put32(ohcip->ohci_hcca_mem_handle, \ 782 ((uint32_t *)&addr), \ 783 ((int32_t)(val))) 784 785 #define Get_OpReg(addr) ddi_get32(ohcip->ohci_regs_handle, \ 786 (uint32_t *)&ohcip->ohci_regsp->addr) 787 788 #define Set_OpReg(addr, val) ddi_put32(ohcip->ohci_regs_handle, \ 789 ((uint32_t *)&ohcip->ohci_regsp->addr), \ 790 ((int32_t)(val))) 791 792 #define Sync_HCCA(ohcip) (void) ddi_dma_sync( \ 793 ohcip->ohci_hcca_dma_handle, \ 794 0, sizeof (ohci_hcca_t), \ 795 DDI_DMA_SYNC_FORCPU); 796 797 #define Sync_ED_TD_Pool(ohcip) (void) ddi_dma_sync( \ 798 ohcip->ohci_ed_pool_dma_handle, \ 799 0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \ 800 DDI_DMA_SYNC_FORCPU); \ 801 (void) ddi_dma_sync( \ 802 ohcip->ohci_td_pool_dma_handle, \ 803 0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \ 804 DDI_DMA_SYNC_FORCPU); 805 806 #define Sync_IO_Buffer(dma_handle, length) \ 807 (void) ddi_dma_sync(dma_handle, \ 808 0, length, DDI_DMA_SYNC_FORCPU); 809 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 810 (void) ddi_dma_sync(dma_handle, \ 811 0, length, DDI_DMA_SYNC_FORDEV); 812 813 /* 814 * Macros to speed handling of 32bit IDs 815 */ 816 #define OHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 817 #define OHCI_LOOKUP_ID(x) id32_lookup((x)) 818 #define OHCI_FREE_ID(x) id32_free((x)) 819 820 821 /* 822 * Miscellaneous definitions. 823 */ 824 825 /* Data toggle bits */ 826 #define DATA0 0 827 #define DATA1 1 828 829 /* sKip bit actions */ 830 #define CLEAR_sKip 0 831 #define SET_sKip 1 832 833 typedef uint_t skip_bit_t; 834 835 /* 836 * Setup Packet 837 */ 838 typedef struct setup_pkt { 839 uchar_t bmRequestType; 840 uchar_t bRequest; 841 ushort_t wValue; 842 ushort_t wIndex; 843 ushort_t wLength; 844 }setup_pkt_t; 845 846 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 847 848 #define REQUEST_TYPE_OFFSET 0 849 #define REQUEST_OFFSET 1 850 #define VALUE_OFFSET 2 851 #define INDEX_OFFSET 4 852 #define LENGTH_OFFSET 6 853 854 #define TYPE_DEV_TO_HOST 0x80000000 855 #define DEVICE 0x00000001 856 #define CONFIGURATION 0x00000002 857 858 /* 859 * The following are used in attach to indicate 860 * what has been succesfully allocated, so detach 861 * can remove them. 862 */ 863 #define OHCI_ATTACH 0x01 /* ohci driver initilization */ 864 #define OHCI_ZALLOC 0x02 /* Memory for ohci state structure */ 865 #define OHCI_INTR 0x04 /* Interrupt handler registered */ 866 #define OHCI_USBAREG 0x08 /* USBA registered */ 867 #define OHCI_RHREG 0x10 /* Root hub driver loaded */ 868 869 #define OHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 870 871 /* 872 * Debug printing 873 * Masks 874 */ 875 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 876 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 877 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 878 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 879 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 880 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 881 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 882 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 883 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ohci info */ 884 #define PRINT_MASK_ALL 0xFFFFFFFF 885 886 887 /* Polling support */ 888 int ohci_hcdi_polled_input_init( 889 usba_pipe_handle_data_t *ph, 890 uchar_t **polled_buf, 891 usb_console_info_impl_t *info); 892 int ohci_hcdi_polled_input_enter( 893 usb_console_info_impl_t *info); 894 int ohci_hcdi_polled_read( 895 usb_console_info_impl_t *info, 896 uint_t *num_characters); 897 int ohci_hcdi_polled_input_exit( 898 usb_console_info_impl_t *info); 899 int ohci_hcdi_polled_input_fini( 900 usb_console_info_impl_t *info); 901 902 int ohci_hcdi_polled_output_init( 903 usba_pipe_handle_data_t *ph, 904 usb_console_info_impl_t *console_output_info); 905 int ohci_hcdi_polled_output_enter( 906 usb_console_info_impl_t *info); 907 int ohci_hcdi_polled_write( 908 usb_console_info_impl_t *info, 909 uchar_t *buf, 910 uint_t num_characters, 911 uint_t *num_characters_written); 912 int ohci_hcdi_polled_output_exit( 913 usb_console_info_impl_t *info); 914 int ohci_hcdi_polled_output_fini( 915 usb_console_info_impl_t *info); 916 917 /* Root hub related functions */ 918 int ohci_init_root_hub( 919 ohci_state_t *ohcip); 920 int ohci_load_root_hub_driver( 921 ohci_state_t *ohcip); 922 int ohci_unload_root_hub_driver( 923 ohci_state_t *ohcip); 924 int ohci_handle_root_hub_pipe_open( 925 usba_pipe_handle_data_t *ph, 926 usb_flags_t flags); 927 int ohci_handle_root_hub_pipe_close( 928 usba_pipe_handle_data_t *ph); 929 int ohci_handle_root_hub_pipe_reset( 930 usba_pipe_handle_data_t *ph, 931 usb_flags_t flags); 932 int ohci_handle_root_hub_request( 933 ohci_state_t *ohcip, 934 usba_pipe_handle_data_t *ph, 935 usb_ctrl_req_t *ctrl_reqp); 936 int ohci_handle_root_hub_pipe_start_intr_polling( 937 usba_pipe_handle_data_t *ph, 938 usb_intr_req_t *intr_reqp, 939 usb_flags_t flags); 940 void ohci_handle_root_hub_pipe_stop_intr_polling( 941 usba_pipe_handle_data_t *ph, 942 usb_flags_t flags); 943 void ohci_handle_root_hub_status_change(void *arg); 944 945 /* Endpoint Descriptor (ED) related functions */ 946 ohci_ed_t *ohci_alloc_hc_ed( 947 ohci_state_t *ohcip, 948 usba_pipe_handle_data_t *ph); 949 void ohci_deallocate_ed( 950 ohci_state_t *ohcip, 951 ohci_ed_t *old_ed); 952 uint32_t ohci_ed_cpu_to_iommu( 953 ohci_state_t *ohcip, 954 ohci_ed_t *addr); 955 956 /* Transfer Descriptor (TD) related functions */ 957 int ohci_start_periodic_pipe_polling( 958 ohci_state_t *ohcip, 959 usba_pipe_handle_data_t *ph, 960 usb_opaque_t periodic_in_reqp, 961 usb_flags_t flags); 962 void ohci_traverse_tds( 963 ohci_state_t *ohcip, 964 usba_pipe_handle_data_t *ph); 965 void ohci_deallocate_td( 966 ohci_state_t *ohcip, 967 ohci_td_t *old_td); 968 uint32_t ohci_td_cpu_to_iommu( 969 ohci_state_t *ohcip, 970 ohci_td_t *addr); 971 ohci_td_t *ohci_td_iommu_to_cpu( 972 ohci_state_t *ohcip, 973 uintptr_t addr); 974 size_t ohci_get_td_residue( 975 ohci_state_t *ohcip, 976 ohci_td_t *td); 977 void ohci_init_td( 978 ohci_state_t *ohcip, 979 ohci_trans_wrapper_t *tw, 980 uint32_t hctd_dma_offs, 981 size_t hctd_length, 982 ohci_td_t *td); 983 984 /* Transfer Wrapper (TW) functions */ 985 void ohci_deallocate_tw_resources( 986 ohci_state_t *ohcip, 987 ohci_pipe_private_t *pp, 988 ohci_trans_wrapper_t *tw); 989 990 /* Interrupt Handling functions */ 991 void ohci_handle_frame_number_overflow( 992 ohci_state_t *ohcip); 993 994 /* Miscillaneous functions */ 995 ohci_state_t *ohci_obtain_state( 996 dev_info_t *dip); 997 int ohci_state_is_operational( 998 ohci_state_t *ohcip); 999 int ohci_do_soft_reset( 1000 ohci_state_t *ohcip); 1001 usb_frame_number_t ohci_get_current_frame_number( 1002 ohci_state_t *ohcip); 1003 void ohci_handle_outstanding_requests( 1004 ohci_state_t *ohcip, 1005 ohci_pipe_private_t *pp); 1006 int ohci_allocate_tds_for_tw( 1007 ohci_state_t *ohcip, 1008 ohci_trans_wrapper_t *tw, 1009 size_t td_count); 1010 1011 #ifdef __cplusplus 1012 } 1013 #endif 1014 1015 #endif /* _SYS_USB_OHCID_H */ 1016