1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_OHCI_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_USB_OHCI_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 33*7c478bd9Sstevel@tonic-gate extern "C" { 34*7c478bd9Sstevel@tonic-gate #endif 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate /* 37*7c478bd9Sstevel@tonic-gate * Open Host Controller Driver (OHCI) 38*7c478bd9Sstevel@tonic-gate * 39*7c478bd9Sstevel@tonic-gate * The USB Open Host Controller driver is a software driver which interfaces 40*7c478bd9Sstevel@tonic-gate * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 41*7c478bd9Sstevel@tonic-gate * The interface to USB Open Host Controller is defined by the OpenHCI Host 42*7c478bd9Sstevel@tonic-gate * Controller Interface. 43*7c478bd9Sstevel@tonic-gate * 44*7c478bd9Sstevel@tonic-gate * This header file describes the registers and data structures shared by the 45*7c478bd9Sstevel@tonic-gate * USB Open Host Controller and the USB Open Host Controller Driver. 46*7c478bd9Sstevel@tonic-gate */ 47*7c478bd9Sstevel@tonic-gate 48*7c478bd9Sstevel@tonic-gate #include <sys/types.h> 49*7c478bd9Sstevel@tonic-gate #include <sys/pci.h> 50*7c478bd9Sstevel@tonic-gate #include <sys/kstat.h> 51*7c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 52*7c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 53*7c478bd9Sstevel@tonic-gate #include <sys/ndi_impldefs.h> 54*7c478bd9Sstevel@tonic-gate 55*7c478bd9Sstevel@tonic-gate #include <sys/usb/usba.h> 56*7c478bd9Sstevel@tonic-gate 57*7c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hcdi.h> 58*7c478bd9Sstevel@tonic-gate 59*7c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hub.h> 60*7c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hubdi.h> 61*7c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hubdvar.h> 62*7c478bd9Sstevel@tonic-gate 63*7c478bd9Sstevel@tonic-gate #include <sys/id32.h> 64*7c478bd9Sstevel@tonic-gate 65*7c478bd9Sstevel@tonic-gate #define OHCI_MAX_RH_PORTS 15 /* Maximum root hub ports */ 66*7c478bd9Sstevel@tonic-gate 67*7c478bd9Sstevel@tonic-gate /* 68*7c478bd9Sstevel@tonic-gate * Each OHCI buffer can hold upto 8k bytes of data. Hence there is a 69*7c478bd9Sstevel@tonic-gate * restriction of 4k alignment while allocating a dma buffer. 70*7c478bd9Sstevel@tonic-gate */ 71*7c478bd9Sstevel@tonic-gate #define OHCI_4K_ALIGN 0x1000 72*7c478bd9Sstevel@tonic-gate 73*7c478bd9Sstevel@tonic-gate /* 74*7c478bd9Sstevel@tonic-gate * USB Host controller DMA scatter gather list defines for 75*7c478bd9Sstevel@tonic-gate * Sparc and non-sparc architectures. 76*7c478bd9Sstevel@tonic-gate */ 77*7c478bd9Sstevel@tonic-gate #if defined(__sparc) 78*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_MAX_XFER 0xffffffffull 79*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_COUNT_MAX 0xffffffffull 80*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_GRANULAR 512 81*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_ALIGNMENT OHCI_4K_ALIGN 82*7c478bd9Sstevel@tonic-gate #else 83*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_MAX_XFER 0x00ffffffull 84*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_COUNT_MAX 0x00ffffffull 85*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_GRANULAR 1 86*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_ALIGNMENT 1 87*7c478bd9Sstevel@tonic-gate #endif 88*7c478bd9Sstevel@tonic-gate 89*7c478bd9Sstevel@tonic-gate /* 90*7c478bd9Sstevel@tonic-gate * According to the OHCI spec ED and TD need to be 16 byte aligned. 91*7c478bd9Sstevel@tonic-gate * However, iTD needs to be 32 byte aligned. Since we do not 92*7c478bd9Sstevel@tonic-gate * distinguish between iTD and TD, make them both 32 byte aligned. 93*7c478bd9Sstevel@tonic-gate * 94*7c478bd9Sstevel@tonic-gate * ED = 16 byte aligned 95*7c478bd9Sstevel@tonic-gate * TD = 32 byte aligned 96*7c478bd9Sstevel@tonic-gate * HCCA = 256 byte aligned 97*7c478bd9Sstevel@tonic-gate */ 98*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_ED_ALIGNMENT 0x010 99*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_TD_ALIGNMENT 0x020 100*7c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_HCCA_ALIGNMENT 0x100 101*7c478bd9Sstevel@tonic-gate 102*7c478bd9Sstevel@tonic-gate /* 103*7c478bd9Sstevel@tonic-gate * OpenHCI Operational Registers 104*7c478bd9Sstevel@tonic-gate * 105*7c478bd9Sstevel@tonic-gate * The Host Controller (HC) contains a set of on-chip operational registers 106*7c478bd9Sstevel@tonic-gate * which are mapped into a noncacheable portion of the system addressable 107*7c478bd9Sstevel@tonic-gate * space and these registers are also used by the Host Controller Driver 108*7c478bd9Sstevel@tonic-gate * (HCD). 109*7c478bd9Sstevel@tonic-gate */ 110*7c478bd9Sstevel@tonic-gate typedef volatile struct ohci_regs { 111*7c478bd9Sstevel@tonic-gate /* Control and status registers */ 112*7c478bd9Sstevel@tonic-gate uint32_t hcr_revision; /* Specification version */ 113*7c478bd9Sstevel@tonic-gate uint32_t hcr_control; /* Control information */ 114*7c478bd9Sstevel@tonic-gate uint32_t hcr_cmd_status; /* Controller status */ 115*7c478bd9Sstevel@tonic-gate uint32_t hcr_intr_status; /* Interrupt status register */ 116*7c478bd9Sstevel@tonic-gate uint32_t hcr_intr_enable; /* Interrupt enable */ 117*7c478bd9Sstevel@tonic-gate uint32_t hcr_intr_disable; /* Interrupt disable */ 118*7c478bd9Sstevel@tonic-gate 119*7c478bd9Sstevel@tonic-gate /* Memory pointer registers */ 120*7c478bd9Sstevel@tonic-gate uint32_t hcr_HCCA; /* Pointer to HCCA */ 121*7c478bd9Sstevel@tonic-gate uint32_t hcr_periodic_curr; /* Curr. isoch or int endpt */ 122*7c478bd9Sstevel@tonic-gate uint32_t hcr_ctrl_head; /* Head of contrl list */ 123*7c478bd9Sstevel@tonic-gate uint32_t hcr_ctrl_curr; /* Curr. control endpt */ 124*7c478bd9Sstevel@tonic-gate uint32_t hcr_bulk_head; /* Head of the bulk list */ 125*7c478bd9Sstevel@tonic-gate uint32_t hcr_bulk_curr; /* Curr. bulk endpt */ 126*7c478bd9Sstevel@tonic-gate uint32_t hcr_done_head; /* Head of the done list */ 127*7c478bd9Sstevel@tonic-gate 128*7c478bd9Sstevel@tonic-gate /* Frame counter registers */ 129*7c478bd9Sstevel@tonic-gate uint32_t hcr_frame_interval; /* Frame interval value */ 130*7c478bd9Sstevel@tonic-gate uint32_t hcr_frame_remaining; /* Time remaining in frame */ 131*7c478bd9Sstevel@tonic-gate uint32_t hcr_frame_number; /* Frame number */ 132*7c478bd9Sstevel@tonic-gate uint32_t hcr_periodic_strt; /* Time to start per. list */ 133*7c478bd9Sstevel@tonic-gate uint32_t hcr_transfer_ls; /* Low speed threshold */ 134*7c478bd9Sstevel@tonic-gate 135*7c478bd9Sstevel@tonic-gate /* Root hub registers */ 136*7c478bd9Sstevel@tonic-gate uint32_t hcr_rh_descriptorA; /* Root hub register A */ 137*7c478bd9Sstevel@tonic-gate uint32_t hcr_rh_descriptorB; /* Root hub register B */ 138*7c478bd9Sstevel@tonic-gate uint32_t hcr_rh_status; /* Root hub status */ 139*7c478bd9Sstevel@tonic-gate uint32_t hcr_rh_portstatus[OHCI_MAX_RH_PORTS]; /* RH port sts */ 140*7c478bd9Sstevel@tonic-gate } ohci_regs_t; 141*7c478bd9Sstevel@tonic-gate 142*7c478bd9Sstevel@tonic-gate /* hcr_revision bits */ 143*7c478bd9Sstevel@tonic-gate #define HCR_REVISION_1_0 0x00000010 /* Revision 1.0 */ 144*7c478bd9Sstevel@tonic-gate #define HCR_REVISION_MASK 0x000000FF /* Revision mask */ 145*7c478bd9Sstevel@tonic-gate 146*7c478bd9Sstevel@tonic-gate /* hcr_control bits */ 147*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_CBSR 0x00000003 /* Control/bulk ratio */ 148*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_PLE 0x00000004 /* Periodic list enable */ 149*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_IE 0x00000008 /* Isochronous enable */ 150*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_CLE 0x00000010 /* Control list enable */ 151*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_BLE 0x00000020 /* Bulk list enable */ 152*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_HCFS 0x000000C0 /* Controller state */ 153*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_IR 0x00000100 /* Interrupt routing */ 154*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RWC 0x00000200 /* Remote wakeup connected */ 155*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RWE 0x00000400 /* Remote wakeup enabled */ 156*7c478bd9Sstevel@tonic-gate 157*7c478bd9Sstevel@tonic-gate /* Values for the Host Controller Functional State bits (HCR_CONTROL_HCFS) */ 158*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RESET 0x00000000 /* USB Reset */ 159*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RESUME 0x00000040 /* USB Resume */ 160*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_OPERAT 0x00000080 /* USB Operational */ 161*7c478bd9Sstevel@tonic-gate #define HCR_CONTROL_SUSPD 0x000000C0 /* USB Suspend */ 162*7c478bd9Sstevel@tonic-gate 163*7c478bd9Sstevel@tonic-gate /* hcr_cmd_status bits */ 164*7c478bd9Sstevel@tonic-gate #define HCR_STATUS_RESET 0x00000001 /* Host controller reset */ 165*7c478bd9Sstevel@tonic-gate #define HCR_STATUS_CLF 0x00000002 /* Control list filled */ 166*7c478bd9Sstevel@tonic-gate #define HCR_STATUS_BLF 0x00000004 /* Bulk list filled */ 167*7c478bd9Sstevel@tonic-gate #define HCR_STATUS_OCR 0x00000008 /* Ownership change */ 168*7c478bd9Sstevel@tonic-gate #define HCR_STATUS_SOC 0x00030000 /* Error frame count */ 169*7c478bd9Sstevel@tonic-gate 170*7c478bd9Sstevel@tonic-gate /* hcr_intr_status bits and hcr_intr_mask bits */ 171*7c478bd9Sstevel@tonic-gate #define HCR_INTR_SO 0x00000001 /* Schedule overrun */ 172*7c478bd9Sstevel@tonic-gate #define HCR_INTR_WDH 0x00000002 /* Writeback done head */ 173*7c478bd9Sstevel@tonic-gate #define HCR_INTR_SOF 0x00000004 /* Start of frame */ 174*7c478bd9Sstevel@tonic-gate #define HCR_INTR_RD 0x00000008 /* Resume detected */ 175*7c478bd9Sstevel@tonic-gate #define HCR_INTR_UE 0x00000010 /* Unrecoverable error */ 176*7c478bd9Sstevel@tonic-gate #define HCR_INTR_FNO 0x00000020 /* Frame no. overflow */ 177*7c478bd9Sstevel@tonic-gate #define HCR_INTR_RHSC 0x00000040 /* Root hub status change */ 178*7c478bd9Sstevel@tonic-gate #define HCR_INTR_OC 0x40000000 /* Change in ownership */ 179*7c478bd9Sstevel@tonic-gate #define HCR_INTR_MIE 0x80000000 /* Master interrupt enable */ 180*7c478bd9Sstevel@tonic-gate 181*7c478bd9Sstevel@tonic-gate /* hcr_frame_interval bits */ 182*7c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FI 0x00003FFF /* Frame interval */ 183*7c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FSMPS 0x7FFF0000 /* Biggest packet */ 184*7c478bd9Sstevel@tonic-gate #define HCR_FRME_FSMPS_SHFT 16 /* FSMPS */ 185*7c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FIT 0x80000000 /* Frame interval toggle */ 186*7c478bd9Sstevel@tonic-gate #define MAX_OVERHEAD 210 /* Max. bit overhead */ 187*7c478bd9Sstevel@tonic-gate 188*7c478bd9Sstevel@tonic-gate /* hcr_frame_remaining bits */ 189*7c478bd9Sstevel@tonic-gate #define HCR_FRME_REM_FR 0x00003FFF /* Frame remaining */ 190*7c478bd9Sstevel@tonic-gate #define HCR_FRME_REM_FRT 0x80000000 /* Frame remaining toggle */ 191*7c478bd9Sstevel@tonic-gate 192*7c478bd9Sstevel@tonic-gate /* hcr_transfer_ls */ 193*7c478bd9Sstevel@tonic-gate #define HCR_TRANS_LST 0x000007FF /* Low Speed threshold */ 194*7c478bd9Sstevel@tonic-gate 195*7c478bd9Sstevel@tonic-gate /* hcr_rh_descriptorA bits */ 196*7c478bd9Sstevel@tonic-gate #define HCR_RHA_NDP 0x000000FF /* No. of ports */ 197*7c478bd9Sstevel@tonic-gate #define HCR_RHA_PSM 0x00000100 /* Power switch mode */ 198*7c478bd9Sstevel@tonic-gate #define HCR_RHA_NPS 0x00000200 /* No power switching */ 199*7c478bd9Sstevel@tonic-gate #define HCR_RHA_DT 0x00000400 /* Device type */ 200*7c478bd9Sstevel@tonic-gate #define HCR_RHA_OCPM 0x00000800 /* Over-current protection */ 201*7c478bd9Sstevel@tonic-gate #define HCR_RHA_NOCP 0x00001000 /* No over-current protection */ 202*7c478bd9Sstevel@tonic-gate #define HCR_RHA_PTPGT 0xFF000000 /* Power on to power good */ 203*7c478bd9Sstevel@tonic-gate #define HCR_RHA_PTPGT_SHIFT 24 /* Shift bits for ptpgt */ 204*7c478bd9Sstevel@tonic-gate 205*7c478bd9Sstevel@tonic-gate /* hcr_rh_descriptorB bits */ 206*7c478bd9Sstevel@tonic-gate #define HCR_RHB_DR 0x0000FFFF /* Device removable */ 207*7c478bd9Sstevel@tonic-gate #define HCR_RHB_PPCM 0xFFFF0000 /* PortPowerControlMask */ 208*7c478bd9Sstevel@tonic-gate 209*7c478bd9Sstevel@tonic-gate /* hcr_rh_status bits */ 210*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_LPS 0x00000001 /* Local power status */ 211*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_OCI 0x00000002 /* Over current indicator */ 212*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_DRWE 0x00008000 /* Device remote wakeup */ 213*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_LPSC 0x00010000 /* Local power status change */ 214*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_OCIC 0x00020000 /* Over current indicator */ 215*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_CRWE 0x80000000 /* Clear remote wakeup enable */ 216*7c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_MASK 0x10038003 /* Status mask */ 217*7c478bd9Sstevel@tonic-gate 218*7c478bd9Sstevel@tonic-gate /* hcr_rh_portstatus bits */ 219*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CCS 0x00000001 /* Current connect status */ 220*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PES 0x00000002 /* Port enable */ 221*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PSS 0x00000004 /* Port suspend status */ 222*7c478bd9Sstevel@tonic-gate #define HCR_PORT_POCI 0x00000008 /* Port over crrnt indicator */ 223*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PRS 0x00000010 /* Port reset status */ 224*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PPS 0x00000100 /* Port power status */ 225*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CPP 0x00000200 /* Clear port power */ 226*7c478bd9Sstevel@tonic-gate #define HCR_PORT_LSDA 0x00000200 /* Low speed device */ 227*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CSC 0x00010000 /* Connect status change */ 228*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PESC 0x00020000 /* Port enable status change */ 229*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PSSC 0x00040000 /* Port suspend status change */ 230*7c478bd9Sstevel@tonic-gate #define HCR_PORT_OCIC 0x00080000 /* Port over current change */ 231*7c478bd9Sstevel@tonic-gate #define HCR_PORT_PRSC 0x00100000 /* Port reset status chnge */ 232*7c478bd9Sstevel@tonic-gate #define HCR_PORT_MASK 0x001F031F /* Reserved written as 0 */ 233*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CHNG_MASK 0x001F0000 /* Mask for change bits */ 234*7c478bd9Sstevel@tonic-gate 235*7c478bd9Sstevel@tonic-gate #define DONE_QUEUE_INTR_COUNTER 0x7 /* Done queue intr counter */ 236*7c478bd9Sstevel@tonic-gate 237*7c478bd9Sstevel@tonic-gate /* 238*7c478bd9Sstevel@tonic-gate * Host Controller Communications Area 239*7c478bd9Sstevel@tonic-gate * 240*7c478bd9Sstevel@tonic-gate * The Host Controller Communications Area (HCCA) is a 256-byte structre 241*7c478bd9Sstevel@tonic-gate * of system memory that is established by the Host Controller Driver (HCD) 242*7c478bd9Sstevel@tonic-gate * and this structre is used for communication between HCD and HC. The HCD 243*7c478bd9Sstevel@tonic-gate * maintains a pointer to this structure in the Host Controller (HC). This 244*7c478bd9Sstevel@tonic-gate * structure must be aligned to a 256-byte boundary. 245*7c478bd9Sstevel@tonic-gate */ 246*7c478bd9Sstevel@tonic-gate 247*7c478bd9Sstevel@tonic-gate #define NUM_INTR_ED_LISTS 32 /* Number of interrupt lists */ 248*7c478bd9Sstevel@tonic-gate #define NUM_STATIC_NODES 31 /* Number of static endpoints */ 249*7c478bd9Sstevel@tonic-gate 250*7c478bd9Sstevel@tonic-gate typedef volatile struct ohci_hcca { 251*7c478bd9Sstevel@tonic-gate uint32_t HccaIntTble[NUM_INTR_ED_LISTS]; /* 32 intr lists */ 252*7c478bd9Sstevel@tonic-gate /* Ptrs to ohci_ed */ 253*7c478bd9Sstevel@tonic-gate uint16_t HccaFrameNo; /* Current frame number */ 254*7c478bd9Sstevel@tonic-gate uint16_t HccaPad; /* 0 when HC updates FrameNo */ 255*7c478bd9Sstevel@tonic-gate uint32_t HccaDoneHead; /* Head ptr */ 256*7c478bd9Sstevel@tonic-gate uint8_t HccaReserved[120]; /* Reserved area */ 257*7c478bd9Sstevel@tonic-gate } ohci_hcca_t; 258*7c478bd9Sstevel@tonic-gate 259*7c478bd9Sstevel@tonic-gate #define HCCA_DONE_HEAD_MASK 0xFFFFFFF0 /* Hcca done head mask */ 260*7c478bd9Sstevel@tonic-gate #define HCCA_DONE_HEAD_LSB 0x00000001 /* Lsb of the Done Head */ 261*7c478bd9Sstevel@tonic-gate 262*7c478bd9Sstevel@tonic-gate 263*7c478bd9Sstevel@tonic-gate /* 264*7c478bd9Sstevel@tonic-gate * Host Controller Endpoint Descriptor 265*7c478bd9Sstevel@tonic-gate * 266*7c478bd9Sstevel@tonic-gate * An Endpoint Descriptor (ED) is a memory structure that describes the 267*7c478bd9Sstevel@tonic-gate * information necessary for the Host Controller (HC) to communicate with 268*7c478bd9Sstevel@tonic-gate * a device endpoint. An ED includes a Transfer Descriptor (TD) pointer. 269*7c478bd9Sstevel@tonic-gate * This structure must be aligned to a 16 byte boundary. 270*7c478bd9Sstevel@tonic-gate */ 271*7c478bd9Sstevel@tonic-gate typedef volatile struct ohci_ed { 272*7c478bd9Sstevel@tonic-gate uint32_t hced_ctrl; /* See below */ 273*7c478bd9Sstevel@tonic-gate uint32_t hced_tailp; /* (ohci_td *) End of trans. list */ 274*7c478bd9Sstevel@tonic-gate uint32_t hced_headp; /* (ohci_td *) Next trans. */ 275*7c478bd9Sstevel@tonic-gate uint32_t hced_next; /* (ohci_ed *) Next endpoint */ 276*7c478bd9Sstevel@tonic-gate uint32_t hced_prev; /* (ohci_ed *)Virt addr. of prev ept */ 277*7c478bd9Sstevel@tonic-gate uint32_t hced_node; /* The node that its attached */ 278*7c478bd9Sstevel@tonic-gate uint32_t hced_reclaim_next; /* (ohci_ed *) Reclaim list */ 279*7c478bd9Sstevel@tonic-gate uint32_t hced_reclaim_frame; /* Reclaim usb frame number */ 280*7c478bd9Sstevel@tonic-gate uint32_t hced_state; /* Endpoint state */ 281*7c478bd9Sstevel@tonic-gate uint8_t hce_pad[12]; /* Required padding */ 282*7c478bd9Sstevel@tonic-gate } ohci_ed_t; 283*7c478bd9Sstevel@tonic-gate 284*7c478bd9Sstevel@tonic-gate /* 285*7c478bd9Sstevel@tonic-gate * hc_endpoint_descriptor control bits 286*7c478bd9Sstevel@tonic-gate */ 287*7c478bd9Sstevel@tonic-gate #define HC_EPT_FUNC 0x0000007F /* Address of function */ 288*7c478bd9Sstevel@tonic-gate #define HC_EPT_EP 0x00000780 /* Address of endpoint */ 289*7c478bd9Sstevel@tonic-gate #define HC_EPT_DataFlow 0x00001800 /* Direction of data flow */ 290*7c478bd9Sstevel@tonic-gate #define HC_EPT_DF_IN 0x00001000 /* Data flow in */ 291*7c478bd9Sstevel@tonic-gate #define HC_EPT_DF_OUT 0x00000800 /* Data flow out */ 292*7c478bd9Sstevel@tonic-gate #define HC_EPT_Speed 0x00002000 /* Speed of the endpoint */ 293*7c478bd9Sstevel@tonic-gate #define HC_EPT_sKip 0x00004000 /* Skip bit */ 294*7c478bd9Sstevel@tonic-gate #define HC_EPT_Format 0x00008000 /* Type of transfer */ 295*7c478bd9Sstevel@tonic-gate #define HC_EPT_MPS 0x0EFF0000 /* Max packet size */ 296*7c478bd9Sstevel@tonic-gate #define HC_EPT_8_MPS 0x00080000 /* 8 byte max packet size */ 297*7c478bd9Sstevel@tonic-gate #define HC_EPT_64_MPS 0x00400000 /* 64 byte max packet size */ 298*7c478bd9Sstevel@tonic-gate #define HC_EPT_Halt 0x00000001 /* Halted */ 299*7c478bd9Sstevel@tonic-gate #define HC_EPT_Carry 0x00000002 /* Toggle carry */ 300*7c478bd9Sstevel@tonic-gate 301*7c478bd9Sstevel@tonic-gate #define HC_EPT_EP_SHFT 7 /* Bits to shift addr */ 302*7c478bd9Sstevel@tonic-gate #define HC_EPT_MAXPKTSZ 16 /* Bits to shift maxpktsize */ 303*7c478bd9Sstevel@tonic-gate 304*7c478bd9Sstevel@tonic-gate #define HC_EPT_TD_TAIL 0xFFFFFFF0 /* TD tail mask */ 305*7c478bd9Sstevel@tonic-gate #define HC_EPT_TD_HEAD 0xFFFFFFF0 /* TD head mask */ 306*7c478bd9Sstevel@tonic-gate #define HC_EPT_NEXT 0xFFFFFFF0 /* Next endpoint mask */ 307*7c478bd9Sstevel@tonic-gate 308*7c478bd9Sstevel@tonic-gate /* 309*7c478bd9Sstevel@tonic-gate * hced_state 310*7c478bd9Sstevel@tonic-gate * 311*7c478bd9Sstevel@tonic-gate * ED states 312*7c478bd9Sstevel@tonic-gate */ 313*7c478bd9Sstevel@tonic-gate #define HC_EPT_FREE 1 /* Free ED */ 314*7c478bd9Sstevel@tonic-gate #define HC_EPT_STATIC 2 /* Static ED */ 315*7c478bd9Sstevel@tonic-gate #define HC_EPT_ACTIVE 3 /* Active ED */ 316*7c478bd9Sstevel@tonic-gate 317*7c478bd9Sstevel@tonic-gate 318*7c478bd9Sstevel@tonic-gate /* 319*7c478bd9Sstevel@tonic-gate * Host Controller Transfer Descriptor 320*7c478bd9Sstevel@tonic-gate * 321*7c478bd9Sstevel@tonic-gate * A Transfer Descriptor (TD) is a memory structure that describes the 322*7c478bd9Sstevel@tonic-gate * information necessary for the Host Controller (HC) to transfer a block 323*7c478bd9Sstevel@tonic-gate * of data to or from a device endpoint. These TD's will be attached to 324*7c478bd9Sstevel@tonic-gate * a Endpoint Descriptor (ED). This structure includes the fields for both 325*7c478bd9Sstevel@tonic-gate * General and Isochronous Transfer Descriptors. The General TDs must be 326*7c478bd9Sstevel@tonic-gate * aligned to 16 byte, where as Isochronous TDs must be aligned to 32 byte. 327*7c478bd9Sstevel@tonic-gate */ 328*7c478bd9Sstevel@tonic-gate typedef volatile struct ohci_td { 329*7c478bd9Sstevel@tonic-gate uint32_t hctd_ctrl; /* See below */ 330*7c478bd9Sstevel@tonic-gate uint32_t hctd_cbp; /* Next buffer addr */ 331*7c478bd9Sstevel@tonic-gate uint32_t hctd_next_td; /* Next TD */ 332*7c478bd9Sstevel@tonic-gate uint32_t hctd_buf_end; /* End of buffer */ 333*7c478bd9Sstevel@tonic-gate uint32_t hctd_offsets[4]; /* Offsets into buf */ 334*7c478bd9Sstevel@tonic-gate /* Used only for isoch */ 335*7c478bd9Sstevel@tonic-gate uint32_t hctd_trans_wrapper; /* Transfer wrapper */ 336*7c478bd9Sstevel@tonic-gate uint32_t hctd_state; /* TD state */ 337*7c478bd9Sstevel@tonic-gate uint32_t hctd_tw_next_td; /* Next TD on TW */ 338*7c478bd9Sstevel@tonic-gate uint32_t hctd_ctrl_phase; /* Control Xfer Phase info */ 339*7c478bd9Sstevel@tonic-gate uint8_t hctd_pad[16]; /* Required padding */ 340*7c478bd9Sstevel@tonic-gate } ohci_td_t; 341*7c478bd9Sstevel@tonic-gate 342*7c478bd9Sstevel@tonic-gate /* 343*7c478bd9Sstevel@tonic-gate * Common hc_td control bits both for the General and Isochronous Transfer 344*7c478bd9Sstevel@tonic-gate * Descriptors. 345*7c478bd9Sstevel@tonic-gate */ 346*7c478bd9Sstevel@tonic-gate #define HC_TD_DI 0x00E00000 /* Delay interrupt */ 347*7c478bd9Sstevel@tonic-gate #define HC_TD_0I 0x00000000 /* 0 frame for interrupt */ 348*7c478bd9Sstevel@tonic-gate #define HC_TD_1I 0x00200000 /* 1 frame for interrupt */ 349*7c478bd9Sstevel@tonic-gate #define HC_TD_2I 0x00400000 /* 2 frame for interrupt */ 350*7c478bd9Sstevel@tonic-gate #define HC_TD_3I 0x00600000 /* 3 frame for interrupt */ 351*7c478bd9Sstevel@tonic-gate #define HC_TD_4I 0x00800000 /* 4 frame's for interrupt */ 352*7c478bd9Sstevel@tonic-gate #define HC_TD_5I 0x00A00000 /* 5 frame for interrupt */ 353*7c478bd9Sstevel@tonic-gate #define HC_TD_6I 0x00C00000 /* 6 frame for interrupt */ 354*7c478bd9Sstevel@tonic-gate #define HC_TD_7I 0x00E00000 /* 7 frame for interrupt */ 355*7c478bd9Sstevel@tonic-gate #define HC_TD_CC 0xF0000000 /* Condition code */ 356*7c478bd9Sstevel@tonic-gate 357*7c478bd9Sstevel@tonic-gate #define HC_TD_R 0x00040000 /* Buffer rounding */ 358*7c478bd9Sstevel@tonic-gate #define HC_TD_PID 0x00180000 /* Pid for the token */ 359*7c478bd9Sstevel@tonic-gate #define HC_TD_SETUP 0x00000000 /* Setup direction */ 360*7c478bd9Sstevel@tonic-gate #define HC_TD_IN 0x00100000 /* In direction */ 361*7c478bd9Sstevel@tonic-gate #define HC_TD_OUT 0x00080000 /* Out direction */ 362*7c478bd9Sstevel@tonic-gate #define HC_TD_DT 0x03000000 /* Data Toggle */ 363*7c478bd9Sstevel@tonic-gate #define HC_TD_MS_DT 0x02000000 /* Master data toggle */ 364*7c478bd9Sstevel@tonic-gate #define HC_TD_DT_0 0x00000000 /* Toggle from TD 0 */ 365*7c478bd9Sstevel@tonic-gate #define HC_TD_DT_1 0x01000000 /* Toggle from TD 1 */ 366*7c478bd9Sstevel@tonic-gate #define HC_TD_EC 0x0C000000 /* Error Count */ 367*7c478bd9Sstevel@tonic-gate 368*7c478bd9Sstevel@tonic-gate /* 369*7c478bd9Sstevel@tonic-gate * hc_td control bits specific to Isochronous Transfer Descriptors. 370*7c478bd9Sstevel@tonic-gate */ 371*7c478bd9Sstevel@tonic-gate #define HC_ITD_SF 0x0000FFFF /* Starting Frame number */ 372*7c478bd9Sstevel@tonic-gate #define HC_ITD_FC 0x07000000 /* Frame count */ 373*7c478bd9Sstevel@tonic-gate 374*7c478bd9Sstevel@tonic-gate #define HC_ITD_FC_SHIFT 24 /* Frame count shift */ 375*7c478bd9Sstevel@tonic-gate #define HC_ITD_PAGE_MASK 0xFFFFF000 376*7c478bd9Sstevel@tonic-gate #define HC_ITD_ODD_OFFSET 0xFFFF0000 /* Odd offset */ 377*7c478bd9Sstevel@tonic-gate #define HC_ITD_EVEN_OFFSET 0x0000FFFF /* Even offset */ 378*7c478bd9Sstevel@tonic-gate #define HC_ITD_OFFSET_SHIFT 16 379*7c478bd9Sstevel@tonic-gate #define HC_ITD_OFFSET_CC 0x0000F000 /* CC of offset or PSW N */ 380*7c478bd9Sstevel@tonic-gate #define HC_ITD_OFFSET_ADDR 0x00000FFF /* Offset N */ 381*7c478bd9Sstevel@tonic-gate #define HC_ITD_4KBOUNDARY_CROSS 0x00001000 /* Set bit 12 for 4k crossing */ 382*7c478bd9Sstevel@tonic-gate 383*7c478bd9Sstevel@tonic-gate /* 384*7c478bd9Sstevel@tonic-gate * Condition codes both to General and Isochronous Transfer Descriptors. 385*7c478bd9Sstevel@tonic-gate * Even these condition codes are valid for offsets of the isochronous 386*7c478bd9Sstevel@tonic-gate * transfer descriptos. 387*7c478bd9Sstevel@tonic-gate */ 388*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_NO_E 0x00000000 /* No error */ 389*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_CRC 0x10000000 /* CRC error */ 390*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_BS 0x20000000 /* Bit stuffing */ 391*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_DTM 0x30000000 /* Data Toggle Mismatch */ 392*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_STALL 0x40000000 /* Stall */ 393*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_DNR 0x50000000 /* Device not responding */ 394*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_PCF 0x60000000 /* PID check failure */ 395*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_UPID 0x70000000 /* Unexpected PID */ 396*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_DO 0x80000000 /* Data overrrun */ 397*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_DU 0x90000000 /* Data underrun */ 398*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_BO 0xC0000000 /* Buffer overrun */ 399*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_BU 0xD0000000 /* Buffer underrun */ 400*7c478bd9Sstevel@tonic-gate #define HC_TD_CC_NA 0xF0000000 /* Not accessed */ 401*7c478bd9Sstevel@tonic-gate 402*7c478bd9Sstevel@tonic-gate #define HC_TD_NEXT 0xFFFFFFF0 /* Next TD */ 403*7c478bd9Sstevel@tonic-gate 404*7c478bd9Sstevel@tonic-gate /* 405*7c478bd9Sstevel@tonic-gate * Condition codes specific to Isochronous Transfer Descriptors. 406*7c478bd9Sstevel@tonic-gate */ 407*7c478bd9Sstevel@tonic-gate #define HC_ITD_CC_SHIFT 16 /* ITD CC shift */ 408*7c478bd9Sstevel@tonic-gate 409*7c478bd9Sstevel@tonic-gate /* 410*7c478bd9Sstevel@tonic-gate * hctd_state 411*7c478bd9Sstevel@tonic-gate * 412*7c478bd9Sstevel@tonic-gate * TD States 413*7c478bd9Sstevel@tonic-gate */ 414*7c478bd9Sstevel@tonic-gate #define HC_TD_FREE 1 /* Free TD */ 415*7c478bd9Sstevel@tonic-gate #define HC_TD_DUMMY 2 /* Dummy TD */ 416*7c478bd9Sstevel@tonic-gate #define HC_TD_ACTIVE 3 /* Active TD */ 417*7c478bd9Sstevel@tonic-gate #define HC_TD_TIMEOUT 4 /* Timeouted TD */ 418*7c478bd9Sstevel@tonic-gate #define HC_TD_RECLAIM 5 /* Reclaimed TD */ 419*7c478bd9Sstevel@tonic-gate 420*7c478bd9Sstevel@tonic-gate /* 421*7c478bd9Sstevel@tonic-gate * hctd_ctrl_phase 422*7c478bd9Sstevel@tonic-gate * 423*7c478bd9Sstevel@tonic-gate * Control Transfer Phase information 424*7c478bd9Sstevel@tonic-gate */ 425*7c478bd9Sstevel@tonic-gate #define OHCI_CTRL_SETUP_PHASE 1 /* Setup phase */ 426*7c478bd9Sstevel@tonic-gate #define OHCI_CTRL_DATA_PHASE 2 /* Data phase */ 427*7c478bd9Sstevel@tonic-gate #define OHCI_CTRL_STATUS_PHASE 3 /* Status phase */ 428*7c478bd9Sstevel@tonic-gate 429*7c478bd9Sstevel@tonic-gate 430*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 431*7c478bd9Sstevel@tonic-gate } 432*7c478bd9Sstevel@tonic-gate #endif 433*7c478bd9Sstevel@tonic-gate 434*7c478bd9Sstevel@tonic-gate #endif /* _SYS_USB_OHCI_H */ 435