1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_EHCID_H 27 #define _SYS_USB_EHCID_H 28 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Enchanced Host Controller Driver (EHCI) 36 * 37 * The EHCI driver is a software driver which interfaces to the Universal 38 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 39 * the Host Controller is defined by the EHCI Host Controller Interface. 40 * 41 * This header file describes the data structures and function prototypes 42 * required for the EHCI Driver to maintain state of Host Controller (HC), 43 * to perform different USB transfers and for the bandwidth allocations. 44 */ 45 46 #include <sys/usb/hcd/ehci/ehci.h> 47 #include <sys/usb/hcd/ehci/ehci_hub.h> 48 49 50 /* 51 * EHCI Bandwidth Maintainence Structure. 52 * 53 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci 54 * host controller. There are 32 bandwidth lists corresponding to 32 ms 55 * periodic frame lists. Each bandwidth list inturn will contain eight 56 * micro frame bandwidth lists. 57 */ 58 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */ 59 60 typedef struct ehci_frame_bandwidth { 61 uint_t ehci_allocated_frame_bandwidth; 62 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES]; 63 } ehci_frame_bandwidth_t; 64 65 66 /* 67 * EHCI Host Controller state structure 68 * 69 * The Host Controller Driver (HCD) maintains the state of Host Controller 70 * (HC). There is an ehci_state structure per instance of the EHCI 71 * host controller. 72 */ 73 typedef struct ehci_state { 74 dev_info_t *ehci_dip; /* Dip of HC */ 75 uint_t ehci_instance; 76 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */ 77 uint_t ehci_flags; /* Used for cleanup */ 78 uint16_t ehci_vendor_id; /* chip vendor */ 79 uint16_t ehci_device_id; /* chip device */ 80 uint8_t ehci_rev_id; /* chip revison */ 81 82 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */ 83 ehci_caps_t *ehci_capsp; /* Capability Regs */ 84 ehci_regs_t *ehci_regsp; /* Operational Regs */ 85 86 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */ 87 uint_t ehci_frame_interval; /* Frme inter reg */ 88 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */ 89 90 ddi_intr_handle_t *ehci_htable; /* intr handle */ 91 int ehci_intr_type; /* intr type used */ 92 int ehci_intr_cnt; /* # of intrs inuse */ 93 uint_t ehci_intr_pri; /* intr priority */ 94 int ehci_intr_cap; /* intr capabilities */ 95 boolean_t ehci_msi_enabled; /* default to true */ 96 kmutex_t ehci_int_mutex; /* Global EHCI mutex */ 97 98 /* Periodic Frame List area */ 99 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep; 100 /* Virtual Periodic Frame List ptr */ 101 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */ 102 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */ 103 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */ 104 105 /* 106 * There are two pools of memory. One pool contains the memory for 107 * the transfer descriptors and other pool contains the memory for 108 * the endpoint descriptors. The advantage of the pools is that it's 109 * easy to go back and forth between the iommu and the cpu addresses. 110 * 111 * The pools are protected by the ehci_int_mutex because the memory 112 * in the pools may be accessed by either the host controller or the 113 * host controller driver. 114 */ 115 116 /* Endpoint descriptor pool */ 117 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */ 118 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */ 119 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */ 120 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */ 121 uint_t ehci_dma_addr_bind_flag; /* DMA flag */ 122 123 /* General transfer descriptor pool */ 124 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */ 125 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */ 126 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */ 127 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */ 128 129 /* Isochronous transfer descriptor pool */ 130 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */ 131 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */ 132 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */ 133 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */ 134 135 /* Condition variable for advance on Asynchronous Schedule */ 136 kcondvar_t ehci_async_schedule_advance_cv; 137 138 /* Head of Asynchronous Schedule List */ 139 ehci_qh_t *ehci_head_of_async_sched_list; 140 141 /* 142 * List of QTD inserted either into Asynchronous or Periodic 143 * Schedule lists. 144 */ 145 ehci_qtd_t *ehci_active_qtd_list; 146 /* 147 * List of ITD active itd list. 148 */ 149 ehci_itd_t *ehci_active_itd_list; 150 151 /* 152 * Bandwidth fields 153 * 154 * The ehci_bandwidth array keeps track of allocated bandwidth for 155 * ehci host controller. There are 32 bandwidth lists corresponding 156 * to 32 ms periodic frame lists. Each bandwidth list in turn will 157 * contain eight micro frame bandwidth lists. 158 * 159 * ehci_min_frame_bandwidth field indicates least allocated milli 160 * second bandwidth list. 161 */ 162 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS]; 163 164 /* No. of open pipes, async qh, and periodic qh */ 165 uint_t ehci_open_pipe_count; 166 uint_t ehci_open_async_count; 167 uint_t ehci_open_periodic_count; 168 169 /* 170 * Endpoint Reclamation List 171 * 172 * The interrupt list processing cannot be stopped when a periodic 173 * endpoint is removed from the list. The endpoints are detached 174 * from the interrupt lattice tree and put on to the reclaimation 175 * list. On next SOF interrupt all those endpoints, which are on 176 * the reclaimation list will be deallocated. 177 */ 178 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */ 179 180 ehci_root_hub_t ehci_root_hub; /* Root hub info */ 181 182 /* Frame number overflow information */ 183 usb_frame_number_t ehci_fno; 184 185 /* For host controller error counter */ 186 uint_t ehci_hc_error; 187 188 /* 189 * ehci_missed_intr_sts is used to save the normal mode interrupt 190 * status information if an interrupt is pending for normal mode 191 * when polled code is entered. 192 */ 193 uint_t ehci_missed_intr_sts; 194 195 /* 196 * Saved copy of the ehci registers of the normal mode & change 197 * required ehci registers values for the polled mode operation. 198 * Before returning from the polled mode to normal mode replace 199 * the required current registers with this saved ehci registers 200 * copy. 201 */ 202 ehci_regs_t ehci_polled_save_regs; 203 204 /* 205 * Saved copy of the interrupt table used in normal ehci mode and 206 * replace this table by another interrupt table that used in the 207 * POLLED mode. 208 */ 209 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS]; 210 211 /* ehci polled mode enter counter */ 212 uint_t ehci_polled_enter_count; 213 214 /* 215 * counter for polled mode and used in suspend mode to see if 216 * there is a keyboard connected. 217 */ 218 uint_t ehci_polled_kbd_count; 219 220 /* counter for polled read and use it to clean the interrupt status */ 221 uint_t ehci_polled_read_count; 222 223 #if defined(__x86) 224 /* counter for polled root hub status */ 225 uint_t ehci_polled_root_hub_count; 226 #endif /* __x86 */ 227 228 /* EHCI Host Controller Software State information */ 229 uint_t ehci_hc_soft_state; 230 231 /* Log handle for debug, console, log messages */ 232 usb_log_handle_t ehci_log_hdl; 233 234 /* Kstat structures */ 235 kstat_t *ehci_intrs_stats; 236 kstat_t *ehci_total_stats; 237 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS]; 238 } ehci_state_t; 239 240 typedef struct ehci_intrs_stats { 241 struct kstat_named ehci_sts_async_sched_status; 242 struct kstat_named ehci_sts_periodic_sched_status; 243 struct kstat_named ehci_sts_empty_async_schedule; 244 struct kstat_named ehci_sts_host_ctrl_halted; 245 struct kstat_named ehci_sts_async_advance_intr; 246 struct kstat_named ehci_sts_host_system_error_intr; 247 struct kstat_named ehci_sts_frm_list_rollover_intr; 248 struct kstat_named ehci_sts_rh_port_change_intr; 249 struct kstat_named ehci_sts_usb_error_intr; 250 struct kstat_named ehci_sts_usb_intr; 251 struct kstat_named ehci_sts_not_claimed; 252 struct kstat_named ehci_sts_total; 253 } ehci_intrs_stats_t; 254 255 /* 256 * ehci kstat defines 257 */ 258 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats) 259 #define EHCI_INTRS_STATS_DATA(ehci) \ 260 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data) 261 262 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats) 263 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats)) 264 #define EHCI_CTRL_STATS(ehci) \ 265 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL])) 266 #define EHCI_BULK_STATS(ehci) \ 267 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK])) 268 #define EHCI_INTR_STATS(ehci) \ 269 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR])) 270 #define EHCI_ISOC_STATS(ehci) \ 271 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH])) 272 273 /* warlock directives, stable data */ 274 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t)) 275 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri)) 276 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip)) 277 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp)) 278 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance)) 279 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id)) 280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id)) 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id)) 282 283 /* this may not be stable data in the future */ 284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr)) 285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle)) 286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie)) 287 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr)) 288 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle)) 289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie)) 290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr)) 291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle)) 292 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie)) 293 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag)) 294 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl)) 295 296 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \ 297 usba_pipe_handle_data::p_mutex \ 298 usba_device::usb_mutex \ 299 usba_ph_impl::usba_ph_mutex)) 300 301 /* 302 * Host Contoller Software States 303 * 304 * EHCI_CTLR_INIT_STATE: 305 * The host controller soft state will be set to this during the 306 * ehci_attach. 307 * 308 * EHCI_CTLR_SUSPEND_STATE: 309 * The host controller soft state will be set to this during the 310 * ehci_cpr_suspend. 311 * 312 * EHCI_CTLR_OPERATIONAL_STATE: 313 * The host controller soft state will be set to this after moving 314 * host controller to operational state and host controller start 315 * generating SOF successfully. 316 * 317 * EHCI_CTLR_ERROR_STATE: 318 * The host controller soft state will be set to this during the 319 * no SOF or UE error conditions. 320 * 321 * Under this state or condition, only pipe stop polling, pipe reset 322 * and pipe close are allowed. But all other entry points like pipe 323 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 324 * isoch send/receive, start polling etc. will fail. 325 * 326 * State Diagram for the host controller software state 327 * 328 * 329 * ehci_attach->[INIT_STATE] 330 * | 331 * | -------->----[ERROR_STATE]--<-----------<--- 332 * | | Failure (UE/no SOF condition) | 333 * | ^ ^ 334 * V | Success | 335 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling 336 * ^ | 337 * | | 338 * | V 339 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend 340 */ 341 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */ 342 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 343 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 344 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 345 346 /* 347 * Flags for initializatoin of host controller 348 */ 349 #define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */ 350 #define EHCI_REINITIALIZATION 1 /* Re-initialization */ 351 352 /* 353 * Periodic and non-periodic macros 354 */ 355 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 356 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 357 ((endpoint->bmAttributes &\ 358 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 359 360 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 361 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 362 ((endpoint->bmAttributes &\ 363 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 364 365 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 366 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 367 368 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 369 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR)) 370 371 372 /* 373 * EHCI QH and QTD Pool sizes. 374 */ 375 #define EHCI_QH_POOL_SIZE 100 376 #define EHCI_QTD_POOL_SIZE 200 377 #define EHCI_ITD_POOL_SIZE 200 378 379 /* 380 * ehci_dma_addr_bind_flag values 381 * 382 * This flag indicates if the various DMA addresses allocated by the EHCI 383 * have been bound to their respective handles. This is needed to recover 384 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle() 385 */ 386 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */ 387 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */ 388 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */ 389 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */ 390 391 /* 392 * Maximum SOF wait count 393 */ 394 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 395 396 /* 397 * One uFrame 125 micro seconds 398 * One Frame 1 milli second or 8 uFrames 399 */ 400 #define EHCI_uFRAMES_PER_USB_FRAME 8 401 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3 402 403 404 /* 405 * Pipe private structure 406 * 407 * There is an instance of this structure per pipe. This structure holds 408 * HCD specific pipe information. A pointer to this structure is kept in 409 * the USBA pipe handle (usba_pipe_handle_data_t). 410 */ 411 typedef struct ehci_pipe_private { 412 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 413 ehci_qh_t *pp_qh; /* Pipe's qh */ 414 415 /* State of the pipe */ 416 uint_t pp_state; /* See below */ 417 418 /* Local copy of the pipe policy */ 419 usb_pipe_policy_t pp_policy; 420 421 /* For Periodic Pipes Only */ 422 uint_t pp_pnode; /* periodic node */ 423 uchar_t pp_smask; /* Start split mask */ 424 uchar_t pp_cmask; /* Comp split mask */ 425 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 426 uint_t pp_max_periodic_req_cnt; /* Max req count */ 427 428 /* For Isochronous pipes only */ 429 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 430 431 /* 432 * Each pipe may have multiple transfer wrappers. Each transfer 433 * wrapper represents a USB transfer on the bus. A transfer is 434 * made up of one or more transactions. 435 */ 436 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */ 437 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 438 439 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */ 440 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */ 441 442 /* 443 * Pipe's transfer timeout handling & this transfer timeout handling 444 * will be per pipe. 445 */ 446 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */ 447 timeout_id_t pp_timer_id; /* Timer id */ 448 449 /* Done td count */ 450 uint_t pp_count_done_qtds; /* Done td count */ 451 452 /* Errors */ 453 usb_cr_t pp_error; /* Pipe error */ 454 455 /* Condition variable for transfers completion event */ 456 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 457 458 /* Pipe flag */ 459 uint_t pp_flag; /* For polled mode */ 460 461 /* Halting States */ 462 uint_t pp_halt_state; /* Is it halting */ 463 464 /* Condition variable for halt completion event */ 465 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */ 466 467 /* 468 * HCD gets Interrupt/Isochronous IN polling request only once and 469 * it has to insert next polling requests after completion of first 470 * request until either stop polling/pipe close is called. So HCD 471 * has to take copy of the original Interrupt/Isochronous IN request. 472 */ 473 usb_opaque_t pp_client_periodic_in_reqp; 474 } ehci_pipe_private_t; 475 476 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t)) 477 478 /* 479 * Pipe states 480 * 481 * ehci pipe states will be similar to usba. Refer usbai.h. 482 */ 483 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 484 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 485 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 486 487 /* Additional ehci pipe states for the ehci_pipe_cleanup */ 488 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 489 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 490 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 491 492 /* 493 * Pipe flag 494 * 495 * For polled mode flag. 496 */ 497 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */ 498 499 /* Pipe specific flags */ 500 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 501 502 /* 503 * Halting States 504 * prevent halting from interleaving. 505 */ 506 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */ 507 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */ 508 509 /* 510 * Request values for Clear_TT_Buffer 511 */ 512 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \ 513 USB_DEV_REQ_RCPT_OTHER) 514 #define EHCI_CLEAR_TT_BUFFER_BREQ 8 515 516 /* 517 * USB frame offset 518 * 519 * Add appropriate frame offset to the current usb frame number and use it 520 * as a starting frame number for a given usb isochronous request. 521 */ 522 #define EHCI_FRAME_OFFSET 2 /* Frame offset */ 523 524 /* 525 * Different interrupt polling intervals supported for high speed 526 * devices and its range must be from 1 to 16 units. This value is 527 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval 528 * of 4 means a period of 8us (2 ^ (4-1)). 529 * 530 * The following values are defined after above convertion in terms 531 * 125us units. 532 */ 533 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */ 534 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */ 535 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */ 536 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */ 537 538 /* 539 * The following indecies are are used to calculate Start and complete 540 * masks as per the polling interval. 541 */ 542 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */ 543 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */ 544 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */ 545 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */ 546 547 /* 548 * Different interrupt polling intervals supported for low/full/high 549 * speed devices. For high speed devices, the following values are 550 * applicable after convertion. 551 */ 552 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */ 553 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */ 554 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */ 555 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */ 556 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */ 557 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */ 558 559 /* 560 * Number of interrupt transfer requests that should be maintained on 561 * the interrupt endpoint corresponding to different polling intervals 562 * supported. 563 */ 564 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */ 565 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */ 566 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 567 568 /* Function prototype */ 569 typedef void (*ehci_handler_function_t)( 570 ehci_state_t *ehcip, 571 ehci_pipe_private_t *pp, 572 struct ehci_trans_wrapper *tw, 573 ehci_qtd_t *qtd, 574 void *ehci_handle_callback_value); 575 576 577 /* 578 * Transfer wrapper 579 * 580 * The transfer wrapper represents a USB transfer on the bus and there 581 * is one instance per USB transfer. A transfer is made up of one or 582 * more transactions. EHCI uses one QTD for one transaction. So one 583 * transfer wrapper may have one or more QTDs associated. 584 * 585 * The data to be transferred are contained in the TW buffer which is 586 * virtually contiguous but physically discontiguous. When preparing 587 * the QTDs for a USB transfer, the DMA cookies corresponding to the 588 * TW buffer need to be walked through to retrieve the DMA addresses. 589 * 590 * Control and bulk pipes will have one transfer wrapper per transfer 591 * and where as Isochronous and Interrupt pipes will only have one 592 * transfer wrapper. The transfers wrapper are continually reused for 593 * the Interrupt and Isochronous pipes as those pipes are polled. 594 */ 595 typedef struct ehci_trans_wrapper { 596 struct ehci_trans_wrapper *tw_next; /* Next wrapper */ 597 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */ 598 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 599 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 600 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 601 uint_t tw_ncookies; /* DMA cookie count */ 602 uint_t tw_cookie_idx; /* DMA cookie index */ 603 size_t tw_dma_offs; /* DMA buffer offset */ 604 uint32_t tw_id; /* 32bit ID */ 605 size_t tw_length; /* Txfer length */ 606 char *tw_buf; /* Buffer for Xfer */ 607 usb_flags_t tw_flags; /* Flags */ 608 uint_t tw_num_qtds; /* Number of QTDs */ 609 ehci_qtd_t *tw_qtd_head; /* Head QTD */ 610 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */ 611 uint_t tw_direction; /* Direction of QTD */ 612 613 /* Current transfer request pointer */ 614 usb_opaque_t tw_curr_xfer_reqp; 615 616 /* Transfer timeout information */ 617 int tw_timeout; /* Timeout value */ 618 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 619 620 /* 621 * This is the function to call when this td is done. This way 622 * we don't have to look in the td to figure out what kind it is. 623 */ 624 ehci_handler_function_t tw_handle_qtd; 625 626 /* 627 * This is the callback value used when processing a done td. 628 */ 629 usb_opaque_t tw_handle_callback_value; 630 631 /* We preallocate all the td's for each tw and place them here */ 632 ehci_qtd_t *tw_qtd_free_list; 633 ehci_qtd_t *tw_alt_qtd; 634 } ehci_trans_wrapper_t; 635 636 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper)) 637 638 /* 639 * Isochronous Transfer Wrapper 640 * 641 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed 642 * isochronous transfers. A transfer wrapper consists of one or more 643 * transactionsl, but there is one one instance per USB transfer request. 644 * 645 * The isochrnous transfer wrapper are continiously reused because these 646 * pipes are polled. 647 */ 648 typedef struct ehci_isoc_xwrapper { 649 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */ 650 ehci_pipe_private_t *itw_pipe_private; 651 652 /* DMA and memory pointers */ 653 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */ 654 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */ 655 ddi_dma_cookie_t itw_cookie; /* DMA cookie */ 656 657 /* Transfer information */ 658 char *itw_buf; /* Buffer for Xfer */ 659 size_t itw_length; /* Txfer length */ 660 usb_flags_t itw_flags; /* Flags */ 661 usb_port_status_t itw_port_status; /* Port Speed */ 662 uint_t itw_direction; /* Direction of ITD */ 663 664 /* ITD information */ 665 uint_t itw_num_itds; /* Number of ITDs */ 666 ehci_itd_t *itw_itd_head; /* Head ITD */ 667 ehci_itd_t *itw_itd_tail; /* Tail ITD */ 668 usb_isoc_req_t *itw_curr_xfer_reqp; 669 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp; 670 671 /* We preallocate all the td's for each tw and place them here */ 672 ehci_itd_t *itw_itd_free_list; 673 674 /* Device and hub information needed by every iTD */ 675 uint_t itw_hub_addr; 676 uint_t itw_hub_port; 677 uint_t itw_endpoint_num; 678 uint_t itw_device_addr; 679 680 /* 681 * Callback handling function and arguement. Called when an iTD is 682 * is done. 683 */ 684 usb_opaque_t itw_handle_callback_value; 685 686 /* 32bit ID */ 687 uint32_t itw_id; 688 } ehci_isoc_xwrapper_t; 689 690 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t)) 691 692 /* 693 * Time waits for the different EHCI specific operations. 694 * These timeout values are specified in terms of microseconds. 695 */ 696 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 697 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */ 698 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */ 699 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */ 700 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */ 701 702 /* These timeout values are specified in seconds */ 703 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 704 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 705 706 /* EHCI flags for general use */ 707 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 708 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 709 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 710 711 /* 712 * Maximum allowable data transfer size per transaction as supported 713 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96) 714 * 715 * Also within QTD, there will be five buffer pointers abd each buffer 716 * pointer can transfer upto 4k bytes of data. 717 */ 718 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */ 719 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */ 720 721 /* 722 * The maximum allowable bulk data transfer size. It can be different 723 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will 724 * take care of breaking a bulk data request into multiples of ehci 725 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this 726 * value is set to 640k bytes. 727 */ 728 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */ 729 730 /* 731 * Timeout flags 732 * 733 * These flags will be used to stop the timer before timeout handler 734 * gets executed. 735 */ 736 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */ 737 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 738 739 740 /* 741 * High speed bandwidth allocation 742 * 743 * The following definitions are used during bandwidth calculations 744 * for a given high speed endpoint or high speed split transactions. 745 */ 746 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */ 747 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */ 748 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */ 749 #define HS_SOF 12 /* Length in bytes of High speed SOF */ 750 #define HS_EOF 70 /* Length in bytes of High speed EOF */ 751 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 752 753 /* 754 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved 755 * for the non-periodic high-speed transfers. Where as peridoic high-speed 756 * transfers will get 80% of the bus time. In one micro-frame or 125us, we 757 * can transfer 7500 bytes or 60,000 bits. 758 */ 759 #define HS_NON_PERIODIC_BANDWIDTH 1500 760 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \ 761 HS_EOF - HS_NON_PERIODIC_BANDWIDTH) 762 763 /* 764 * High speed periodic frame bandwidth will be eight times the micro frame 765 * high speed periodic bandwidth. 766 */ 767 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES 768 769 /* 770 * The following are the protocol overheads in terms of Bytes for the 771 * different transfer types. All these protocol overhead values are 772 * derived from the 5.11.3 section of USB 2.0 Specification. 773 */ 774 #define HS_NON_ISOC_PROTO_OVERHEAD 55 775 #define HS_ISOC_PROTO_OVERHEAD 38 776 777 /* 778 * The following are THE protocol overheads in terms of Bytes for the 779 * start and complete split transactions tokens overheads. All these 780 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3 781 * of USB2.0 Specification. 782 */ 783 #define START_SPLIT_OVERHEAD 04 784 #define COMPLETE_SPLIT_OVERHEAD 04 785 786 /* 787 * The Host Controller (HC) delays are the USB host controller specific 788 * delays. The value shown below is the host controller delay for the 789 * given EHCI host controller. 790 */ 791 #define EHCI_HOST_CONTROLLER_DELAY 18 792 793 /* 794 * Low/Full speed bandwidth allocation 795 * 796 * The following definitions are used during bandwidth calculations for 797 * a given high speed hub or a transaction translator (TT) and for a 798 * given low/full speed device connected to high speed hub or TT using 799 * split transactions 800 */ 801 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */ 802 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */ 803 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */ 804 #define FS_SOF 6 /* Length in bytes of Full speed SOF */ 805 #define FS_EOF 4 /* Length in bytes of Full speed EOF */ 806 807 /* 808 * Minimum polling interval for low speed endpoint 809 * 810 * According USB 2.0 Specification, a full-speed endpoint can specify 811 * a desired polling interval 1ms to 255ms and a low speed endpoints 812 * are limited to specifying only 10ms to 255ms. But some old keyboards 813 * and mice uses polling interval of 8ms. For compatibility purpose, 814 * we are using polling interval between 8ms and 255ms for low speed 815 * endpoints. The ehci driver will use 8ms polling interval if a low 816 * speed device reports a polling interval that is less than 8ms. 817 */ 818 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */ 819 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */ 820 821 /* 822 * For non-periodic transfers, reserve atleast for one low-speed device 823 * transaction. According to USB Bandwidth Analysis white paper and also 824 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 825 * transaction takes 0x628h full speed bits (197 bytes), which comes to 826 * around 13% of USB frame time. 827 * 828 * The periodic transfers will get around 87% of USB frame time. 829 */ 830 #define FS_NON_PERIODIC_BANDWIDTH 197 831 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \ 832 FS_EOF - FS_NON_PERIODIC_BANDWIDTH) 833 834 /* 835 * The following are the protocol overheads in terms of Bytes for the 836 * different transfer types. All these protocol overhead values are 837 * derived from the 5.11.3 section of USB Specification and with the 838 * help of Bandwidth Analysis white paper which is posted on the USB 839 * developer forum. 840 */ 841 #define FS_NON_ISOC_PROTO_OVERHEAD 14 842 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 843 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 844 #define LOW_SPEED_PROTO_OVERHEAD 97 845 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 846 847 /* The maximum amount of isoch data that can be transferred in one uFrame */ 848 #define MAX_UFRAME_SITD_XFER 188 849 850 /* 851 * The low speed clock below represents that to transmit one low-speed 852 * bit takes eight times more than one full speed bit time. 853 */ 854 #define LOW_SPEED_CLOCK 8 855 856 /* 857 * The Transaction Translator (TT) delay is the additional time needed 858 * to execute low/full speed transaction from high speed split transaction 859 * for the low/full device connected to the high speed extrenal hub. 860 */ 861 #define TT_DELAY 18 862 863 864 /* 865 * Macros for setting/getting information 866 */ 867 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \ 868 (uint32_t *)&addr) 869 870 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \ 871 ((uint32_t *)&addr), \ 872 ((int32_t)(val))) 873 874 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \ 875 (uint32_t *)&addr) 876 877 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \ 878 ((uint32_t *)&addr), \ 879 ((int32_t)(val))) 880 881 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \ 882 (uint32_t *)&addr) 883 884 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \ 885 ((uint32_t *)&addr), \ 886 ((int32_t)(val))) 887 888 #define Get_ITD_BODY(ptr, addr) ddi_get32( \ 889 ehcip->ehci_itd_pool_mem_handle, \ 890 (uint32_t *)&ptr->itd_body[addr]) 891 892 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \ 893 ehcip->ehci_itd_pool_mem_handle, \ 894 ((uint32_t *)&ptr->itd_body[addr]),\ 895 ((int32_t)(val))) 896 897 #define Get_ITD_INDEX(ptr, pos) ddi_get32( \ 898 ehcip->ehci_itd_pool_mem_handle, \ 899 (uint32_t *)&ptr->itd_index[pos]) 900 901 #define Set_ITD_INDEX(ptr, pos, val) ddi_put32( \ 902 ehcip->ehci_itd_pool_mem_handle, \ 903 ((uint32_t *)&ptr->itd_index[pos]),\ 904 ((uint32_t)(val))) 905 906 #define Get_ITD_FRAME(addr) ddi_get64( \ 907 ehcip->ehci_itd_pool_mem_handle, \ 908 (uint64_t *)&addr) 909 910 #define Set_ITD_FRAME(addr, val) ddi_put64( \ 911 ehcip->ehci_itd_pool_mem_handle, \ 912 ((uint64_t *)&addr), \ 913 (val)) 914 915 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \ 916 (uint32_t *)&addr) 917 918 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \ 919 ((uint32_t *)&addr), \ 920 ((int32_t)(uintptr_t)(val))) 921 922 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \ 923 (uint8_t *)&ehcip->ehci_capsp->addr) 924 925 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \ 926 (uint16_t *)&ehcip->ehci_capsp->addr) 927 928 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \ 929 (uint32_t *)&ehcip->ehci_capsp->addr) 930 931 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \ 932 (uint32_t *)&ehcip->ehci_regsp->addr) 933 934 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \ 935 ((uint32_t *)&ehcip->ehci_regsp->addr), \ 936 ((int32_t)(val))) 937 938 #define CalculateITDMultiField(pkgSize) (1 + (((pkgSize)>>11) & 0x03)) 939 940 #define EHCI_MAX_RETRY 10 941 942 #define Set_OpRegRetry(addr, val, r) \ 943 while (Get_OpReg(addr) != val) { \ 944 if (r >= EHCI_MAX_RETRY) \ 945 break; \ 946 r++; \ 947 Set_OpReg(addr, val); \ 948 } 949 950 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \ 951 ehcip->ehci_qh_pool_dma_handle, \ 952 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \ 953 DDI_DMA_SYNC_FORCPU); \ 954 (void) ddi_dma_sync( \ 955 ehcip->ehci_qtd_pool_dma_handle, \ 956 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \ 957 DDI_DMA_SYNC_FORCPU); 958 959 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \ 960 ehcip->ehci_itd_pool_dma_handle, \ 961 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \ 962 DDI_DMA_SYNC_FORCPU); 963 964 #define Sync_IO_Buffer(dma_handle, length) \ 965 (void) ddi_dma_sync(dma_handle, \ 966 0, length, DDI_DMA_SYNC_FORCPU); 967 968 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 969 (void) ddi_dma_sync(dma_handle, \ 970 0, length, DDI_DMA_SYNC_FORDEV); 971 972 /* 973 * Macros to speed handling of 32bit IDs 974 */ 975 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 976 #define EHCI_LOOKUP_ID(x) id32_lookup((x)) 977 #define EHCI_FREE_ID(x) id32_free((x)) 978 979 980 /* 981 * Miscellaneous definitions. 982 */ 983 984 /* Data toggle bits */ 985 #define DATA0 0 986 #define DATA1 1 987 988 /* Halt bit actions */ 989 #define CLEAR_HALT 0 990 #define SET_HALT 1 991 992 typedef uint_t halt_bit_t; 993 994 /* 995 * Setup Packet 996 */ 997 typedef struct setup_pkt { 998 uchar_t bmRequestType; 999 uchar_t bRequest; 1000 ushort_t wValue; 1001 ushort_t wIndex; 1002 ushort_t wLength; 1003 }setup_pkt_t; 1004 1005 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 1006 1007 #define REQUEST_TYPE_OFFSET 0 1008 #define REQUEST_OFFSET 1 1009 #define VALUE_OFFSET 2 1010 #define INDEX_OFFSET 4 1011 #define LENGTH_OFFSET 6 1012 1013 #define TYPE_DEV_TO_HOST 0x80000000 1014 #define DEVICE 0x00000001 1015 #define CONFIGURATION 0x00000002 1016 1017 /* 1018 * The following are used in attach to indicate 1019 * what has been succesfully allocated, so detach 1020 * can remove them. 1021 */ 1022 #define EHCI_ATTACH 0x01 /* ehci driver initilization */ 1023 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */ 1024 #define EHCI_INTR 0x04 /* Interrupt handler registered */ 1025 #define EHCI_USBAREG 0x08 /* USBA registered */ 1026 #define EHCI_RHREG 0x10 /* Root hub driver loaded */ 1027 1028 /* 1029 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase 1030 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to 1031 * make sure that EHCI is receiving interrupts. 1032 */ 1033 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */ 1034 1035 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 1036 1037 /* 1038 * Debug printing 1039 * Masks 1040 */ 1041 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 1042 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 1043 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 1044 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 1045 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 1046 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 1047 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 1048 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 1049 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */ 1050 #define PRINT_MASK_ALL 0xFFFFFFFF 1051 1052 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */ 1053 #define PCI_DEVICE_NVIDIA_CK804 0x5b 1054 #define PCI_DEVICE_NVIDIA_MCP04 0x3c 1055 /* 1056 * workaround for ALI chips 1057 */ 1058 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */ 1059 1060 /* 1061 * NEC on COMBO and Uli M1575 can support PM 1062 */ 1063 #define PCI_VENDOR_NEC_COMBO 0x1033 1064 #define PCI_DEVICE_NEC_COMBO 0xe0 1065 #define PCI_VENDOR_ULi_M1575 0x10b9 1066 #define PCI_DEVICE_ULi_M1575 0x5239 1067 1068 /* 1069 * VIA chips have some problems, the workaround can ensure those chips 1070 * work reliably. Revisions >= 0x80 are part of a southbridge and appear 1071 * to be reliable. 1072 */ 1073 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */ 1074 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */ 1075 1076 #define EHCI_VIA_LOST_INTERRUPTS 0x01 1077 #define EHCI_VIA_ASYNC_SCHEDULE 0x02 1078 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04 1079 1080 #define EHCI_VIA_WORKAROUNDS \ 1081 (EHCI_VIA_LOST_INTERRUPTS | \ 1082 EHCI_VIA_ASYNC_SCHEDULE | \ 1083 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE) 1084 1085 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */ 1086 1087 1088 /* 1089 * EHCI HCDI entry points 1090 * 1091 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 1092 * between the Universal Serial Bus Driver (USBA) and the Host Controller 1093 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 1094 */ 1095 int ehci_hcdi_pipe_open( 1096 usba_pipe_handle_data_t *ph, 1097 usb_flags_t usb_flags); 1098 int ehci_hcdi_pipe_close( 1099 usba_pipe_handle_data_t *ph, 1100 usb_flags_t usb_flags); 1101 int ehci_hcdi_pipe_reset( 1102 usba_pipe_handle_data_t *ph, 1103 usb_flags_t usb_flags); 1104 void ehci_hcdi_pipe_reset_data_toggle( 1105 usba_pipe_handle_data_t *ph); 1106 int ehci_hcdi_pipe_ctrl_xfer( 1107 usba_pipe_handle_data_t *ph, 1108 usb_ctrl_req_t *ctrl_reqp, 1109 usb_flags_t usb_flags); 1110 int ehci_hcdi_bulk_transfer_size( 1111 usba_device_t *usba_device, 1112 size_t *size); 1113 int ehci_hcdi_pipe_bulk_xfer( 1114 usba_pipe_handle_data_t *ph, 1115 usb_bulk_req_t *bulk_reqp, 1116 usb_flags_t usb_flags); 1117 int ehci_hcdi_pipe_intr_xfer( 1118 usba_pipe_handle_data_t *ph, 1119 usb_intr_req_t *intr_req, 1120 usb_flags_t usb_flags); 1121 int ehci_hcdi_pipe_stop_intr_polling( 1122 usba_pipe_handle_data_t *ph, 1123 usb_flags_t usb_flags); 1124 int ehci_hcdi_get_current_frame_number( 1125 usba_device_t *usba_device, 1126 usb_frame_number_t *frame_number); 1127 int ehci_hcdi_get_max_isoc_pkts( 1128 usba_device_t *usba_device, 1129 uint_t *max_isoc_pkts_per_request); 1130 int ehci_hcdi_pipe_isoc_xfer( 1131 usba_pipe_handle_data_t *ph, 1132 usb_isoc_req_t *isoc_reqp, 1133 usb_flags_t usb_flags); 1134 int ehci_hcdi_pipe_stop_isoc_polling( 1135 usba_pipe_handle_data_t *ph, 1136 usb_flags_t usb_flags); 1137 1138 /* 1139 * EHCI Polled entry points function prototypes. 1140 */ 1141 int ehci_hcdi_polled_input_init( 1142 usba_pipe_handle_data_t *ph, 1143 uchar_t **polled_buf, 1144 usb_console_info_impl_t *info); 1145 int ehci_hcdi_polled_input_enter( 1146 usb_console_info_impl_t *info); 1147 int ehci_hcdi_polled_read( 1148 usb_console_info_impl_t *info, 1149 uint_t *num_characters); 1150 int ehci_hcdi_polled_input_exit( 1151 usb_console_info_impl_t *info); 1152 int ehci_hcdi_polled_input_fini( 1153 usb_console_info_impl_t *info); 1154 int ehci_hcdi_polled_output_init( 1155 usba_pipe_handle_data_t *ph, 1156 usb_console_info_impl_t *console_output_info); 1157 int ehci_hcdi_polled_output_enter( 1158 usb_console_info_impl_t *info); 1159 int ehci_hcdi_polled_write( 1160 usb_console_info_impl_t *info, 1161 uchar_t *buf, 1162 uint_t num_characters, 1163 uint_t *num_characters_written); 1164 int ehci_hcdi_polled_output_exit( 1165 usb_console_info_impl_t *info); 1166 int ehci_hcdi_polled_output_fini( 1167 usb_console_info_impl_t *info); 1168 /* 1169 * EHCI Root Hub entry points function prototypes. 1170 */ 1171 int ehci_init_root_hub( 1172 ehci_state_t *ehcip); 1173 int ehci_load_root_hub_driver( 1174 ehci_state_t *ehcip); 1175 int ehci_unload_root_hub_driver( 1176 ehci_state_t *ehcip); 1177 int ehci_handle_root_hub_pipe_open( 1178 usba_pipe_handle_data_t *ph, 1179 usb_flags_t flags); 1180 int ehci_handle_root_hub_pipe_close( 1181 usba_pipe_handle_data_t *ph); 1182 int ehci_handle_root_hub_pipe_reset( 1183 usba_pipe_handle_data_t *ph, 1184 usb_flags_t flags); 1185 int ehci_handle_root_hub_request( 1186 ehci_state_t *ehcip, 1187 usba_pipe_handle_data_t *ph, 1188 usb_ctrl_req_t *ctrl_reqp); 1189 int ehci_handle_root_hub_pipe_start_intr_polling( 1190 usba_pipe_handle_data_t *ph, 1191 usb_intr_req_t *intr_reqp, 1192 usb_flags_t flags); 1193 void ehci_handle_root_hub_pipe_stop_intr_polling( 1194 usba_pipe_handle_data_t *ph, 1195 usb_flags_t flags); 1196 1197 /* 1198 * EHCI Interrupt Handler entry point. 1199 */ 1200 uint_t ehci_intr(caddr_t arg1, 1201 caddr_t arg2); 1202 1203 #ifdef __cplusplus 1204 } 1205 #endif 1206 1207 #endif /* _SYS_USB_EHCID_H */ 1208