1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_EHCID_H 27 #define _SYS_USB_EHCID_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Enchanced Host Controller Driver (EHCI) 37 * 38 * The EHCI driver is a software driver which interfaces to the Universal 39 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 40 * the Host Controller is defined by the EHCI Host Controller Interface. 41 * 42 * This header file describes the data structures and function prototypes 43 * required for the EHCI Driver to maintain state of Host Controller (HC), 44 * to perform different USB transfers and for the bandwidth allocations. 45 */ 46 47 #include <sys/usb/hcd/ehci/ehci.h> 48 #include <sys/usb/hcd/ehci/ehci_hub.h> 49 50 51 /* 52 * EHCI Bandwidth Maintainence Structure. 53 * 54 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci 55 * host controller. There are 32 bandwidth lists corresponding to 32 ms 56 * periodic frame lists. Each bandwidth list inturn will contain eight 57 * micro frame bandwidth lists. 58 */ 59 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */ 60 61 typedef struct ehci_frame_bandwidth { 62 uint_t ehci_allocated_frame_bandwidth; 63 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES]; 64 } ehci_frame_bandwidth_t; 65 66 67 /* 68 * EHCI Host Controller state structure 69 * 70 * The Host Controller Driver (HCD) maintains the state of Host Controller 71 * (HC). There is an ehci_state structure per instance of the EHCI 72 * host controller. 73 */ 74 typedef struct ehci_state { 75 dev_info_t *ehci_dip; /* Dip of HC */ 76 uint_t ehci_instance; 77 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */ 78 uint_t ehci_flags; /* Used for cleanup */ 79 uint16_t ehci_vendor_id; /* chip vendor */ 80 uint16_t ehci_device_id; /* chip device */ 81 uint8_t ehci_rev_id; /* chip revison */ 82 83 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */ 84 ehci_caps_t *ehci_capsp; /* Capability Regs */ 85 ehci_regs_t *ehci_regsp; /* Operational Regs */ 86 87 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */ 88 uint_t ehci_frame_interval; /* Frme inter reg */ 89 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */ 90 91 ddi_intr_handle_t *ehci_htable; /* intr handle */ 92 int ehci_intr_type; /* intr type used */ 93 int ehci_intr_cnt; /* # of intrs inuse */ 94 uint_t ehci_intr_pri; /* intr priority */ 95 int ehci_intr_cap; /* intr capabilities */ 96 boolean_t ehci_msi_enabled; /* default to true */ 97 kmutex_t ehci_int_mutex; /* Global EHCI mutex */ 98 99 /* Periodic Frame List area */ 100 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep; 101 /* Virtual Periodic Frame List ptr */ 102 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */ 103 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */ 104 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */ 105 106 /* 107 * There are two pools of memory. One pool contains the memory for 108 * the transfer descriptors and other pool contains the memory for 109 * the endpoint descriptors. The advantage of the pools is that it's 110 * easy to go back and forth between the iommu and the cpu addresses. 111 * 112 * The pools are protected by the ehci_int_mutex because the memory 113 * in the pools may be accessed by either the host controller or the 114 * host controller driver. 115 */ 116 117 /* Endpoint descriptor pool */ 118 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */ 119 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */ 120 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */ 121 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */ 122 uint_t ehci_dma_addr_bind_flag; /* DMA flag */ 123 124 /* General transfer descriptor pool */ 125 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */ 126 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */ 127 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */ 128 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */ 129 130 /* Isochronous transfer descriptor pool */ 131 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */ 132 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */ 133 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */ 134 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */ 135 136 /* Condition variable for advance on Asynchronous Schedule */ 137 kcondvar_t ehci_async_schedule_advance_cv; 138 139 /* Head of Asynchronous Schedule List */ 140 ehci_qh_t *ehci_head_of_async_sched_list; 141 142 /* 143 * List of QTD inserted either into Asynchronous or Periodic 144 * Schedule lists. 145 */ 146 ehci_qtd_t *ehci_active_qtd_list; 147 /* 148 * List of ITD active itd list. 149 */ 150 ehci_itd_t *ehci_active_itd_list; 151 152 /* 153 * Bandwidth fields 154 * 155 * The ehci_bandwidth array keeps track of allocated bandwidth for 156 * ehci host controller. There are 32 bandwidth lists corresponding 157 * to 32 ms periodic frame lists. Each bandwidth list in turn will 158 * contain eight micro frame bandwidth lists. 159 * 160 * ehci_min_frame_bandwidth field indicates least allocated milli 161 * second bandwidth list. 162 */ 163 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS]; 164 165 /* No. of open pipes, async qh, and periodic qh */ 166 uint_t ehci_open_pipe_count; 167 uint_t ehci_open_async_count; 168 uint_t ehci_open_periodic_count; 169 170 /* 171 * Endpoint Reclamation List 172 * 173 * The interrupt list processing cannot be stopped when a periodic 174 * endpoint is removed from the list. The endpoints are detached 175 * from the interrupt lattice tree and put on to the reclaimation 176 * list. On next SOF interrupt all those endpoints, which are on 177 * the reclaimation list will be deallocated. 178 */ 179 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */ 180 181 ehci_root_hub_t ehci_root_hub; /* Root hub info */ 182 183 /* Frame number overflow information */ 184 usb_frame_number_t ehci_fno; 185 186 /* For host controller error counter */ 187 uint_t ehci_hc_error; 188 189 /* 190 * ehci_missed_intr_sts is used to save the normal mode interrupt 191 * status information if an interrupt is pending for normal mode 192 * when polled code is entered. 193 */ 194 uint_t ehci_missed_intr_sts; 195 196 /* 197 * Saved copy of the ehci registers of the normal mode & change 198 * required ehci registers values for the polled mode operation. 199 * Before returning from the polled mode to normal mode replace 200 * the required current registers with this saved ehci registers 201 * copy. 202 */ 203 ehci_regs_t ehci_polled_save_regs; 204 205 /* 206 * Saved copy of the interrupt table used in normal ehci mode and 207 * replace this table by another interrupt table that used in the 208 * POLLED mode. 209 */ 210 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS]; 211 212 /* ehci polled mode enter counter */ 213 uint_t ehci_polled_enter_count; 214 215 /* 216 * counter for polled mode and used in suspend mode to see if 217 * there is a keyboard connected. 218 */ 219 uint_t ehci_polled_kbd_count; 220 221 /* counter for polled read and use it to clean the interrupt status */ 222 uint_t ehci_polled_read_count; 223 224 #if defined(__x86) 225 /* counter for polled root hub status */ 226 uint_t ehci_polled_root_hub_count; 227 #endif /* __x86 */ 228 229 /* EHCI Host Controller Software State information */ 230 uint_t ehci_hc_soft_state; 231 232 /* Log handle for debug, console, log messages */ 233 usb_log_handle_t ehci_log_hdl; 234 235 /* Kstat structures */ 236 kstat_t *ehci_intrs_stats; 237 kstat_t *ehci_total_stats; 238 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS]; 239 } ehci_state_t; 240 241 typedef struct ehci_intrs_stats { 242 struct kstat_named ehci_sts_async_sched_status; 243 struct kstat_named ehci_sts_periodic_sched_status; 244 struct kstat_named ehci_sts_empty_async_schedule; 245 struct kstat_named ehci_sts_host_ctrl_halted; 246 struct kstat_named ehci_sts_async_advance_intr; 247 struct kstat_named ehci_sts_host_system_error_intr; 248 struct kstat_named ehci_sts_frm_list_rollover_intr; 249 struct kstat_named ehci_sts_rh_port_change_intr; 250 struct kstat_named ehci_sts_usb_error_intr; 251 struct kstat_named ehci_sts_usb_intr; 252 struct kstat_named ehci_sts_not_claimed; 253 struct kstat_named ehci_sts_total; 254 } ehci_intrs_stats_t; 255 256 /* 257 * ehci kstat defines 258 */ 259 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats) 260 #define EHCI_INTRS_STATS_DATA(ehci) \ 261 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data) 262 263 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats) 264 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats)) 265 #define EHCI_CTRL_STATS(ehci) \ 266 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL])) 267 #define EHCI_BULK_STATS(ehci) \ 268 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK])) 269 #define EHCI_INTR_STATS(ehci) \ 270 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR])) 271 #define EHCI_ISOC_STATS(ehci) \ 272 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH])) 273 274 /* warlock directives, stable data */ 275 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t)) 276 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri)) 277 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip)) 278 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp)) 279 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance)) 280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id)) 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id)) 282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id)) 283 284 /* this may not be stable data in the future */ 285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr)) 286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle)) 287 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie)) 288 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr)) 289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle)) 290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie)) 291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr)) 292 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle)) 293 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie)) 294 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag)) 295 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl)) 296 297 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \ 298 usba_pipe_handle_data::p_mutex \ 299 usba_device::usb_mutex \ 300 usba_ph_impl::usba_ph_mutex)) 301 302 /* 303 * Host Contoller Software States 304 * 305 * EHCI_CTLR_INIT_STATE: 306 * The host controller soft state will be set to this during the 307 * ehci_attach. 308 * 309 * EHCI_CTLR_SUSPEND_STATE: 310 * The host controller soft state will be set to this during the 311 * ehci_cpr_suspend. 312 * 313 * EHCI_CTLR_OPERATIONAL_STATE: 314 * The host controller soft state will be set to this after moving 315 * host controller to operational state and host controller start 316 * generating SOF successfully. 317 * 318 * EHCI_CTLR_ERROR_STATE: 319 * The host controller soft state will be set to this during the 320 * no SOF or UE error conditions. 321 * 322 * Under this state or condition, only pipe stop polling, pipe reset 323 * and pipe close are allowed. But all other entry points like pipe 324 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 325 * isoch send/receive, start polling etc. will fail. 326 * 327 * State Diagram for the host controller software state 328 * 329 * 330 * ehci_attach->[INIT_STATE] 331 * | 332 * | -------->----[ERROR_STATE]--<-----------<--- 333 * | | Failure (UE/no SOF condition) | 334 * | ^ ^ 335 * V | Success | 336 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling 337 * ^ | 338 * | | 339 * | V 340 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend 341 */ 342 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */ 343 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 344 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 345 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 346 347 /* 348 * Flags for initializatoin of host controller 349 */ 350 #define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */ 351 #define EHCI_REINITIALIZATION 1 /* Re-initialization */ 352 353 /* 354 * Periodic and non-periodic macros 355 */ 356 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 357 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 358 ((endpoint->bmAttributes &\ 359 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 360 361 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 362 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 363 ((endpoint->bmAttributes &\ 364 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 365 366 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 367 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 368 369 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 370 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR)) 371 372 373 /* 374 * EHCI QH and QTD Pool sizes. 375 */ 376 #define EHCI_QH_POOL_SIZE 100 377 #define EHCI_QTD_POOL_SIZE 200 378 #define EHCI_ITD_POOL_SIZE 200 379 380 /* 381 * ehci_dma_addr_bind_flag values 382 * 383 * This flag indicates if the various DMA addresses allocated by the EHCI 384 * have been bound to their respective handles. This is needed to recover 385 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle() 386 */ 387 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */ 388 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */ 389 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */ 390 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */ 391 392 /* 393 * Maximum SOF wait count 394 */ 395 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 396 397 /* 398 * One uFrame 125 micro seconds 399 * One Frame 1 milli second or 8 uFrames 400 */ 401 #define EHCI_uFRAMES_PER_USB_FRAME 8 402 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3 403 404 405 /* 406 * Pipe private structure 407 * 408 * There is an instance of this structure per pipe. This structure holds 409 * HCD specific pipe information. A pointer to this structure is kept in 410 * the USBA pipe handle (usba_pipe_handle_data_t). 411 */ 412 typedef struct ehci_pipe_private { 413 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 414 ehci_qh_t *pp_qh; /* Pipe's qh */ 415 416 /* State of the pipe */ 417 uint_t pp_state; /* See below */ 418 419 /* Local copy of the pipe policy */ 420 usb_pipe_policy_t pp_policy; 421 422 /* For Periodic Pipes Only */ 423 uint_t pp_pnode; /* periodic node */ 424 uchar_t pp_smask; /* Start split mask */ 425 uchar_t pp_cmask; /* Comp split mask */ 426 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 427 uint_t pp_max_periodic_req_cnt; /* Max req count */ 428 429 /* For Isochronous pipes only */ 430 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 431 432 /* 433 * Each pipe may have multiple transfer wrappers. Each transfer 434 * wrapper represents a USB transfer on the bus. A transfer is 435 * made up of one or more transactions. 436 */ 437 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */ 438 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 439 440 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */ 441 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */ 442 443 /* 444 * Pipe's transfer timeout handling & this transfer timeout handling 445 * will be per pipe. 446 */ 447 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */ 448 timeout_id_t pp_timer_id; /* Timer id */ 449 450 /* Done td count */ 451 uint_t pp_count_done_qtds; /* Done td count */ 452 453 /* Errors */ 454 usb_cr_t pp_error; /* Pipe error */ 455 456 /* Condition variable for transfers completion event */ 457 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 458 459 /* Pipe flag */ 460 uint_t pp_flag; /* For polled mode */ 461 462 /* Halting States */ 463 uint_t pp_halt_state; /* Is it halting */ 464 465 /* Condition variable for halt completion event */ 466 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */ 467 468 /* 469 * HCD gets Interrupt/Isochronous IN polling request only once and 470 * it has to insert next polling requests after completion of first 471 * request until either stop polling/pipe close is called. So HCD 472 * has to take copy of the original Interrupt/Isochronous IN request. 473 */ 474 usb_opaque_t pp_client_periodic_in_reqp; 475 } ehci_pipe_private_t; 476 477 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t)) 478 479 /* 480 * Pipe states 481 * 482 * ehci pipe states will be similar to usba. Refer usbai.h. 483 */ 484 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 485 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 486 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 487 488 /* Additional ehci pipe states for the ehci_pipe_cleanup */ 489 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 490 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 491 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 492 493 /* 494 * Pipe flag 495 * 496 * For polled mode flag. 497 */ 498 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */ 499 500 /* Pipe specific flags */ 501 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 502 503 /* 504 * Halting States 505 * prevent halting from interleaving. 506 */ 507 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */ 508 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */ 509 510 /* 511 * Request values for Clear_TT_Buffer 512 */ 513 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \ 514 USB_DEV_REQ_RCPT_OTHER) 515 #define EHCI_CLEAR_TT_BUFFER_BREQ 8 516 517 /* 518 * USB frame offset 519 * 520 * Add appropriate frame offset to the current usb frame number and use it 521 * as a starting frame number for a given usb isochronous request. 522 */ 523 #define EHCI_FRAME_OFFSET 2 /* Frame offset */ 524 525 /* 526 * Different interrupt polling intervals supported for high speed 527 * devices and its range must be from 1 to 16 units. This value is 528 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval 529 * of 4 means a period of 8us (2 ^ (4-1)). 530 * 531 * The following values are defined after above convertion in terms 532 * 125us units. 533 */ 534 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */ 535 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */ 536 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */ 537 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */ 538 539 /* 540 * The following indecies are are used to calculate Start and complete 541 * masks as per the polling interval. 542 */ 543 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */ 544 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */ 545 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */ 546 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */ 547 548 /* 549 * Different interrupt polling intervals supported for low/full/high 550 * speed devices. For high speed devices, the following values are 551 * applicable after convertion. 552 */ 553 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */ 554 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */ 555 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */ 556 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */ 557 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */ 558 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */ 559 560 /* 561 * Number of interrupt transfer requests that should be maintained on 562 * the interrupt endpoint corresponding to different polling intervals 563 * supported. 564 */ 565 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */ 566 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */ 567 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 568 569 /* Function prototype */ 570 typedef void (*ehci_handler_function_t)( 571 ehci_state_t *ehcip, 572 ehci_pipe_private_t *pp, 573 struct ehci_trans_wrapper *tw, 574 ehci_qtd_t *qtd, 575 void *ehci_handle_callback_value); 576 577 578 /* 579 * Transfer wrapper 580 * 581 * The transfer wrapper represents a USB transfer on the bus and there 582 * is one instance per USB transfer. A transfer is made up of one or 583 * more transactions. EHCI uses one QTD for one transaction. So one 584 * transfer wrapper may have one or more QTDs associated. 585 * 586 * The data to be transferred are contained in the TW buffer which is 587 * virtually contiguous but physically discontiguous. When preparing 588 * the QTDs for a USB transfer, the DMA cookies corresponding to the 589 * TW buffer need to be walked through to retrieve the DMA addresses. 590 * 591 * Control and bulk pipes will have one transfer wrapper per transfer 592 * and where as Isochronous and Interrupt pipes will only have one 593 * transfer wrapper. The transfers wrapper are continually reused for 594 * the Interrupt and Isochronous pipes as those pipes are polled. 595 */ 596 typedef struct ehci_trans_wrapper { 597 struct ehci_trans_wrapper *tw_next; /* Next wrapper */ 598 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */ 599 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 600 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 601 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 602 uint_t tw_ncookies; /* DMA cookie count */ 603 uint_t tw_cookie_idx; /* DMA cookie index */ 604 size_t tw_dma_offs; /* DMA buffer offset */ 605 uint32_t tw_id; /* 32bit ID */ 606 size_t tw_length; /* Txfer length */ 607 char *tw_buf; /* Buffer for Xfer */ 608 usb_flags_t tw_flags; /* Flags */ 609 uint_t tw_num_qtds; /* Number of QTDs */ 610 ehci_qtd_t *tw_qtd_head; /* Head QTD */ 611 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */ 612 uint_t tw_direction; /* Direction of QTD */ 613 614 /* Current transfer request pointer */ 615 usb_opaque_t tw_curr_xfer_reqp; 616 617 /* Transfer timeout information */ 618 int tw_timeout; /* Timeout value */ 619 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 620 621 /* 622 * This is the function to call when this td is done. This way 623 * we don't have to look in the td to figure out what kind it is. 624 */ 625 ehci_handler_function_t tw_handle_qtd; 626 627 /* 628 * This is the callback value used when processing a done td. 629 */ 630 usb_opaque_t tw_handle_callback_value; 631 632 /* We preallocate all the td's for each tw and place them here */ 633 ehci_qtd_t *tw_qtd_free_list; 634 ehci_qtd_t *tw_alt_qtd; 635 } ehci_trans_wrapper_t; 636 637 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper)) 638 639 /* 640 * Isochronous Transfer Wrapper 641 * 642 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed 643 * isochronous transfers. A transfer wrapper consists of one or more 644 * transactionsl, but there is one one instance per USB transfer request. 645 * 646 * The isochrnous transfer wrapper are continiously reused because these 647 * pipes are polled. 648 */ 649 typedef struct ehci_isoc_xwrapper { 650 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */ 651 ehci_pipe_private_t *itw_pipe_private; 652 653 /* DMA and memory pointers */ 654 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */ 655 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */ 656 ddi_dma_cookie_t itw_cookie; /* DMA cookie */ 657 658 /* Transfer information */ 659 char *itw_buf; /* Buffer for Xfer */ 660 size_t itw_length; /* Txfer length */ 661 usb_flags_t itw_flags; /* Flags */ 662 usb_port_status_t itw_port_status; /* Port Speed */ 663 uint_t itw_direction; /* Direction of ITD */ 664 665 /* ITD information */ 666 uint_t itw_num_itds; /* Number of ITDs */ 667 ehci_itd_t *itw_itd_head; /* Head ITD */ 668 ehci_itd_t *itw_itd_tail; /* Tail ITD */ 669 usb_isoc_req_t *itw_curr_xfer_reqp; 670 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp; 671 672 /* We preallocate all the td's for each tw and place them here */ 673 ehci_itd_t *itw_itd_free_list; 674 675 /* Device and hub information needed by every iTD */ 676 uint_t itw_hub_addr; 677 uint_t itw_hub_port; 678 uint_t itw_endpoint_num; 679 uint_t itw_device_addr; 680 681 /* 682 * Callback handling function and arguement. Called when an iTD is 683 * is done. 684 */ 685 usb_opaque_t itw_handle_callback_value; 686 687 /* 32bit ID */ 688 uint32_t itw_id; 689 } ehci_isoc_xwrapper_t; 690 691 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t)) 692 693 /* 694 * Time waits for the different EHCI specific operations. 695 * These timeout values are specified in terms of microseconds. 696 */ 697 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 698 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */ 699 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */ 700 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */ 701 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */ 702 703 /* These timeout values are specified in seconds */ 704 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 705 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 706 707 /* EHCI flags for general use */ 708 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 709 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 710 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 711 712 /* 713 * Maximum allowable data transfer size per transaction as supported 714 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96) 715 * 716 * Also within QTD, there will be five buffer pointers abd each buffer 717 * pointer can transfer upto 4k bytes of data. 718 */ 719 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */ 720 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */ 721 722 /* 723 * The maximum allowable bulk data transfer size. It can be different 724 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will 725 * take care of breaking a bulk data request into multiples of ehci 726 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this 727 * value is set to 640k bytes. 728 */ 729 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */ 730 731 /* 732 * Timeout flags 733 * 734 * These flags will be used to stop the timer before timeout handler 735 * gets executed. 736 */ 737 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */ 738 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 739 740 741 /* 742 * High speed bandwidth allocation 743 * 744 * The following definitions are used during bandwidth calculations 745 * for a given high speed endpoint or high speed split transactions. 746 */ 747 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */ 748 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */ 749 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */ 750 #define HS_SOF 12 /* Length in bytes of High speed SOF */ 751 #define HS_EOF 70 /* Length in bytes of High speed EOF */ 752 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 753 754 /* 755 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved 756 * for the non-periodic high-speed transfers. Where as peridoic high-speed 757 * transfers will get 80% of the bus time. In one micro-frame or 125us, we 758 * can transfer 7500 bytes or 60,000 bits. 759 */ 760 #define HS_NON_PERIODIC_BANDWIDTH 1500 761 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \ 762 HS_EOF - HS_NON_PERIODIC_BANDWIDTH) 763 764 /* 765 * High speed periodic frame bandwidth will be eight times the micro frame 766 * high speed periodic bandwidth. 767 */ 768 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES 769 770 /* 771 * The following are the protocol overheads in terms of Bytes for the 772 * different transfer types. All these protocol overhead values are 773 * derived from the 5.11.3 section of USB 2.0 Specification. 774 */ 775 #define HS_NON_ISOC_PROTO_OVERHEAD 55 776 #define HS_ISOC_PROTO_OVERHEAD 38 777 778 /* 779 * The following are THE protocol overheads in terms of Bytes for the 780 * start and complete split transactions tokens overheads. All these 781 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3 782 * of USB2.0 Specification. 783 */ 784 #define START_SPLIT_OVERHEAD 04 785 #define COMPLETE_SPLIT_OVERHEAD 04 786 787 /* 788 * The Host Controller (HC) delays are the USB host controller specific 789 * delays. The value shown below is the host controller delay for the 790 * given EHCI host controller. 791 */ 792 #define EHCI_HOST_CONTROLLER_DELAY 18 793 794 /* 795 * Low/Full speed bandwidth allocation 796 * 797 * The following definitions are used during bandwidth calculations for 798 * a given high speed hub or a transaction translator (TT) and for a 799 * given low/full speed device connected to high speed hub or TT using 800 * split transactions 801 */ 802 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */ 803 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */ 804 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */ 805 #define FS_SOF 6 /* Length in bytes of Full speed SOF */ 806 #define FS_EOF 4 /* Length in bytes of Full speed EOF */ 807 808 /* 809 * Minimum polling interval for low speed endpoint 810 * 811 * According USB 2.0 Specification, a full-speed endpoint can specify 812 * a desired polling interval 1ms to 255ms and a low speed endpoints 813 * are limited to specifying only 10ms to 255ms. But some old keyboards 814 * and mice uses polling interval of 8ms. For compatibility purpose, 815 * we are using polling interval between 8ms and 255ms for low speed 816 * endpoints. The ehci driver will use 8ms polling interval if a low 817 * speed device reports a polling interval that is less than 8ms. 818 */ 819 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */ 820 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */ 821 822 /* 823 * For non-periodic transfers, reserve atleast for one low-speed device 824 * transaction. According to USB Bandwidth Analysis white paper and also 825 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 826 * transaction takes 0x628h full speed bits (197 bytes), which comes to 827 * around 13% of USB frame time. 828 * 829 * The periodic transfers will get around 87% of USB frame time. 830 */ 831 #define FS_NON_PERIODIC_BANDWIDTH 197 832 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \ 833 FS_EOF - FS_NON_PERIODIC_BANDWIDTH) 834 835 /* 836 * The following are the protocol overheads in terms of Bytes for the 837 * different transfer types. All these protocol overhead values are 838 * derived from the 5.11.3 section of USB Specification and with the 839 * help of Bandwidth Analysis white paper which is posted on the USB 840 * developer forum. 841 */ 842 #define FS_NON_ISOC_PROTO_OVERHEAD 14 843 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 844 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 845 #define LOW_SPEED_PROTO_OVERHEAD 97 846 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 847 848 /* The maximum amount of isoch data that can be transferred in one uFrame */ 849 #define MAX_UFRAME_SITD_XFER 188 850 851 /* 852 * The low speed clock below represents that to transmit one low-speed 853 * bit takes eight times more than one full speed bit time. 854 */ 855 #define LOW_SPEED_CLOCK 8 856 857 /* 858 * The Transaction Translator (TT) delay is the additional time needed 859 * to execute low/full speed transaction from high speed split transaction 860 * for the low/full device connected to the high speed extrenal hub. 861 */ 862 #define TT_DELAY 18 863 864 865 /* 866 * Macros for setting/getting information 867 */ 868 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \ 869 (uint32_t *)&addr) 870 871 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \ 872 ((uint32_t *)&addr), \ 873 ((int32_t)(val))) 874 875 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \ 876 (uint32_t *)&addr) 877 878 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \ 879 ((uint32_t *)&addr), \ 880 ((int32_t)(val))) 881 882 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \ 883 (uint32_t *)&addr) 884 885 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \ 886 ((uint32_t *)&addr), \ 887 ((int32_t)(val))) 888 889 #define Get_ITD_BODY(ptr, addr) ddi_get32( \ 890 ehcip->ehci_itd_pool_mem_handle, \ 891 (uint32_t *)&ptr->itd_body[addr]) 892 893 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \ 894 ehcip->ehci_itd_pool_mem_handle, \ 895 ((uint32_t *)&ptr->itd_body[addr]),\ 896 ((int32_t)(val))) 897 898 #define Get_ITD_INDEX(ptr, pos) ddi_get32( \ 899 ehcip->ehci_itd_pool_mem_handle, \ 900 (uint32_t *)&ptr->itd_index[pos]) 901 902 #define Set_ITD_INDEX(ptr, pos, val) ddi_put32( \ 903 ehcip->ehci_itd_pool_mem_handle, \ 904 ((uint32_t *)&ptr->itd_index[pos]),\ 905 ((uint32_t)(val))) 906 907 #define Get_ITD_FRAME(addr) ddi_get64( \ 908 ehcip->ehci_itd_pool_mem_handle, \ 909 (uint64_t *)&addr) 910 911 #define Set_ITD_FRAME(addr, val) ddi_put64( \ 912 ehcip->ehci_itd_pool_mem_handle, \ 913 ((uint64_t *)&addr), \ 914 (val)) 915 916 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \ 917 (uint32_t *)&addr) 918 919 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \ 920 ((uint32_t *)&addr), \ 921 ((int32_t)(uintptr_t)(val))) 922 923 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \ 924 (uint8_t *)&ehcip->ehci_capsp->addr) 925 926 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \ 927 (uint16_t *)&ehcip->ehci_capsp->addr) 928 929 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \ 930 (uint32_t *)&ehcip->ehci_capsp->addr) 931 932 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \ 933 (uint32_t *)&ehcip->ehci_regsp->addr) 934 935 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \ 936 ((uint32_t *)&ehcip->ehci_regsp->addr), \ 937 ((int32_t)(val))) 938 939 #define CalculateITDMultiField(pkgSize) (1 + (((pkgSize)>>11) & 0x03)) 940 941 #define EHCI_MAX_RETRY 10 942 943 #define Set_OpRegRetry(addr, val, r) \ 944 while (Get_OpReg(addr) != val) { \ 945 if (r >= EHCI_MAX_RETRY) \ 946 break; \ 947 r++; \ 948 Set_OpReg(addr, val); \ 949 } 950 951 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \ 952 ehcip->ehci_qh_pool_dma_handle, \ 953 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \ 954 DDI_DMA_SYNC_FORCPU); \ 955 (void) ddi_dma_sync( \ 956 ehcip->ehci_qtd_pool_dma_handle, \ 957 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \ 958 DDI_DMA_SYNC_FORCPU); 959 960 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \ 961 ehcip->ehci_itd_pool_dma_handle, \ 962 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \ 963 DDI_DMA_SYNC_FORCPU); 964 965 #define Sync_IO_Buffer(dma_handle, length) \ 966 (void) ddi_dma_sync(dma_handle, \ 967 0, length, DDI_DMA_SYNC_FORCPU); 968 969 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 970 (void) ddi_dma_sync(dma_handle, \ 971 0, length, DDI_DMA_SYNC_FORDEV); 972 973 /* 974 * Macros to speed handling of 32bit IDs 975 */ 976 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 977 #define EHCI_LOOKUP_ID(x) id32_lookup((x)) 978 #define EHCI_FREE_ID(x) id32_free((x)) 979 980 981 /* 982 * Miscellaneous definitions. 983 */ 984 985 /* Data toggle bits */ 986 #define DATA0 0 987 #define DATA1 1 988 989 /* Halt bit actions */ 990 #define CLEAR_HALT 0 991 #define SET_HALT 1 992 993 typedef uint_t halt_bit_t; 994 995 /* 996 * Setup Packet 997 */ 998 typedef struct setup_pkt { 999 uchar_t bmRequestType; 1000 uchar_t bRequest; 1001 ushort_t wValue; 1002 ushort_t wIndex; 1003 ushort_t wLength; 1004 }setup_pkt_t; 1005 1006 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 1007 1008 #define REQUEST_TYPE_OFFSET 0 1009 #define REQUEST_OFFSET 1 1010 #define VALUE_OFFSET 2 1011 #define INDEX_OFFSET 4 1012 #define LENGTH_OFFSET 6 1013 1014 #define TYPE_DEV_TO_HOST 0x80000000 1015 #define DEVICE 0x00000001 1016 #define CONFIGURATION 0x00000002 1017 1018 /* 1019 * The following are used in attach to indicate 1020 * what has been succesfully allocated, so detach 1021 * can remove them. 1022 */ 1023 #define EHCI_ATTACH 0x01 /* ehci driver initilization */ 1024 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */ 1025 #define EHCI_INTR 0x04 /* Interrupt handler registered */ 1026 #define EHCI_USBAREG 0x08 /* USBA registered */ 1027 #define EHCI_RHREG 0x10 /* Root hub driver loaded */ 1028 1029 /* 1030 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase 1031 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to 1032 * make sure that EHCI is receiving interrupts. 1033 */ 1034 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */ 1035 1036 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 1037 1038 /* 1039 * Debug printing 1040 * Masks 1041 */ 1042 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 1043 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 1044 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 1045 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 1046 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 1047 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 1048 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 1049 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 1050 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */ 1051 #define PRINT_MASK_ALL 0xFFFFFFFF 1052 1053 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */ 1054 #define PCI_DEVICE_NVIDIA_CK804 0x5b 1055 /* 1056 * workaround for ALI chips 1057 */ 1058 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */ 1059 1060 /* 1061 * NEC on COMBO and Uli M1575 can support PM 1062 */ 1063 #define PCI_VENDOR_NEC_COMBO 0x1033 1064 #define PCI_DEVICE_NEC_COMBO 0xe0 1065 #define PCI_VENDOR_ULi_M1575 0x10b9 1066 #define PCI_DEVICE_ULi_M1575 0x5239 1067 1068 /* 1069 * VIA chips have some problems, the workaround can ensure those chips 1070 * work reliably. Revisions >= 0x80 are part of a southbridge and appear 1071 * to be reliable. 1072 */ 1073 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */ 1074 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */ 1075 1076 #define EHCI_VIA_LOST_INTERRUPTS 0x01 1077 #define EHCI_VIA_ASYNC_SCHEDULE 0x02 1078 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04 1079 1080 #define EHCI_VIA_WORKAROUNDS \ 1081 (EHCI_VIA_LOST_INTERRUPTS | \ 1082 EHCI_VIA_ASYNC_SCHEDULE | \ 1083 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE) 1084 1085 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */ 1086 1087 1088 /* 1089 * EHCI HCDI entry points 1090 * 1091 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 1092 * between the Universal Serial Bus Driver (USBA) and the Host Controller 1093 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 1094 */ 1095 int ehci_hcdi_pipe_open( 1096 usba_pipe_handle_data_t *ph, 1097 usb_flags_t usb_flags); 1098 int ehci_hcdi_pipe_close( 1099 usba_pipe_handle_data_t *ph, 1100 usb_flags_t usb_flags); 1101 int ehci_hcdi_pipe_reset( 1102 usba_pipe_handle_data_t *ph, 1103 usb_flags_t usb_flags); 1104 int ehci_hcdi_pipe_ctrl_xfer( 1105 usba_pipe_handle_data_t *ph, 1106 usb_ctrl_req_t *ctrl_reqp, 1107 usb_flags_t usb_flags); 1108 int ehci_hcdi_bulk_transfer_size( 1109 usba_device_t *usba_device, 1110 size_t *size); 1111 int ehci_hcdi_pipe_bulk_xfer( 1112 usba_pipe_handle_data_t *ph, 1113 usb_bulk_req_t *bulk_reqp, 1114 usb_flags_t usb_flags); 1115 int ehci_hcdi_pipe_intr_xfer( 1116 usba_pipe_handle_data_t *ph, 1117 usb_intr_req_t *intr_req, 1118 usb_flags_t usb_flags); 1119 int ehci_hcdi_pipe_stop_intr_polling( 1120 usba_pipe_handle_data_t *ph, 1121 usb_flags_t usb_flags); 1122 int ehci_hcdi_get_current_frame_number( 1123 usba_device_t *usba_device, 1124 usb_frame_number_t *frame_number); 1125 int ehci_hcdi_get_max_isoc_pkts( 1126 usba_device_t *usba_device, 1127 uint_t *max_isoc_pkts_per_request); 1128 int ehci_hcdi_pipe_isoc_xfer( 1129 usba_pipe_handle_data_t *ph, 1130 usb_isoc_req_t *isoc_reqp, 1131 usb_flags_t usb_flags); 1132 int ehci_hcdi_pipe_stop_isoc_polling( 1133 usba_pipe_handle_data_t *ph, 1134 usb_flags_t usb_flags); 1135 1136 /* 1137 * EHCI Polled entry points function prototypes. 1138 */ 1139 int ehci_hcdi_polled_input_init( 1140 usba_pipe_handle_data_t *ph, 1141 uchar_t **polled_buf, 1142 usb_console_info_impl_t *info); 1143 int ehci_hcdi_polled_input_enter( 1144 usb_console_info_impl_t *info); 1145 int ehci_hcdi_polled_read( 1146 usb_console_info_impl_t *info, 1147 uint_t *num_characters); 1148 int ehci_hcdi_polled_input_exit( 1149 usb_console_info_impl_t *info); 1150 int ehci_hcdi_polled_input_fini( 1151 usb_console_info_impl_t *info); 1152 1153 /* 1154 * EHCI Root Hub entry points function prototypes. 1155 */ 1156 int ehci_init_root_hub( 1157 ehci_state_t *ehcip); 1158 int ehci_load_root_hub_driver( 1159 ehci_state_t *ehcip); 1160 int ehci_unload_root_hub_driver( 1161 ehci_state_t *ehcip); 1162 int ehci_handle_root_hub_pipe_open( 1163 usba_pipe_handle_data_t *ph, 1164 usb_flags_t flags); 1165 int ehci_handle_root_hub_pipe_close( 1166 usba_pipe_handle_data_t *ph); 1167 int ehci_handle_root_hub_pipe_reset( 1168 usba_pipe_handle_data_t *ph, 1169 usb_flags_t flags); 1170 int ehci_handle_root_hub_request( 1171 ehci_state_t *ehcip, 1172 usba_pipe_handle_data_t *ph, 1173 usb_ctrl_req_t *ctrl_reqp); 1174 int ehci_handle_root_hub_pipe_start_intr_polling( 1175 usba_pipe_handle_data_t *ph, 1176 usb_intr_req_t *intr_reqp, 1177 usb_flags_t flags); 1178 void ehci_handle_root_hub_pipe_stop_intr_polling( 1179 usba_pipe_handle_data_t *ph, 1180 usb_flags_t flags); 1181 1182 /* 1183 * EHCI Interrupt Handler entry point. 1184 */ 1185 uint_t ehci_intr(caddr_t arg1, 1186 caddr_t arg2); 1187 1188 #ifdef __cplusplus 1189 } 1190 #endif 1191 1192 #endif /* _SYS_USB_EHCID_H */ 1193