xref: /illumos-gate/usr/src/uts/common/sys/smbios.h (revision 516627f338a630bcf9806a91aa873bbbae9a2fac)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
24  * Copyright 2015 Joyent, Inc.
25  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
26  * Use is subject to license terms.
27  */
28 
29 /*
30  * This header file defines the interfaces available from the SMBIOS access
31  * library, libsmbios, and an equivalent kernel module.  This API can be used
32  * to access DMTF SMBIOS data from a device, file, or raw memory buffer.
33  *
34  * This is NOT a Public interface, and should be considered Unstable, as it is
35  * subject to change without notice as the DMTF SMBIOS specification evolves.
36  * Therefore, be aware that any program linked with this API in this
37  * instance of illumos is almost guaranteed to break in the next release.
38  */
39 
40 #ifndef	_SYS_SMBIOS_H
41 #define	_SYS_SMBIOS_H
42 
43 #include <sys/types.h>
44 
45 #ifdef	__cplusplus
46 extern "C" {
47 #endif
48 
49 /*
50  * SMBIOS Structure Table Entry Point.  See DSP0134 5.2.1 for more information.
51  * The structure table entry point is located by searching for the anchor.
52  */
53 #pragma pack(1)
54 
55 typedef struct smbios_entry {
56 	char smbe_eanchor[4];		/* anchor tag (SMB_ENTRY_EANCHOR) */
57 	uint8_t smbe_ecksum;		/* checksum of entry point structure */
58 	uint8_t smbe_elen;		/* length in bytes of entry point */
59 	uint8_t smbe_major;		/* major version of the SMBIOS spec */
60 	uint8_t smbe_minor;		/* minor version of the SMBIOS spec */
61 	uint16_t smbe_maxssize;		/* maximum size in bytes of a struct */
62 	uint8_t smbe_revision;		/* entry point structure revision */
63 	uint8_t smbe_format[5];		/* entry point revision-specific data */
64 	char smbe_ianchor[5];		/* intermed. tag (SMB_ENTRY_IANCHOR) */
65 	uint8_t smbe_icksum;		/* intermed. checksum */
66 	uint16_t smbe_stlen;		/* length in bytes of structure table */
67 	uint32_t smbe_staddr;		/* physical addr of structure table */
68 	uint16_t smbe_stnum;		/* number of structure table entries */
69 	uint8_t smbe_bcdrev;		/* BCD value representing DMI version */
70 } smbios_entry_t;
71 
72 #pragma pack()
73 
74 #define	SMB_ENTRY_EANCHOR	"_SM_"	/* structure table entry point anchor */
75 #define	SMB_ENTRY_EANCHORLEN	4	/* length of entry point anchor */
76 #define	SMB_ENTRY_IANCHOR	"_DMI_"	/* intermediate anchor string */
77 #define	SMB_ENTRY_IANCHORLEN	5	/* length of intermediate anchor */
78 #define	SMB_ENTRY_MAXLEN	255	/* maximum length of entry point */
79 
80 /*
81  * Structure type codes.  The comments next to each type include an (R) note to
82  * indicate a structure that is required as of SMBIOS v2.8 and an (O) note to
83  * indicate a structure that is obsolete as of SMBIOS v2.8.
84  */
85 #define	SMB_TYPE_BIOS		0	/* BIOS information (R) */
86 #define	SMB_TYPE_SYSTEM		1	/* system information (R) */
87 #define	SMB_TYPE_BASEBOARD	2	/* base board */
88 #define	SMB_TYPE_CHASSIS	3	/* system enclosure or chassis (R) */
89 #define	SMB_TYPE_PROCESSOR	4	/* processor (R) */
90 #define	SMB_TYPE_MEMCTL		5	/* memory controller (O) */
91 #define	SMB_TYPE_MEMMOD		6	/* memory module (O) */
92 #define	SMB_TYPE_CACHE		7	/* processor cache (R) */
93 #define	SMB_TYPE_PORT		8	/* port connector */
94 #define	SMB_TYPE_SLOT		9	/* upgradeable system slot (R) */
95 #define	SMB_TYPE_OBDEVS		10	/* on-board devices (O) */
96 #define	SMB_TYPE_OEMSTR		11	/* OEM string table */
97 #define	SMB_TYPE_SYSCONFSTR	12	/* system configuration string table */
98 #define	SMB_TYPE_LANG		13	/* BIOS language information */
99 #define	SMB_TYPE_GROUP		14	/* group associations */
100 #define	SMB_TYPE_EVENTLOG	15	/* system event log */
101 #define	SMB_TYPE_MEMARRAY	16	/* physical memory array (R) */
102 #define	SMB_TYPE_MEMDEVICE	17	/* memory device (R) */
103 #define	SMB_TYPE_MEMERR32	18	/* 32-bit memory error information */
104 #define	SMB_TYPE_MEMARRAYMAP	19	/* memory array mapped address (R) */
105 #define	SMB_TYPE_MEMDEVICEMAP	20	/* memory device mapped address */
106 #define	SMB_TYPE_POINTDEV	21	/* built-in pointing device */
107 #define	SMB_TYPE_BATTERY	22	/* portable battery */
108 #define	SMB_TYPE_RESET		23	/* system reset settings */
109 #define	SMB_TYPE_SECURITY	24	/* hardware security settings */
110 #define	SMB_TYPE_POWERCTL	25	/* system power controls */
111 #define	SMB_TYPE_VPROBE		26	/* voltage probe */
112 #define	SMB_TYPE_COOLDEV	27	/* cooling device */
113 #define	SMB_TYPE_TPROBE		28	/* temperature probe */
114 #define	SMB_TYPE_IPROBE		29	/* current probe */
115 #define	SMB_TYPE_OOBRA		30	/* out-of-band remote access facility */
116 #define	SMB_TYPE_BIS		31	/* boot integrity services */
117 #define	SMB_TYPE_BOOT		32	/* system boot status (R) */
118 #define	SMB_TYPE_MEMERR64	33	/* 64-bit memory error information */
119 #define	SMB_TYPE_MGMTDEV	34	/* management device */
120 #define	SMB_TYPE_MGMTDEVCP	35	/* management device component */
121 #define	SMB_TYPE_MGMTDEVDATA	36	/* management device threshold data */
122 #define	SMB_TYPE_MEMCHAN	37	/* memory channel */
123 #define	SMB_TYPE_IPMIDEV	38	/* IPMI device information */
124 #define	SMB_TYPE_POWERSUP	39	/* system power supply */
125 #define	SMB_TYPE_ADDINFO	40	/* additional information */
126 #define	SMB_TYPE_OBDEVEXT	41	/* on-board device extended info */
127 #define	SMB_TYPE_MCHI		42	/* mgmt controller host interface */
128 #define	SMB_TYPE_INACTIVE	126	/* inactive table entry */
129 #define	SMB_TYPE_EOT		127	/* end of table */
130 
131 #define	SMB_TYPE_OEM_LO		128	/* start of OEM-specific type range */
132 #define	SUN_OEM_EXT_PROCESSOR	132	/* processor extended info */
133 #define	SUN_OEM_EXT_PORT	136	/* port exteded info */
134 #define	SUN_OEM_PCIEXRC		138	/* PCIE RootComplex/RootPort info */
135 #define	SUN_OEM_EXT_MEMARRAY	144	/* phys memory array extended info */
136 #define	SUN_OEM_EXT_MEMDEVICE	145	/* memory device extended info */
137 #define	SMB_TYPE_OEM_HI		256	/* end of OEM-specific type range */
138 
139 /*
140  * OEM string indicating "Platform Resource Management Specification"
141  * compliance.
142  */
143 #define	SMB_PRMS1	"SUNW-PRMS-1"
144 
145 /*
146  * Some default values set by BIOS vendor
147  */
148 #define	SMB_DEFAULT1	"To Be Filled By O.E.M."
149 #define	SMB_DEFAULT2	"Not Available"
150 
151 /*
152  * SMBIOS Common Information.  These structures do not correspond to anything
153  * in the SMBIOS specification, but allow library clients to more easily read
154  * information that is frequently encoded into the various SMBIOS structures.
155  */
156 typedef struct smbios_info {
157 	const char *smbi_manufacturer;	/* manufacturer */
158 	const char *smbi_product;	/* product name */
159 	const char *smbi_version;	/* version */
160 	const char *smbi_serial;	/* serial number */
161 	const char *smbi_asset;		/* asset tag */
162 	const char *smbi_location;	/* location tag */
163 	const char *smbi_part;		/* part number */
164 } smbios_info_t;
165 
166 typedef struct smbios_version {
167 	uint8_t smbv_major;		/* version major number */
168 	uint8_t smbv_minor;		/* version minor number */
169 } smbios_version_t;
170 
171 #define	SMB_CONT_BYTE	1		/* contained elements are byte size */
172 #define	SMB_CONT_WORD	2		/* contained elements are word size */
173 #define	SMB_CONT_MAX	255		/* maximum contained objects */
174 
175 /*
176  * SMBIOS Bios Information.  See DSP0134 Section 7.1 for more information.
177  * smbb_romsize is converted from the implementation format into bytes.
178  */
179 typedef struct smbios_bios {
180 	const char *smbb_vendor;	/* bios vendor string */
181 	const char *smbb_version;	/* bios version string */
182 	const char *smbb_reldate;	/* bios release date */
183 	uint32_t smbb_segment;		/* bios address segment location */
184 	uint32_t smbb_romsize;		/* bios rom size in bytes */
185 	uint32_t smbb_runsize;		/* bios image size in bytes */
186 	uint64_t smbb_cflags;		/* bios characteristics */
187 	const uint8_t *smbb_xcflags;	/* bios characteristics extensions */
188 	size_t smbb_nxcflags;		/* number of smbb_xcflags[] bytes */
189 	smbios_version_t smbb_biosv;	/* bios version */
190 	smbios_version_t smbb_ecfwv;	/* bios embedded ctrl f/w version */
191 } smbios_bios_t;
192 
193 #define	SMB_BIOSFL_RSV0		0x00000001	/* reserved bit zero */
194 #define	SMB_BIOSFL_RSV1		0x00000002	/* reserved bit one */
195 #define	SMB_BIOSFL_UNKNOWN	0x00000004	/* unknown */
196 #define	SMB_BIOSFL_BCNOTSUP	0x00000008	/* BIOS chars not supported */
197 #define	SMB_BIOSFL_ISA		0x00000010	/* ISA is supported */
198 #define	SMB_BIOSFL_MCA		0x00000020	/* MCA is supported */
199 #define	SMB_BIOSFL_EISA		0x00000040	/* EISA is supported */
200 #define	SMB_BIOSFL_PCI		0x00000080	/* PCI is supported */
201 #define	SMB_BIOSFL_PCMCIA	0x00000100	/* PCMCIA is supported */
202 #define	SMB_BIOSFL_PLUGNPLAY	0x00000200	/* Plug and Play is supported */
203 #define	SMB_BIOSFL_APM		0x00000400	/* APM is supported */
204 #define	SMB_BIOSFL_FLASH	0x00000800	/* BIOS is Flash Upgradeable */
205 #define	SMB_BIOSFL_SHADOW	0x00001000	/* BIOS shadowing is allowed */
206 #define	SMB_BIOSFL_VLVESA	0x00002000	/* VL-VESA is supported */
207 #define	SMB_BIOSFL_ESCD		0x00004000	/* ESCD support is available */
208 #define	SMB_BIOSFL_CDBOOT	0x00008000	/* Boot from CD is supported */
209 #define	SMB_BIOSFL_SELBOOT	0x00010000	/* Selectable Boot supported */
210 #define	SMB_BIOSFL_ROMSOCK	0x00020000	/* BIOS ROM is socketed */
211 #define	SMB_BIOSFL_PCMBOOT	0x00040000	/* Boot from PCMCIA supported */
212 #define	SMB_BIOSFL_EDD		0x00080000	/* EDD Spec is supported */
213 #define	SMB_BIOSFL_NEC9800	0x00100000	/* int 0x13 NEC 9800 floppy */
214 #define	SMB_BIOSFL_TOSHIBA	0x00200000	/* int 0x13 Toshiba floppy */
215 #define	SMB_BIOSFL_525_360K	0x00400000	/* int 0x13 5.25" 360K floppy */
216 #define	SMB_BIOSFL_525_12M	0x00800000	/* int 0x13 5.25" 1.2M floppy */
217 #define	SMB_BIOSFL_35_720K	0x01000000	/* int 0x13 3.5" 720K floppy */
218 #define	SMB_BIOSFL_35_288M	0x02000000	/* int 0x13 3.5" 2.88M floppy */
219 #define	SMB_BIOSFL_I5_PRINT	0x04000000	/* int 0x5 print screen svcs */
220 #define	SMB_BIOSFL_I9_KBD	0x08000000	/* int 0x9 8042 keyboard svcs */
221 #define	SMB_BIOSFL_I14_SER	0x10000000	/* int 0x14 serial svcs */
222 #define	SMB_BIOSFL_I17_PRINTER	0x20000000	/* int 0x17 printer svcs */
223 #define	SMB_BIOSFL_I10_CGA	0x40000000	/* int 0x10 CGA svcs */
224 #define	SMB_BIOSFL_NEC_PC98	0x80000000	/* NEC PC-98 */
225 
226 #define	SMB_BIOSXB_1		0	/* bios extension byte 1 (7.1.2.1) */
227 #define	SMB_BIOSXB_2		1	/* bios extension byte 2 (7.1.2.2) */
228 #define	SMB_BIOSXB_BIOS_MAJ	2	/* bios major version */
229 #define	SMB_BIOSXB_BIOS_MIN	3	/* bios minor version */
230 #define	SMB_BIOSXB_ECFW_MAJ	4	/* extended ctlr f/w major version */
231 #define	SMB_BIOSXB_ECFW_MIN	5	/* extended ctlr f/w minor version */
232 
233 #define	SMB_BIOSXB1_ACPI	0x01	/* ACPI is supported */
234 #define	SMB_BIOSXB1_USBL	0x02	/* USB legacy is supported */
235 #define	SMB_BIOSXB1_AGP		0x04	/* AGP is supported */
236 #define	SMB_BIOSXB1_I20		0x08	/* I2O boot is supported */
237 #define	SMB_BIOSXB1_LS120	0x10	/* LS-120 boot is supported */
238 #define	SMB_BIOSXB1_ATZIP	0x20	/* ATAPI ZIP drive boot is supported */
239 #define	SMB_BIOSXB1_1394	0x40	/* 1394 boot is supported */
240 #define	SMB_BIOSXB1_SMBAT	0x80	/* Smart Battery is supported */
241 
242 #define	SMB_BIOSXB2_BBOOT	0x01	/* BIOS Boot Specification supported */
243 #define	SMB_BIOSXB2_FKNETSVC	0x02	/* F-key Network Svc boot supported */
244 #define	SMB_BIOSXB2_ETCDIST	0x04	/* Enable Targeted Content Distrib. */
245 #define	SMB_BIOSXB2_UEFI	0x08	/* UEFI Specification supported */
246 #define	SMB_BIOSXB2_VM		0x10	/* SMBIOS table describes a VM */
247 
248 /*
249  * SMBIOS System Information.  See DSP0134 Section 7.2 for more information.
250  * The current set of smbs_wakeup values is defined after the structure.
251  */
252 typedef struct smbios_system {
253 	const uint8_t *smbs_uuid;	/* UUID byte array */
254 	uint8_t smbs_uuidlen;		/* UUID byte array length */
255 	uint8_t smbs_wakeup;		/* wake-up event */
256 	const char *smbs_sku;		/* SKU number */
257 	const char *smbs_family;	/* family */
258 } smbios_system_t;
259 
260 #define	SMB_WAKEUP_RSV0		0x00	/* reserved */
261 #define	SMB_WAKEUP_OTHER	0x01	/* other */
262 #define	SMB_WAKEUP_UNKNOWN	0x02	/* unknown */
263 #define	SMB_WAKEUP_APM		0x03	/* APM timer */
264 #define	SMB_WAKEUP_MODEM	0x04	/* modem ring */
265 #define	SMB_WAKEUP_LAN		0x05	/* LAN remote */
266 #define	SMB_WAKEUP_SWITCH	0x06	/* power switch */
267 #define	SMB_WAKEUP_PCIPME	0x07	/* PCI PME# */
268 #define	SMB_WAKEUP_AC		0x08	/* AC power restored */
269 
270 /*
271  * SMBIOS Base Board description.  See DSP0134 Section 7.3 for more
272  * information.  smbb_flags and smbb_type definitions are below.
273  */
274 typedef struct smbios_bboard {
275 	id_t smbb_chassis;		/* chassis containing this board */
276 	uint8_t smbb_flags;		/* flags (see below) */
277 	uint8_t smbb_type;		/* board type (see below) */
278 	uint8_t smbb_contn;		/* number of contained object hdls */
279 } smbios_bboard_t;
280 
281 #define	SMB_BBFL_MOTHERBOARD	0x01	/* board is a motherboard */
282 #define	SMB_BBFL_NEEDAUX	0x02	/* auxiliary card or daughter req'd */
283 #define	SMB_BBFL_REMOVABLE	0x04	/* board is removable */
284 #define	SMB_BBFL_REPLACABLE	0x08	/* board is field-replacable */
285 #define	SMB_BBFL_HOTSWAP	0x10	/* board is hot-swappable */
286 
287 #define	SMB_BBT_UNKNOWN		0x1	/* unknown */
288 #define	SMB_BBT_OTHER		0x2	/* other */
289 #define	SMB_BBT_SBLADE		0x3	/* server blade */
290 #define	SMB_BBT_CSWITCH		0x4	/* connectivity switch */
291 #define	SMB_BBT_SMM		0x5	/* system management module */
292 #define	SMB_BBT_PROC		0x6	/* processor module */
293 #define	SMB_BBT_IO		0x7	/* i/o module */
294 #define	SMB_BBT_MEM		0x8	/* memory module */
295 #define	SMB_BBT_DAUGHTER	0x9	/* daughterboard */
296 #define	SMB_BBT_MOTHER		0xA	/* motherboard */
297 #define	SMB_BBT_PROCMEM		0xB	/* processor/memory module */
298 #define	SMB_BBT_PROCIO		0xC	/* processor/i/o module */
299 #define	SMB_BBT_INTER		0xD	/* interconnect board */
300 
301 /*
302  * SMBIOS Chassis description.  See DSP0134 Section 7.4 for more information.
303  * We move the lock bit of the type field into smbc_lock for easier processing.
304  */
305 typedef struct smbios_chassis {
306 	uint32_t smbc_oemdata;		/* OEM-specific data */
307 	uint8_t smbc_lock;		/* lock present? */
308 	uint8_t smbc_type;		/* type */
309 	uint8_t smbc_bustate;		/* boot-up state */
310 	uint8_t smbc_psstate;		/* power supply state */
311 	uint8_t smbc_thstate;		/* thermal state */
312 	uint8_t smbc_security;		/* security status */
313 	uint8_t smbc_uheight;		/* enclosure height in U's */
314 	uint8_t smbc_cords;		/* number of power cords */
315 	uint8_t smbc_elems;		/* number of element records (n) */
316 	uint8_t smbc_elemlen;		/* length of contained element (m) */
317 	char smbc_sku[256];		/* SKU number (as a string) */
318 } smbios_chassis_t;
319 
320 #define	SMB_CHT_OTHER		0x01	/* other */
321 #define	SMB_CHT_UNKNOWN		0x02	/* unknown */
322 #define	SMB_CHT_DESKTOP		0x03	/* desktop */
323 #define	SMB_CHT_LPDESKTOP	0x04	/* low-profile desktop */
324 #define	SMB_CHT_PIZZA		0x05	/* pizza box */
325 #define	SMB_CHT_MINITOWER	0x06	/* mini-tower */
326 #define	SMB_CHT_TOWER		0x07	/* tower */
327 #define	SMB_CHT_PORTABLE	0x08	/* portable */
328 #define	SMB_CHT_LAPTOP		0x09	/* laptop */
329 #define	SMB_CHT_NOTEBOOK	0x0A	/* notebook */
330 #define	SMB_CHT_HANDHELD	0x0B	/* hand-held */
331 #define	SMB_CHT_DOCK		0x0C	/* docking station */
332 #define	SMB_CHT_ALLIN1		0x0D	/* all-in-one */
333 #define	SMB_CHT_SUBNOTE		0x0E	/* sub-notebook */
334 #define	SMB_CHT_SPACESAVE	0x0F	/* space-saving */
335 #define	SMB_CHT_LUNCHBOX	0x10	/* lunchbox */
336 #define	SMB_CHT_MAIN		0x11	/* main server chassis */
337 #define	SMB_CHT_EXPANSION	0x12	/* expansion chassis */
338 #define	SMB_CHT_SUB		0x13	/* sub-chassis */
339 #define	SMB_CHT_BUS		0x14	/* bus expansion chassis */
340 #define	SMB_CHT_PERIPHERAL	0x15	/* peripheral chassis */
341 #define	SMB_CHT_RAID		0x16	/* raid chassis */
342 #define	SMB_CHT_RACK		0x17	/* rack mount chassis */
343 #define	SMB_CHT_SEALED		0x18	/* sealed case pc */
344 #define	SMB_CHT_MULTI		0x19	/* multi-system chassis */
345 #define	SMB_CHT_CPCI		0x1A	/* compact PCI */
346 #define	SMB_CHT_ATCA		0x1B	/* advanced TCA */
347 #define	SMB_CHT_BLADE		0x1C	/* blade */
348 #define	SMB_CHT_BLADEENC	0x1D	/* blade enclosure */
349 #define	SMB_CHT_TABLET		0x1E	/* tablet */
350 #define	SMB_CHT_CONVERTIBLE	0x1F	/* convertible */
351 #define	SMB_CHT_DETACHABLE	0x20	/* detachable */
352 
353 #define	SMB_CHST_OTHER		0x01	/* other */
354 #define	SMB_CHST_UNKNOWN	0x02	/* unknown */
355 #define	SMB_CHST_SAFE		0x03	/* safe */
356 #define	SMB_CHST_WARNING	0x04	/* warning */
357 #define	SMB_CHST_CRITICAL	0x05	/* critical */
358 #define	SMB_CHST_NONREC		0x06	/* non-recoverable */
359 
360 #define	SMB_CHSC_OTHER		0x01	/* other */
361 #define	SMB_CHSC_UNKNOWN	0x02	/* unknown */
362 #define	SMB_CHSC_NONE		0x03	/* none */
363 #define	SMB_CHSC_EILOCK		0x04	/* external interface locked out */
364 #define	SMB_CHSC_EIENAB		0x05	/* external interface enabled */
365 
366 /*
367  * SMBIOS Processor description.  See DSP0134 Section 7.5 for more details.
368  * If the L1, L2, or L3 cache handle is -1, the cache information is unknown.
369  * If the handle refers to something of size 0, that type of cache is absent.
370  *
371  * NOTE: Although SMBIOS exports a 64-bit CPUID result, this value should not
372  * be used for any purpose other than BIOS debugging.  illumos itself computes
373  * its own CPUID value and applies knowledge of additional errata and processor
374  * specific CPUID variations, so this value should not be used for anything.
375  */
376 typedef struct smbios_processor {
377 	uint64_t smbp_cpuid;		/* processor cpuid information */
378 	uint32_t smbp_family;		/* processor family */
379 	uint8_t smbp_type;		/* processor type (SMB_PRT_*) */
380 	uint8_t smbp_voltage;		/* voltage (SMB_PRV_*) */
381 	uint8_t smbp_status;		/* status (SMB_PRS_*) */
382 	uint8_t smbp_upgrade;		/* upgrade (SMB_PRU_*) */
383 	uint32_t smbp_clkspeed;		/* external clock speed in MHz */
384 	uint32_t smbp_maxspeed;		/* maximum speed in MHz */
385 	uint32_t smbp_curspeed;		/* current speed in MHz */
386 	id_t smbp_l1cache;		/* L1 cache handle */
387 	id_t smbp_l2cache;		/* L2 cache handle */
388 	id_t smbp_l3cache;		/* L3 cache handle */
389 	uint32_t smbp_corecount;
390 		/* number of cores per processor socket */
391 	uint32_t smbp_coresenabled;
392 		/* number of enabled cores per processor socket */
393 	uint32_t smbp_threadcount;
394 		/* number of threads per processor socket */
395 	uint16_t smbp_cflags;
396 		/* processor characteristics (SMB_PRC_*) */
397 	uint16_t smbp_family2;		/* processor family 2 */
398 	uint16_t smbp_corecount2;	/* core count 2 */
399 	uint16_t smbp_coresenabled2;	/* cores enabled 2 */
400 	uint16_t smbp_threadcount2;	/* thread count 2 */
401 } smbios_processor_t;
402 
403 #define	SMB_PRT_OTHER		0x01	/* other */
404 #define	SMB_PRT_UNKNOWN		0x02	/* unknown */
405 #define	SMB_PRT_CENTRAL		0x03	/* central processor */
406 #define	SMB_PRT_MATH		0x04	/* math processor */
407 #define	SMB_PRT_DSP		0x05	/* DSP processor */
408 #define	SMB_PRT_VIDEO		0x06	/* video processor */
409 
410 #define	SMB_PRV_LEGACY(v)	(!((v) & 0x80))	/* legacy voltage mode */
411 #define	SMB_PRV_FIXED(v)	((v) & 0x80)	/* fixed voltage mode */
412 
413 #define	SMB_PRV_5V		0x01	/* 5V is supported */
414 #define	SMB_PRV_33V		0x02	/* 3.3V is supported */
415 #define	SMB_PRV_29V		0x04	/* 2.9V is supported */
416 
417 #define	SMB_PRV_VOLTAGE(v)	((v) & 0x7f)
418 
419 #define	SMB_PRSTATUS_PRESENT(s)	((s) & 0x40)	/* socket is populated */
420 #define	SMB_PRSTATUS_STATUS(s)	((s) & 0x07)	/* status (see below) */
421 
422 #define	SMB_PRS_UNKNOWN		0x0	/* unknown */
423 #define	SMB_PRS_ENABLED		0x1	/* enabled */
424 #define	SMB_PRS_BDISABLED	0x2	/* disabled in bios user setup */
425 #define	SMB_PRS_PDISABLED	0x3	/* disabled in bios from post error */
426 #define	SMB_PRS_IDLE		0x4	/* waiting to be enabled */
427 #define	SMB_PRS_OTHER		0x7	/* other */
428 
429 #define	SMB_PRU_OTHER		0x01	/* other */
430 #define	SMB_PRU_UNKNOWN		0x02	/* unknown */
431 #define	SMB_PRU_DAUGHTER	0x03	/* daughter board */
432 #define	SMB_PRU_ZIF		0x04	/* ZIF socket */
433 #define	SMB_PRU_PIGGY		0x05	/* replaceable piggy back */
434 #define	SMB_PRU_NONE		0x06	/* none */
435 #define	SMB_PRU_LIF		0x07	/* LIF socket */
436 #define	SMB_PRU_SLOT1		0x08	/* slot 1 */
437 #define	SMB_PRU_SLOT2		0x09	/* slot 2 */
438 #define	SMB_PRU_370PIN		0x0A	/* 370-pin socket */
439 #define	SMB_PRU_SLOTA		0x0B	/* slot A */
440 #define	SMB_PRU_SLOTM		0x0C	/* slot M */
441 #define	SMB_PRU_423		0x0D	/* socket 423 */
442 #define	SMB_PRU_A		0x0E	/* socket A (socket 462) */
443 #define	SMB_PRU_478		0x0F	/* socket 478 */
444 #define	SMB_PRU_754		0x10	/* socket 754 */
445 #define	SMB_PRU_940		0x11	/* socket 940 */
446 #define	SMB_PRU_939		0x12	/* socket 939 */
447 #define	SMB_PRU_MPGA604		0x13	/* mPGA604 */
448 #define	SMB_PRU_LGA771		0x14	/* LGA771 */
449 #define	SMB_PRU_LGA775		0x15	/* LGA775 */
450 #define	SMB_PRU_S1		0x16	/* socket S1 */
451 #define	SMB_PRU_AM2		0x17	/* socket AM2 */
452 #define	SMB_PRU_F		0x18	/* socket F */
453 #define	SMB_PRU_LGA1366		0x19	/* LGA1366 */
454 #define	SMB_PRU_G34		0x1A	/* socket G34 */
455 #define	SMB_PRU_AM3		0x1B	/* socket AM3 */
456 #define	SMB_PRU_C32		0x1C	/* socket C32 */
457 #define	SMB_PRU_LGA1156		0x1D	/* LGA1156 */
458 #define	SMB_PRU_LGA1567		0x1E	/* LGA1567 */
459 #define	SMB_PRU_PGA988A		0x1F	/* PGA988A */
460 #define	SMB_PRU_BGA1288		0x20	/* BGA1288 */
461 #define	SMB_PRU_RPGA988B	0x21	/* rPGA988B */
462 #define	SMB_PRU_BGA1023		0x22	/* BGA1023 */
463 #define	SMB_PRU_BGA1224		0x23	/* BGA1224 */
464 #define	SMB_PRU_LGA1155		0x24	/* LGA1155 */
465 #define	SMB_PRU_LGA1356		0x25	/* LGA1356 */
466 #define	SMB_PRU_LGA2011		0x26	/* LGA2011 */
467 #define	SMB_PRU_FS1		0x27	/* socket FS1 */
468 #define	SMB_PRU_FS2		0x28	/* socket FS2 */
469 #define	SMB_PRU_FM1		0x29	/* socket FM1 */
470 #define	SMB_PRU_FM2		0x2A	/* socket FM2 */
471 #define	SMB_PRU_LGA20113	0x2B	/* LGA2011-3 */
472 #define	SMB_PRU_LGA13563	0x2C	/* LGA1356-3 */
473 #define	SMB_PRU_LGA1150		0x2D	/* LGA1150 */
474 #define	SMB_PRU_BGA1168		0x2E	/* BGA1168 */
475 #define	SMB_PRU_BGA1234		0x2F	/* BGA1234 */
476 #define	SMB_PRU_BGA1364		0x30	/* BGA1364 */
477 
478 #define	SMB_PRC_RESERVED	0x0001	/* reserved */
479 #define	SMB_PRC_UNKNOWN		0x0002	/* unknown */
480 #define	SMB_PRC_64BIT		0x0004	/* 64-bit capable */
481 #define	SMB_PRC_MC		0x0008	/* multi-core */
482 #define	SMB_PRC_HT		0x0010	/* hardware thread */
483 #define	SMB_PRC_NX		0x0020	/* execution protection */
484 #define	SMB_PRC_VT		0x0040	/* enhanced virtualization */
485 #define	SMB_PRC_PM		0x0080	/* power/performance control */
486 
487 #define	SMB_PRF_OTHER		0x01	/* other */
488 #define	SMB_PRF_UNKNOWN		0x02	/* unknown */
489 #define	SMB_PRF_8086		0x03	/* 8086 */
490 #define	SMB_PRF_80286		0x04	/* 80286 */
491 #define	SMB_PRF_I386		0x05	/* Intel 386 */
492 #define	SMB_PRF_I486		0x06	/* Intel 486 */
493 #define	SMB_PRF_8087		0x07	/* 8087 */
494 #define	SMB_PRF_80287		0x08	/* 80287 */
495 #define	SMB_PRF_80387		0x09	/* 80387 */
496 #define	SMB_PRF_80487		0x0A	/* 80487 */
497 #define	SMB_PRF_PENTIUM		0x0B	/* Pentium Family */
498 #define	SMB_PRF_PENTIUMPRO	0x0C	/* Pentium Pro */
499 #define	SMB_PRF_PENTIUMII	0x0D	/* Pentium II */
500 #define	SMB_PRF_PENTIUM_MMX	0x0E	/* Pentium w/ MMX */
501 #define	SMB_PRF_CELERON		0x0F	/* Celeron */
502 #define	SMB_PRF_PENTIUMII_XEON	0x10	/* Pentium II Xeon */
503 #define	SMB_PRF_PENTIUMIII	0x11	/* Pentium III */
504 #define	SMB_PRF_M1		0x12	/* M1 */
505 #define	SMB_PRF_M2		0x13	/* M2 */
506 #define	SMB_PRF_CELERON_M	0x14	/* Celeron M */
507 #define	SMB_PRF_PENTIUMIV_HT	0x15	/* Pentium 4 HT */
508 #define	SMB_PRF_DURON		0x18	/* AMD Duron */
509 #define	SMB_PRF_K5		0x19	/* K5 */
510 #define	SMB_PRF_K6		0x1A	/* K6 */
511 #define	SMB_PRF_K6_2		0x1B	/* K6-2 */
512 #define	SMB_PRF_K6_3		0x1C	/* K6-3 */
513 #define	SMB_PRF_ATHLON		0x1D	/* Athlon */
514 #define	SMB_PRF_2900		0x1E	/* AMD 2900 */
515 #define	SMB_PRF_K6_2PLUS	0x1F	/* K6-2+ */
516 #define	SMB_PRF_PPC		0x20	/* PowerPC */
517 #define	SMB_PRF_PPC_601		0x21	/* PowerPC 601 */
518 #define	SMB_PRF_PPC_603		0x22	/* PowerPC 603 */
519 #define	SMB_PRF_PPC_603PLUS	0x23	/* PowerPC 603+ */
520 #define	SMB_PRF_PPC_604		0x24	/* PowerPC 604 */
521 #define	SMB_PRF_PPC_620		0x25	/* PowerPC 620 */
522 #define	SMB_PRF_PPC_704		0x26	/* PowerPC x704 */
523 #define	SMB_PRF_PPC_750		0x27	/* PowerPC 750 */
524 #define	SMB_PRF_CORE_DUO	0x28	/* Core Duo */
525 #define	SMB_PRF_CORE_DUO_M	0x29	/* Core Duo mobile */
526 #define	SMB_PRF_CORE_SOLO_M	0x2A	/* Core Solo mobile */
527 #define	SMB_PRF_ATOM		0x2B	/* Intel Atom */
528 #define	SMB_PRF_CORE_M		0x2C	/* Intel Core M */
529 #define	SMB_PRF_ALPHA		0x30	/* Alpha */
530 #define	SMB_PRF_ALPHA_21064	0x31	/* Alpha 21064 */
531 #define	SMB_PRF_ALPHA_21066	0x32	/* Alpha 21066 */
532 #define	SMB_PRF_ALPHA_21164	0x33	/* Alpha 21164 */
533 #define	SMB_PRF_ALPHA_21164PC	0x34	/* Alpha 21164PC */
534 #define	SMB_PRF_ALPHA_21164A	0x35	/* Alpha 21164a */
535 #define	SMB_PRF_ALPHA_21264	0x36	/* Alpha 21264 */
536 #define	SMB_PRF_ALPHA_21364	0x37	/* Alpha 21364 */
537 #define	SMB_PRF_TURION2U_2C_MM	0x38
538 			/* AMD Turion II Ultra Dual-Core Mobile M */
539 #define	SMB_PRF_TURION2_2C_MM	0x39	/* AMD Turion II Dual-Core Mobile M */
540 #define	SMB_PRF_ATHLON2_2C_M	0x3A	/* AMD Athlon II Dual-Core M */
541 #define	SMB_PRF_OPTERON_6100	0x3B	/* AMD Opteron 6100 series */
542 #define	SMB_PRF_OPTERON_4100	0x3C	/* AMD Opteron 4100 series */
543 #define	SMB_PRF_OPTERON_6200	0x3D	/* AMD Opteron 6200 series */
544 #define	SMB_PRF_OPTERON_4200	0x3E	/* AMD Opteron 4200 series */
545 #define	SMB_PRF_AMD_FX		0x3F	/* AMD FX series */
546 #define	SMB_PRF_MIPS		0x40	/* MIPS */
547 #define	SMB_PRF_MIPS_R4000	0x41	/* MIPS R4000 */
548 #define	SMB_PRF_MIPS_R4200	0x42	/* MIPS R4200 */
549 #define	SMB_PRF_MIPS_R4400	0x43	/* MIPS R4400 */
550 #define	SMB_PRF_MIPS_R4600	0x44	/* MIPS R4600 */
551 #define	SMB_PRF_MIPS_R10000	0x45	/* MIPS R10000 */
552 #define	SMB_PRF_AMD_C		0x46	/* AMD C-series */
553 #define	SMB_PRF_AMD_E		0x47	/* AMD E-series */
554 #define	SMB_PRF_AMD_A		0x48	/* AMD A-series */
555 #define	SMB_PRF_AMD_G		0x49	/* AMD G-series */
556 #define	SMB_PRF_AMD_Z		0x4A	/* AMD Z-series */
557 #define	SMB_PRF_AMD_R		0x4B	/* AMD R-series */
558 #define	SMB_PRF_OPTERON_4300	0x4C	/* AMD Opteron 4300 series */
559 #define	SMB_PRF_OPTERON_6300	0x4D	/* AMD Opteron 6300 series */
560 #define	SMB_PRF_OPTERON_3300	0x4E	/* AMD Opteron 3300 series */
561 #define	SMB_PRF_AMD_FIREPRO	0x4F	/* AMD FirePro series */
562 #define	SMB_PRF_SPARC		0x50	/* SPARC */
563 #define	SMB_PRF_SUPERSPARC	0x51	/* SuperSPARC */
564 #define	SMB_PRF_MICROSPARCII	0x52	/* microSPARC II */
565 #define	SMB_PRF_MICROSPARCIIep	0x53	/* microSPARC IIep */
566 #define	SMB_PRF_ULTRASPARC	0x54	/* UltraSPARC */
567 #define	SMB_PRF_USII		0x55	/* UltraSPARC II */
568 #define	SMB_PRF_USIIi		0x56	/* UltraSPARC IIi */
569 #define	SMB_PRF_USIII		0x57	/* UltraSPARC III */
570 #define	SMB_PRF_USIIIi		0x58	/* UltraSPARC IIIi */
571 #define	SMB_PRF_68040		0x60	/* 68040 */
572 #define	SMB_PRF_68XXX		0x61	/* 68XXX */
573 #define	SMB_PRF_68000		0x62	/* 68000 */
574 #define	SMB_PRF_68010		0x63	/* 68010 */
575 #define	SMB_PRF_68020		0x64	/* 68020 */
576 #define	SMB_PRF_68030		0x65	/* 68030 */
577 #define	SMB_PRF_ATHLON_X4	0x66	/* AMD Athlon X4 Quad-Core */
578 #define	SMB_PRF_OPTERON_X1K	0x67	/* AMD Opteron X1000 */
579 #define	SMB_PRF_OPTERON_X2K	0x68	/* AMD Opteron X2000 APU */
580 #define	SMB_PRF_HOBBIT		0x70	/* Hobbit */
581 #define	SMB_PRF_TM5000		0x78	/* Crusoe TM5000 */
582 #define	SMB_PRF_TM3000		0x79	/* Crusoe TM3000 */
583 #define	SMB_PRF_TM8000		0x7A	/* Efficeon TM8000 */
584 #define	SMB_PRF_WEITEK		0x80	/* Weitek */
585 #define	SMB_PRF_ITANIC		0x82	/* Itanium */
586 #define	SMB_PRF_ATHLON64	0x83	/* Athlon64 */
587 #define	SMB_PRF_OPTERON		0x84	/* Opteron */
588 #define	SMB_PRF_SEMPRON		0x85    /* Sempron */
589 #define	SMB_PRF_TURION64_M	0x86	/* Turion 64 Mobile */
590 #define	SMB_PRF_OPTERON_2C	0x87	/* AMD Opteron Dual-Core */
591 #define	SMB_PRF_ATHLON64_X2_2C	0x88	/* AMD Athlon 64 X2 Dual-Core */
592 #define	SMB_PRF_TURION64_X2_M	0x89	/* AMD Turion 64 X2 Mobile */
593 #define	SMB_PRF_OPTERON_4C	0x8A	/* AMD Opteron Quad-Core */
594 #define	SMB_PRF_OPTERON_3G	0x8B	/* AMD Opteron 3rd Generation */
595 #define	SMB_PRF_PHENOM_FX_4C	0x8C	/* AMD Phenom FX Quad-Core */
596 #define	SMB_PRF_PHENOM_X4_4C	0x8D	/* AMD Phenom X4 Quad-Core */
597 #define	SMB_PRF_PHENOM_X2_2C	0x8E	/* AMD Phenom X2 Dual-Core */
598 #define	SMB_PRF_ATHLON_X2_2C	0x8F	/* AMD Athlon X2 Dual-Core */
599 #define	SMB_PRF_PA		0x90	/* PA-RISC */
600 #define	SMB_PRF_PA8500		0x91	/* PA-RISC 8500 */
601 #define	SMB_PRF_PA8000		0x92	/* PA-RISC 8000 */
602 #define	SMB_PRF_PA7300LC	0x93	/* PA-RISC 7300LC */
603 #define	SMB_PRF_PA7200		0x94	/* PA-RISC 7200 */
604 #define	SMB_PRF_PA7100LC	0x95	/* PA-RISC 7100LC */
605 #define	SMB_PRF_PA7100		0x96	/* PA-RISC 7100 */
606 #define	SMB_PRF_V30		0xA0	/* V30 */
607 #define	SMB_PRF_XEON_4C_3200	0xA1	/* Xeon Quad Core 3200 */
608 #define	SMB_PRF_XEON_2C_3000	0xA2	/* Xeon Dual Core 3000 */
609 #define	SMB_PRF_XEON_4C_5300	0xA3	/* Xeon Quad Core 5300 */
610 #define	SMB_PRF_XEON_2C_5100	0xA4	/* Xeon Dual Core 5100 */
611 #define	SMB_PRF_XEON_2C_5000	0xA5	/* Xeon Dual Core 5000 */
612 #define	SMB_PRF_XEON_2C_LV	0xA6	/* Xeon Dual Core LV */
613 #define	SMB_PRF_XEON_2C_ULV	0xA7	/* Xeon Dual Core ULV */
614 #define	SMB_PRF_XEON_2C_7100	0xA8	/* Xeon Dual Core 7100 */
615 #define	SMB_PRF_XEON_4C_5400	0xA9	/* Xeon Quad Core 5400 */
616 #define	SMB_PRF_XEON_4C		0xAA	/* Xeon Quad Core */
617 #define	SMB_PRF_XEON_2C_5200	0xAB	/* Xeon Dual Core 5200 */
618 #define	SMB_PRF_XEON_2C_7200	0xAC	/* Xeon Dual Core 7200 */
619 #define	SMB_PRF_XEON_4C_7300	0xAD	/* Xeon Quad Core 7300 */
620 #define	SMB_PRF_XEON_4C_7400	0xAE	/* Xeon Quad Core 7400 */
621 #define	SMB_PRF_XEON_XC_7400	0xAF	/* Xeon Multi Core 7400 */
622 #define	SMB_PRF_PENTIUMIII_XEON	0xB0	/* Pentium III Xeon */
623 #define	SMB_PRF_PENTIUMIII_SS	0xB1	/* Pentium III with SpeedStep */
624 #define	SMB_PRF_P4		0xB2	/* Pentium 4 */
625 #define	SMB_PRF_XEON		0xB3	/* Intel Xeon */
626 #define	SMB_PRF_AS400		0xB4	/* AS400 */
627 #define	SMB_PRF_XEON_MP		0xB5	/* Intel Xeon MP */
628 #define	SMB_PRF_ATHLON_XP	0xB6	/* AMD Athlon XP */
629 #define	SMB_PRF_ATHLON_MP	0xB7	/* AMD Athlon MP */
630 #define	SMB_PRF_ITANIC2		0xB8	/* Itanium 2 */
631 #define	SMB_PRF_PENTIUM_M	0xB9	/* Pentium M */
632 #define	SMB_PRF_CELERON_D	0xBA	/* Celeron D */
633 #define	SMB_PRF_PENTIUM_D	0xBB	/* Pentium D */
634 #define	SMB_PRF_PENTIUM_EE	0xBC	/* Pentium Extreme Edition */
635 #define	SMB_PRF_CORE_SOLO	0xBD	/* Intel Core Solo */
636 #define	SMB_PRF_CORE2_DUO	0xBF	/* Intel Core 2 Duo */
637 #define	SMB_PRF_CORE2_SOLO	0xC0	/* Intel Core 2 Solo */
638 #define	SMB_PRF_CORE2_EX	0xC1	/* Intel Core 2 Extreme */
639 #define	SMB_PRF_CORE2_QUAD	0xC2	/* Intel Core 2 Quad */
640 #define	SMB_PRF_CORE2_EX_M	0xC3	/* Intel Core 2 Extreme mobile */
641 #define	SMB_PRF_CORE2_DUO_M	0xC4	/* Intel Core 2 Duo mobile */
642 #define	SMB_PRF_CORE2_SOLO_M	0xC5	/* Intel Core 2 Solo mobile */
643 #define	SMB_PRF_CORE_I7		0xC6	/* Intel Core i7 */
644 #define	SMB_PRF_CELERON_2C	0xC7	/* Celeron Dual-Core */
645 #define	SMB_PRF_IBM390		0xC8	/* IBM 390 */
646 #define	SMB_PRF_G4		0xC9	/* G4 */
647 #define	SMB_PRF_G5		0xCA	/* G5 */
648 #define	SMB_PRF_ESA390		0xCB	/* ESA390 */
649 #define	SMB_PRF_ZARCH		0xCC	/* z/Architecture */
650 #define	SMB_PRF_CORE_I5		0xCD	/* Intel Core i5 */
651 #define	SMB_PRF_CORE_I3		0xCE	/* Intel Core i3 */
652 #define	SMB_PRF_C7M		0xD2	/* VIA C7-M */
653 #define	SMB_PRF_C7D		0xD3	/* VIA C7-D */
654 #define	SMB_PRF_C7		0xD4	/* VIA C7 */
655 #define	SMB_PRF_EDEN		0xD5	/* VIA Eden */
656 #define	SMB_PRF_XEON_XC		0xD6	/* Intel Xeon Multi-Core */
657 #define	SMB_PRF_XEON_2C_3XXX	0xD7	/* Intel Xeon Dual-Core 3xxx */
658 #define	SMB_PRF_XEON_4C_3XXX	0xD8	/* Intel Xeon Quad-Core 3xxx */
659 #define	SMB_PRF_VIA_NANO	0xD9	/* VIA Nano */
660 #define	SMB_PRF_XEON_2C_5XXX	0xDA	/* Intel Xeon Dual-Core 5xxx */
661 #define	SMB_PRF_XEON_4C_5XXX	0xDB	/* Intel Xeon Quad-Core 5xxx */
662 #define	SMB_PRF_XEON_2C_7XXX	0xDD	/* Intel Xeon Dual-Core 7xxx */
663 #define	SMB_PRF_XEON_4C_7XXX	0xDE	/* Intel Xeon Quad-Core 7xxx */
664 #define	SMB_PRF_XEON_XC_7XXX	0xDF	/* Intel Xeon Multi-Core 7xxx */
665 #define	SMB_PRF_XEON_XC_3400	0xE0	/* Intel Xeon Multi-Core 3400 */
666 #define	SMB_PRF_OPTERON_3000	0xE4	/* AMD Opteron 3000 */
667 #define	SMB_PRF_SEMPRON_II	0xE5	/* AMD Sempron II */
668 #define	SMB_PRF_OPTERON_4C_EM	0xE6	/* AMD Opteron Quad-Core embedded */
669 #define	SMB_PRF_PHENOM_3C	0xE7	/* AMD Phenom Triple-Core */
670 #define	SMB_PRF_TURIONU_2C_M	0xE8	/* AMD Turion Ultra Dual-Core mobile */
671 #define	SMB_PRF_TURION_2C_M	0xE9	/* AMD Turion Dual-Core mobile */
672 #define	SMB_PRF_ATHLON_2C	0xEA	/* AMD Athlon Dual-Core */
673 #define	SMB_PRF_SEMPRON_SI	0xEB	/* AMD Sempron SI */
674 #define	SMB_PRF_PHENOM_II	0xEC	/* AMD Phenom II */
675 #define	SMB_PRF_ATHLON_II	0xED	/* AMD Athlon II */
676 #define	SMB_PRF_OPTERON_6C	0xEE	/* AMD Opteron Six-Core */
677 #define	SMB_PRF_SEMPRON_M	0xEF	/* AMD Sempron M */
678 #define	SMB_PRF_I860		0xFA	/* i860 */
679 #define	SMB_PRF_I960		0xFB	/* i960 */
680 #define	SMB_PRF_SH3		0x104	/* SH-3 */
681 #define	SMB_PRF_SH4		0x105	/* SH-4 */
682 #define	SMB_PRF_ARM		0x118	/* ARM */
683 #define	SMB_PRF_SARM		0x119	/* StrongARM */
684 #define	SMB_PRF_6X86		0x12C	/* 6x86 */
685 #define	SMB_PRF_MEDIAGX		0x12D	/* MediaGX */
686 #define	SMB_PRF_MII		0x12E	/* MII */
687 #define	SMB_PRF_WINCHIP		0x140	/* WinChip */
688 #define	SMB_PRF_DSP		0x15E	/* DSP */
689 #define	SMB_PRF_VIDEO		0x1F4	/* Video Processor */
690 
691 /*
692  * SMBIOS Cache Information.  See DSP0134 Section 7.8 for more information.
693  * If smba_size is zero, this indicates the specified cache is not present.
694  */
695 typedef struct smbios_cache {
696 	uint32_t smba_maxsize;		/* maximum installed size in bytes */
697 	uint32_t smba_size;		/* installed size in bytes */
698 	uint16_t smba_stype;		/* supported SRAM types (SMB_CAT_*) */
699 	uint16_t smba_ctype;		/* current SRAM type (SMB_CAT_*) */
700 	uint8_t smba_speed;		/* speed in nanoseconds */
701 	uint8_t smba_etype;		/* error correction type (SMB_CAE_*) */
702 	uint8_t smba_ltype;		/* logical cache type (SMB_CAG_*) */
703 	uint8_t smba_assoc;		/* associativity (SMB_CAA_*) */
704 	uint8_t smba_level;		/* cache level */
705 	uint8_t smba_mode;		/* cache mode (SMB_CAM_*) */
706 	uint8_t smba_location;		/* cache location (SMB_CAL_*) */
707 	uint8_t smba_flags;		/* cache flags (SMB_CAF_*) */
708 } smbios_cache_t;
709 
710 #define	SMB_CAT_OTHER		0x0001		/* other */
711 #define	SMB_CAT_UNKNOWN		0x0002		/* unknown */
712 #define	SMB_CAT_NONBURST	0x0004		/* non-burst */
713 #define	SMB_CAT_BURST		0x0008		/* burst */
714 #define	SMB_CAT_PBURST		0x0010		/* pipeline burst */
715 #define	SMB_CAT_SYNC		0x0020		/* synchronous */
716 #define	SMB_CAT_ASYNC		0x0040		/* asynchronous */
717 
718 #define	SMB_CAE_OTHER		0x01		/* other */
719 #define	SMB_CAE_UNKNOWN		0x02		/* unknown */
720 #define	SMB_CAE_NONE		0x03		/* none */
721 #define	SMB_CAE_PARITY		0x04		/* parity */
722 #define	SMB_CAE_SBECC		0x05		/* single-bit ECC */
723 #define	SMB_CAE_MBECC		0x06		/* multi-bit ECC */
724 
725 #define	SMB_CAG_OTHER		0x01		/* other */
726 #define	SMB_CAG_UNKNOWN		0x02		/* unknown */
727 #define	SMB_CAG_INSTR		0x03		/* instruction */
728 #define	SMB_CAG_DATA		0x04		/* data */
729 #define	SMB_CAG_UNIFIED		0x05		/* unified */
730 
731 #define	SMB_CAA_OTHER		0x01		/* other */
732 #define	SMB_CAA_UNKNOWN		0x02		/* unknown */
733 #define	SMB_CAA_DIRECT		0x03		/* direct mapped */
734 #define	SMB_CAA_2WAY		0x04		/* 2-way set associative */
735 #define	SMB_CAA_4WAY		0x05		/* 4-way set associative */
736 #define	SMB_CAA_FULL		0x06		/* fully associative */
737 #define	SMB_CAA_8WAY		0x07		/* 8-way set associative */
738 #define	SMB_CAA_16WAY		0x08		/* 16-way set associative */
739 #define	SMB_CAA_12WAY		0x09		/* 12-way set associative */
740 #define	SMB_CAA_24WAY		0x0A		/* 24-way set associative */
741 #define	SMB_CAA_32WAY		0x0B		/* 32-way set associative */
742 #define	SMB_CAA_48WAY		0x0C		/* 48-way set associative */
743 #define	SMB_CAA_64WAY		0x0D		/* 64-way set associative */
744 #define	SMB_CAA_20WAY		0x0E		/* 20-way set associative */
745 
746 #define	SMB_CAM_WT		0x00		/* write-through */
747 #define	SMB_CAM_WB		0x01		/* write-back */
748 #define	SMB_CAM_VARY		0x02		/* varies by address */
749 #define	SMB_CAM_UNKNOWN		0x03		/* unknown */
750 
751 #define	SMB_CAL_INTERNAL	0x00		/* internal */
752 #define	SMB_CAL_EXTERNAL	0x01		/* external */
753 #define	SMB_CAL_RESERVED	0x02		/* reserved */
754 #define	SMB_CAL_UNKNOWN		0x03		/* unknown */
755 
756 #define	SMB_CAF_ENABLED		0x01		/* enabled at boot time */
757 #define	SMB_CAF_SOCKETED	0x02		/* cache is socketed */
758 
759 /*
760  * SMBIOS Port Information.  See DSP0134 Section 7.9 for more information.
761  * The internal reference designator string is also mapped to the location.
762  */
763 typedef struct smbios_port {
764 	const char *smbo_iref;	/* internal reference designator */
765 	const char *smbo_eref;	/* external reference designator */
766 	uint8_t smbo_itype;	/* internal connector type (SMB_POC_*) */
767 	uint8_t smbo_etype;	/* external connector type (SMB_POC_*) */
768 	uint8_t smbo_ptype;	/* port type (SMB_POT_*) */
769 	uint8_t smbo_pad;	/* padding */
770 } smbios_port_t;
771 
772 #define	SMB_POC_NONE		0x00		/* none */
773 #define	SMB_POC_CENT		0x01		/* Centronics */
774 #define	SMB_POC_MINICENT	0x02		/* Mini-Centronics */
775 #define	SMB_POC_PROPRIETARY	0x03		/* proprietary */
776 #define	SMB_POC_DB25M		0x04		/* DB-25 pin male */
777 #define	SMB_POC_DB25F		0x05		/* DB-25 pin female */
778 #define	SMB_POC_DB15M		0x06		/* DB-15 pin male */
779 #define	SMB_POC_DB15F		0x07		/* DB-15 pin female */
780 #define	SMB_POC_DB9M		0x08		/* DB-9 pin male */
781 #define	SMB_POC_DB9F		0x09		/* DB-9 pin female */
782 #define	SMB_POC_RJ11		0x0A		/* RJ-11 */
783 #define	SMB_POC_RJ45		0x0B		/* RJ-45 */
784 #define	SMB_POC_MINISCSI	0x0C		/* 50-pin MiniSCSI */
785 #define	SMB_POC_MINIDIN		0x0D		/* Mini-DIN */
786 #define	SMB_POC_MICRODIN	0x0E		/* Micro-DIN */
787 #define	SMB_POC_PS2		0x0F		/* PS/2 */
788 #define	SMB_POC_IR		0x10		/* Infrared */
789 #define	SMB_POC_HPHIL		0x11		/* HP-HIL */
790 #define	SMB_POC_USB		0x12		/* USB */
791 #define	SMB_POC_SSA		0x13		/* SSA SCSI */
792 #define	SMB_POC_DIN8M		0x14		/* Circular DIN-8 male */
793 #define	SMB_POC_DIN8F		0x15		/* Circular DIN-8 female */
794 #define	SMB_POC_OBIDE		0x16		/* on-board IDE */
795 #define	SMB_POC_OBFLOPPY	0x17		/* on-board floppy */
796 #define	SMB_POC_DI9		0x18		/* 9p dual inline (p10 cut) */
797 #define	SMB_POC_DI25		0x19		/* 25p dual inline (p26 cut) */
798 #define	SMB_POC_DI50		0x1A		/* 50p dual inline */
799 #define	SMB_POC_DI68		0x1B		/* 68p dual inline */
800 #define	SMB_POC_CDROM		0x1C		/* on-board sound from CDROM */
801 #define	SMB_POC_MINI14		0x1D		/* Mini-Centronics Type 14 */
802 #define	SMB_POC_MINI26		0x1E		/* Mini-Centronics Type 26 */
803 #define	SMB_POC_MINIJACK	0x1F		/* Mini-jack (headphones) */
804 #define	SMB_POC_BNC		0x20		/* BNC */
805 #define	SMB_POC_1394		0x21		/* 1394 */
806 #define	SMB_POC_SATA		0x22		/* SAS/SATA plug receptacle */
807 #define	SMB_POC_PC98		0xA0		/* PC-98 */
808 #define	SMB_POC_PC98HR		0xA1		/* PC-98Hireso */
809 #define	SMB_POC_PCH98		0xA2		/* PC-H98 */
810 #define	SMB_POC_PC98NOTE	0xA3		/* PC-98Note */
811 #define	SMB_POC_PC98FULL	0xA4		/* PC-98Full */
812 #define	SMB_POC_OTHER		0xFF		/* other */
813 
814 #define	SMB_POT_NONE		0x00		/* none */
815 #define	SMB_POT_PP_XTAT		0x01		/* Parallel Port XT/AT compat */
816 #define	SMB_POT_PP_PS2		0x02		/* Parallel Port PS/2 */
817 #define	SMB_POT_PP_ECP		0x03		/* Parallel Port ECP */
818 #define	SMB_POT_PP_EPP		0x04		/* Parallel Port EPP */
819 #define	SMB_POT_PP_ECPEPP	0x05		/* Parallel Port ECP/EPP */
820 #define	SMB_POT_SP_XTAT		0x06		/* Serial Port XT/AT compat */
821 #define	SMB_POT_SP_16450	0x07		/* Serial Port 16450 compat */
822 #define	SMB_POT_SP_16550	0x08		/* Serial Port 16550 compat */
823 #define	SMB_POT_SP_16550A	0x09		/* Serial Port 16550A compat */
824 #define	SMB_POT_SCSI		0x0A		/* SCSI port */
825 #define	SMB_POT_MIDI		0x0B		/* MIDI port */
826 #define	SMB_POT_JOYSTICK	0x0C		/* Joystick port */
827 #define	SMB_POT_KEYBOARD	0x0D		/* Keyboard port */
828 #define	SMB_POT_MOUSE		0x0E		/* Mouse port */
829 #define	SMB_POT_SSA		0x0F		/* SSA SCSI */
830 #define	SMB_POT_USB		0x10		/* USB */
831 #define	SMB_POT_FIREWIRE	0x11		/* FireWrite (IEEE P1394) */
832 #define	SMB_POT_PCMII		0x12		/* PCMCIA Type II */
833 #define	SMB_POT_PCMIIa		0x13		/* PCMCIA Type II (alternate) */
834 #define	SMB_POT_PCMIII		0x14		/* PCMCIA Type III */
835 #define	SMB_POT_CARDBUS		0x15		/* Cardbus */
836 #define	SMB_POT_ACCESS		0x16		/* Access Bus Port */
837 #define	SMB_POT_SCSI2		0x17		/* SCSI II */
838 #define	SMB_POT_SCSIW		0x18		/* SCSI Wide */
839 #define	SMB_POT_PC98		0x19		/* PC-98 */
840 #define	SMB_POT_PC98HR		0x1A		/* PC-98Hireso */
841 #define	SMB_POT_PCH98		0x1B		/* PC-H98 */
842 #define	SMB_POT_VIDEO		0x1C		/* Video port */
843 #define	SMB_POT_AUDIO		0x1D		/* Audio port */
844 #define	SMB_POT_MODEM		0x1E		/* Modem port */
845 #define	SMB_POT_NETWORK		0x1F		/* Network port */
846 #define	SMB_POT_SATA		0x20		/* SATA */
847 #define	SMB_POT_SAS		0x21		/* SAS */
848 #define	SMB_POT_8251		0xA0		/* 8251 compatible */
849 #define	SMB_POT_8251F		0xA1		/* 8251 FIFO compatible */
850 #define	SMB_POT_OTHER		0xFF		/* other */
851 
852 /*
853  * SMBIOS Slot Information.  See DSP0134 Section 7.10 for more information.
854  * See DSP0134 7.10.5 for how to interpret the value of smbl_id.
855  */
856 typedef struct smbios_slot {
857 	const char *smbl_name;		/* reference designation */
858 	uint8_t smbl_type;		/* slot type */
859 	uint8_t smbl_width;		/* slot data bus width */
860 	uint8_t smbl_usage;		/* current usage */
861 	uint8_t smbl_length;		/* slot length */
862 	uint16_t smbl_id;		/* slot ID */
863 	uint8_t smbl_ch1;		/* slot characteristics 1 */
864 	uint8_t smbl_ch2;		/* slot characteristics 2 */
865 	uint16_t smbl_sg;		/* segment group number */
866 	uint8_t smbl_bus;		/* bus number */
867 	uint8_t smbl_df;		/* device/function number */
868 } smbios_slot_t;
869 
870 #define	SMB_SLT_OTHER		0x01	/* other */
871 #define	SMB_SLT_UNKNOWN		0x02	/* unknown */
872 #define	SMB_SLT_ISA		0x03	/* ISA */
873 #define	SMB_SLT_MCA		0x04	/* MCA */
874 #define	SMB_SLT_EISA		0x05	/* EISA */
875 #define	SMB_SLT_PCI		0x06	/* PCI */
876 #define	SMB_SLT_PCMCIA		0x07	/* PCMCIA */
877 #define	SMB_SLT_VLVESA		0x08	/* VL-VESA */
878 #define	SMB_SLT_PROPRIETARY	0x09	/* proprietary */
879 #define	SMB_SLT_PROC		0x0A	/* processor card slot */
880 #define	SMB_SLT_MEM		0x0B	/* proprietary memory card slot */
881 #define	SMB_SLT_IOR		0x0C	/* I/O riser card slot */
882 #define	SMB_SLT_NUBUS		0x0D	/* NuBus */
883 #define	SMB_SLT_PCI66		0x0E	/* PCI (66MHz capable) */
884 #define	SMB_SLT_AGP		0x0F	/* AGP */
885 #define	SMB_SLT_AGP2X		0x10	/* AGP 2X */
886 #define	SMB_SLT_AGP4X		0x11	/* AGP 4X */
887 #define	SMB_SLT_PCIX		0x12	/* PCI-X */
888 #define	SMB_SLT_AGP8X		0x13	/* AGP 8X */
889 #define	SMB_SLT_M2_1DP		0x14	/* M.2 Socket 1-DP (Mechanical Key A) */
890 #define	SMB_SLT_M2_1SD		0x15	/* M.2 Socket 1-SD (Mechanical Key E) */
891 #define	SMB_SLT_M2_2		0x16	/* M.2 Socket 2 (Mechanical Key B) */
892 #define	SMB_SLT_M2_3		0x17	/* M.2 Socket 3 (Mechanical Key M) */
893 #define	SMB_SLT_MXM_I		0x18	/* MXM Type I */
894 #define	SMB_SLT_MXM_II		0x19	/* MXM Type II */
895 #define	SMB_SLT_MXM_III		0x1A	/* MXM Type III (standard connector) */
896 #define	SMB_SLT_MXM_III_HE	0x1B	/* MXM Type III (HE connector) */
897 #define	SMB_SLT_MXM_V		0x1C	/* MXM Type IV */
898 #define	SMB_SLT_MXM3_A		0x1D	/* MXM 3.0 Type A */
899 #define	SMB_SLT_MXM3_B		0x1E	/* MXM 3.0 Type B */
900 #define	SMB_SLT_PCIEG2_SFF	0x1F	/* PCI Express Gen 2 SFF-8639 */
901 #define	SMB_SLT_PCIEG3_SFF	0x20	/* PCI Express Gen 3 SFF-8639 */
902 #define	SMB_SLT_PC98_C20	0xA0	/* PC-98/C20 */
903 #define	SMB_SLT_PC98_C24	0xA1	/* PC-98/C24 */
904 #define	SMB_SLT_PC98_E		0xA2	/* PC-98/E */
905 #define	SMB_SLT_PC98_LB		0xA3	/* PC-98/Local Bus */
906 #define	SMB_SLT_PC98_C		0xA4	/* PC-98/Card */
907 #define	SMB_SLT_PCIE		0xA5	/* PCI Express */
908 #define	SMB_SLT_PCIE1		0xA6	/* PCI Express x1 */
909 #define	SMB_SLT_PCIE2		0xA7	/* PCI Express x2 */
910 #define	SMB_SLT_PCIE4		0xA8	/* PCI Express x4 */
911 #define	SMB_SLT_PCIE8		0xA9	/* PCI Express x8 */
912 #define	SMB_SLT_PCIE16		0xAA	/* PCI Express x16 */
913 #define	SMB_SLT_PCIE2G		0xAB	/* PCI Exp. Gen 2 */
914 #define	SMB_SLT_PCIE2G1		0xAC	/* PCI Exp. Gen 2 x1 */
915 #define	SMB_SLT_PCIE2G2		0xAD	/* PCI Exp. Gen 2 x2 */
916 #define	SMB_SLT_PCIE2G4		0xAE	/* PCI Exp. Gen 2 x4 */
917 #define	SMB_SLT_PCIE2G8		0xAF	/* PCI Exp. Gen 2 x8 */
918 #define	SMB_SLT_PCIE2G16	0xB0	/* PCI Exp. Gen 2 x16 */
919 #define	SMB_SLT_PCIE3G		0xB1	/* PCI Exp. Gen 3 */
920 #define	SMB_SLT_PCIE3G1		0xB2	/* PCI Exp. Gen 3 x1 */
921 #define	SMB_SLT_PCIE3G2		0xB3	/* PCI Exp. Gen 3 x2 */
922 #define	SMB_SLT_PCIE3G4		0xB4	/* PCI Exp. Gen 3 x4 */
923 #define	SMB_SLT_PCIE3G8		0xB5	/* PCI Exp. Gen 3 x8 */
924 #define	SMB_SLT_PCIE3G16	0xB6	/* PCI Exp. Gen 3 x16 */
925 
926 #define	SMB_SLW_OTHER		0x01	/* other */
927 #define	SMB_SLW_UNKNOWN		0x02	/* unknown */
928 #define	SMB_SLW_8		0x03	/* 8 bit */
929 #define	SMB_SLW_16		0x04	/* 16 bit */
930 #define	SMB_SLW_32		0x05	/* 32 bit */
931 #define	SMB_SLW_64		0x06	/* 64 bit */
932 #define	SMB_SLW_128		0x07	/* 128 bit */
933 #define	SMB_SLW_1X		0x08	/* 1x or x1 */
934 #define	SMB_SLW_2X		0x09	/* 2x or x2 */
935 #define	SMB_SLW_4X		0x0A	/* 4x or x4 */
936 #define	SMB_SLW_8X		0x0B	/* 8x or x8 */
937 #define	SMB_SLW_12X		0x0C	/* 12x or x12 */
938 #define	SMB_SLW_16X		0x0D	/* 16x or x16 */
939 #define	SMB_SLW_32X		0x0E	/* 32x or x32 */
940 
941 #define	SMB_SLU_OTHER		0x01	/* other */
942 #define	SMB_SLU_UNKNOWN		0x02	/* unknown */
943 #define	SMB_SLU_AVAIL		0x03	/* available */
944 #define	SMB_SLU_INUSE		0x04	/* in use */
945 
946 #define	SMB_SLL_OTHER		0x01	/* other */
947 #define	SMB_SLL_UNKNOWN		0x02	/* unknown */
948 #define	SMB_SLL_SHORT		0x03	/* short length */
949 #define	SMB_SLL_LONG		0x04	/* long length */
950 
951 #define	SMB_SLCH1_UNKNOWN	0x01	/* characteristics unknown */
952 #define	SMB_SLCH1_5V		0x02	/* provides 5.0V */
953 #define	SMB_SLCH1_33V		0x04	/* provides 3.3V */
954 #define	SMB_SLCH1_SHARED	0x08	/* opening shared with other slot */
955 #define	SMB_SLCH1_PC16		0x10	/* slot supports PC Card-16 */
956 #define	SMB_SLCH1_PCCB		0x20	/* slot supports CardBus */
957 #define	SMB_SLCH1_PCZV		0x40	/* slot supports Zoom Video */
958 #define	SMB_SLCH1_PCMRR		0x80	/* slot supports Modem Ring Resume */
959 
960 #define	SMB_SLCH2_PME		0x01	/* slot supports PME# signal */
961 #define	SMB_SLCH2_HOTPLUG	0x02	/* slot supports hot-plug devices */
962 #define	SMB_SLCH2_SMBUS		0x04	/* slot supports SMBus signal */
963 
964 /*
965  * SMBIOS On-Board Device Information.  See DSP0134 Section 7.11 for more
966  * information.  Any number of on-board device sections may be present, each
967  * containing one or more records.  The smbios_info_obdevs() function permits
968  * the caller to retrieve one or more of the records from a given section.
969  */
970 typedef struct smbios_obdev {
971 	const char *smbd_name;		/* description string for this device */
972 	uint8_t smbd_type;		/* type code (SMB_OBT_*) */
973 	uint8_t smbd_enabled;		/* boolean (device is enabled) */
974 } smbios_obdev_t;
975 
976 #define	SMB_OBT_OTHER		0x01	/* other */
977 #define	SMB_OBT_UNKNOWN		0x02	/* unknown */
978 #define	SMB_OBT_VIDEO		0x03	/* video */
979 #define	SMB_OBT_SCSI		0x04	/* scsi */
980 #define	SMB_OBT_ETHERNET	0x05	/* ethernet */
981 #define	SMB_OBT_TOKEN		0x06	/* token ring */
982 #define	SMB_OBT_SOUND		0x07	/* sound */
983 #define	SMB_OBT_PATA		0x08	/* pata */
984 #define	SMB_OBT_SATA		0x09	/* sata */
985 #define	SMB_OBT_SAS		0x0A	/* sas */
986 
987 /*
988  * SMBIOS BIOS Language Information.  See DSP0134 Section 7.14 for more
989  * information.  The smbios_info_strtab() function can be applied using a
990  * count of smbla_num to retrieve the other possible language settings.
991  */
992 typedef struct smbios_lang {
993 	const char *smbla_cur;		/* current language setting */
994 	uint_t smbla_fmt;		/* language name format (see below) */
995 	uint_t smbla_num;		/* number of installed languages */
996 } smbios_lang_t;
997 
998 #define	SMB_LFMT_LONG	0		/* <ISO639>|<ISO3166>|Encoding Method */
999 #define	SMB_LFMT_SHORT	1		/* <ISO930><ISO3166> */
1000 
1001 /*
1002  * SMBIOS System Event Log Information.  See DSP0134 Section 7.16 for more
1003  * information.  Accessing the event log itself requires additional interfaces.
1004  */
1005 typedef struct smbios_evtype {
1006 	uint8_t smbevt_ltype;		/* log type */
1007 	uint8_t smbevt_dtype;		/* variable data format type */
1008 } smbios_evtype_t;
1009 
1010 typedef struct smbios_evlog {
1011 	size_t smbev_size;		/* size in bytes of log area */
1012 	size_t smbev_hdr;		/* offset or index of header */
1013 	size_t smbev_data;		/* offset or index of data */
1014 	uint8_t smbev_method;		/* data access method (see below) */
1015 	uint8_t smbev_flags;		/* flags (see below) */
1016 	uint8_t smbev_format;		/* log header format (see below) */
1017 	uint8_t smbev_pad;		/* padding */
1018 	uint32_t smbev_token;		/* data update change token */
1019 	union {
1020 		struct {
1021 			uint16_t evi_iaddr; /* index address */
1022 			uint16_t evi_daddr; /* data address */
1023 		} eva_io;		/* i/o address for SMB_EVM_XxY */
1024 		uint32_t eva_addr;	/* address for SMB_EVM_MEM32 */
1025 		uint16_t eva_gpnv;	/* handle for SMB_EVM_GPNV */
1026 	} smbev_addr;
1027 	uint32_t smbev_typec;		/* number of type descriptors */
1028 	const smbios_evtype_t *smbev_typev; /* type descriptor array */
1029 } smbios_evlog_t;
1030 
1031 #define	SMB_EVM_1x1i_1x1d	0	/* I/O: 1 1b idx port, 1 1b data port */
1032 #define	SMB_EVM_2x1i_1x1d	1	/* I/O: 2 1b idx port, 1 1b data port */
1033 #define	SMB_EVM_1x2i_1x1d	2	/* I/O: 1 2b idx port, 1 1b data port */
1034 #define	SMB_EVM_MEM32		3	/* Memory-Mapped 32-bit Physical Addr */
1035 #define	SMB_EVM_GPNV		4	/* GP Non-Volatile API Access */
1036 
1037 #define	SMB_EVFL_VALID		0x1	/* log area valid */
1038 #define	SMB_EVFL_FULL		0x2	/* log area full */
1039 
1040 #define	SMB_EVHF_NONE		0	/* no log headers used */
1041 #define	SMB_EVHF_F1		1	/* DMTF log header type 1 */
1042 
1043 /*
1044  * SMBIOS Physical Memory Array Information.  See DSP0134 Section 7.17 for
1045  * more information.  This describes a collection of physical memory devices.
1046  */
1047 typedef struct smbios_memarray {
1048 	uint8_t smbma_location;		/* physical device location */
1049 	uint8_t smbma_use;		/* physical device functional purpose */
1050 	uint8_t smbma_ecc;		/* error detect/correct mechanism */
1051 	uint8_t smbma_pad0;		/* padding */
1052 	uint32_t smbma_pad1;		/* padding */
1053 	uint32_t smbma_ndevs;		/* number of slots or sockets */
1054 	id_t smbma_err;			/* handle of error (if any) */
1055 	uint64_t smbma_size;		/* maximum capacity in bytes */
1056 } smbios_memarray_t;
1057 
1058 #define	SMB_MAL_OTHER		0x01	/* other */
1059 #define	SMB_MAL_UNKNOWN		0x02	/* unknown */
1060 #define	SMB_MAL_SYSMB		0x03	/* system board or motherboard */
1061 #define	SMB_MAL_ISA		0x04	/* ISA add-on card */
1062 #define	SMB_MAL_EISA		0x05	/* EISA add-on card */
1063 #define	SMB_MAL_PCI		0x06	/* PCI add-on card */
1064 #define	SMB_MAL_MCA		0x07	/* MCA add-on card */
1065 #define	SMB_MAL_PCMCIA		0x08	/* PCMCIA add-on card */
1066 #define	SMB_MAL_PROP		0x09	/* proprietary add-on card */
1067 #define	SMB_MAL_NUBUS		0x0A	/* NuBus */
1068 #define	SMB_MAL_PC98C20		0xA0	/* PC-98/C20 add-on card */
1069 #define	SMB_MAL_PC98C24		0xA1	/* PC-98/C24 add-on card */
1070 #define	SMB_MAL_PC98E		0xA2	/* PC-98/E add-on card */
1071 #define	SMB_MAL_PC98LB		0xA3	/* PC-98/Local bus add-on card */
1072 
1073 #define	SMB_MAU_OTHER		0x01	/* other */
1074 #define	SMB_MAU_UNKNOWN		0x02	/* unknown */
1075 #define	SMB_MAU_SYSTEM		0x03	/* system memory */
1076 #define	SMB_MAU_VIDEO		0x04	/* video memory */
1077 #define	SMB_MAU_FLASH		0x05	/* flash memory */
1078 #define	SMB_MAU_NVRAM		0x06	/* non-volatile RAM */
1079 #define	SMB_MAU_CACHE		0x07	/* cache memory */
1080 
1081 #define	SMB_MAE_OTHER		0x01	/* other */
1082 #define	SMB_MAE_UNKNOWN		0x02	/* unknown */
1083 #define	SMB_MAE_NONE		0x03	/* none */
1084 #define	SMB_MAE_PARITY		0x04	/* parity */
1085 #define	SMB_MAE_SECC		0x05	/* single-bit ECC */
1086 #define	SMB_MAE_MECC		0x06	/* multi-bit ECC */
1087 #define	SMB_MAE_CRC		0x07	/* CRC */
1088 
1089 /*
1090  * SMBIOS Memory Device Information.  See DSP0134 Section 7.18 for more
1091  * information.  One or more of these structures are associated with each
1092  * smbios_memarray_t.  A structure is present even for unpopulated sockets.
1093  * Unknown values are set to -1.  A smbmd_size of 0 indicates unpopulated.
1094  * WARNING: Some BIOSes appear to export the *maximum* size of the device
1095  * that can appear in the corresponding socket as opposed to the current one.
1096  */
1097 typedef struct smbios_memdevice {
1098 	id_t smbmd_array;		/* handle of physical memory array */
1099 	id_t smbmd_error;		/* handle of memory error data */
1100 	uint32_t smbmd_twidth;		/* total width in bits including ecc */
1101 	uint32_t smbmd_dwidth;		/* data width in bits */
1102 	uint64_t smbmd_size;		/* size in bytes (see note above) */
1103 	uint8_t smbmd_form;		/* form factor */
1104 	uint8_t smbmd_set;		/* set (0x00=none, 0xFF=unknown) */
1105 	uint8_t smbmd_type;		/* memory type */
1106 	uint8_t smbmd_pad;		/* padding */
1107 	uint32_t smbmd_flags;		/* flags (see below) */
1108 	uint32_t smbmd_speed;		/* speed in MHz */
1109 	const char *smbmd_dloc;		/* physical device locator string */
1110 	const char *smbmd_bloc;		/* physical bank locator string */
1111 	uint8_t smbmd_rank;		/* rank */
1112 	uint16_t smbmd_clkspeed;	/* configured clock speed */
1113 	uint16_t smbmd_minvolt;		/* minimum voltage */
1114 	uint16_t smbmd_maxvolt;		/* maximum voltage */
1115 	uint16_t smbmd_confvolt;	/* configured voltage */
1116 } smbios_memdevice_t;
1117 
1118 #define	SMB_MDFF_OTHER		0x01	/* other */
1119 #define	SMB_MDFF_UNKNOWN	0x02	/* unknown */
1120 #define	SMB_MDFF_SIMM		0x03	/* SIMM */
1121 #define	SMB_MDFF_SIP		0x04	/* SIP */
1122 #define	SMB_MDFF_CHIP		0x05	/* chip */
1123 #define	SMB_MDFF_DIP		0x06	/* DIP */
1124 #define	SMB_MDFF_ZIP		0x07	/* ZIP */
1125 #define	SMB_MDFF_PROP		0x08	/* proprietary card */
1126 #define	SMB_MDFF_DIMM		0x09	/* DIMM */
1127 #define	SMB_MDFF_TSOP		0x0A	/* TSOP */
1128 #define	SMB_MDFF_CHIPROW	0x0B	/* row of chips */
1129 #define	SMB_MDFF_RIMM		0x0C	/* RIMM */
1130 #define	SMB_MDFF_SODIMM		0x0D	/* SODIMM */
1131 #define	SMB_MDFF_SRIMM		0x0E	/* SRIMM */
1132 #define	SMB_MDFF_FBDIMM		0x0F	/* FBDIMM */
1133 
1134 #define	SMB_MDT_OTHER		0x01	/* other */
1135 #define	SMB_MDT_UNKNOWN		0x02	/* unknown */
1136 #define	SMB_MDT_DRAM		0x03	/* DRAM */
1137 #define	SMB_MDT_EDRAM		0x04	/* EDRAM */
1138 #define	SMB_MDT_VRAM		0x05	/* VRAM */
1139 #define	SMB_MDT_SRAM		0x06	/* SRAM */
1140 #define	SMB_MDT_RAM		0x07	/* RAM */
1141 #define	SMB_MDT_ROM		0x08	/* ROM */
1142 #define	SMB_MDT_FLASH		0x09	/* FLASH */
1143 #define	SMB_MDT_EEPROM		0x0A	/* EEPROM */
1144 #define	SMB_MDT_FEPROM		0x0B	/* FEPROM */
1145 #define	SMB_MDT_EPROM		0x0C	/* EPROM */
1146 #define	SMB_MDT_CDRAM		0x0D	/* CDRAM */
1147 #define	SMB_MDT_3DRAM		0x0E	/* 3DRAM */
1148 #define	SMB_MDT_SDRAM		0x0F	/* SDRAM */
1149 #define	SMB_MDT_SGRAM		0x10	/* SGRAM */
1150 #define	SMB_MDT_RDRAM		0x11	/* RDRAM */
1151 #define	SMB_MDT_DDR		0x12	/* DDR */
1152 #define	SMB_MDT_DDR2		0x13	/* DDR2 */
1153 #define	SMB_MDT_DDR2FBDIMM	0x14	/* DDR2 FBDIMM */
1154 #define	SMB_MDT_DDR3		0x18	/* DDR3 */
1155 #define	SMB_MDT_FBD2		0x19	/* FBD2 */
1156 #define	SMB_MDT_DDR4		0x1A	/* DDR4 */
1157 #define	SMB_MDT_LPDDR		0x1B	/* LPDDR */
1158 #define	SMB_MDT_LPDDR2		0x1C	/* LPDDR2 */
1159 #define	SMB_MDT_LPDDR3		0x1D	/* LPDDR3 */
1160 #define	SMB_MDT_LPDDR4		0x1E	/* LPDDR4 */
1161 
1162 #define	SMB_MDF_OTHER		0x0002	/* other */
1163 #define	SMB_MDF_UNKNOWN		0x0004	/* unknown */
1164 #define	SMB_MDF_FASTPG		0x0008	/* fast-paged */
1165 #define	SMB_MDF_STATIC		0x0010	/* static column */
1166 #define	SMB_MDF_PSTATIC		0x0020	/* pseudo-static */
1167 #define	SMB_MDF_RAMBUS		0x0040	/* RAMBUS */
1168 #define	SMB_MDF_SYNC		0x0080	/* synchronous */
1169 #define	SMB_MDF_CMOS		0x0100	/* CMOS */
1170 #define	SMB_MDF_EDO		0x0200	/* EDO */
1171 #define	SMB_MDF_WDRAM		0x0400	/* Window DRAM */
1172 #define	SMB_MDF_CDRAM		0x0800	/* Cache DRAM */
1173 #define	SMB_MDF_NV		0x1000	/* non-volatile */
1174 #define	SMB_MDF_REG		0x2000	/* Registered (Buffered) */
1175 #define	SMB_MDF_UNREG		0x4000	/* Unregistered (Unbuffered) */
1176 #define	SMB_MDF_LRDIMM		0x8000	/* LRDIMM */
1177 
1178 #define	SMB_MDR_SINGLE		0x01	/* single */
1179 #define	SMB_MDR_DUAL		0x02	/* dual */
1180 #define	SMB_MDR_QUAD		0x04	/* quad */
1181 #define	SMB_MDR_OCTAL		0x08	/* octal */
1182 
1183 /*
1184  * SMBIOS Memory Array Mapped Address.  See DSP0134 Section 7.20 for more
1185  * information.  We convert start/end addresses into addr/size for convenience.
1186  */
1187 typedef struct smbios_memarrmap {
1188 	id_t smbmam_array;		/* physical memory array handle */
1189 	uint32_t smbmam_width;		/* number of devices that form a row */
1190 	uint64_t smbmam_addr;		/* physical address of mapping */
1191 	uint64_t smbmam_size;		/* size in bytes of address range */
1192 } smbios_memarrmap_t;
1193 
1194 /*
1195  * SMBIOS Memory Device Mapped Address.  See DSP0134 Section 7.21 for more
1196  * information.  We convert start/end addresses into addr/size for convenience.
1197  */
1198 typedef struct smbios_memdevmap {
1199 	id_t smbmdm_device;		/* memory device handle */
1200 	id_t smbmdm_arrmap;		/* memory array mapped address handle */
1201 	uint64_t smbmdm_addr;		/* physical address of mapping */
1202 	uint64_t smbmdm_size;		/* size in bytes of address range */
1203 	uint8_t smbmdm_rpos;		/* partition row position */
1204 	uint8_t smbmdm_ipos;		/* interleave position */
1205 	uint8_t smbmdm_idepth;		/* interleave data depth */
1206 } smbios_memdevmap_t;
1207 
1208 /*
1209  * SMBIOS Hardware Security Settings.  See DSP0134 Section 7.25 for more
1210  * information.  Only one such record will be present in the SMBIOS.
1211  */
1212 typedef struct smbios_hwsec {
1213 	uint8_t smbh_pwr_ps;		/* power-on password status */
1214 	uint8_t smbh_kbd_ps;		/* keyboard password status */
1215 	uint8_t smbh_adm_ps;		/* administrator password status */
1216 	uint8_t smbh_pan_ps;		/* front panel reset status */
1217 } smbios_hwsec_t;
1218 
1219 #define	SMB_HWSEC_PS_DISABLED	0x00	/* password disabled */
1220 #define	SMB_HWSEC_PS_ENABLED	0x01	/* password enabled */
1221 #define	SMB_HWSEC_PS_NOTIMPL	0x02	/* password not implemented */
1222 #define	SMB_HWSEC_PS_UNKNOWN	0x03	/* password status unknown */
1223 
1224 /*
1225  * SMBIOS System Boot Information.  See DSP0134 Section 7.33 for more
1226  * information.  The contents of the data varies by type and is undocumented
1227  * from the perspective of DSP0134 -- it seems to be left as vendor-specific.
1228  * The (D) annotation next to SMB_BOOT_* below indicates possible data payload.
1229  */
1230 typedef struct smbios_boot {
1231 	uint8_t smbt_status;		/* boot status code (see below) */
1232 	const void *smbt_data;		/* data buffer specific to status */
1233 	size_t smbt_size;		/* size of smbt_data buffer in bytes */
1234 } smbios_boot_t;
1235 
1236 #define	SMB_BOOT_NORMAL		0	/* no errors detected */
1237 #define	SMB_BOOT_NOMEDIA	1	/* no bootable media */
1238 #define	SMB_BOOT_OSFAIL		2	/* normal o/s failed to load */
1239 #define	SMB_BOOT_FWHWFAIL	3	/* firmware-detected hardware failure */
1240 #define	SMB_BOOT_OSHWFAIL	4	/* o/s-detected hardware failure */
1241 #define	SMB_BOOT_USERREQ	5	/* user-requested boot (keystroke) */
1242 #define	SMB_BOOT_SECURITY	6	/* system security violation */
1243 #define	SMB_BOOT_PREVREQ	7	/* previously requested image (D) */
1244 #define	SMB_BOOT_WATCHDOG	8	/* watchdog initiated reboot */
1245 #define	SMB_BOOT_RESV_LO	9	/* low end of reserved range */
1246 #define	SMB_BOOT_RESV_HI	127	/* high end of reserved range */
1247 #define	SMB_BOOT_OEM_LO		128	/* low end of OEM-specific range */
1248 #define	SMB_BOOT_OEM_HI		191	/* high end of OEM-specific range */
1249 #define	SMB_BOOT_PROD_LO	192	/* low end of product-specific range */
1250 #define	SMB_BOOT_PROD_HI	255	/* high end of product-specific range */
1251 
1252 /*
1253  * SMBIOS IPMI Device Information.  See DSP0134 Section 7.39 and also
1254  * Appendix C1 of the IPMI specification for more information on this record.
1255  */
1256 typedef struct smbios_ipmi {
1257 	uint_t smbip_type;		/* BMC interface type */
1258 	smbios_version_t smbip_vers;	/* BMC's IPMI specification version */
1259 	uint32_t smbip_i2c;		/* BMC I2C bus slave address */
1260 	uint32_t smbip_bus;		/* bus ID of NV storage device, or -1 */
1261 	uint64_t smbip_addr;		/* BMC base address */
1262 	uint32_t smbip_flags;		/* flags (see below) */
1263 	uint16_t smbip_intr;		/* interrupt number (or zero if none) */
1264 	uint16_t smbip_regspacing;	/* i/o space register spacing (bytes) */
1265 } smbios_ipmi_t;
1266 
1267 #define	SMB_IPMI_T_UNKNOWN	0x00	/* unknown */
1268 #define	SMB_IPMI_T_KCS		0x01	/* KCS: Keyboard Controller Style */
1269 #define	SMB_IPMI_T_SMIC		0x02	/* SMIC: Server Mgmt Interface Chip */
1270 #define	SMB_IPMI_T_BT		0x03	/* BT: Block Transfer */
1271 #define	SMB_IPMI_T_SSIF		0x04	/* SSIF: SMBus System Interface */
1272 
1273 #define	SMB_IPMI_F_IOADDR	0x01	/* base address is in i/o space */
1274 #define	SMB_IPMI_F_INTRSPEC	0x02	/* intr information is specified */
1275 #define	SMB_IPMI_F_INTRHIGH	0x04	/* intr active high (else low) */
1276 #define	SMB_IPMI_F_INTREDGE	0x08	/* intr is edge triggered (else lvl) */
1277 
1278 /*
1279  * SMBIOS Onboard Devices Extended Information.  See DSP0134 Section 7.42
1280  * for more information.
1281  */
1282 typedef struct smbios_obdev_ext {
1283 	const char *smboe_name;		/* reference designation */
1284 	uint8_t smboe_dtype;		/* device type */
1285 	uint8_t smboe_dti;		/* device type instance */
1286 	uint16_t smboe_sg;		/* segment group number */
1287 	uint8_t smboe_bus;		/* bus number */
1288 	uint8_t smboe_df;		/* device/function number */
1289 } smbios_obdev_ext_t;
1290 
1291 
1292 /*
1293  * SMBIOS OEM-specific (Type 132) Processor Extended Information.
1294  */
1295 typedef struct smbios_processor_ext {
1296 	uint16_t smbpe_processor;	/* extending processor handle */
1297 	uint8_t smbpe_fru;		/* FRU indicaor */
1298 	uint8_t smbpe_n;		/* number of APIC IDs */
1299 	uint16_t *smbpe_apicid;		/* strand Inital APIC IDs */
1300 } smbios_processor_ext_t;
1301 
1302 /*
1303  * SMBIOS OEM-specific (Type 136) Port Extended Information.
1304  */
1305 typedef struct smbios_port_ext {
1306 	uint16_t smbporte_chassis;	/* chassis handle */
1307 	uint16_t smbporte_port;		/* port connector handle */
1308 	uint8_t smbporte_dtype;		/* device type */
1309 	uint16_t smbporte_devhdl;	/* device handle */
1310 	uint8_t smbporte_phy;		/* PHY number */
1311 } smbios_port_ext_t;
1312 
1313 /*
1314  * SMBIOS OEM-specific (Type 138) PCI-Express RC/RP Information.
1315  */
1316 typedef struct smbios_pciexrc {
1317 	uint16_t smbpcie_bb;		/* base board handle */
1318 	uint16_t smbpcie_bdf;		/* Bus/Dev/Funct (PCI) */
1319 } smbios_pciexrc_t;
1320 
1321 /*
1322  * SMBIOS OEM-specific (Type 144) Memory Array Extended Information.
1323  */
1324 typedef struct smbios_memarray_ext {
1325 	uint16_t smbmae_ma;		/* memory array handle */
1326 	uint16_t smbmae_comp;		/* component parent handle */
1327 	uint16_t smbmae_bdf;		/* Bus/Dev/Funct (PCI) */
1328 } smbios_memarray_ext_t;
1329 
1330 /*
1331  * SMBIOS OEM-specific (Type 145) Memory Device Extended Information.
1332  */
1333 typedef struct smbios_memdevice_ext {
1334 	uint16_t smbmdeve_md;		/* memory device handle */
1335 	uint8_t smbmdeve_drch;		/* DRAM channel */
1336 	uint8_t smbmdeve_ncs;		/* number of chip selects */
1337 	uint8_t *smbmdeve_cs;		/* array of chip select numbers */
1338 } smbios_memdevice_ext_t;
1339 
1340 /*
1341  * SMBIOS Interfaces.  An SMBIOS image can be opened by either providing a file
1342  * pathname, device pathname, file descriptor, or raw memory buffer.  Once an
1343  * image is opened the functions below can be used to iterate over the various
1344  * structures and convert the underlying data representation into the simpler
1345  * data structures described earlier in this header file.  The SMB_VERSION
1346  * constant specified when opening an image indicates the version of the ABI
1347  * the caller expects and the DMTF SMBIOS version the client can understand.
1348  * The library will then map older or newer data structures to that as needed.
1349  */
1350 
1351 #define	SMB_VERSION_23	0x0203		/* SMBIOS encoding for DMTF spec 2.3 */
1352 #define	SMB_VERSION_24	0x0204		/* SMBIOS encoding for DMTF spec 2.4 */
1353 #define	SMB_VERSION_25	0x0205		/* SMBIOS encoding for DMTF spec 2.5 */
1354 #define	SMB_VERSION_26	0x0206		/* SMBIOS encoding for DMTF spec 2.6 */
1355 #define	SMB_VERSION_27	0x0207		/* SMBIOS encoding for DMTF spec 2.7 */
1356 #define	SMB_VERSION_28	0x0208		/* SMBIOS encoding for DMTF spec 2.8 */
1357 #define	SMB_VERSION_30	0x0300		/* SMBIOS encoding for DMTF spec 3.0 */
1358 #define	SMB_VERSION	SMB_VERSION_30	/* SMBIOS latest version definitions */
1359 
1360 #define	SMB_O_NOCKSUM	0x1		/* do not verify header checksums */
1361 #define	SMB_O_NOVERS	0x2		/* do not verify header versions */
1362 #define	SMB_O_ZIDS	0x4		/* strip out identification numbers */
1363 #define	SMB_O_MASK	0x7		/* mask of valid smbios_*open flags */
1364 
1365 #define	SMB_ID_NOTSUP	0xFFFE		/* structure is not supported by BIOS */
1366 #define	SMB_ID_NONE	0xFFFF		/* structure is a null reference */
1367 
1368 #define	SMB_ERR		(-1)		/* id_t value indicating error */
1369 
1370 typedef struct smbios_hdl smbios_hdl_t;
1371 
1372 typedef struct smbios_struct {
1373 	id_t smbstr_id;			/* structure ID handle */
1374 	uint_t smbstr_type;		/* structure type */
1375 	const void *smbstr_data;	/* structure data */
1376 	size_t smbstr_size;		/* structure size */
1377 } smbios_struct_t;
1378 
1379 typedef int smbios_struct_f(smbios_hdl_t *,
1380     const smbios_struct_t *, void *);
1381 
1382 extern smbios_hdl_t *smbios_open(const char *, int, int, int *);
1383 extern smbios_hdl_t *smbios_fdopen(int, int, int, int *);
1384 extern smbios_hdl_t *smbios_bufopen(const smbios_entry_t *,
1385     const void *, size_t, int, int, int *);
1386 
1387 extern const void *smbios_buf(smbios_hdl_t *);
1388 extern size_t smbios_buflen(smbios_hdl_t *);
1389 
1390 extern void smbios_checksum(smbios_hdl_t *, smbios_entry_t *);
1391 extern int smbios_write(smbios_hdl_t *, int);
1392 extern void smbios_close(smbios_hdl_t *);
1393 
1394 extern boolean_t smbios_truncated(smbios_hdl_t *);
1395 extern int smbios_errno(smbios_hdl_t *);
1396 extern const char *smbios_errmsg(int);
1397 
1398 extern int smbios_lookup_id(smbios_hdl_t *, id_t, smbios_struct_t *);
1399 extern int smbios_lookup_type(smbios_hdl_t *, uint_t, smbios_struct_t *);
1400 extern int smbios_iter(smbios_hdl_t *, smbios_struct_f *, void *);
1401 
1402 extern void smbios_info_smbios(smbios_hdl_t *, smbios_entry_t *);
1403 extern int smbios_info_common(smbios_hdl_t *, id_t, smbios_info_t *);
1404 extern int smbios_info_contains(smbios_hdl_t *, id_t, uint_t, id_t *);
1405 extern id_t smbios_info_bios(smbios_hdl_t *, smbios_bios_t *);
1406 extern id_t smbios_info_system(smbios_hdl_t *, smbios_system_t *);
1407 extern int smbios_info_bboard(smbios_hdl_t *, id_t, smbios_bboard_t *);
1408 extern int smbios_info_chassis(smbios_hdl_t *, id_t, smbios_chassis_t *);
1409 extern int smbios_info_processor(smbios_hdl_t *, id_t, smbios_processor_t *);
1410 extern int smbios_info_extprocessor(smbios_hdl_t *, id_t,
1411     smbios_processor_ext_t *);
1412 extern int smbios_info_cache(smbios_hdl_t *, id_t, smbios_cache_t *);
1413 extern int smbios_info_port(smbios_hdl_t *, id_t, smbios_port_t *);
1414 extern int smbios_info_extport(smbios_hdl_t *, id_t, smbios_port_ext_t *);
1415 extern int smbios_info_slot(smbios_hdl_t *, id_t, smbios_slot_t *);
1416 extern int smbios_info_obdevs(smbios_hdl_t *, id_t, int, smbios_obdev_t *);
1417 extern int smbios_info_obdevs_ext(smbios_hdl_t *, id_t, smbios_obdev_ext_t *);
1418 extern int smbios_info_strtab(smbios_hdl_t *, id_t, int, const char *[]);
1419 extern id_t smbios_info_lang(smbios_hdl_t *, smbios_lang_t *);
1420 extern id_t smbios_info_eventlog(smbios_hdl_t *, smbios_evlog_t *);
1421 extern int smbios_info_memarray(smbios_hdl_t *, id_t, smbios_memarray_t *);
1422 extern int smbios_info_extmemarray(smbios_hdl_t *, id_t,
1423     smbios_memarray_ext_t *);
1424 extern int smbios_info_memarrmap(smbios_hdl_t *, id_t, smbios_memarrmap_t *);
1425 extern int smbios_info_memdevice(smbios_hdl_t *, id_t, smbios_memdevice_t *);
1426 extern int smbios_info_extmemdevice(smbios_hdl_t *, id_t,
1427     smbios_memdevice_ext_t *);
1428 extern int smbios_info_memdevmap(smbios_hdl_t *, id_t, smbios_memdevmap_t *);
1429 extern id_t smbios_info_hwsec(smbios_hdl_t *, smbios_hwsec_t *);
1430 extern id_t smbios_info_boot(smbios_hdl_t *, smbios_boot_t *);
1431 extern id_t smbios_info_ipmi(smbios_hdl_t *, smbios_ipmi_t *);
1432 extern int smbios_info_pciexrc(smbios_hdl_t *, id_t, smbios_pciexrc_t *);
1433 
1434 extern const char *smbios_psn(smbios_hdl_t *);
1435 extern const char *smbios_csn(smbios_hdl_t *);
1436 
1437 #ifndef _KERNEL
1438 /*
1439  * The smbios_*_desc() and smbios_*_name() interfaces can be used for utilities
1440  * such as smbios(1M) that wish to decode SMBIOS fields for humans.  The _desc
1441  * functions return the comment string next to the #defines listed above, and
1442  * the _name functions return the appropriate #define identifier itself.
1443  */
1444 extern const char *smbios_bboard_flag_desc(uint_t);
1445 extern const char *smbios_bboard_flag_name(uint_t);
1446 extern const char *smbios_bboard_type_desc(uint_t);
1447 
1448 extern const char *smbios_bios_flag_desc(uint64_t);
1449 extern const char *smbios_bios_flag_name(uint64_t);
1450 
1451 extern const char *smbios_bios_xb1_desc(uint_t);
1452 extern const char *smbios_bios_xb1_name(uint_t);
1453 extern const char *smbios_bios_xb2_desc(uint_t);
1454 extern const char *smbios_bios_xb2_name(uint_t);
1455 
1456 extern const char *smbios_boot_desc(uint_t);
1457 
1458 extern const char *smbios_cache_assoc_desc(uint_t);
1459 extern const char *smbios_cache_ctype_desc(uint_t);
1460 extern const char *smbios_cache_ctype_name(uint_t);
1461 extern const char *smbios_cache_ecc_desc(uint_t);
1462 extern const char *smbios_cache_flag_desc(uint_t);
1463 extern const char *smbios_cache_flag_name(uint_t);
1464 extern const char *smbios_cache_loc_desc(uint_t);
1465 extern const char *smbios_cache_logical_desc(uint_t);
1466 extern const char *smbios_cache_mode_desc(uint_t);
1467 
1468 extern const char *smbios_chassis_state_desc(uint_t);
1469 extern const char *smbios_chassis_type_desc(uint_t);
1470 
1471 extern const char *smbios_evlog_flag_desc(uint_t);
1472 extern const char *smbios_evlog_flag_name(uint_t);
1473 extern const char *smbios_evlog_format_desc(uint_t);
1474 extern const char *smbios_evlog_method_desc(uint_t);
1475 
1476 extern const char *smbios_ipmi_flag_name(uint_t);
1477 extern const char *smbios_ipmi_flag_desc(uint_t);
1478 extern const char *smbios_ipmi_type_desc(uint_t);
1479 
1480 extern const char *smbios_hwsec_desc(uint_t);
1481 
1482 extern const char *smbios_memarray_loc_desc(uint_t);
1483 extern const char *smbios_memarray_use_desc(uint_t);
1484 extern const char *smbios_memarray_ecc_desc(uint_t);
1485 
1486 extern const char *smbios_memdevice_form_desc(uint_t);
1487 extern const char *smbios_memdevice_type_desc(uint_t);
1488 extern const char *smbios_memdevice_flag_name(uint_t);
1489 extern const char *smbios_memdevice_flag_desc(uint_t);
1490 extern const char *smbios_memdevice_rank_desc(uint_t);
1491 
1492 extern const char *smbios_onboard_type_desc(uint_t);
1493 
1494 extern const char *smbios_port_conn_desc(uint_t);
1495 extern const char *smbios_port_type_desc(uint_t);
1496 
1497 extern const char *smbios_processor_family_desc(uint_t);
1498 extern const char *smbios_processor_status_desc(uint_t);
1499 extern const char *smbios_processor_type_desc(uint_t);
1500 extern const char *smbios_processor_upgrade_desc(uint_t);
1501 extern const char *smbios_processor_core_flag_name(uint_t);
1502 extern const char *smbios_processor_core_flag_desc(uint_t);
1503 
1504 extern const char *smbios_slot_type_desc(uint_t);
1505 extern const char *smbios_slot_width_desc(uint_t);
1506 extern const char *smbios_slot_usage_desc(uint_t);
1507 extern const char *smbios_slot_length_desc(uint_t);
1508 extern const char *smbios_slot_ch1_desc(uint_t);
1509 extern const char *smbios_slot_ch1_name(uint_t);
1510 extern const char *smbios_slot_ch2_desc(uint_t);
1511 extern const char *smbios_slot_ch2_name(uint_t);
1512 
1513 extern const char *smbios_type_desc(uint_t);
1514 extern const char *smbios_type_name(uint_t);
1515 
1516 extern const char *smbios_system_wakeup_desc(uint_t);
1517 #endif /* !_KERNEL */
1518 
1519 #ifdef _KERNEL
1520 /*
1521  * For SMBIOS clients within the kernel itself, ksmbios is used to refer to
1522  * the kernel's current snapshot of the SMBIOS, if one exists, and the
1523  * ksmbios_flags tunable is the set of flags for use with smbios_open().
1524  */
1525 extern smbios_hdl_t *ksmbios;
1526 extern int ksmbios_flags;
1527 #endif /* _KERNEL */
1528 
1529 #ifdef	__cplusplus
1530 }
1531 #endif
1532 
1533 #endif	/* _SYS_SMBIOS_H */
1534