xref: /illumos-gate/usr/src/uts/common/sys/scsi/adapters/pmcs/pmcs_param.h (revision 1f81b46471e38fdeb9ab74c25510b2f903f8af12)
14c06356bSdh142964 /*
24c06356bSdh142964  * CDDL HEADER START
34c06356bSdh142964  *
44c06356bSdh142964  * The contents of this file are subject to the terms of the
54c06356bSdh142964  * Common Development and Distribution License (the "License").
64c06356bSdh142964  * You may not use this file except in compliance with the License.
74c06356bSdh142964  *
84c06356bSdh142964  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94c06356bSdh142964  * or http://www.opensolaris.org/os/licensing.
104c06356bSdh142964  * See the License for the specific language governing permissions
114c06356bSdh142964  * and limitations under the License.
124c06356bSdh142964  *
134c06356bSdh142964  * When distributing Covered Code, include this CDDL HEADER in each
144c06356bSdh142964  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154c06356bSdh142964  * If applicable, add the following below this CDDL HEADER, with the
164c06356bSdh142964  * fields enclosed by brackets "[]" replaced with your own identifying
174c06356bSdh142964  * information: Portions Copyright [yyyy] [name of copyright owner]
184c06356bSdh142964  *
194c06356bSdh142964  * CDDL HEADER END
204c06356bSdh142964  */
214c06356bSdh142964 /*
22*1f81b464SDavid Hollister  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
23*1f81b464SDavid Hollister  */
24*1f81b464SDavid Hollister 
25*1f81b464SDavid Hollister /*
264c06356bSdh142964  * PMC Compile Time Tunable Parameters
274c06356bSdh142964  */
284c06356bSdh142964 #ifndef	_PMCS_PARAM_H
294c06356bSdh142964 #define	_PMCS_PARAM_H
304c06356bSdh142964 #ifdef	__cplusplus
314c06356bSdh142964 extern "C" {
324c06356bSdh142964 #endif
334c06356bSdh142964 
344c06356bSdh142964 /*
354c06356bSdh142964  * Maximum number of microseconds we will try to configure a PHY
364c06356bSdh142964  */
374c06356bSdh142964 #define	PMCS_MAX_CONFIG_TIME	(60 * 1000000)
384c06356bSdh142964 
394c06356bSdh142964 #define	PMCS_MAX_OQ		64	/* maximum number of OutBound Queues */
404c06356bSdh142964 #define	PMCS_MAX_IQ		64	/* maximum number of InBound Queues */
414c06356bSdh142964 
424c06356bSdh142964 #define	PMCS_MAX_PORTS		16	/* maximum port contexts */
434c06356bSdh142964 
444c06356bSdh142964 #define	PMCS_MAX_XPND		16	/* 16 levels of expansion */
454c06356bSdh142964 
464c06356bSdh142964 #define	PMCS_INDICES_SIZE	512
474c06356bSdh142964 
484c06356bSdh142964 #define	PMCS_MIN_CHUNK_PAGES	512
494c06356bSdh142964 #define	PMCS_ADDTL_CHUNK_PAGES	8
504c06356bSdh142964 
514c06356bSdh142964 /*
52*1f81b464SDavid Hollister  * Maximum amount of time (in milliseconds) we'll wait for writing one chunk
53*1f81b464SDavid Hollister  * of firmware image data to the chip
54*1f81b464SDavid Hollister  */
55*1f81b464SDavid Hollister #define	PMCS_FLASH_WAIT_TIME	10000	/* 10 seconds */
56*1f81b464SDavid Hollister 
57*1f81b464SDavid Hollister /*
584c06356bSdh142964  * Scratch area has to hold Max SMP Request and Max SMP Response,
594c06356bSdh142964  * plus some slop.
604c06356bSdh142964  */
614c06356bSdh142964 #define	PMCS_SCRATCH_SIZE	2304
624c06356bSdh142964 #define	PMCS_INITIAL_DMA_OFF	PMCS_INDICES_SIZE+PMCS_SCRATCH_SIZE
634c06356bSdh142964 #define	PMCS_CONTROL_SIZE	ptob(1)
644c06356bSdh142964 
654c06356bSdh142964 /*
664c06356bSdh142964  * 2M bytes was allocated to firmware log and split between two logs
674c06356bSdh142964  */
684c06356bSdh142964 #define	PMCS_FWLOG_SIZE		(2 << 20)
694c06356bSdh142964 #define	PMCS_FWLOG_MAX		5	/* maximum logging level */
709719310aSDavid Hollister #define	PMCS_FWLOG_THRESH	75	/* Write to file when log this % full */
719719310aSDavid Hollister 
724c06356bSdh142964 #define	SATLSIZE		1024
734c06356bSdh142964 
744c06356bSdh142964 /*
754c06356bSdh142964  * PMCS_NQENTRY is tunable by setting pmcs-num-io-qentries
764c06356bSdh142964  */
774c06356bSdh142964 #define	PMCS_NQENTRY		512	/* 512 entries per queue */
784c06356bSdh142964 #define	PMCS_MIN_NQENTRY	32	/* No less than 32 entries per queue */
794c06356bSdh142964 #define	PMCS_QENTRY_SIZE	64	/* 64 bytes per entry */
804c06356bSdh142964 #define	PMCS_MSG_SIZE		(PMCS_QENTRY_SIZE >> 2)
814c06356bSdh142964 
824c06356bSdh142964 /*
834c06356bSdh142964  * Watchdog interval, in usecs.
844c06356bSdh142964  * NB: Needs to be evenly divisible by 10
854c06356bSdh142964  */
864c06356bSdh142964 #define	PMCS_WATCH_INTERVAL	250000	/* watchdog interval in us */
874c06356bSdh142964 
884c06356bSdh142964 /*
895c45adf0SJesse Butler  * Forward progress trigger. This is the number of times we run through
905c45adf0SJesse Butler  * watchdog before checking for forward progress.  Implicitly bound to
915c45adf0SJesse Butler  * PMCS_WATCH_INTERVAL above. For example, with a PMCS_WATCH_INTERVAL of
925c45adf0SJesse Butler  * 250000, the watchdog will run every quarter second, so forward progress
935c45adf0SJesse Butler  * will be checked every 16th watchdog fire, or every four seconds.
945c45adf0SJesse Butler  */
955c45adf0SJesse Butler #define	PMCS_FWD_PROG_TRIGGER	16
965c45adf0SJesse Butler 
975c45adf0SJesse Butler /*
984c06356bSdh142964  * Inbound Queue definitions
994c06356bSdh142964  */
1004c06356bSdh142964 #define	PMCS_NIQ		9	/* 9 Inbound Queues */
1014c06356bSdh142964 #define	PMCS_IO_IQ_MASK		7	/* IO queues are 0..7 */
1024c06356bSdh142964 #define	PMCS_IQ_OTHER		8	/* "Other" queue is 8 (HiPri) */
1034c06356bSdh142964 #define	PMCS_NON_HIPRI_QUEUES	PMCS_IO_IQ_MASK
1044c06356bSdh142964 
1054c06356bSdh142964 /*
1064c06356bSdh142964  * Outbound Queue definitions
1074c06356bSdh142964  *
1084c06356bSdh142964  * Note that the OQ definitions map to bits set in
1094c06356bSdh142964  * the Outbound Doorbell register to indicate service
1104c06356bSdh142964  * is needed on one of these queues.
1114c06356bSdh142964  */
1124c06356bSdh142964 #define	PMCS_NOQ		3	/* 3 Outbound Queues */
1134c06356bSdh142964 
1144c06356bSdh142964 #define	PMCS_OQ_IODONE		0	/* I/O completion Outbound Queue */
1154c06356bSdh142964 #define	PMCS_OQ_GENERAL		1	/* General Outbound Queue */
1164c06356bSdh142964 #define	PMCS_OQ_EVENTS		2	/* Event Outbound Queue */
1174c06356bSdh142964 
1184c06356bSdh142964 
1194c06356bSdh142964 /*
1204c06356bSdh142964  * External Scatter Gather come in chunks- each this many deep.
1214c06356bSdh142964  */
1224c06356bSdh142964 #define	PMCS_SGL_NCHUNKS	16	/* S/G List Chunk Size */
1234c06356bSdh142964 #define	PMCS_MAX_CHUNKS		32	/* max chunks per command */
1244c06356bSdh142964 
1254c06356bSdh142964 /*
1264c06356bSdh142964  * MSI/MSI-X related definitions.
1274c06356bSdh142964  *
1284c06356bSdh142964  * These are the maximum number of interrupt vectors we could use.
1294c06356bSdh142964  */
1304c06356bSdh142964 #define	PMCS_MAX_MSIX		(PMCS_NOQ + 1)
1314c06356bSdh142964 #define	PMCS_MAX_MSI		PMCS_MAX_MSIX
1324c06356bSdh142964 #define	PMCS_MAX_FIXED		1
1334c06356bSdh142964 
1344c06356bSdh142964 #define	PMCS_MSIX_IODONE	PMCS_OQ_IODONE	/* I/O Interrupt vector */
1354c06356bSdh142964 #define	PMCS_MSIX_GENERAL	PMCS_OQ_GENERAL	/* General Interrupt vector */
1364c06356bSdh142964 #define	PMCS_MSIX_EVENTS	PMCS_OQ_EVENTS	/* Events Interrupt vector */
1374c06356bSdh142964 #define	PMCS_MSIX_FATAL		(PMCS_MAX_MSIX-1)	/* Fatal Int vector */
1384c06356bSdh142964 
1394c06356bSdh142964 #define	PMCS_FATAL_INTERRUPT	15	/* fatal interrupt OBDB bit */
1404c06356bSdh142964 
1414c06356bSdh142964 /*
1424c06356bSdh142964  * Blessed firmware version
1434c06356bSdh142964  */
1444c06356bSdh142964 #define	PMCS_FIRMWARE_CODE_NAME		"firmware"
1454c06356bSdh142964 #define	PMCS_FIRMWARE_ILA_NAME		"ila"
1464c06356bSdh142964 #define	PMCS_FIRMWARE_SPCBOOT_NAME	"SPCBoot"
1474c06356bSdh142964 #define	PMCS_FIRMWARE_START_SUF		".bin_start"
1484c06356bSdh142964 #define	PMCS_FIRMWARE_END_SUF		".bin_end"
1494c06356bSdh142964 #define	PMCS_FIRMWARE_FILENAME		"misc/pmcs/pmcs8001fw"
1504c06356bSdh142964 #define	PMCS_FIRMWARE_VERSION_NAME	"pmcs8001_fwversion"
1514c06356bSdh142964 
1522ac4abe8SDavid Hollister /*
1532ac4abe8SDavid Hollister  * These are offsets from the end of the image
1542ac4abe8SDavid Hollister  */
1552ac4abe8SDavid Hollister #define	PMCS_FW_VER_OFFSET		528
1562ac4abe8SDavid Hollister #define	PMCS_ILA_VER_OFFSET		528
1572ac4abe8SDavid Hollister 
1584c06356bSdh142964 #ifdef	__cplusplus
1594c06356bSdh142964 }
1604c06356bSdh142964 #endif
1614c06356bSdh142964 #endif	/* _PMCS_PARAM_H */
162