1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _PMCS_DEF_H 26 #define _PMCS_DEF_H 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 typedef enum { 32 NOTHING, /* nothing connected here */ 33 SATA, /* SATA connection */ 34 SAS, /* direct or indirect SAS connection */ 35 EXPANDER, /* connection to an expander */ 36 NEW /* Brand new device (pending state) */ 37 } pmcs_dtype_t; 38 39 /* 40 * This structure defines a PHY device that represents what we 41 * are connected to. 42 * 43 * The eight real physical PHYs that are in the PMC8X6G are represented 44 * as an array of eight of these structures which define what these 45 * real PHYs are connected to. 46 * 47 * Depending upon what is actually connected to each PHY, the 48 * type set will define what we're connected to. If it is 49 * a direct SATA connection, the phy will describe a SATA endpoint 50 * If it is a direct SAS connection, it will describe a SAS 51 * endpoint. 52 * 53 * If it is an EXPANDER, this will describe the edge of an expander. 54 * As we perform discovery on what is in an EXPANDER we define an 55 * additional list of phys that represent what the Expander is connected to. 56 */ 57 #define PMCS_HW_MIN_LINK_RATE SAS_LINK_RATE_1_5GBIT 58 #define PMCS_HW_MAX_LINK_RATE SAS_LINK_RATE_6GBIT 59 60 #define PMCS_INVALID_DEVICE_ID 0xffffffff 61 62 struct pmcs_phy { 63 pmcs_phy_t *sibling; /* sibling phy */ 64 pmcs_phy_t *parent; /* parent phy */ 65 pmcs_phy_t *children; /* head of list of children */ 66 pmcs_phy_t *dead_next; /* dead PHY list link */ 67 list_node_t list_node; /* list element */ 68 uint32_t device_id; /* PMC8X6G device handle */ 69 uint32_t 70 ncphy : 8, /* # of contained phys for expander */ 71 hw_event_ack : 24; /* XXX: first level phy event acked */ 72 uint8_t phynum; /* phy number on parent expander */ 73 uint8_t width; /* how many phys wide */ 74 uint8_t ds_recovery_retries; /* # error retry attempts */ 75 pmcs_dtype_t dtype; /* current dtype of the phy */ 76 pmcs_dtype_t pend_dtype; /* new dtype (pending change) */ 77 uint32_t 78 level : 8, /* level in expander tree */ 79 tolerates_sas2 : 1, /* tolerates SAS2 SMP */ 80 spinup_hold : 1, /* spinup hold needs releasing */ 81 atdt : 3, /* attached device type */ 82 portid : 4, /* PMC8X6G port context */ 83 link_rate : 4, /* current supported speeds */ 84 valid_device_id : 1, /* device id is valid */ 85 abort_sent : 1, /* we've sent an abort */ 86 abort_pending : 1, /* we have an abort pending */ 87 need_rl_ext : 1, /* need SATA RL_EXT recocvery */ 88 subsidiary : 1, /* this is part of a wide phy */ 89 configured : 1, /* is configured */ 90 dead : 1, /* dead */ 91 changed : 1; /* this phy is changing */ 92 clock_t config_stop; /* When config attempts will stop */ 93 hrtime_t abort_all_start; 94 kcondvar_t abort_all_cv; /* Wait for ABORT_ALL completion */ 95 kmutex_t phy_lock; 96 volatile uint32_t ref_count; /* Targets & work on this PHY */ 97 uint8_t sas_address[8]; /* SAS address for this PHY */ 98 struct { 99 uint32_t 100 prog_min_rate :4, 101 hw_min_rate :4, 102 prog_max_rate :4, 103 hw_max_rate :4, 104 reserved :16; 105 } state; 106 char path[32]; /* path name for this phy */ 107 pmcs_hw_t *pwp; /* back ptr to hba struct */ 108 pmcs_iport_t *iport; /* back ptr to the iport handle */ 109 pmcs_xscsi_t *target; /* back ptr to current target */ 110 kstat_t *phy_stats; /* kstats for this phy */ 111 }; 112 113 /* maximum number of ds recovery retries (ds_recovery_retries) */ 114 #define PMCS_MAX_DS_RECOVERY_RETRIES 4 115 116 117 /* 118 * Inbound and Outbound Queue Related Definitions. 119 * 120 * The PMC8X6G has a programmable number of inbound and outbound circular 121 * queues for use in message passing between the host and the PMC8X6G 122 * (up to 64 queues for the Rev C Chip). This driver does not use all 123 * possible queues. 124 * 125 * Each Queue is given 4K of consistent memory and we set a 64 byte size for 126 * the queue entry size (this gives us 256 queue entries per queue). 127 * 128 * This allocation then continues up a further PMCS_SCRATCH_SIZE bytes 129 * that the driver uses as a temporary scratch area for things like 130 * SMP discovery. 131 * 132 * This control area looks like this: 133 * 134 * Offset What 135 * ------------------------------------------------ 136 * 0 IQ 0 Consumer Index 137 * 4 IQ 1 Consumer Index 138 * 8..255 ... 139 * 252..255 IQ 63 Consumer Index 140 * 256 OQ 0 Producer Index 141 * 260 OQ 1 Producer Index 142 * 264..259 .... 143 * 508..511 OQ 63 Producer Index 144 * 512..512+PMCS_SCRATCH_SIZE-1 Scratch area. 145 */ 146 #define IQCI_BASE_OFFSET 0 147 #define IQ_OFFSET(qnum) (IQCI_BASE_OFFSET + (qnum << 2)) 148 #define OQPI_BASE_OFFSET 256 149 #define OQ_OFFSET(qnum) (OQPI_BASE_OFFSET + (qnum << 2)) 150 151 /* 152 * Work related structures. Each one of these structures is paired 153 * with *any* command that is fed to the PMC8X6G via one of the 154 * Inbound Queues. The work structure has a tag to compare with 155 * the message that comes back out of an Outbound Queue. The 156 * work structure also points to the phy which this command is 157 * tied to. It also has a pointer a callback function (if defined). 158 * See that TAG Architecture below for the various kinds of 159 * dispositions of a work structure. 160 */ 161 162 /* 163 * Work Structure States 164 * 165 * NIL -> READY 166 * READY -> NIL 167 * READY -> ONCHIP 168 * ONCHIP -> INTR 169 * INTR -> READY 170 * INTR -> NIL 171 * INTR -> ABORTED 172 * INTR -> TIMED_OUT 173 * ABORTED -> NIL 174 * TIMED_OUT -> NIL 175 */ 176 typedef enum { 177 PMCS_WORK_STATE_NIL = 0, 178 PMCS_WORK_STATE_READY, 179 PMCS_WORK_STATE_ONCHIP, 180 PMCS_WORK_STATE_INTR, 181 PMCS_WORK_STATE_IOCOMPQ, 182 PMCS_WORK_STATE_ABORTED, 183 PMCS_WORK_STATE_TIMED_OUT 184 } pmcs_work_state_t; 185 186 struct pmcwork { 187 STAILQ_ENTRY(pmcwork) next; 188 kmutex_t lock; 189 kcondvar_t sleep_cv; 190 void *ptr; /* linkage or callback function */ 191 void *arg; /* command specific data */ 192 pmcs_phy_t *phy; /* phy who owns this command */ 193 pmcs_xscsi_t *xp; /* Back pointer to xscsi struct */ 194 volatile uint32_t htag; /* tag for this structure */ 195 uint32_t abt_htag; /* Tag of command to be aborted */ 196 uint32_t 197 timer : 27, 198 onwire : 1, 199 dead : 1, 200 state : 3; 201 hrtime_t start; /* timestamp start */ 202 uint32_t ssp_event; /* ssp event */ 203 pmcs_dtype_t dtype; /* stash, incase phy gets cleared */ 204 205 void *last_ptr; 206 void *last_arg; 207 pmcs_phy_t *last_phy; 208 pmcs_xscsi_t *last_xp; 209 uint32_t last_htag; 210 pmcs_work_state_t last_state; 211 hrtime_t finish; 212 }; 213 214 #define PMCS_REC_EVENT 0xffffffff /* event recovery */ 215 216 /* 217 * This structure defines a PMC-Sierra defined firmware header. 218 */ 219 #pragma pack(4) 220 typedef struct { 221 char vendor_id[8]; 222 uint8_t product_id; 223 uint8_t hwrev; 224 uint8_t destination_partition; 225 uint8_t reserved0; 226 uint8_t fwrev[4]; 227 uint32_t firmware_length; 228 uint32_t crc; 229 uint32_t start_address; 230 uint8_t data[]; 231 } pmcs_fw_hdr_t; 232 #pragma pack() 233 234 /* 235 * Offlevel work as a bit pattern. 236 */ 237 #define PMCS_WORK_DISCOVER 0 238 #define PMCS_WORK_ABORT_HANDLE 3 239 #define PMCS_WORK_SPINUP_RELEASE 4 240 #define PMCS_WORK_SAS_HW_ACK 5 241 #define PMCS_WORK_SATA_RUN 6 242 #define PMCS_WORK_RUN_QUEUES 7 243 #define PMCS_WORK_ADD_DMA_CHUNKS 8 244 #define PMCS_WORK_DS_ERR_RECOVERY 9 245 #define PMCS_WORK_SSP_EVT_RECOVERY 10 246 247 /* 248 * The actual values as they appear in work_flags 249 */ 250 #define PMCS_WORK_FLAG_DISCOVER (1 << 0) 251 #define PMCS_WORK_FLAG_ABORT_HANDLE (1 << 3) 252 #define PMCS_WORK_FLAG_SPINUP_RELEASE (1 << 4) 253 #define PMCS_WORK_FLAG_SAS_HW_ACK (1 << 5) 254 #define PMCS_WORK_FLAG_SATA_RUN (1 << 6) 255 #define PMCS_WORK_FLAG_RUN_QUEUES (1 << 7) 256 #define PMCS_WORK_FLAG_ADD_DMA_CHUNKS (1 << 8) 257 #define PMCS_WORK_FLAG_DS_ERR_RECOVERY (1 << 9) 258 #define PMCS_WORK_FLAG_SSP_EVT_RECOVERY (1 << 10) 259 260 /* 261 * This structure is used by this function to test MPI (and interrupts) 262 * after MPI has been started to make sure it's working reliably. 263 */ 264 typedef struct { 265 uint32_t signature; 266 uint32_t count; 267 uint32_t *ptr; 268 } echo_test_t; 269 #define ECHO_SIGNATURE 0xbebebeef 270 271 /* 272 * Tag Architecture. The PMC has 32 bit tags for MPI messages. 273 * We use this tag this way. 274 * 275 * bits what 276 * ------------------------ 277 * 31 done bit 278 * 30..28 tag type 279 * 27..12 rolling serial number 280 * 11..0 index into work area to get pmcwork structure 281 * 282 * A tag type of NONE means that nobody is waiting on any results, 283 * so the interrupt code frees the work structure that has this 284 * tag. 285 * 286 * A tag type of CBACK means that the the interrupt handler 287 * takes the tag 'arg' in the work structure to be a callback 288 * function pointer (see pmcs_cb_t). The callee is responsible 289 * for freeing the work structure that has this tag. 290 * 291 * A tag type of WAIT means that the issuer of the work needs 292 * be woken up from interrupt level when the command completes 293 * (or times out). If work structure tag 'arg' is non-null, 294 * up to 2*PMCS_QENTRY_SIZE bits of data from the Outbound Queue 295 * entry may be copied to the area pointed to by 'arg'. This 296 * allows issuers to get directly at the results of the command 297 * they issed. The synchronization point for the issuer and the 298 * interrupt code for command done notification is the setting 299 * of the 'DONE' bit in the tag as stored in the work structure. 300 */ 301 #define PMCS_TAG_TYPE_FREE 0 302 #define PMCS_TAG_TYPE_NONE 1 303 #define PMCS_TAG_TYPE_CBACK 2 304 #define PMCS_TAG_TYPE_WAIT 3 305 #define PMCS_TAG_TYPE_SHIFT 28 306 #define PMCS_TAG_SERNO_SHIFT 12 307 #define PMCS_TAG_INDEX_SHIFT 0 308 #define PMCS_TAG_TYPE_MASK 0x70000000 309 #define PMCS_TAG_DONE 0x80000000 310 #define PMCS_TAG_SERNO_MASK 0x0ffff000 311 #define PMCS_TAG_INDEX_MASK 0x00000fff 312 #define PMCS_TAG_TYPE(x) \ 313 (((x) & PMCS_TAG_TYPE_MASK) >> PMCS_TAG_TYPE_SHIFT) 314 #define PMCS_TAG_SERNO(x) \ 315 (((x) & PMCS_TAG_SERNO_MASK) >> PMCS_TAG_SERNO_SHIFT) 316 #define PMCS_TAG_INDEX(x) \ 317 (((x) & PMCS_TAG_INDEX_MASK) >> PMCS_TAG_INDEX_SHIFT) 318 #define PMCS_TAG_FREE 0 319 #define PMCS_COMMAND_DONE(x) \ 320 (((x)->htag == PMCS_TAG_FREE) || (((x)->htag & PMCS_TAG_DONE) != 0)) 321 #define PMCS_COMMAND_ACTIVE(x) \ 322 ((x)->htag != PMCS_TAG_FREE && (x)->state == PMCS_WORK_STATE_ONCHIP) 323 324 /* 325 * Miscellaneous Definitions 326 */ 327 #define CLEAN_MESSAGE(m, x) { \ 328 int _j = x; \ 329 while (_j < PMCS_MSG_SIZE) { \ 330 m[_j++] = 0; \ 331 } \ 332 } 333 334 #define COPY_MESSAGE(t, f, a) { \ 335 int _j; \ 336 for (_j = 0; _j < a; _j++) { \ 337 t[_j] = f[_j]; \ 338 } \ 339 while (_j < PMCS_MSG_SIZE) { \ 340 t[_j++] = 0; \ 341 } \ 342 } 343 344 #define PMCS_PHY_ADDRESSABLE(pp) \ 345 ((pp)->level == 0 && (pp)->dtype == SATA && \ 346 ((pp)->sas_address[0] >> 4) != 5) 347 348 #define RESTART_DISCOVERY(pwp) \ 349 ASSERT(!mutex_owned(&pwp->config_lock)); \ 350 mutex_enter(&pwp->config_lock); \ 351 pwp->config_changed = B_TRUE; \ 352 mutex_exit(&pwp->config_lock); \ 353 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 354 355 #define RESTART_DISCOVERY_LOCKED(pwp) \ 356 ASSERT(mutex_owned(&pwp->config_lock)); \ 357 pwp->config_changed = B_TRUE; \ 358 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 359 360 #define PHY_CHANGED(pwp, p) \ 361 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 362 "%s line %d", p->path, __func__, __LINE__); \ 363 p->changed = 1 364 365 #define PHY_CHANGED_AT_LOCATION(pwp, p, func, line) \ 366 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 367 "%s line %d", p->path, func, line); \ 368 p->changed = 1 369 370 #define PHY_TYPE(pptr) \ 371 (((pptr)->dtype == NOTHING)? "NOTHING" : \ 372 (((pptr)->dtype == SATA)? "SATA" : \ 373 (((pptr)->dtype == SAS)? "SAS" : "EXPANDER"))) 374 375 #define IS_ROOT_PHY(pptr) (pptr->parent == NULL) 376 377 #define PMCS_HIPRI(pwp, oq, c) \ 378 (pwp->hipri_queue & (1 << PMCS_IQ_OTHER)) ? \ 379 (PMCS_IOMB_HIPRI | PMCS_IOMB_IN_SAS(oq, c)) : \ 380 (PMCS_IOMB_IN_SAS(oq, c)) 381 382 #define SCHEDULE_WORK(hwp, wrk) \ 383 (void) atomic_set_long_excl(&hwp->work_flags, wrk) 384 385 /* 386 * Check to see if the requested work bit is set. Either way, the bit will 387 * be cleared upon return. 388 */ 389 #define WORK_SCHEDULED(hwp, wrk) \ 390 (atomic_clear_long_excl(&hwp->work_flags, wrk) == 0) 391 392 /* 393 * Check to see if the requested work bit is set. The value will not be 394 * changed in this case. The atomic_xx_nv operations can be quite expensive 395 * so this should not be used in non-DEBUG code. 396 */ 397 #define WORK_IS_SCHEDULED(hwp, wrk) \ 398 ((atomic_and_ulong_nv(&hwp->work_flags, (ulong_t)-1) & (1 << wrk)) != 0) 399 400 #define WAIT_FOR(p, t, r) \ 401 r = 0; \ 402 while (!PMCS_COMMAND_DONE(p)) { \ 403 clock_t tmp = cv_timedwait(&p->sleep_cv, \ 404 &p->lock, ddi_get_lbolt() + \ 405 drv_usectohz(t * 1000)); \ 406 if (!PMCS_COMMAND_DONE(p) && tmp < 0) { \ 407 r = 1; \ 408 break; \ 409 } \ 410 } 411 412 /* 413 * Signal the next I/O completion thread to start running. 414 */ 415 416 #define PMCS_CQ_RUN_LOCKED(hwp) \ 417 if (!STAILQ_EMPTY(&hwp->cq) || hwp->iocomp_cb_head) { \ 418 pmcs_cq_thr_info_t *cqti; \ 419 cqti = &hwp->cq_info.cq_thr_info \ 420 [hwp->cq_info.cq_next_disp_thr]; \ 421 hwp->cq_info.cq_next_disp_thr++; \ 422 if (hwp->cq_info.cq_next_disp_thr == \ 423 hwp->cq_info.cq_threads) { \ 424 hwp->cq_info.cq_next_disp_thr = 0; \ 425 } \ 426 mutex_enter(&cqti->cq_thr_lock); \ 427 cv_signal(&cqti->cq_cv); \ 428 mutex_exit(&cqti->cq_thr_lock); \ 429 } \ 430 431 #define PMCS_CQ_RUN(hwp) \ 432 mutex_enter(&hwp->cq_lock); \ 433 PMCS_CQ_RUN_LOCKED(hwp); \ 434 mutex_exit(&hwp->cq_lock); 435 436 437 /* 438 * Watchdog/SCSA timer definitions 439 */ 440 /* usecs to SCSA watchdog ticks */ 441 #define US2WT(x) (x)/10 442 443 /* 444 * More misc 445 */ 446 #define BYTE0(x) (((x) >> 0) & 0xff) 447 #define BYTE1(x) (((x) >> 8) & 0xff) 448 #define BYTE2(x) (((x) >> 16) & 0xff) 449 #define BYTE3(x) (((x) >> 24) & 0xff) 450 #define BYTE4(x) (((x) >> 32) & 0xff) 451 #define BYTE5(x) (((x) >> 40) & 0xff) 452 #define BYTE6(x) (((x) >> 48) & 0xff) 453 #define BYTE7(x) (((x) >> 56) & 0xff) 454 #define WORD0(x) (((x) >> 0) & 0xffff) 455 #define WORD1(x) (((x) >> 16) & 0xffff) 456 #define WORD2(x) (((x) >> 32) & 0xffff) 457 #define WORD3(x) (((x) >> 48) & 0xffff) 458 #define DWORD0(x) ((uint32_t)(x)) 459 #define DWORD1(x) ((uint32_t)(((uint64_t)x) >> 32)) 460 461 #define SAS_ADDR_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" 462 #define SAS_ADDR_PRT(x) x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7] 463 464 #define PMCS_VALID_LINK_RATE(r) \ 465 ((r == SAS_LINK_RATE_1_5GBIT) || (r == SAS_LINK_RATE_3GBIT) || \ 466 (r == SAS_LINK_RATE_6GBIT)) 467 468 /* 469 * This is here to avoid inclusion of <sys/ctype.h> which is not lint clean. 470 */ 471 #define HEXDIGIT(x) (((x) >= '0' && (x) <= '9') || \ 472 ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F')) 473 474 475 typedef void (*pmcs_cb_t) (pmcs_hw_t *, pmcwork_t *, uint32_t *); 476 477 /* 478 * Defines and structure used for tracing/logging information 479 */ 480 481 #define PMCS_TBUF_ELEM_SIZE 120 482 483 #ifdef DEBUG 484 #define PMCS_TBUF_NUM_ELEMS_DEF 100000 485 #else 486 #define PMCS_TBUF_NUM_ELEMS_DEF 15000 487 #endif 488 489 #define PMCS_TBUF_UA_MAX_SIZE 32 490 typedef struct { 491 /* Target-specific data */ 492 uint16_t target_num; 493 char target_ua[PMCS_TBUF_UA_MAX_SIZE]; 494 /* PHY-specific data */ 495 uint8_t phy_sas_address[8]; 496 char phy_path[32]; 497 pmcs_dtype_t phy_dtype; 498 /* Log data */ 499 timespec_t timestamp; 500 char buf[PMCS_TBUF_ELEM_SIZE]; 501 } pmcs_tbuf_t; 502 503 /* 504 * Firmware event log header format 505 */ 506 507 typedef struct pmcs_fw_event_hdr_s { 508 uint32_t fw_el_signature; 509 uint32_t fw_el_entry_start_offset; 510 uint32_t fw_el_rsvd1; 511 uint32_t fw_el_buf_size; 512 uint32_t fw_el_rsvd2; 513 uint32_t fw_el_oldest_idx; 514 uint32_t fw_el_latest_idx; 515 uint32_t fw_el_entry_size; 516 } pmcs_fw_event_hdr_t; 517 518 #ifdef __cplusplus 519 } 520 #endif 521 #endif /* _PMCS_DEF_H */ 522