1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/file.h> 42 #include <sys/isa_defs.h> 43 #include <sys/sunmdi.h> 44 #include <sys/mdi_impldefs.h> 45 #include <sys/scsi/scsi.h> 46 #include <sys/scsi/impl/scsi_reset_notify.h> 47 #include <sys/scsi/impl/scsi_sas.h> 48 #include <sys/scsi/impl/smp_transport.h> 49 #include <sys/scsi/generic/sas.h> 50 #include <sys/scsi/generic/smp_frames.h> 51 #include <sys/atomic.h> 52 #include <sys/byteorder.h> 53 #include <sys/sysmacros.h> 54 #include <sys/bitmap.h> 55 #include <sys/queue.h> 56 #include <sys/sdt.h> 57 #include <sys/ddifm.h> 58 #include <sys/fm/protocol.h> 59 #include <sys/fm/util.h> 60 #include <sys/fm/io/ddi.h> 61 #include <sys/scsi/impl/spc3_types.h> 62 63 typedef struct pmcs_hw pmcs_hw_t; 64 typedef struct pmcs_iport pmcs_iport_t; 65 typedef struct pmcs_phy pmcs_phy_t; 66 typedef struct lsas_cmd lsas_cmd_t; 67 typedef struct lsas_result lsas_result_t; 68 typedef struct lsata_cmd lsata_cmd_t; 69 typedef struct lsata_result lsata_result_t; 70 typedef struct pmcwork pmcwork_t; 71 typedef struct pmcs_cmd pmcs_cmd_t; 72 typedef struct pmcs_xscsi pmcs_xscsi_t; 73 typedef struct pmcs_lun pmcs_lun_t; 74 typedef struct pmcs_chunk pmcs_chunk_t; 75 76 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 80 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 81 82 #include <sys/scsi/adapters/pmcs/ata.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 86 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 87 88 #define PMCS_MAX_UA_SIZE 32 89 90 struct pmcs_xscsi { 91 uint32_t 92 ca : 1, /* SATA specific */ 93 ncq : 1, /* SATA specific */ 94 pio : 1, /* SATA specific */ 95 special_needed : 1, /* SATA specific */ 96 special_running : 1, /* SATA specific */ 97 reset_success : 1, /* last reset ok */ 98 reset_wait : 1, /* wait for reset */ 99 resetting : 1, /* now resetting */ 100 recover_wait : 1, /* wait for recovery */ 101 recovering : 1, /* now recovering */ 102 event_recovery : 1, /* event recovery */ 103 draining : 1, 104 new : 1, 105 assigned : 1, 106 dev_gone : 1, 107 phy_addressable : 1, /* Direct attach SATA */ 108 dev_state : 4; 109 uint16_t maxdepth; 110 uint16_t qdepth; 111 uint16_t actv_cnt; /* Pkts ON CHIP */ 112 uint16_t actv_pkts; /* Pkts in driver */ 113 uint16_t target_num; 114 /* statlock protects both target stats and the special queue (sq) */ 115 kmutex_t statlock; 116 int32_t ref_count; 117 dev_info_t *dip; /* Solaris device dip */ 118 pmcs_phy_t *phy; 119 STAILQ_HEAD(wqh, pmcs_cmd) wq; 120 pmcs_cmd_t *wq_recovery_tail; /* See below */ 121 kmutex_t wqlock; 122 STAILQ_HEAD(aqh, pmcs_cmd) aq; 123 kmutex_t aqlock; 124 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 125 uint32_t tagmap; /* SATA specific */ 126 pmcs_hw_t *pwp; 127 ddi_soft_state_bystr *lun_sstate; 128 uint64_t capacity; /* SATA specific */ 129 char unit_address[PMCS_MAX_UA_SIZE]; 130 kcondvar_t reset_cv; 131 kcondvar_t abort_cv; 132 char *ua; 133 pmcs_dtype_t dtype; 134 list_t lun_list; /* list of LUNs */ 135 struct smp_device *smpd; /* Ptr to smp_device */ 136 }; 137 138 /* 139 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 140 * the wait queue (wq). That pointer is the last command in the wait queue 141 * that needs to be reissued after device state recovery is complete. Commands 142 * that need to be retried are reinserted into the wq after wq_recovery_tail 143 * to maintain the order in which the commands were originally submitted. 144 */ 145 146 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 147 148 #define PMCS_TGT_WAIT_QUEUE 0x01 149 #define PMCS_TGT_ACTIVE_QUEUE 0x02 150 #define PMCS_TGT_SPECIAL_QUEUE 0x04 151 #define PMCS_TGT_ALL_QUEUES 0xff 152 153 /* 154 * LUN representation. Just a LUN (number) and pointer to the target 155 * structure (pmcs_xscsi). 156 */ 157 158 struct pmcs_lun { 159 list_node_t lun_list_next; 160 pmcs_xscsi_t *target; 161 struct scsi_device *sd; 162 uint64_t lun_num; /* lun64 */ 163 scsi_lun_t scsi_lun; /* Wire format */ 164 char unit_address[PMCS_MAX_UA_SIZE]; 165 }; 166 167 /* 168 * Interrupt coalescing values 169 */ 170 #define PMCS_MAX_IO_COMPS_PER_INTR 12 171 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 172 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 173 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 174 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 175 #define PMCS_MAX_CQ_THREADS 4 176 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 177 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 178 179 /* 180 * This structure is used to maintain state with regard to I/O interrupt 181 * coalescing. 182 */ 183 184 typedef struct pmcs_io_intr_coal_s { 185 hrtime_t nsecs_between_intrs; 186 hrtime_t last_io_comp; 187 clock_t quantum; 188 uint32_t num_io_completions; 189 uint32_t num_intrs; 190 uint32_t max_io_completions; 191 uint32_t intr_latency; 192 uint32_t intr_threshold; 193 uint16_t intr_coal_timer; 194 boolean_t timer_on; 195 boolean_t stop_thread; 196 boolean_t int_cleared; 197 } pmcs_io_intr_coal_t; 198 199 typedef struct pmcs_cq_thr_info_s { 200 kthread_t *cq_thread; 201 kmutex_t cq_thr_lock; 202 kcondvar_t cq_cv; 203 pmcs_hw_t *cq_pwp; 204 } pmcs_cq_thr_info_t; 205 206 typedef struct pmcs_cq_info_s { 207 uint32_t cq_threads; 208 uint32_t cq_next_disp_thr; 209 boolean_t cq_stop; 210 pmcs_cq_thr_info_t *cq_thr_info; 211 } pmcs_cq_info_t; 212 213 typedef struct pmcs_iocomp_cb_s { 214 pmcwork_t *pwrk; 215 char iomb[PMCS_QENTRY_SIZE << 1]; 216 struct pmcs_iocomp_cb_s *next; 217 } pmcs_iocomp_cb_t; 218 219 typedef struct pmcs_iqp_trace_s { 220 char *head; 221 char *curpos; 222 uint32_t size_left; 223 } pmcs_iqp_trace_t; 224 225 /* 226 * Used by string-based softstate as hint to possible size. 227 */ 228 229 #define PMCS_TGT_SSTATE_SZ 64 230 #define PMCS_LUN_SSTATE_SZ 4 231 232 /* 233 * HBA iport node softstate 234 */ 235 #define PMCS_IPORT_INVALID_PORT_ID 0xf 236 237 struct pmcs_iport { 238 kmutex_t lock; /* iport lock */ 239 list_node_t list_node; /* list node for pwp->iports list_t */ 240 kmutex_t refcnt_lock; /* refcnt lock */ 241 kcondvar_t refcnt_cv; /* refcnt cv */ 242 int refcnt; /* refcnt for this iport */ 243 dev_info_t *dip; /* iport dip */ 244 pmcs_hw_t *pwp; /* back pointer to HBA state */ 245 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 246 enum { /* unit address state in the phymap */ 247 UA_INACTIVE, 248 UA_PEND_ACTIVATE, 249 UA_ACTIVE, 250 UA_PEND_DEACTIVATE 251 } ua_state; 252 char *ua; /* unit address (phy mask) */ 253 int portid; /* portid */ 254 int report_skip; /* skip or report during discovery */ 255 list_t phys; /* list of phys on this port */ 256 int nphy; /* number of phys in this port */ 257 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 258 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 259 /* SMP serialization */ 260 kmutex_t smp_lock; 261 kcondvar_t smp_cv; 262 boolean_t smp_active; 263 kthread_t *smp_active_thread; 264 }; 265 266 struct pmcs_chunk { 267 pmcs_chunk_t *next; 268 ddi_acc_handle_t acc_handle; 269 ddi_dma_handle_t dma_handle; 270 uint8_t *addrp; 271 uint64_t dma_addr; 272 }; 273 274 /* 275 * HBA node (i.e. non-iport) softstate 276 */ 277 struct pmcs_hw { 278 /* 279 * Identity 280 */ 281 dev_info_t *dip; 282 283 /* 284 * 16 possible initiator PHY WWNs 285 */ 286 uint64_t sas_wwns[PMCS_MAX_PORTS]; 287 288 /* 289 * Card State 290 */ 291 enum pwpstate { 292 STATE_NIL, 293 STATE_PROBING, 294 STATE_RUNNING, 295 STATE_UNPROBING, 296 STATE_IN_RESET, 297 STATE_DEAD 298 } state; 299 300 /* 301 * Last reason for a soft reset 302 */ 303 enum pwp_last_reset_reason { 304 PMCS_LAST_RST_UNINIT, 305 PMCS_LAST_RST_ATTACH, 306 PMCS_LAST_RST_FW_UPGRADE, 307 PMCS_LAST_RST_FATAL_ERROR, 308 PMCS_LAST_RST_STALL, 309 PMCS_LAST_RST_QUIESCE, 310 PMCS_LAST_RST_DETACH 311 } last_reset_reason; 312 313 uint32_t 314 fw_disable_update : 1, 315 fw_force_update : 1, 316 blocked : 1, 317 stuck : 1, 318 locks_initted : 1, 319 mpi_table_setup : 1, 320 hba_attached : 1, 321 iports_attached : 1, 322 suspended : 1, 323 separate_ports : 1, 324 fwlog : 4, 325 phymode : 3, 326 physpeed : 3, 327 resource_limited : 1, 328 configuring : 1, 329 ds_err_recovering : 1, 330 quiesced : 1, 331 fwlog_file : 1, 332 fw_active_img : 1; /* 1='A', 0='B' */ 333 334 /* 335 * This HBA instance's iportmap and list of iport states. 336 * Note: iports_lock protects iports, iports_attached, and 337 * num_iports on the HBA softstate. 338 */ 339 krwlock_t iports_lock; 340 scsi_hba_iportmap_t *hss_iportmap; 341 list_t iports; 342 int num_iports; 343 344 sas_phymap_t *hss_phymap; 345 int phymap_active; 346 347 /* 348 * Locks 349 */ 350 kmutex_t lock; 351 kmutex_t dma_lock; 352 kmutex_t axil_lock; 353 kcondvar_t drain_cv; 354 355 /* 356 * FMA Capabilities 357 */ 358 int fm_capabilities; 359 360 /* 361 * Register Access Handles 362 */ 363 ddi_device_acc_attr_t dev_acc_attr; 364 ddi_device_acc_attr_t reg_acc_attr; 365 ddi_acc_handle_t pci_acc_handle; 366 ddi_acc_handle_t msg_acc_handle; 367 ddi_acc_handle_t top_acc_handle; 368 ddi_acc_handle_t mpi_acc_handle; 369 ddi_acc_handle_t gsm_acc_handle; 370 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 371 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 372 ddi_acc_handle_t cip_acchdls; 373 ddi_acc_handle_t fwlog_acchdl; 374 ddi_acc_handle_t regdump_acchdl; 375 376 /* 377 * DMA Handles 378 */ 379 ddi_dma_attr_t iqp_dma_attr; 380 ddi_dma_attr_t oqp_dma_attr; 381 ddi_dma_attr_t cip_dma_attr; 382 ddi_dma_attr_t fwlog_dma_attr; 383 ddi_dma_attr_t regdump_dma_attr; 384 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 385 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 386 ddi_dma_handle_t cip_handles; 387 ddi_dma_handle_t fwlog_hndl; 388 ddi_dma_handle_t regdump_hndl; 389 390 /* 391 * Register Pointers 392 */ 393 uint32_t *msg_regs; /* message unit registers */ 394 uint32_t *top_regs; /* top unit registers */ 395 uint32_t *mpi_regs; /* message passing unit registers */ 396 uint32_t *gsm_regs; /* GSM registers */ 397 398 /* 399 * Message Passing and other offsets. 400 * 401 * mpi_offset is the offset within the fourth register set (mpi_regs) 402 * that contains the base of the MPI structures. Since this is actually 403 * set by the card firmware, it can change from startup to startup. 404 * 405 * The other offsets (gst, iqc, oqc) are for similar tables in 406 * MPI space, typically only accessed during setup. 407 */ 408 uint32_t mpi_offset; 409 uint32_t mpi_gst_offset; 410 uint32_t mpi_iqc_offset; 411 uint32_t mpi_oqc_offset; 412 413 /* 414 * Inbound and outbound queue depth 415 */ 416 uint32_t ioq_depth; 417 418 /* 419 * Kernel addresses and offsets for Inbound Queue Producer Indices 420 * 421 * See comments in pmcs_iomb.h about Inbound Queues. Since it 422 * is relatively expensive to go across the PCIe bus to read or 423 * write inside the card, we maintain shadow copies in kernel 424 * memory and update the card as needed. 425 */ 426 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 427 uint32_t iqpi_offset[PMCS_MAX_IQ]; 428 uint32_t last_iqci[PMCS_MAX_IQ]; 429 uint32_t last_htag[PMCS_MAX_IQ]; 430 uint32_t *iqp[PMCS_MAX_IQ]; 431 kmutex_t iqp_lock[PMCS_NIQ]; 432 433 pmcs_iqp_trace_t *iqpt; 434 435 /* 436 * Kernel addresses and offsets for Outbound Queue Consumer Indices 437 */ 438 uint32_t *oqp[PMCS_MAX_OQ]; 439 uint32_t oqci_offset[PMCS_MAX_OQ]; 440 441 /* 442 * Driver's copy of the outbound queue indices 443 */ 444 445 uint32_t oqci[PMCS_NOQ]; 446 uint32_t oqpi[PMCS_NOQ]; 447 448 /* 449 * DMA addresses for both Inbound and Outbound queues. 450 */ 451 uint64_t oqaddr[PMCS_MAX_OQ]; 452 uint64_t iqaddr[PMCS_MAX_IQ]; 453 454 /* 455 * Producer/Queue Host Memory Pointers and scratch areas, 456 * as well as DMA scatter/gather chunk areas. 457 * 458 * See discussion in pmcs_def.h about how this is laid out. 459 */ 460 uint8_t *cip; 461 uint64_t ciaddr; 462 463 /* 464 * Scratch area pointer and DMA addrress for SATA and SMP operations. 465 */ 466 void *scratch; 467 uint64_t scratch_dma; 468 volatile uint8_t scratch_locked; /* Scratch area ownership */ 469 470 /* 471 * Firmware info 472 * 473 * fwlogp: Pointer to block of memory mapped for the event logs 474 * fwlogp_aap1: Pointer to the beginning of the AAP1 event log 475 * fwlogp_iop: Pointer to the beginning of the IOP event log 476 * fwaddr: The physical address of fwlogp 477 * 478 * fwlogfile_aap1/iop: Path to the saved AAP1/IOP event logs 479 * fwlog_max_entries_aap1/iop: Max # of entries in each log 480 * fwlog_oldest_idx_aap1/iop: Index of oldest entry in each log 481 * fwlog_latest_idx_aap1/iop: Index of newest entry in each log 482 * fwlog_threshold_aap1/iop: % full at which we save the event log 483 * fwlog_findex_aap1/iop: Suffix to each event log's next filename 484 * 485 * Firmware event logs are written out to the filenames specified in 486 * fwlogp_aap1/iop when the number of entries in the in-memory copy 487 * reaches or exceeds the threshold value. The filenames are suffixed 488 * with .X where X is an integer ranging from 0 to 4. This allows us 489 * to save up to 5MB of event log data for each log. 490 */ 491 uint32_t *fwlogp; 492 pmcs_fw_event_hdr_t *fwlogp_aap1; 493 pmcs_fw_event_hdr_t *fwlogp_iop; 494 uint64_t fwaddr; 495 char fwlogfile_aap1[MAXPATHLEN + 1]; 496 uint32_t fwlog_max_entries_aap1; 497 uint32_t fwlog_oldest_idx_aap1; 498 uint32_t fwlog_latest_idx_aap1; 499 uint32_t fwlog_threshold_aap1; 500 uint32_t fwlog_findex_aap1; 501 char fwlogfile_iop[MAXPATHLEN + 1]; 502 uint32_t fwlog_max_entries_iop; 503 uint32_t fwlog_oldest_idx_iop; 504 uint32_t fwlog_latest_idx_iop; 505 uint32_t fwlog_threshold_iop; 506 uint32_t fwlog_findex_iop; 507 508 /* 509 * Internal register dump region and flash chunk DMA info 510 */ 511 512 caddr_t regdumpp; 513 uint32_t *flash_chunkp; 514 uint64_t flash_chunk_addr; 515 516 /* 517 * Copies of the last read MSGU and IOP heartbeats. 518 */ 519 uint32_t last_msgu_tick; 520 uint32_t last_iop_tick; 521 522 /* 523 * Card information, some determined during MPI setup 524 */ 525 uint32_t fw; /* firmware version */ 526 uint32_t ila_ver; /* ILA version */ 527 uint8_t max_iq; /* maximum inbound queues this card */ 528 uint8_t max_oq; /* "" outbound "" */ 529 uint8_t nphy; /* number of phys this card */ 530 uint8_t chiprev; /* chip revision */ 531 uint16_t max_cmd; /* max number of commands supported */ 532 uint16_t max_dev; /* max number of devices supported */ 533 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 534 535 /* 536 * Counter for the number of times watchdog fires. We can use this 537 * to throttle events which fire off of the watchdog, such as the 538 * forward progress detection routine. 539 */ 540 uint8_t watchdog_count; 541 542 /* 543 * Interrupt Setup stuff. 544 * 545 * int_type defines the kind of interrupt we're using with this card. 546 * oqvec defines the relationship between an Outbound Queue Number and 547 * a MSI-X vector. 548 */ 549 enum { 550 PMCS_INT_NONE, 551 PMCS_INT_TIMER, 552 PMCS_INT_MSI, 553 PMCS_INT_MSIX, 554 PMCS_INT_FIXED 555 } int_type; 556 uint8_t oqvec[PMCS_NOQ]; 557 558 /* 559 * Interrupt handle table and size 560 */ 561 ddi_intr_handle_t *ih_table; 562 size_t ih_table_size; 563 564 timeout_id_t wdhandle; 565 uint32_t intr_mask; 566 int intr_cnt; 567 int intr_cap; 568 uint32_t odb_auto_clear; 569 570 /* 571 * DMA S/G chunk list 572 */ 573 int nchunks; 574 pmcs_chunk_t *dma_chunklist; 575 576 /* 577 * Front of the DMA S/G chunk freelist 578 */ 579 pmcs_dmachunk_t *dma_freelist; 580 581 /* 582 * PHY and Discovery Related Stuff 583 * 584 * The PMC chip can have up to 16 local phys. We build a level-first 585 * traversal tree of phys starting with the physical phys on the 586 * chip itself (i.e., treating the chip as if it were an expander). 587 * 588 * Our discovery process goes through a level and discovers what 589 * each entity is (and it's phy number within that expander's 590 * address space). It then configures each non-empty item (SAS, 591 * SATA/STP, EXPANDER). For expanders, it then performs 592 * discover on that expander itself via REPORT GENERAL and 593 * DISCOVERY SMP commands, attaching the discovered entities 594 * to the next level. Then we step down a level and continue 595 * (and so on). 596 * 597 * The PMC chip maintains an I_T_NEXUS notion based upon our 598 * registering each new device found (getting back a device handle). 599 * 600 * Like with the number of physical PHYS being a maximum of 16, 601 * there are a maximum number of PORTS also being 16. Some 602 * events apply to PORTS entirely, so we track PORTS as well. 603 */ 604 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 605 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 606 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 607 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 608 609 kmem_cache_t *phy_cache; 610 611 /* 612 * Discovery-related items. 613 * config_lock: Protects config_changed and should never be held 614 * outside of getting or setting the value of config_changed. 615 * config_changed: Boolean indicating whether discovery needs to 616 * be restarted. 617 * configuring: 1 = discovery is running, 0 = discovery not running. 618 * NOTE: configuring is now in the bitfield above. 619 * 620 * config_restart_time is set by the tgtmap_[de]activate callbacks each 621 * time we decide we want SCSA to retry enumeration on some device. 622 * The watchdog timer will not fire discovery unless it has reached 623 * config_restart_time and config_restart is TRUE. This ensures that 624 * we don't ask SCSA to retry enumerating devices while it is still 625 * running. 626 */ 627 kmutex_t config_lock; 628 volatile boolean_t config_changed; 629 boolean_t config_restart; 630 clock_t config_restart_time; 631 632 /* 633 * Work Related Stuff 634 * 635 * Each command given to the PMC chip has an associated work structure. 636 * See the discussion in pmcs_def.h about work structures. 637 */ 638 pmcwork_t *work; /* pool of work structures */ 639 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 640 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 641 uint16_t wserno; /* rolling serial number */ 642 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 643 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 644 645 /* 646 * Solaris/SCSA items. 647 */ 648 scsi_hba_tran_t *tran; 649 smp_hba_tran_t *smp_tran; 650 struct scsi_reset_notify_entry *reset_notify_listf; 651 652 /* 653 * Thread Level stuff. 654 * 655 * A number of tasks are done off worker thread taskq. 656 */ 657 ddi_taskq_t *tq; /* For the worker thread */ 658 volatile ulong_t work_flags; 659 660 /* 661 * Solaris target representation. 662 * targets = array of pointers to xscsi structures 663 * allocated by ssoftstate. 664 */ 665 pmcs_xscsi_t **targets; 666 667 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 668 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 669 kmutex_t cq_lock; 670 kmem_cache_t *iocomp_cb_cache; 671 pmcs_iocomp_cb_t *iocomp_cb_head; 672 pmcs_iocomp_cb_t *iocomp_cb_tail; 673 674 uint16_t debug_mask; 675 uint16_t phyid_block_mask; 676 uint16_t phys_started; 677 uint32_t hipri_queue; 678 uint32_t mpibar; 679 uint32_t intr_pri; 680 681 pmcs_io_intr_coal_t io_intr_coal; 682 pmcs_cq_info_t cq_info; 683 kmutex_t ict_lock; 684 kcondvar_t ict_cv; 685 kthread_t *ict_thread; 686 687 #ifdef DEBUG 688 kmutex_t dbglock; 689 uint32_t ltags[256]; 690 uint32_t ftags[256]; 691 hrtime_t ltime[256]; 692 hrtime_t ftime[256]; 693 uint16_t ftag_lines[256]; 694 uint8_t lti; /* last tag index */ 695 uint8_t fti; /* first tag index */ 696 #endif 697 }; 698 699 extern void *pmcs_softc_state; 700 extern void *pmcs_iport_softstate; 701 702 /* 703 * Some miscellaneous, oft used strings 704 */ 705 extern const char pmcs_nowrk[]; 706 extern const char pmcs_nomsg[]; 707 extern const char pmcs_timeo[]; 708 709 /* 710 * Other externs 711 */ 712 extern int modrootloaded; 713 714 #ifdef __cplusplus 715 } 716 #endif 717 #endif /* _PMCS_H */ 718