1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/sysmacros.h> 53 #include <sys/bitmap.h> 54 #include <sys/queue.h> 55 #include <sys/sdt.h> 56 #include <sys/ddifm.h> 57 #include <sys/fm/protocol.h> 58 #include <sys/fm/util.h> 59 #include <sys/fm/io/ddi.h> 60 #include <sys/scsi/impl/spc3_types.h> 61 62 typedef struct pmcs_hw pmcs_hw_t; 63 typedef struct pmcs_iport pmcs_iport_t; 64 typedef struct pmcs_phy pmcs_phy_t; 65 typedef struct lsas_cmd lsas_cmd_t; 66 typedef struct lsas_result lsas_result_t; 67 typedef struct lsata_cmd lsata_cmd_t; 68 typedef struct lsata_result lsata_result_t; 69 typedef struct pmcwork pmcwork_t; 70 typedef struct pmcs_cmd pmcs_cmd_t; 71 typedef struct pmcs_xscsi pmcs_xscsi_t; 72 typedef struct pmcs_lun pmcs_lun_t; 73 typedef struct pmcs_chunk pmcs_chunk_t; 74 75 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 80 81 #include <sys/scsi/adapters/pmcs/ata.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 86 87 #define PMCS_MAX_UA_SIZE 32 88 89 struct pmcs_xscsi { 90 uint32_t 91 ca : 1, /* SATA specific */ 92 ncq : 1, /* SATA specific */ 93 pio : 1, /* SATA specific */ 94 special_needed : 1, /* SATA specific */ 95 special_running : 1, /* SATA specific */ 96 reset_success : 1, /* last reset ok */ 97 reset_wait : 1, /* wait for reset */ 98 resetting : 1, /* now resetting */ 99 recover_wait : 1, /* wait for recovery */ 100 recovering : 1, /* now recovering */ 101 event_recovery : 1, /* event recovery */ 102 draining : 1, 103 new : 1, 104 assigned : 1, 105 dev_gone : 1, 106 phy_addressable : 1, /* Direct attach SATA */ 107 dev_state : 4; 108 uint16_t maxdepth; 109 uint16_t qdepth; 110 uint16_t actv_cnt; /* Pkts ON CHIP */ 111 uint16_t actv_pkts; /* Pkts in driver */ 112 uint16_t target_num; 113 /* statlock protects both target stats and the special queue (sq) */ 114 kmutex_t statlock; 115 int32_t ref_count; 116 dev_info_t *dip; /* Solaris device dip */ 117 pmcs_phy_t *phy; 118 STAILQ_HEAD(wqh, pmcs_cmd) wq; 119 pmcs_cmd_t *wq_recovery_tail; /* See below */ 120 kmutex_t wqlock; 121 STAILQ_HEAD(aqh, pmcs_cmd) aq; 122 kmutex_t aqlock; 123 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 124 uint32_t tagmap; /* SATA specific */ 125 pmcs_hw_t *pwp; 126 ddi_soft_state_bystr *lun_sstate; 127 uint64_t capacity; /* SATA specific */ 128 char unit_address[PMCS_MAX_UA_SIZE]; 129 kcondvar_t reset_cv; 130 kcondvar_t abort_cv; 131 char *ua; 132 pmcs_dtype_t dtype; 133 struct scsi_device *sd; /* Ptr to scsi_device */ 134 struct smp_device *smpd; /* Ptr to smp_device */ 135 }; 136 137 /* 138 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 139 * the wait queue (wq). That pointer is the last command in the wait queue 140 * that needs to be reissued after device state recovery is complete. Commands 141 * that need to be retried are reinserted into the wq after wq_recovery_tail 142 * to maintain the order in which the commands were originally submitted. 143 */ 144 145 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 146 147 #define PMCS_TGT_WAIT_QUEUE 0x01 148 #define PMCS_TGT_ACTIVE_QUEUE 0x02 149 #define PMCS_TGT_SPECIAL_QUEUE 0x04 150 #define PMCS_TGT_ALL_QUEUES 0xff 151 152 /* 153 * LUN representation. Just a LUN (number) and pointer to the target 154 * structure (pmcs_xscsi). 155 */ 156 157 struct pmcs_lun { 158 pmcs_xscsi_t *target; 159 uint64_t lun_num; /* lun64 */ 160 scsi_lun_t scsi_lun; /* Wire format */ 161 char unit_address[PMCS_MAX_UA_SIZE]; 162 }; 163 164 /* 165 * Interrupt coalescing values 166 */ 167 #define PMCS_MAX_IO_COMPS_PER_INTR 12 168 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 169 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 170 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 171 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 172 #define PMCS_MAX_CQ_THREADS 4 173 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 174 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 175 176 /* 177 * This structure is used to maintain state with regard to I/O interrupt 178 * coalescing. 179 */ 180 181 typedef struct pmcs_io_intr_coal_s { 182 hrtime_t nsecs_between_intrs; 183 hrtime_t last_io_comp; 184 clock_t quantum; 185 uint32_t num_io_completions; 186 uint32_t num_intrs; 187 uint32_t max_io_completions; 188 uint32_t intr_latency; 189 uint32_t intr_threshold; 190 uint16_t intr_coal_timer; 191 boolean_t timer_on; 192 boolean_t stop_thread; 193 boolean_t int_cleared; 194 } pmcs_io_intr_coal_t; 195 196 typedef struct pmcs_cq_thr_info_s { 197 kthread_t *cq_thread; 198 kmutex_t cq_thr_lock; 199 kcondvar_t cq_cv; 200 pmcs_hw_t *cq_pwp; 201 } pmcs_cq_thr_info_t; 202 203 typedef struct pmcs_cq_info_s { 204 uint32_t cq_threads; 205 uint32_t cq_next_disp_thr; 206 boolean_t cq_stop; 207 pmcs_cq_thr_info_t *cq_thr_info; 208 } pmcs_cq_info_t; 209 210 typedef struct pmcs_iocomp_cb_s { 211 pmcwork_t *pwrk; 212 char iomb[PMCS_QENTRY_SIZE << 1]; 213 struct pmcs_iocomp_cb_s *next; 214 } pmcs_iocomp_cb_t; 215 216 typedef struct pmcs_iqp_trace_s { 217 char *head; 218 char *curpos; 219 uint32_t size_left; 220 } pmcs_iqp_trace_t; 221 222 /* 223 * Used by string-based softstate as hint to possible size. 224 */ 225 226 #define PMCS_TGT_SSTATE_SZ 64 227 #define PMCS_LUN_SSTATE_SZ 4 228 229 /* 230 * HBA iport node softstate 231 */ 232 #define PMCS_IPORT_INVALID_PORT_ID 0xf 233 234 struct pmcs_iport { 235 kmutex_t lock; /* iport lock */ 236 list_node_t list_node; /* list node for pwp->iports list_t */ 237 kmutex_t refcnt_lock; /* refcnt lock */ 238 kcondvar_t refcnt_cv; /* refcnt cv */ 239 int refcnt; /* refcnt for this iport */ 240 dev_info_t *dip; /* iport dip */ 241 pmcs_hw_t *pwp; /* back pointer to HBA state */ 242 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 243 enum { /* unit address state in the phymap */ 244 UA_INACTIVE, 245 UA_PEND_ACTIVATE, 246 UA_ACTIVE, 247 UA_PEND_DEACTIVATE 248 } ua_state; 249 char *ua; /* unit address (phy mask) */ 250 int portid; /* portid */ 251 int report_skip; /* skip or report during discovery */ 252 list_t phys; /* list of phys on this port */ 253 int nphy; /* number of phys in this port */ 254 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 255 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 256 /* SMP serialization */ 257 kmutex_t smp_lock; 258 kcondvar_t smp_cv; 259 boolean_t smp_active; 260 kthread_t *smp_active_thread; 261 }; 262 263 struct pmcs_chunk { 264 pmcs_chunk_t *next; 265 ddi_acc_handle_t acc_handle; 266 ddi_dma_handle_t dma_handle; 267 uint8_t *addrp; 268 uint64_t dma_addr; 269 }; 270 271 /* 272 * HBA node (i.e. non-iport) softstate 273 */ 274 struct pmcs_hw { 275 /* 276 * Identity 277 */ 278 dev_info_t *dip; 279 280 /* 281 * 16 possible initiator PHY WWNs 282 */ 283 uint64_t sas_wwns[PMCS_MAX_PORTS]; 284 285 /* 286 * Card State 287 */ 288 enum pwpstate { 289 STATE_NIL, 290 STATE_PROBING, 291 STATE_RUNNING, 292 STATE_UNPROBING, 293 STATE_DEAD 294 } state; 295 296 uint32_t 297 fw_disable_update : 1, 298 fw_force_update : 1, 299 blocked : 1, 300 stuck : 1, 301 locks_initted : 1, 302 mpi_table_setup : 1, 303 hba_attached : 1, 304 iports_attached : 1, 305 suspended : 1, 306 separate_ports : 1, 307 fwlog : 4, 308 phymode : 3, 309 physpeed : 3, 310 resource_limited : 1, 311 configuring : 1, 312 ds_err_recovering : 1; 313 314 /* 315 * This HBA instance's iportmap and list of iport states. 316 * Note: iports_lock protects iports, iports_attached, and 317 * num_iports on the HBA softstate. 318 */ 319 krwlock_t iports_lock; 320 scsi_hba_iportmap_t *hss_iportmap; 321 list_t iports; 322 int num_iports; 323 324 sas_phymap_t *hss_phymap; 325 int phymap_active; 326 327 /* 328 * Locks 329 */ 330 kmutex_t lock; 331 kmutex_t dma_lock; 332 kmutex_t axil_lock; 333 kcondvar_t drain_cv; 334 335 /* 336 * FMA Capabilities 337 */ 338 int fm_capabilities; 339 340 /* 341 * Register Access Handles 342 */ 343 ddi_device_acc_attr_t dev_acc_attr; 344 ddi_device_acc_attr_t reg_acc_attr; 345 ddi_acc_handle_t pci_acc_handle; 346 ddi_acc_handle_t msg_acc_handle; 347 ddi_acc_handle_t top_acc_handle; 348 ddi_acc_handle_t mpi_acc_handle; 349 ddi_acc_handle_t gsm_acc_handle; 350 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 351 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 352 ddi_acc_handle_t cip_acchdls; 353 ddi_acc_handle_t fwlog_acchdl; 354 ddi_acc_handle_t regdump_acchdl; 355 356 /* 357 * DMA Handles 358 */ 359 ddi_dma_attr_t iqp_dma_attr; 360 ddi_dma_attr_t oqp_dma_attr; 361 ddi_dma_attr_t cip_dma_attr; 362 ddi_dma_attr_t fwlog_dma_attr; 363 ddi_dma_attr_t regdump_dma_attr; 364 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 365 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 366 ddi_dma_handle_t cip_handles; 367 ddi_dma_handle_t fwlog_hndl; 368 ddi_dma_handle_t regdump_hndl; 369 370 /* 371 * Register Pointers 372 */ 373 uint32_t *msg_regs; /* message unit registers */ 374 uint32_t *top_regs; /* top unit registers */ 375 uint32_t *mpi_regs; /* message passing unit registers */ 376 uint32_t *gsm_regs; /* GSM registers */ 377 378 /* 379 * Message Passing and other offsets. 380 * 381 * mpi_offset is the offset within the fourth register set (mpi_regs) 382 * that contains the base of the MPI structures. Since this is actually 383 * set by the card firmware, it can change from startup to startup. 384 * 385 * The other offsets (gst, iqc, oqc) are for similar tables in 386 * MPI space, typically only accessed during setup. 387 */ 388 uint32_t mpi_offset; 389 uint32_t mpi_gst_offset; 390 uint32_t mpi_iqc_offset; 391 uint32_t mpi_oqc_offset; 392 393 /* 394 * Inbound and outbound queue depth 395 */ 396 uint32_t ioq_depth; 397 398 /* 399 * Kernel addresses and offsets for Inbound Queue Producer Indices 400 * 401 * See comments in pmcs_iomb.h about Inbound Queues. Since it 402 * is relatively expensive to go across the PCIe bus to read or 403 * write inside the card, we maintain shadow copies in kernel 404 * memory and update the card as needed. 405 */ 406 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 407 uint32_t iqpi_offset[PMCS_MAX_IQ]; 408 uint32_t *iqp[PMCS_MAX_IQ]; 409 kmutex_t iqp_lock[PMCS_NIQ]; 410 411 pmcs_iqp_trace_t *iqpt; 412 413 /* 414 * Kernel addresses and offsets for Outbound Queue Consumer Indices 415 */ 416 uint32_t *oqp[PMCS_MAX_OQ]; 417 uint32_t oqci_offset[PMCS_MAX_OQ]; 418 419 /* 420 * Driver's copy of the outbound queue indices 421 */ 422 423 uint32_t oqci[PMCS_NOQ]; 424 uint32_t oqpi[PMCS_NOQ]; 425 426 /* 427 * DMA addresses for both Inbound and Outbound queues. 428 */ 429 uint64_t oqaddr[PMCS_MAX_OQ]; 430 uint64_t iqaddr[PMCS_MAX_IQ]; 431 432 /* 433 * Producer/Queue Host Memory Pointers and scratch areas, 434 * as well as DMA scatter/gather chunk areas. 435 * 436 * See discussion in pmcs_def.h about how this is laid out. 437 */ 438 uint8_t *cip; 439 uint64_t ciaddr; 440 441 /* 442 * Scratch area pointer and DMA addrress for SATA and SMP operations. 443 */ 444 void *scratch; 445 uint64_t scratch_dma; 446 volatile uint8_t scratch_locked; /* Scratch area ownership */ 447 448 /* 449 * Firmware log pointer 450 */ 451 uint32_t *fwlogp; 452 uint64_t fwaddr; 453 454 /* 455 * Internal register dump region and flash chunk DMA info 456 */ 457 458 caddr_t regdumpp; 459 uint32_t *flash_chunkp; 460 uint64_t flash_chunk_addr; 461 462 /* 463 * Card information, some determined during MPI setup 464 */ 465 uint32_t fw; /* firmware version */ 466 uint8_t max_iq; /* maximum inbound queues this card */ 467 uint8_t max_oq; /* "" outbound "" */ 468 uint8_t nphy; /* number of phys this card */ 469 uint8_t chiprev; /* chip revision */ 470 uint16_t max_cmd; /* max number of commands supported */ 471 uint16_t max_dev; /* max number of devices supported */ 472 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 473 474 475 /* 476 * Interrupt Setup stuff. 477 * 478 * int_type defines the kind of interrupt we're using with this card. 479 * oqvec defines the relationship between an Outbound Queue Number and 480 * a MSI-X vector. 481 */ 482 enum { 483 PMCS_INT_NONE, 484 PMCS_INT_TIMER, 485 PMCS_INT_MSI, 486 PMCS_INT_MSIX, 487 PMCS_INT_FIXED 488 } int_type; 489 uint8_t oqvec[PMCS_NOQ]; 490 491 /* 492 * Interrupt handle table and size 493 */ 494 ddi_intr_handle_t *ih_table; 495 size_t ih_table_size; 496 497 timeout_id_t wdhandle; 498 uint32_t intr_mask; 499 int intr_cnt; 500 int intr_cap; 501 uint32_t odb_auto_clear; 502 503 /* 504 * DMA S/G chunk list 505 */ 506 int nchunks; 507 pmcs_chunk_t *dma_chunklist; 508 509 /* 510 * Front of the DMA S/G chunk freelist 511 */ 512 pmcs_dmachunk_t *dma_freelist; 513 514 /* 515 * PHY and Discovery Related Stuff 516 * 517 * The PMC chip can have up to 16 local phys. We build a level-first 518 * traversal tree of phys starting with the physical phys on the 519 * chip itself (i.e., treating the chip as if it were an expander). 520 * 521 * Our discovery process goes through a level and discovers what 522 * each entity is (and it's phy number within that expander's 523 * address space). It then configures each non-empty item (SAS, 524 * SATA/STP, EXPANDER). For expanders, it then performs 525 * discover on that expander itself via REPORT GENERAL and 526 * DISCOVERY SMP commands, attaching the discovered entities 527 * to the next level. Then we step down a level and continue 528 * (and so on). 529 * 530 * The PMC chip maintains an I_T_NEXUS notion based upon our 531 * registering each new device found (getting back a device handle). 532 * 533 * Like with the number of physical PHYS being a maximum of 16, 534 * there are a maximum number of PORTS also being 16. Some 535 * events apply to PORTS entirely, so we track PORTS as well. 536 */ 537 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 538 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 539 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 540 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 541 542 kmem_cache_t *phy_cache; 543 544 /* 545 * Discovery-related items. 546 * config_lock: Protects config_changed and should never be held 547 * outside of getting or setting the value of config_changed. 548 * config_changed: Boolean indicating whether discovery needs to 549 * be restarted. 550 * configuring: 1 = discovery is running, 0 = discovery not running. 551 * NOTE: configuring is now in the bitfield above. 552 */ 553 kmutex_t config_lock; 554 volatile boolean_t config_changed; 555 556 /* 557 * Work Related Stuff 558 * 559 * Each command given to the PMC chip has an associated work structure. 560 * See the discussion in pmcs_def.h about work structures. 561 */ 562 pmcwork_t *work; /* pool of work structures */ 563 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 564 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 565 uint16_t wserno; /* rolling serial number */ 566 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 567 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 568 569 /* 570 * Solaris/SCSA items. 571 */ 572 scsi_hba_tran_t *tran; 573 smp_hba_tran_t *smp_tran; 574 struct scsi_reset_notify_entry *reset_notify_listf; 575 576 /* 577 * Thread Level stuff. 578 * 579 * A number of tasks are done off worker thread taskq. 580 */ 581 ddi_taskq_t *tq; /* For the worker thread */ 582 volatile ulong_t work_flags; 583 584 /* 585 * Solaris target representation. 586 * targets = array of pointers to xscsi structures 587 * allocated by ssoftstate. 588 */ 589 pmcs_xscsi_t **targets; 590 591 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 592 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 593 kmutex_t cq_lock; 594 kmem_cache_t *iocomp_cb_cache; 595 pmcs_iocomp_cb_t *iocomp_cb_head; 596 pmcs_iocomp_cb_t *iocomp_cb_tail; 597 598 uint16_t debug_mask; 599 uint16_t phyid_block_mask; 600 uint16_t phys_started; 601 uint32_t hipri_queue; 602 uint32_t mpibar; 603 uint32_t intr_pri; 604 605 pmcs_io_intr_coal_t io_intr_coal; 606 pmcs_cq_info_t cq_info; 607 kmutex_t ict_lock; 608 kcondvar_t ict_cv; 609 kthread_t *ict_thread; 610 611 #ifdef DEBUG 612 kmutex_t dbglock; 613 uint32_t ltags[256]; 614 uint32_t ftags[256]; 615 hrtime_t ltime[256]; 616 hrtime_t ftime[256]; 617 uint16_t ftag_lines[256]; 618 uint8_t lti; /* last tag index */ 619 uint8_t fti; /* first tag index */ 620 #endif 621 }; 622 623 extern void *pmcs_softc_state; 624 extern void *pmcs_iport_softstate; 625 626 /* 627 * Some miscellaneous, oft used strings 628 */ 629 extern const char pmcs_nowrk[]; 630 extern const char pmcs_nomsg[]; 631 extern const char pmcs_timeo[]; 632 633 #ifdef __cplusplus 634 } 635 #endif 636 #endif /* _PMCS_H */ 637