1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/sysmacros.h> 53 #include <sys/bitmap.h> 54 #include <sys/queue.h> 55 #include <sys/sdt.h> 56 #include <sys/ddifm.h> 57 #include <sys/fm/protocol.h> 58 #include <sys/fm/util.h> 59 #include <sys/fm/io/ddi.h> 60 #include <sys/scsi/impl/spc3_types.h> 61 62 typedef struct pmcs_hw pmcs_hw_t; 63 typedef struct pmcs_iport pmcs_iport_t; 64 typedef struct pmcs_phy pmcs_phy_t; 65 typedef struct lsas_cmd lsas_cmd_t; 66 typedef struct lsas_result lsas_result_t; 67 typedef struct lsata_cmd lsata_cmd_t; 68 typedef struct lsata_result lsata_result_t; 69 typedef struct pmcwork pmcwork_t; 70 typedef struct pmcs_cmd pmcs_cmd_t; 71 typedef struct pmcs_xscsi pmcs_xscsi_t; 72 typedef struct pmcs_lun pmcs_lun_t; 73 typedef struct pmcs_chunk pmcs_chunk_t; 74 75 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 80 81 #include <sys/scsi/adapters/pmcs/ata.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 86 87 #define PMCS_MAX_UA_SIZE 32 88 89 struct pmcs_xscsi { 90 uint32_t 91 ca : 1, /* SATA specific */ 92 ncq : 1, /* SATA specific */ 93 pio : 1, /* SATA specific */ 94 special_needed : 1, /* SATA specific */ 95 special_running : 1, /* SATA specific */ 96 reset_success : 1, /* last reset ok */ 97 reset_wait : 1, /* wait for reset */ 98 resetting : 1, /* now resetting */ 99 recover_wait : 1, /* wait for recovery */ 100 recovering : 1, /* now recovering */ 101 event_recovery : 1, /* event recovery */ 102 draining : 1, 103 new : 1, 104 assigned : 1, 105 dev_gone : 1, 106 phy_addressable : 1, /* Direct attach SATA */ 107 dev_state : 4; 108 uint16_t maxdepth; 109 uint16_t qdepth; 110 uint16_t actv_cnt; 111 uint16_t target_num; 112 /* statlock protects both target stats and the special queue (sq) */ 113 kmutex_t statlock; 114 int32_t ref_count; 115 dev_info_t *dip; /* Solaris device dip */ 116 pmcs_phy_t *phy; 117 STAILQ_HEAD(wqh, pmcs_cmd) wq; 118 pmcs_cmd_t *wq_recovery_tail; /* See below */ 119 kmutex_t wqlock; 120 STAILQ_HEAD(aqh, pmcs_cmd) aq; 121 kmutex_t aqlock; 122 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 123 uint32_t tagmap; /* SATA specific */ 124 pmcs_hw_t *pwp; 125 ddi_soft_state_bystr *lun_sstate; 126 uint64_t capacity; /* SATA specific */ 127 char unit_address[PMCS_MAX_UA_SIZE]; 128 kcondvar_t reset_cv; 129 kcondvar_t abort_cv; 130 char *ua; 131 pmcs_dtype_t dtype; 132 struct scsi_device *sd; /* Ptr to scsi_device */ 133 struct smp_device *smpd; /* Ptr to smp_device */ 134 }; 135 136 /* 137 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 138 * the wait queue (wq). That pointer is the last command in the wait queue 139 * that needs to be reissued after device state recovery is complete. Commands 140 * that need to be retried are reinserted into the wq after wq_recovery_tail 141 * to maintain the order in which the commands were originally submitted. 142 */ 143 144 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 145 146 #define PMCS_TGT_WAIT_QUEUE 0x01 147 #define PMCS_TGT_ACTIVE_QUEUE 0x02 148 #define PMCS_TGT_SPECIAL_QUEUE 0x04 149 #define PMCS_TGT_ALL_QUEUES 0xff 150 151 /* 152 * LUN representation. Just a LUN (number) and pointer to the target 153 * structure (pmcs_xscsi). 154 */ 155 156 struct pmcs_lun { 157 pmcs_xscsi_t *target; 158 uint64_t lun_num; /* lun64 */ 159 scsi_lun_t scsi_lun; /* Wire format */ 160 char unit_address[PMCS_MAX_UA_SIZE]; 161 }; 162 163 /* 164 * Interrupt coalescing values 165 */ 166 #define PMCS_MAX_IO_COMPS_PER_INTR 12 167 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 168 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 169 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 170 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 171 #define PMCS_MAX_CQ_THREADS 4 172 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 173 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 174 175 /* 176 * This structure is used to maintain state with regard to I/O interrupt 177 * coalescing. 178 */ 179 180 typedef struct pmcs_io_intr_coal_s { 181 hrtime_t nsecs_between_intrs; 182 hrtime_t last_io_comp; 183 clock_t quantum; 184 uint32_t num_io_completions; 185 uint32_t num_intrs; 186 uint32_t max_io_completions; 187 uint32_t intr_latency; 188 uint32_t intr_threshold; 189 uint16_t intr_coal_timer; 190 boolean_t timer_on; 191 boolean_t stop_thread; 192 boolean_t int_cleared; 193 } pmcs_io_intr_coal_t; 194 195 typedef struct pmcs_cq_thr_info_s { 196 kthread_t *cq_thread; 197 kmutex_t cq_thr_lock; 198 kcondvar_t cq_cv; 199 pmcs_hw_t *cq_pwp; 200 } pmcs_cq_thr_info_t; 201 202 typedef struct pmcs_cq_info_s { 203 uint32_t cq_threads; 204 uint32_t cq_next_disp_thr; 205 boolean_t cq_stop; 206 pmcs_cq_thr_info_t *cq_thr_info; 207 } pmcs_cq_info_t; 208 209 typedef struct pmcs_iocomp_cb_s { 210 pmcwork_t *pwrk; 211 char iomb[PMCS_QENTRY_SIZE << 1]; 212 struct pmcs_iocomp_cb_s *next; 213 } pmcs_iocomp_cb_t; 214 215 typedef struct pmcs_iqp_trace_s { 216 char *head; 217 char *curpos; 218 uint32_t size_left; 219 } pmcs_iqp_trace_t; 220 221 /* 222 * Used by string-based softstate as hint to possible size. 223 */ 224 225 #define PMCS_TGT_SSTATE_SZ 64 226 #define PMCS_LUN_SSTATE_SZ 4 227 228 /* 229 * HBA iport node softstate 230 */ 231 #define PMCS_IPORT_INVALID_PORT_ID 0xffff 232 233 struct pmcs_iport { 234 kmutex_t lock; /* iport lock */ 235 list_node_t list_node; /* list node for pwp->iports list_t */ 236 kmutex_t refcnt_lock; /* refcnt lock */ 237 kcondvar_t refcnt_cv; /* refcnt cv */ 238 int refcnt; /* refcnt for this iport */ 239 dev_info_t *dip; /* iport dip */ 240 pmcs_hw_t *pwp; /* back pointer to HBA state */ 241 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 242 enum { /* unit address state in the phymap */ 243 UA_INACTIVE, 244 UA_PEND_ACTIVATE, 245 UA_ACTIVE, 246 UA_PEND_DEACTIVATE 247 } ua_state; 248 char *ua; /* unit address (phy mask) */ 249 int portid; /* portid */ 250 int report_skip; /* skip or report during discovery */ 251 list_t phys; /* list of phys on this port */ 252 int nphy; /* number of phys in this port */ 253 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 254 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 255 /* SMP serialization */ 256 kmutex_t smp_lock; 257 kcondvar_t smp_cv; 258 boolean_t smp_active; 259 kthread_t *smp_active_thread; 260 }; 261 262 struct pmcs_chunk { 263 pmcs_chunk_t *next; 264 ddi_acc_handle_t acc_handle; 265 ddi_dma_handle_t dma_handle; 266 uint8_t *addrp; 267 uint64_t dma_addr; 268 }; 269 270 /* 271 * HBA node (i.e. non-iport) softstate 272 */ 273 struct pmcs_hw { 274 /* 275 * Identity 276 */ 277 dev_info_t *dip; 278 279 /* 280 * 16 possible initiator PHY WWNs 281 */ 282 uint64_t sas_wwns[PMCS_MAX_PORTS]; 283 284 /* 285 * Card State 286 */ 287 enum pwpstate { 288 STATE_NIL, 289 STATE_PROBING, 290 STATE_RUNNING, 291 STATE_UNPROBING, 292 STATE_DEAD 293 } state; 294 295 uint32_t 296 fw_disable_update : 1, 297 fw_force_update : 1, 298 blocked : 1, 299 stuck : 1, 300 locks_initted : 1, 301 mpi_table_setup : 1, 302 hba_attached : 1, 303 iports_attached : 1, 304 suspended : 1, 305 separate_ports : 1, 306 fwlog : 4, 307 phymode : 3, 308 physpeed : 3, 309 resource_limited : 1, 310 configuring : 1, 311 ds_err_recovering : 1; 312 313 /* 314 * This HBA instance's iportmap and list of iport states. 315 * Note: iports_lock protects iports, iports_attached, and 316 * num_iports on the HBA softstate. 317 */ 318 krwlock_t iports_lock; 319 scsi_hba_iportmap_t *hss_iportmap; 320 list_t iports; 321 int num_iports; 322 323 sas_phymap_t *hss_phymap; 324 int phymap_active; 325 326 /* 327 * Locks 328 */ 329 kmutex_t lock; 330 kmutex_t dma_lock; 331 kmutex_t axil_lock; 332 kcondvar_t drain_cv; 333 334 /* 335 * FMA Capabilities 336 */ 337 int fm_capabilities; 338 339 /* 340 * Register Access Handles 341 */ 342 ddi_device_acc_attr_t dev_acc_attr; 343 ddi_device_acc_attr_t reg_acc_attr; 344 ddi_acc_handle_t pci_acc_handle; 345 ddi_acc_handle_t msg_acc_handle; 346 ddi_acc_handle_t top_acc_handle; 347 ddi_acc_handle_t mpi_acc_handle; 348 ddi_acc_handle_t gsm_acc_handle; 349 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 350 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 351 ddi_acc_handle_t cip_acchdls; 352 ddi_acc_handle_t fwlog_acchdl; 353 ddi_acc_handle_t regdump_acchdl; 354 355 /* 356 * DMA Handles 357 */ 358 ddi_dma_attr_t iqp_dma_attr; 359 ddi_dma_attr_t oqp_dma_attr; 360 ddi_dma_attr_t cip_dma_attr; 361 ddi_dma_attr_t fwlog_dma_attr; 362 ddi_dma_attr_t regdump_dma_attr; 363 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 364 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 365 ddi_dma_handle_t cip_handles; 366 ddi_dma_handle_t fwlog_hndl; 367 ddi_dma_handle_t regdump_hndl; 368 369 /* 370 * Register Pointers 371 */ 372 uint32_t *msg_regs; /* message unit registers */ 373 uint32_t *top_regs; /* top unit registers */ 374 uint32_t *mpi_regs; /* message passing unit registers */ 375 uint32_t *gsm_regs; /* GSM registers */ 376 377 /* 378 * Message Passing and other offsets. 379 * 380 * mpi_offset is the offset within the fourth register set (mpi_regs) 381 * that contains the base of the MPI structures. Since this is actually 382 * set by the card firmware, it can change from startup to startup. 383 * 384 * The other offsets (gst, iqc, oqc) are for similar tables in 385 * MPI space, typically only accessed during setup. 386 */ 387 uint32_t mpi_offset; 388 uint32_t mpi_gst_offset; 389 uint32_t mpi_iqc_offset; 390 uint32_t mpi_oqc_offset; 391 392 /* 393 * Inbound and outbound queue depth 394 */ 395 uint32_t ioq_depth; 396 397 /* 398 * Kernel addresses and offsets for Inbound Queue Producer Indices 399 * 400 * See comments in pmcs_iomb.h about Inbound Queues. Since it 401 * is relatively expensive to go across the PCIe bus to read or 402 * write inside the card, we maintain shadow copies in kernel 403 * memory and update the card as needed. 404 */ 405 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 406 uint32_t iqpi_offset[PMCS_MAX_IQ]; 407 uint32_t *iqp[PMCS_MAX_IQ]; 408 kmutex_t iqp_lock[PMCS_NIQ]; 409 410 pmcs_iqp_trace_t *iqpt; 411 412 /* 413 * Kernel addresses and offsets for Outbound Queue Consumer Indices 414 */ 415 uint32_t *oqp[PMCS_MAX_OQ]; 416 uint32_t oqci_offset[PMCS_MAX_OQ]; 417 418 /* 419 * Driver's copy of the outbound queue indices 420 */ 421 422 uint32_t oqci[PMCS_NOQ]; 423 uint32_t oqpi[PMCS_NOQ]; 424 425 /* 426 * DMA addresses for both Inbound and Outbound queues. 427 */ 428 uint64_t oqaddr[PMCS_MAX_OQ]; 429 uint64_t iqaddr[PMCS_MAX_IQ]; 430 431 /* 432 * Producer/Queue Host Memory Pointers and scratch areas, 433 * as well as DMA scatter/gather chunk areas. 434 * 435 * See discussion in pmcs_def.h about how this is laid out. 436 */ 437 uint8_t *cip; 438 uint64_t ciaddr; 439 440 /* 441 * Scratch area pointer and DMA addrress for SATA and SMP operations. 442 */ 443 void *scratch; 444 uint64_t scratch_dma; 445 volatile uint8_t scratch_locked; /* Scratch area ownership */ 446 447 /* 448 * Firmware log pointer 449 */ 450 uint32_t *fwlogp; 451 uint64_t fwaddr; 452 453 /* 454 * Internal register dump region and flash chunk DMA info 455 */ 456 457 caddr_t regdumpp; 458 uint32_t *flash_chunkp; 459 uint64_t flash_chunk_addr; 460 461 /* 462 * Card information, some determined during MPI setup 463 */ 464 uint32_t fw; /* firmware version */ 465 uint8_t max_iq; /* maximum inbound queues this card */ 466 uint8_t max_oq; /* "" outbound "" */ 467 uint8_t nphy; /* number of phys this card */ 468 uint8_t chiprev; /* chip revision */ 469 uint16_t max_cmd; /* max number of commands supported */ 470 uint16_t max_dev; /* max number of devices supported */ 471 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 472 473 474 /* 475 * Interrupt Setup stuff. 476 * 477 * int_type defines the kind of interrupt we're using with this card. 478 * oqvec defines the relationship between an Outbound Queue Number and 479 * a MSI-X vector. 480 */ 481 enum { 482 PMCS_INT_NONE, 483 PMCS_INT_TIMER, 484 PMCS_INT_MSI, 485 PMCS_INT_MSIX, 486 PMCS_INT_FIXED 487 } int_type; 488 uint8_t oqvec[PMCS_NOQ]; 489 490 /* 491 * Interrupt handle table and size 492 */ 493 ddi_intr_handle_t *ih_table; 494 size_t ih_table_size; 495 496 timeout_id_t wdhandle; 497 uint32_t intr_mask; 498 int intr_cnt; 499 int intr_cap; 500 uint32_t odb_auto_clear; 501 502 /* 503 * DMA S/G chunk list 504 */ 505 int nchunks; 506 pmcs_chunk_t *dma_chunklist; 507 508 /* 509 * Front of the DMA S/G chunk freelist 510 */ 511 pmcs_dmachunk_t *dma_freelist; 512 513 /* 514 * PHY and Discovery Related Stuff 515 * 516 * The PMC chip can have up to 16 local phys. We build a level-first 517 * traversal tree of phys starting with the physical phys on the 518 * chip itself (i.e., treating the chip as if it were an expander). 519 * 520 * Our discovery process goes through a level and discovers what 521 * each entity is (and it's phy number within that expander's 522 * address space). It then configures each non-empty item (SAS, 523 * SATA/STP, EXPANDER). For expanders, it then performs 524 * discover on that expander itself via REPORT GENERAL and 525 * DISCOVERY SMP commands, attaching the discovered entities 526 * to the next level. Then we step down a level and continue 527 * (and so on). 528 * 529 * The PMC chip maintains an I_T_NEXUS notion based upon our 530 * registering each new device found (getting back a device handle). 531 * 532 * Like with the number of physical PHYS being a maximum of 16, 533 * there are a maximum number of PORTS also being 16. Some 534 * events apply to PORTS entirely, so we track PORTS as well. 535 */ 536 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 537 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 538 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 539 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 540 541 kmem_cache_t *phy_cache; 542 543 /* 544 * Discovery-related items. 545 * config_lock: Protects config_changed and should never be held 546 * outside of getting or setting the value of config_changed. 547 * config_changed: Boolean indicating whether discovery needs to 548 * be restarted. 549 * configuring: 1 = discovery is running, 0 = discovery not running. 550 * NOTE: configuring is now in the bitfield above. 551 */ 552 kmutex_t config_lock; 553 volatile boolean_t config_changed; 554 555 /* 556 * Work Related Stuff 557 * 558 * Each command given to the PMC chip has an associated work structure. 559 * See the discussion in pmcs_def.h about work structures. 560 */ 561 pmcwork_t *work; /* pool of work structures */ 562 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 563 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 564 uint16_t wserno; /* rolling serial number */ 565 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 566 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 567 568 /* 569 * Solaris/SCSA items. 570 */ 571 scsi_hba_tran_t *tran; 572 smp_hba_tran_t *smp_tran; 573 struct scsi_reset_notify_entry *reset_notify_listf; 574 575 /* 576 * Thread Level stuff. 577 * 578 * A number of tasks are done off worker thread taskq. 579 */ 580 ddi_taskq_t *tq; /* For the worker thread */ 581 volatile ulong_t work_flags; 582 583 /* 584 * Solaris target representation. 585 * targets = array of pointers to xscsi structures 586 * allocated by ssoftstate. 587 */ 588 pmcs_xscsi_t **targets; 589 590 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 591 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 592 kmutex_t cq_lock; 593 kmem_cache_t *iocomp_cb_cache; 594 pmcs_iocomp_cb_t *iocomp_cb_head; 595 pmcs_iocomp_cb_t *iocomp_cb_tail; 596 597 uint16_t debug_mask; 598 uint16_t phyid_block_mask; 599 uint16_t phys_started; 600 uint32_t hipri_queue; 601 uint32_t mpibar; 602 uint32_t intr_pri; 603 604 pmcs_io_intr_coal_t io_intr_coal; 605 pmcs_cq_info_t cq_info; 606 kmutex_t ict_lock; 607 kcondvar_t ict_cv; 608 kthread_t *ict_thread; 609 610 #ifdef DEBUG 611 kmutex_t dbglock; 612 uint32_t ltags[256]; 613 uint32_t ftags[256]; 614 hrtime_t ltime[256]; 615 hrtime_t ftime[256]; 616 uint16_t ftag_lines[256]; 617 uint8_t lti; /* last tag index */ 618 uint8_t fti; /* first tag index */ 619 #endif 620 }; 621 622 extern void *pmcs_softc_state; 623 extern void *pmcs_iport_softstate; 624 625 /* 626 * Some miscellaneous, oft used strings 627 */ 628 extern const char pmcs_nowrk[]; 629 extern const char pmcs_nomsg[]; 630 extern const char pmcs_timeo[]; 631 632 #ifdef __cplusplus 633 } 634 #endif 635 #endif /* _PMCS_H */ 636