1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/sysmacros.h> 53 #include <sys/bitmap.h> 54 #include <sys/queue.h> 55 #include <sys/sdt.h> 56 #include <sys/ddifm.h> 57 #include <sys/fm/protocol.h> 58 #include <sys/fm/util.h> 59 #include <sys/fm/io/ddi.h> 60 #include <sys/scsi/impl/spc3_types.h> 61 62 typedef struct pmcs_hw pmcs_hw_t; 63 typedef struct pmcs_iport pmcs_iport_t; 64 typedef struct pmcs_phy pmcs_phy_t; 65 typedef struct lsas_cmd lsas_cmd_t; 66 typedef struct lsas_result lsas_result_t; 67 typedef struct lsata_cmd lsata_cmd_t; 68 typedef struct lsata_result lsata_result_t; 69 typedef struct pmcwork pmcwork_t; 70 typedef struct pmcs_cmd pmcs_cmd_t; 71 typedef struct pmcs_xscsi pmcs_xscsi_t; 72 typedef struct pmcs_lun pmcs_lun_t; 73 typedef struct pmcs_chunk pmcs_chunk_t; 74 75 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 80 81 #include <sys/scsi/adapters/pmcs/ata.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 86 87 #define PMCS_MAX_UA_SIZE 32 88 89 struct pmcs_xscsi { 90 uint32_t 91 ca : 1, /* SATA specific */ 92 ncq : 1, /* SATA specific */ 93 pio : 1, /* SATA specific */ 94 special_needed : 1, /* SATA specific */ 95 special_running : 1, /* SATA specific */ 96 reset_success : 1, /* last reset ok */ 97 reset_wait : 1, /* wait for reset */ 98 resetting : 1, /* now resetting */ 99 recover_wait : 1, /* wait for recovery */ 100 recovering : 1, /* now recovering */ 101 event_recovery : 1, /* event recovery */ 102 draining : 1, 103 new : 1, 104 assigned : 1, 105 dev_gone : 1, 106 phy_addressable : 1, /* Direct attach SATA */ 107 dev_state : 4; 108 uint16_t maxdepth; 109 uint16_t qdepth; 110 uint16_t actv_cnt; /* Pkts ON CHIP */ 111 uint16_t actv_pkts; /* Pkts in driver */ 112 uint16_t target_num; 113 /* statlock protects both target stats and the special queue (sq) */ 114 kmutex_t statlock; 115 int32_t ref_count; 116 dev_info_t *dip; /* Solaris device dip */ 117 pmcs_phy_t *phy; 118 STAILQ_HEAD(wqh, pmcs_cmd) wq; 119 pmcs_cmd_t *wq_recovery_tail; /* See below */ 120 kmutex_t wqlock; 121 STAILQ_HEAD(aqh, pmcs_cmd) aq; 122 kmutex_t aqlock; 123 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 124 uint32_t tagmap; /* SATA specific */ 125 pmcs_hw_t *pwp; 126 ddi_soft_state_bystr *lun_sstate; 127 uint64_t capacity; /* SATA specific */ 128 char unit_address[PMCS_MAX_UA_SIZE]; 129 kcondvar_t reset_cv; 130 kcondvar_t abort_cv; 131 char *ua; 132 pmcs_dtype_t dtype; 133 list_t lun_list; /* list of LUNs */ 134 struct smp_device *smpd; /* Ptr to smp_device */ 135 }; 136 137 /* 138 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 139 * the wait queue (wq). That pointer is the last command in the wait queue 140 * that needs to be reissued after device state recovery is complete. Commands 141 * that need to be retried are reinserted into the wq after wq_recovery_tail 142 * to maintain the order in which the commands were originally submitted. 143 */ 144 145 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 146 147 #define PMCS_TGT_WAIT_QUEUE 0x01 148 #define PMCS_TGT_ACTIVE_QUEUE 0x02 149 #define PMCS_TGT_SPECIAL_QUEUE 0x04 150 #define PMCS_TGT_ALL_QUEUES 0xff 151 152 /* 153 * LUN representation. Just a LUN (number) and pointer to the target 154 * structure (pmcs_xscsi). 155 */ 156 157 struct pmcs_lun { 158 list_node_t lun_list_next; 159 pmcs_xscsi_t *target; 160 struct scsi_device *sd; 161 uint64_t lun_num; /* lun64 */ 162 scsi_lun_t scsi_lun; /* Wire format */ 163 char unit_address[PMCS_MAX_UA_SIZE]; 164 }; 165 166 /* 167 * Interrupt coalescing values 168 */ 169 #define PMCS_MAX_IO_COMPS_PER_INTR 12 170 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 171 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 172 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 173 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 174 #define PMCS_MAX_CQ_THREADS 4 175 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 176 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 177 178 /* 179 * This structure is used to maintain state with regard to I/O interrupt 180 * coalescing. 181 */ 182 183 typedef struct pmcs_io_intr_coal_s { 184 hrtime_t nsecs_between_intrs; 185 hrtime_t last_io_comp; 186 clock_t quantum; 187 uint32_t num_io_completions; 188 uint32_t num_intrs; 189 uint32_t max_io_completions; 190 uint32_t intr_latency; 191 uint32_t intr_threshold; 192 uint16_t intr_coal_timer; 193 boolean_t timer_on; 194 boolean_t stop_thread; 195 boolean_t int_cleared; 196 } pmcs_io_intr_coal_t; 197 198 typedef struct pmcs_cq_thr_info_s { 199 kthread_t *cq_thread; 200 kmutex_t cq_thr_lock; 201 kcondvar_t cq_cv; 202 pmcs_hw_t *cq_pwp; 203 } pmcs_cq_thr_info_t; 204 205 typedef struct pmcs_cq_info_s { 206 uint32_t cq_threads; 207 uint32_t cq_next_disp_thr; 208 boolean_t cq_stop; 209 pmcs_cq_thr_info_t *cq_thr_info; 210 } pmcs_cq_info_t; 211 212 typedef struct pmcs_iocomp_cb_s { 213 pmcwork_t *pwrk; 214 char iomb[PMCS_QENTRY_SIZE << 1]; 215 struct pmcs_iocomp_cb_s *next; 216 } pmcs_iocomp_cb_t; 217 218 typedef struct pmcs_iqp_trace_s { 219 char *head; 220 char *curpos; 221 uint32_t size_left; 222 } pmcs_iqp_trace_t; 223 224 /* 225 * Used by string-based softstate as hint to possible size. 226 */ 227 228 #define PMCS_TGT_SSTATE_SZ 64 229 #define PMCS_LUN_SSTATE_SZ 4 230 231 /* 232 * HBA iport node softstate 233 */ 234 #define PMCS_IPORT_INVALID_PORT_ID 0xf 235 236 struct pmcs_iport { 237 kmutex_t lock; /* iport lock */ 238 list_node_t list_node; /* list node for pwp->iports list_t */ 239 kmutex_t refcnt_lock; /* refcnt lock */ 240 kcondvar_t refcnt_cv; /* refcnt cv */ 241 int refcnt; /* refcnt for this iport */ 242 dev_info_t *dip; /* iport dip */ 243 pmcs_hw_t *pwp; /* back pointer to HBA state */ 244 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 245 enum { /* unit address state in the phymap */ 246 UA_INACTIVE, 247 UA_PEND_ACTIVATE, 248 UA_ACTIVE, 249 UA_PEND_DEACTIVATE 250 } ua_state; 251 char *ua; /* unit address (phy mask) */ 252 int portid; /* portid */ 253 int report_skip; /* skip or report during discovery */ 254 list_t phys; /* list of phys on this port */ 255 int nphy; /* number of phys in this port */ 256 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 257 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 258 /* SMP serialization */ 259 kmutex_t smp_lock; 260 kcondvar_t smp_cv; 261 boolean_t smp_active; 262 kthread_t *smp_active_thread; 263 }; 264 265 struct pmcs_chunk { 266 pmcs_chunk_t *next; 267 ddi_acc_handle_t acc_handle; 268 ddi_dma_handle_t dma_handle; 269 uint8_t *addrp; 270 uint64_t dma_addr; 271 }; 272 273 /* 274 * HBA node (i.e. non-iport) softstate 275 */ 276 struct pmcs_hw { 277 /* 278 * Identity 279 */ 280 dev_info_t *dip; 281 282 /* 283 * 16 possible initiator PHY WWNs 284 */ 285 uint64_t sas_wwns[PMCS_MAX_PORTS]; 286 287 /* 288 * Card State 289 */ 290 enum pwpstate { 291 STATE_NIL, 292 STATE_PROBING, 293 STATE_RUNNING, 294 STATE_UNPROBING, 295 STATE_DEAD 296 } state; 297 298 uint32_t 299 fw_disable_update : 1, 300 fw_force_update : 1, 301 blocked : 1, 302 stuck : 1, 303 locks_initted : 1, 304 mpi_table_setup : 1, 305 hba_attached : 1, 306 iports_attached : 1, 307 suspended : 1, 308 separate_ports : 1, 309 fwlog : 4, 310 phymode : 3, 311 physpeed : 3, 312 resource_limited : 1, 313 configuring : 1, 314 ds_err_recovering : 1; 315 316 /* 317 * This HBA instance's iportmap and list of iport states. 318 * Note: iports_lock protects iports, iports_attached, and 319 * num_iports on the HBA softstate. 320 */ 321 krwlock_t iports_lock; 322 scsi_hba_iportmap_t *hss_iportmap; 323 list_t iports; 324 int num_iports; 325 326 sas_phymap_t *hss_phymap; 327 int phymap_active; 328 329 /* 330 * Locks 331 */ 332 kmutex_t lock; 333 kmutex_t dma_lock; 334 kmutex_t axil_lock; 335 kcondvar_t drain_cv; 336 337 /* 338 * FMA Capabilities 339 */ 340 int fm_capabilities; 341 342 /* 343 * Register Access Handles 344 */ 345 ddi_device_acc_attr_t dev_acc_attr; 346 ddi_device_acc_attr_t reg_acc_attr; 347 ddi_acc_handle_t pci_acc_handle; 348 ddi_acc_handle_t msg_acc_handle; 349 ddi_acc_handle_t top_acc_handle; 350 ddi_acc_handle_t mpi_acc_handle; 351 ddi_acc_handle_t gsm_acc_handle; 352 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 353 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 354 ddi_acc_handle_t cip_acchdls; 355 ddi_acc_handle_t fwlog_acchdl; 356 ddi_acc_handle_t regdump_acchdl; 357 358 /* 359 * DMA Handles 360 */ 361 ddi_dma_attr_t iqp_dma_attr; 362 ddi_dma_attr_t oqp_dma_attr; 363 ddi_dma_attr_t cip_dma_attr; 364 ddi_dma_attr_t fwlog_dma_attr; 365 ddi_dma_attr_t regdump_dma_attr; 366 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 367 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 368 ddi_dma_handle_t cip_handles; 369 ddi_dma_handle_t fwlog_hndl; 370 ddi_dma_handle_t regdump_hndl; 371 372 /* 373 * Register Pointers 374 */ 375 uint32_t *msg_regs; /* message unit registers */ 376 uint32_t *top_regs; /* top unit registers */ 377 uint32_t *mpi_regs; /* message passing unit registers */ 378 uint32_t *gsm_regs; /* GSM registers */ 379 380 /* 381 * Message Passing and other offsets. 382 * 383 * mpi_offset is the offset within the fourth register set (mpi_regs) 384 * that contains the base of the MPI structures. Since this is actually 385 * set by the card firmware, it can change from startup to startup. 386 * 387 * The other offsets (gst, iqc, oqc) are for similar tables in 388 * MPI space, typically only accessed during setup. 389 */ 390 uint32_t mpi_offset; 391 uint32_t mpi_gst_offset; 392 uint32_t mpi_iqc_offset; 393 uint32_t mpi_oqc_offset; 394 395 /* 396 * Inbound and outbound queue depth 397 */ 398 uint32_t ioq_depth; 399 400 /* 401 * Kernel addresses and offsets for Inbound Queue Producer Indices 402 * 403 * See comments in pmcs_iomb.h about Inbound Queues. Since it 404 * is relatively expensive to go across the PCIe bus to read or 405 * write inside the card, we maintain shadow copies in kernel 406 * memory and update the card as needed. 407 */ 408 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 409 uint32_t iqpi_offset[PMCS_MAX_IQ]; 410 uint32_t *iqp[PMCS_MAX_IQ]; 411 kmutex_t iqp_lock[PMCS_NIQ]; 412 413 pmcs_iqp_trace_t *iqpt; 414 415 /* 416 * Kernel addresses and offsets for Outbound Queue Consumer Indices 417 */ 418 uint32_t *oqp[PMCS_MAX_OQ]; 419 uint32_t oqci_offset[PMCS_MAX_OQ]; 420 421 /* 422 * Driver's copy of the outbound queue indices 423 */ 424 425 uint32_t oqci[PMCS_NOQ]; 426 uint32_t oqpi[PMCS_NOQ]; 427 428 /* 429 * DMA addresses for both Inbound and Outbound queues. 430 */ 431 uint64_t oqaddr[PMCS_MAX_OQ]; 432 uint64_t iqaddr[PMCS_MAX_IQ]; 433 434 /* 435 * Producer/Queue Host Memory Pointers and scratch areas, 436 * as well as DMA scatter/gather chunk areas. 437 * 438 * See discussion in pmcs_def.h about how this is laid out. 439 */ 440 uint8_t *cip; 441 uint64_t ciaddr; 442 443 /* 444 * Scratch area pointer and DMA addrress for SATA and SMP operations. 445 */ 446 void *scratch; 447 uint64_t scratch_dma; 448 volatile uint8_t scratch_locked; /* Scratch area ownership */ 449 450 /* 451 * Firmware log pointer 452 */ 453 uint32_t *fwlogp; 454 uint64_t fwaddr; 455 456 /* 457 * Internal register dump region and flash chunk DMA info 458 */ 459 460 caddr_t regdumpp; 461 uint32_t *flash_chunkp; 462 uint64_t flash_chunk_addr; 463 464 /* 465 * Card information, some determined during MPI setup 466 */ 467 uint32_t fw; /* firmware version */ 468 uint8_t max_iq; /* maximum inbound queues this card */ 469 uint8_t max_oq; /* "" outbound "" */ 470 uint8_t nphy; /* number of phys this card */ 471 uint8_t chiprev; /* chip revision */ 472 uint16_t max_cmd; /* max number of commands supported */ 473 uint16_t max_dev; /* max number of devices supported */ 474 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 475 476 477 /* 478 * Interrupt Setup stuff. 479 * 480 * int_type defines the kind of interrupt we're using with this card. 481 * oqvec defines the relationship between an Outbound Queue Number and 482 * a MSI-X vector. 483 */ 484 enum { 485 PMCS_INT_NONE, 486 PMCS_INT_TIMER, 487 PMCS_INT_MSI, 488 PMCS_INT_MSIX, 489 PMCS_INT_FIXED 490 } int_type; 491 uint8_t oqvec[PMCS_NOQ]; 492 493 /* 494 * Interrupt handle table and size 495 */ 496 ddi_intr_handle_t *ih_table; 497 size_t ih_table_size; 498 499 timeout_id_t wdhandle; 500 uint32_t intr_mask; 501 int intr_cnt; 502 int intr_cap; 503 uint32_t odb_auto_clear; 504 505 /* 506 * DMA S/G chunk list 507 */ 508 int nchunks; 509 pmcs_chunk_t *dma_chunklist; 510 511 /* 512 * Front of the DMA S/G chunk freelist 513 */ 514 pmcs_dmachunk_t *dma_freelist; 515 516 /* 517 * PHY and Discovery Related Stuff 518 * 519 * The PMC chip can have up to 16 local phys. We build a level-first 520 * traversal tree of phys starting with the physical phys on the 521 * chip itself (i.e., treating the chip as if it were an expander). 522 * 523 * Our discovery process goes through a level and discovers what 524 * each entity is (and it's phy number within that expander's 525 * address space). It then configures each non-empty item (SAS, 526 * SATA/STP, EXPANDER). For expanders, it then performs 527 * discover on that expander itself via REPORT GENERAL and 528 * DISCOVERY SMP commands, attaching the discovered entities 529 * to the next level. Then we step down a level and continue 530 * (and so on). 531 * 532 * The PMC chip maintains an I_T_NEXUS notion based upon our 533 * registering each new device found (getting back a device handle). 534 * 535 * Like with the number of physical PHYS being a maximum of 16, 536 * there are a maximum number of PORTS also being 16. Some 537 * events apply to PORTS entirely, so we track PORTS as well. 538 */ 539 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 540 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 541 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 542 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 543 544 kmem_cache_t *phy_cache; 545 546 /* 547 * Discovery-related items. 548 * config_lock: Protects config_changed and should never be held 549 * outside of getting or setting the value of config_changed. 550 * config_changed: Boolean indicating whether discovery needs to 551 * be restarted. 552 * configuring: 1 = discovery is running, 0 = discovery not running. 553 * NOTE: configuring is now in the bitfield above. 554 */ 555 kmutex_t config_lock; 556 volatile boolean_t config_changed; 557 558 /* 559 * Work Related Stuff 560 * 561 * Each command given to the PMC chip has an associated work structure. 562 * See the discussion in pmcs_def.h about work structures. 563 */ 564 pmcwork_t *work; /* pool of work structures */ 565 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 566 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 567 uint16_t wserno; /* rolling serial number */ 568 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 569 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 570 571 /* 572 * Solaris/SCSA items. 573 */ 574 scsi_hba_tran_t *tran; 575 smp_hba_tran_t *smp_tran; 576 struct scsi_reset_notify_entry *reset_notify_listf; 577 578 /* 579 * Thread Level stuff. 580 * 581 * A number of tasks are done off worker thread taskq. 582 */ 583 ddi_taskq_t *tq; /* For the worker thread */ 584 volatile ulong_t work_flags; 585 586 /* 587 * Solaris target representation. 588 * targets = array of pointers to xscsi structures 589 * allocated by ssoftstate. 590 */ 591 pmcs_xscsi_t **targets; 592 593 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 594 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 595 kmutex_t cq_lock; 596 kmem_cache_t *iocomp_cb_cache; 597 pmcs_iocomp_cb_t *iocomp_cb_head; 598 pmcs_iocomp_cb_t *iocomp_cb_tail; 599 600 uint16_t debug_mask; 601 uint16_t phyid_block_mask; 602 uint16_t phys_started; 603 uint32_t hipri_queue; 604 uint32_t mpibar; 605 uint32_t intr_pri; 606 607 pmcs_io_intr_coal_t io_intr_coal; 608 pmcs_cq_info_t cq_info; 609 kmutex_t ict_lock; 610 kcondvar_t ict_cv; 611 kthread_t *ict_thread; 612 613 #ifdef DEBUG 614 kmutex_t dbglock; 615 uint32_t ltags[256]; 616 uint32_t ftags[256]; 617 hrtime_t ltime[256]; 618 hrtime_t ftime[256]; 619 uint16_t ftag_lines[256]; 620 uint8_t lti; /* last tag index */ 621 uint8_t fti; /* first tag index */ 622 #endif 623 }; 624 625 extern void *pmcs_softc_state; 626 extern void *pmcs_iport_softstate; 627 628 /* 629 * Some miscellaneous, oft used strings 630 */ 631 extern const char pmcs_nowrk[]; 632 extern const char pmcs_nomsg[]; 633 extern const char pmcs_timeo[]; 634 635 #ifdef __cplusplus 636 } 637 #endif 638 #endif /* _PMCS_H */ 639