1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/sysmacros.h> 53 #include <sys/bitmap.h> 54 #include <sys/queue.h> 55 #include <sys/sdt.h> 56 #include <sys/ddifm.h> 57 #include <sys/fm/protocol.h> 58 #include <sys/fm/util.h> 59 #include <sys/fm/io/ddi.h> 60 #include <sys/scsi/impl/spc3_types.h> 61 62 typedef struct pmcs_hw pmcs_hw_t; 63 typedef struct pmcs_iport pmcs_iport_t; 64 typedef struct pmcs_phy pmcs_phy_t; 65 typedef struct lsas_cmd lsas_cmd_t; 66 typedef struct lsas_result lsas_result_t; 67 typedef struct lsata_cmd lsata_cmd_t; 68 typedef struct lsata_result lsata_result_t; 69 typedef struct pmcwork pmcwork_t; 70 typedef struct pmcs_cmd pmcs_cmd_t; 71 typedef struct pmcs_xscsi pmcs_xscsi_t; 72 typedef struct pmcs_lun pmcs_lun_t; 73 typedef struct pmcs_chunk pmcs_chunk_t; 74 75 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 80 81 #include <sys/scsi/adapters/pmcs/ata.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 86 87 #define PMCS_MAX_UA_SIZE 32 88 89 struct pmcs_xscsi { 90 uint32_t 91 ca : 1, /* SATA specific */ 92 ncq : 1, /* SATA specific */ 93 pio : 1, /* SATA specific */ 94 special_needed : 1, /* SATA specific */ 95 special_running : 1, /* SATA specific */ 96 reset_success : 1, /* last reset ok */ 97 reset_wait : 1, /* wait for reset */ 98 resetting : 1, /* now resetting */ 99 recover_wait : 1, /* wait for recovery */ 100 recovering : 1, /* now recovering */ 101 event_recovery : 1, /* event recovery */ 102 draining : 1, 103 new : 1, 104 assigned : 1, 105 dev_gone : 1, 106 phy_addressable : 1, /* Direct attach SATA */ 107 dev_state : 4; 108 uint16_t maxdepth; 109 uint16_t qdepth; 110 uint16_t actv_cnt; 111 uint16_t target_num; 112 /* statlock protects both target stats and the special queue (sq) */ 113 kmutex_t statlock; 114 int32_t ref_count; 115 dev_info_t *dip; /* Solaris device dip */ 116 pmcs_phy_t *phy; 117 STAILQ_HEAD(wqh, pmcs_cmd) wq; 118 pmcs_cmd_t *wq_recovery_tail; /* See below */ 119 kmutex_t wqlock; 120 STAILQ_HEAD(aqh, pmcs_cmd) aq; 121 kmutex_t aqlock; 122 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 123 uint32_t tagmap; /* SATA specific */ 124 pmcs_hw_t *pwp; 125 ddi_soft_state_bystr *lun_sstate; 126 uint64_t capacity; /* SATA specific */ 127 char unit_address[PMCS_MAX_UA_SIZE]; 128 kcondvar_t reset_cv; 129 kcondvar_t abort_cv; 130 char *ua; 131 pmcs_dtype_t dtype; 132 }; 133 134 /* 135 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 136 * the wait queue (wq). That pointer is the last command in the wait queue 137 * that needs to be reissued after device state recovery is complete. Commands 138 * that need to be retried are reinserted into the wq after wq_recovery_tail 139 * to maintain the order in which the commands were originally submitted. 140 */ 141 142 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 143 144 #define PMCS_TGT_WAIT_QUEUE 0x01 145 #define PMCS_TGT_ACTIVE_QUEUE 0x02 146 #define PMCS_TGT_SPECIAL_QUEUE 0x04 147 #define PMCS_TGT_ALL_QUEUES 0xff 148 149 /* 150 * LUN representation. Just a LUN (number) and pointer to the target 151 * structure (pmcs_xscsi). 152 */ 153 154 struct pmcs_lun { 155 pmcs_xscsi_t *target; 156 uint64_t lun_num; /* lun64 */ 157 scsi_lun_t scsi_lun; /* Wire format */ 158 char unit_address[PMCS_MAX_UA_SIZE]; 159 }; 160 161 /* 162 * Interrupt coalescing values 163 */ 164 #define PMCS_MAX_IO_COMPS_PER_INTR 12 165 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 166 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 167 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 168 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 169 #define PMCS_MAX_CQ_THREADS 4 170 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 171 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 172 173 /* 174 * This structure is used to maintain state with regard to I/O interrupt 175 * coalescing. 176 */ 177 178 typedef struct pmcs_io_intr_coal_s { 179 hrtime_t nsecs_between_intrs; 180 hrtime_t last_io_comp; 181 clock_t quantum; 182 uint32_t num_io_completions; 183 uint32_t num_intrs; 184 uint32_t max_io_completions; 185 uint32_t intr_latency; 186 uint32_t intr_threshold; 187 uint16_t intr_coal_timer; 188 boolean_t timer_on; 189 boolean_t stop_thread; 190 boolean_t int_cleared; 191 } pmcs_io_intr_coal_t; 192 193 typedef struct pmcs_cq_thr_info_s { 194 kthread_t *cq_thread; 195 kmutex_t cq_thr_lock; 196 kcondvar_t cq_cv; 197 pmcs_hw_t *cq_pwp; 198 } pmcs_cq_thr_info_t; 199 200 typedef struct pmcs_cq_info_s { 201 uint32_t cq_threads; 202 uint32_t cq_next_disp_thr; 203 boolean_t cq_stop; 204 pmcs_cq_thr_info_t *cq_thr_info; 205 } pmcs_cq_info_t; 206 207 typedef struct pmcs_iocomp_cb_s { 208 pmcwork_t *pwrk; 209 char iomb[PMCS_QENTRY_SIZE << 1]; 210 struct pmcs_iocomp_cb_s *next; 211 } pmcs_iocomp_cb_t; 212 213 typedef struct pmcs_iqp_trace_s { 214 char *head; 215 char *curpos; 216 uint32_t size_left; 217 } pmcs_iqp_trace_t; 218 219 /* 220 * Used by string-based softstate as hint to possible size. 221 */ 222 223 #define PMCS_TGT_SSTATE_SZ 64 224 #define PMCS_LUN_SSTATE_SZ 4 225 226 /* 227 * HBA iport node softstate 228 */ 229 #define PMCS_IPORT_INVALID_PORT_ID 0xffff 230 231 struct pmcs_iport { 232 kmutex_t lock; /* iport lock */ 233 list_node_t list_node; /* list node for pwp->iports list_t */ 234 kmutex_t refcnt_lock; /* refcnt lock */ 235 kcondvar_t refcnt_cv; /* refcnt cv */ 236 int refcnt; /* refcnt for this iport */ 237 dev_info_t *dip; /* iport dip */ 238 pmcs_hw_t *pwp; /* back pointer to HBA state */ 239 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 240 enum { /* unit address state in the phymap */ 241 UA_INACTIVE, 242 UA_PEND_ACTIVATE, 243 UA_ACTIVE, 244 UA_PEND_DEACTIVATE 245 } ua_state; 246 char *ua; /* unit address (phy mask) */ 247 int portid; /* portid */ 248 int report_skip; /* skip or report during discovery */ 249 list_t phys; /* list of phys on this port */ 250 int nphy; /* number of phys in this port */ 251 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 252 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 253 /* SMP serialization */ 254 kmutex_t smp_lock; 255 kcondvar_t smp_cv; 256 boolean_t smp_active; 257 kthread_t *smp_active_thread; 258 }; 259 260 struct pmcs_chunk { 261 pmcs_chunk_t *next; 262 ddi_acc_handle_t acc_handle; 263 ddi_dma_handle_t dma_handle; 264 uint8_t *addrp; 265 uint64_t dma_addr; 266 }; 267 268 /* 269 * HBA node (i.e. non-iport) softstate 270 */ 271 struct pmcs_hw { 272 /* 273 * Identity 274 */ 275 dev_info_t *dip; 276 277 /* 278 * 16 possible initiator PHY WWNs 279 */ 280 uint64_t sas_wwns[PMCS_MAX_PORTS]; 281 282 /* 283 * Card State 284 */ 285 enum pwpstate { 286 STATE_NIL, 287 STATE_PROBING, 288 STATE_RUNNING, 289 STATE_UNPROBING, 290 STATE_DEAD 291 } state; 292 293 uint32_t 294 fw_disable_update : 1, 295 fw_force_update : 1, 296 blocked : 1, 297 stuck : 1, 298 locks_initted : 1, 299 mpi_table_setup : 1, 300 hba_attached : 1, 301 iports_attached : 1, 302 suspended : 1, 303 separate_ports : 1, 304 fwlog : 4, 305 phymode : 3, 306 physpeed : 3, 307 resource_limited : 1, 308 configuring : 1, 309 ds_err_recovering : 1; 310 311 /* 312 * This HBA instance's iportmap and list of iport states. 313 * Note: iports_lock protects iports, iports_attached, and 314 * num_iports on the HBA softstate. 315 */ 316 krwlock_t iports_lock; 317 scsi_hba_iportmap_t *hss_iportmap; 318 list_t iports; 319 int num_iports; 320 321 sas_phymap_t *hss_phymap; 322 int phymap_active; 323 324 /* 325 * Locks 326 */ 327 kmutex_t lock; 328 kmutex_t dma_lock; 329 kmutex_t axil_lock; 330 kcondvar_t drain_cv; 331 332 /* 333 * FMA Capabilities 334 */ 335 int fm_capabilities; 336 337 /* 338 * Register Access Handles 339 */ 340 ddi_device_acc_attr_t dev_acc_attr; 341 ddi_device_acc_attr_t reg_acc_attr; 342 ddi_acc_handle_t pci_acc_handle; 343 ddi_acc_handle_t msg_acc_handle; 344 ddi_acc_handle_t top_acc_handle; 345 ddi_acc_handle_t mpi_acc_handle; 346 ddi_acc_handle_t gsm_acc_handle; 347 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 348 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 349 ddi_acc_handle_t cip_acchdls; 350 ddi_acc_handle_t fwlog_acchdl; 351 ddi_acc_handle_t regdump_acchdl; 352 353 /* 354 * DMA Handles 355 */ 356 ddi_dma_attr_t iqp_dma_attr; 357 ddi_dma_attr_t oqp_dma_attr; 358 ddi_dma_attr_t cip_dma_attr; 359 ddi_dma_attr_t fwlog_dma_attr; 360 ddi_dma_attr_t regdump_dma_attr; 361 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 362 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 363 ddi_dma_handle_t cip_handles; 364 ddi_dma_handle_t fwlog_hndl; 365 ddi_dma_handle_t regdump_hndl; 366 367 /* 368 * Register Pointers 369 */ 370 uint32_t *msg_regs; /* message unit registers */ 371 uint32_t *top_regs; /* top unit registers */ 372 uint32_t *mpi_regs; /* message passing unit registers */ 373 uint32_t *gsm_regs; /* GSM registers */ 374 375 /* 376 * Message Passing and other offsets. 377 * 378 * mpi_offset is the offset within the fourth register set (mpi_regs) 379 * that contains the base of the MPI structures. Since this is actually 380 * set by the card firmware, it can change from startup to startup. 381 * 382 * The other offsets (gst, iqc, oqc) are for similar tables in 383 * MPI space, typically only accessed during setup. 384 */ 385 uint32_t mpi_offset; 386 uint32_t mpi_gst_offset; 387 uint32_t mpi_iqc_offset; 388 uint32_t mpi_oqc_offset; 389 390 /* 391 * Inbound and outbound queue depth 392 */ 393 uint32_t ioq_depth; 394 395 /* 396 * Kernel addresses and offsets for Inbound Queue Producer Indices 397 * 398 * See comments in pmcs_iomb.h about Inbound Queues. Since it 399 * is relatively expensive to go across the PCIe bus to read or 400 * write inside the card, we maintain shadow copies in kernel 401 * memory and update the card as needed. 402 */ 403 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 404 uint32_t iqpi_offset[PMCS_MAX_IQ]; 405 uint32_t *iqp[PMCS_MAX_IQ]; 406 kmutex_t iqp_lock[PMCS_NIQ]; 407 408 pmcs_iqp_trace_t *iqpt; 409 410 /* 411 * Kernel addresses and offsets for Outbound Queue Consumer Indices 412 */ 413 uint32_t *oqp[PMCS_MAX_OQ]; 414 uint32_t oqci_offset[PMCS_MAX_OQ]; 415 416 /* 417 * Driver's copy of the outbound queue indices 418 */ 419 420 uint32_t oqci[PMCS_NOQ]; 421 uint32_t oqpi[PMCS_NOQ]; 422 423 /* 424 * DMA addresses for both Inbound and Outbound queues. 425 */ 426 uint64_t oqaddr[PMCS_MAX_OQ]; 427 uint64_t iqaddr[PMCS_MAX_IQ]; 428 429 /* 430 * Producer/Queue Host Memory Pointers and scratch areas, 431 * as well as DMA scatter/gather chunk areas. 432 * 433 * See discussion in pmcs_def.h about how this is laid out. 434 */ 435 uint8_t *cip; 436 uint64_t ciaddr; 437 438 /* 439 * Scratch area pointer and DMA addrress for SATA and SMP operations. 440 */ 441 void *scratch; 442 uint64_t scratch_dma; 443 volatile uint8_t scratch_locked; /* Scratch area ownership */ 444 445 /* 446 * Firmware log pointer 447 */ 448 uint32_t *fwlogp; 449 uint64_t fwaddr; 450 451 /* 452 * Internal register dump region and flash chunk DMA info 453 */ 454 455 caddr_t regdumpp; 456 uint32_t *flash_chunkp; 457 uint64_t flash_chunk_addr; 458 459 /* 460 * Card information, some determined during MPI setup 461 */ 462 uint32_t fw; /* firmware version */ 463 uint8_t max_iq; /* maximum inbound queues this card */ 464 uint8_t max_oq; /* "" outbound "" */ 465 uint8_t nphy; /* number of phys this card */ 466 uint8_t chiprev; /* chip revision */ 467 uint16_t max_cmd; /* max number of commands supported */ 468 uint16_t max_dev; /* max number of devices supported */ 469 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 470 471 472 /* 473 * Interrupt Setup stuff. 474 * 475 * int_type defines the kind of interrupt we're using with this card. 476 * oqvec defines the relationship between an Outbound Queue Number and 477 * a MSI-X vector. 478 */ 479 enum { 480 PMCS_INT_NONE, 481 PMCS_INT_TIMER, 482 PMCS_INT_MSI, 483 PMCS_INT_MSIX, 484 PMCS_INT_FIXED 485 } int_type; 486 uint8_t oqvec[PMCS_NOQ]; 487 488 /* 489 * Interrupt handle table and size 490 */ 491 ddi_intr_handle_t *ih_table; 492 size_t ih_table_size; 493 494 timeout_id_t wdhandle; 495 uint32_t intr_mask; 496 int intr_cnt; 497 int intr_cap; 498 uint32_t odb_auto_clear; 499 500 /* 501 * DMA S/G chunk list 502 */ 503 int nchunks; 504 pmcs_chunk_t *dma_chunklist; 505 506 /* 507 * Front of the DMA S/G chunk freelist 508 */ 509 pmcs_dmachunk_t *dma_freelist; 510 511 /* 512 * PHY and Discovery Related Stuff 513 * 514 * The PMC chip can have up to 16 local phys. We build a level-first 515 * traversal tree of phys starting with the physical phys on the 516 * chip itself (i.e., treating the chip as if it were an expander). 517 * 518 * Our discovery process goes through a level and discovers what 519 * each entity is (and it's phy number within that expander's 520 * address space). It then configures each non-empty item (SAS, 521 * SATA/STP, EXPANDER). For expanders, it then performs 522 * discover on that expander itself via REPORT GENERAL and 523 * DISCOVERY SMP commands, attaching the discovered entities 524 * to the next level. Then we step down a level and continue 525 * (and so on). 526 * 527 * The PMC chip maintains an I_T_NEXUS notion based upon our 528 * registering each new device found (getting back a device handle). 529 * 530 * Like with the number of physical PHYS being a maximum of 16, 531 * there are a maximum number of PORTS also being 16. Some 532 * events apply to PORTS entirely, so we track PORTS as well. 533 */ 534 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 535 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 536 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 537 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 538 539 kmem_cache_t *phy_cache; 540 541 /* 542 * Discovery-related items. 543 * config_lock: Protects config_changed and should never be held 544 * outside of getting or setting the value of config_changed. 545 * config_changed: Boolean indicating whether discovery needs to 546 * be restarted. 547 * configuring: 1 = discovery is running, 0 = discovery not running. 548 * NOTE: configuring is now in the bitfield above. 549 */ 550 kmutex_t config_lock; 551 volatile boolean_t config_changed; 552 553 /* 554 * Work Related Stuff 555 * 556 * Each command given to the PMC chip has an associated work structure. 557 * See the discussion in pmcs_def.h about work structures. 558 */ 559 pmcwork_t *work; /* pool of work structures */ 560 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 561 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 562 uint16_t wserno; /* rolling serial number */ 563 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 564 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 565 566 /* 567 * Solaris/SCSA items. 568 */ 569 scsi_hba_tran_t *tran; 570 smp_hba_tran_t *smp_tran; 571 struct scsi_reset_notify_entry *reset_notify_listf; 572 573 /* 574 * Thread Level stuff. 575 * 576 * A number of tasks are done off worker thread taskq. 577 */ 578 ddi_taskq_t *tq; /* For the worker thread */ 579 volatile ulong_t work_flags; 580 581 /* 582 * Solaris target representation. 583 * targets = array of pointers to xscsi structures 584 * allocated by ssoftstate. 585 */ 586 pmcs_xscsi_t **targets; 587 588 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 589 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 590 kmutex_t cq_lock; 591 kmem_cache_t *iocomp_cb_cache; 592 pmcs_iocomp_cb_t *iocomp_cb_head; 593 pmcs_iocomp_cb_t *iocomp_cb_tail; 594 595 uint16_t debug_mask; 596 uint16_t phyid_block_mask; 597 uint16_t phys_started; 598 uint32_t hipri_queue; 599 uint32_t mpibar; 600 uint32_t intr_pri; 601 602 pmcs_io_intr_coal_t io_intr_coal; 603 pmcs_cq_info_t cq_info; 604 kmutex_t ict_lock; 605 kcondvar_t ict_cv; 606 kthread_t *ict_thread; 607 608 #ifdef DEBUG 609 kmutex_t dbglock; 610 uint32_t ltags[256]; 611 uint32_t ftags[256]; 612 hrtime_t ltime[256]; 613 hrtime_t ftime[256]; 614 uint16_t ftag_lines[256]; 615 uint8_t lti; /* last tag index */ 616 uint8_t fti; /* first tag index */ 617 #endif 618 }; 619 620 extern void *pmcs_softc_state; 621 extern void *pmcs_iport_softstate; 622 623 /* 624 * Some miscellaneous, oft used strings 625 */ 626 extern const char pmcs_nowrk[]; 627 extern const char pmcs_nomsg[]; 628 extern const char pmcs_timeo[]; 629 630 #ifdef __cplusplus 631 } 632 #endif 633 #endif /* _PMCS_H */ 634