1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2014 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved. 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 27 */ 28 29 /* 30 * Copyright (c) 2000 to 2010, LSI Corporation. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms of all code within 34 * this file that is exclusively owned by LSI, with or without 35 * modification, is permitted provided that, in addition to the CDDL 1.0 36 * License requirements, the following conditions are met: 37 * 38 * Neither the name of the author nor the names of its contributors may be 39 * used to endorse or promote products derived from this software without 40 * specific prior written permission. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 53 * DAMAGE. 54 */ 55 56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 58 59 #include <sys/byteorder.h> 60 #include <sys/queue.h> 61 #include <sys/isa_defs.h> 62 #include <sys/sunmdi.h> 63 #include <sys/mdi_impldefs.h> 64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 68 69 #ifdef __cplusplus 70 extern "C" { 71 #endif 72 73 /* 74 * Compile options 75 */ 76 #ifdef DEBUG 77 #define MPTSAS_DEBUG /* turn on debugging code */ 78 #endif /* DEBUG */ 79 80 #define MPTSAS_INITIAL_SOFT_SPACE 4 81 82 #define MAX_MPI_PORTS 16 83 84 /* 85 * Note below macro definition and data type definition 86 * are used for phy mask handling, it should be changed 87 * simultaneously. 88 */ 89 #define MPTSAS_MAX_PHYS 16 90 typedef uint16_t mptsas_phymask_t; 91 92 #define MPTSAS_INVALID_DEVHDL 0xffff 93 #define MPTSAS_SATA_GUID "sata-guid" 94 95 /* 96 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 97 * targets. There's no need to go overboard here, as the ordinary paths for 98 * I/O do not normally require hashed target lookups. These should be good 99 * enough and then some for any fabric within the hardware's capabilities. 100 */ 101 #define MPTSAS_SMP_BUCKET_COUNT 23 102 #define MPTSAS_TARGET_BUCKET_COUNT 97 103 104 /* 105 * MPT HW defines 106 */ 107 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 108 #define MPTSAS_MAX_DISKS_IN_VOL 10 109 #define MPTSAS_MAX_HOTSPARES 2 110 #define MPTSAS_MAX_RAIDVOLS 2 111 #define MPTSAS_MAX_RAIDCONFIGS 5 112 113 /* 114 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 115 * plus two means the prefix 'w' and end of the string '\0'. 116 */ 117 #define MPTSAS_WWN_STRLEN (16 + 2) 118 #define MPTSAS_MAX_GUID_LEN 64 119 120 /* 121 * DMA routine flags 122 */ 123 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 124 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 125 #define MPTSAS_DMA_HANDLE_BOUND 0x8 126 127 /* 128 * If the HBA supports DMA or bus-mastering, you may have your own 129 * scatter-gather list for physically non-contiguous memory in one 130 * I/O operation; if so, there's probably a size for that list. 131 * It must be placed in the ddi_dma_lim_t structure, so that the system 132 * DMA-support routines can use it to break up the I/O request, so we 133 * define it here. 134 */ 135 #if defined(__sparc) 136 #define MPTSAS_MAX_DMA_SEGS 1 137 #define MPTSAS_MAX_CMD_SEGS 1 138 #else 139 #define MPTSAS_MAX_DMA_SEGS 256 140 #define MPTSAS_MAX_CMD_SEGS 257 141 #endif 142 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 143 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 144 145 #define MPTSAS_SGE_SIZE(mpt) \ 146 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \ 147 sizeof (MPI2_SGE_SIMPLE64)) 148 149 /* 150 * Calculating how many 64-bit DMA simple elements can be stored in the first 151 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 152 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 153 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words 154 * (16 bytes). 155 */ 156 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 157 ((mpt->m_req_frame_size - \ 158 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \ 159 MPTSAS_SGE_SIZE(mpt)) 160 161 /* 162 * Scatter-gather list structure defined by HBA hardware 163 */ 164 typedef struct NcrTableIndirect { /* Table Indirect entries */ 165 uint32_t count; /* 24 bit count */ 166 union { 167 uint32_t address32; /* 32 bit address */ 168 struct { 169 uint32_t Low; 170 uint32_t High; 171 } address64; /* 64 bit address */ 172 } addr; 173 } mptti_t; 174 175 /* 176 * preferred pkt_private length in 64-bit quantities 177 */ 178 #ifdef _LP64 179 #define PKT_PRIV_SIZE 2 180 #define PKT_PRIV_LEN 16 /* in bytes */ 181 #else /* _ILP32 */ 182 #define PKT_PRIV_SIZE 1 183 #define PKT_PRIV_LEN 8 /* in bytes */ 184 #endif 185 186 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 187 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 188 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 189 190 /* 191 * get offset of item in structure 192 */ 193 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 194 195 /* 196 * WWID provided by LSI firmware is generated by firmware but the WWID is not 197 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 198 * address. According LSI's confirmation, the top nibble of RAID WWID is 199 * meanless, so the consensus between Solaris and OBP is to replace top nibble 200 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 201 * format unit address. 202 */ 203 #define MPTSAS_RAID_WWID(wwid) \ 204 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 205 206 typedef struct mptsas_target_addr { 207 uint64_t mta_wwn; 208 mptsas_phymask_t mta_phymask; 209 } mptsas_target_addr_t; 210 211 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd); 212 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t; 213 214 typedef struct mptsas_target { 215 mptsas_target_addr_t m_addr; 216 refhash_link_t m_link; 217 uint8_t m_dr_flag; 218 uint16_t m_devhdl; 219 uint32_t m_deviceinfo; 220 uint8_t m_phynum; 221 uint32_t m_dups; 222 mptsas_active_cmdq_t m_active_cmdq; 223 int32_t m_t_throttle; 224 int32_t m_t_ncmds; 225 int32_t m_reset_delay; 226 int32_t m_t_nwait; 227 228 uint16_t m_qfull_retry_interval; 229 uint8_t m_qfull_retries; 230 uint16_t m_io_flags; 231 uint16_t m_enclosure; 232 uint16_t m_slot_num; 233 uint32_t m_tgt_unconfigured; 234 uint8_t m_led_status; 235 uint8_t m_scsi_req_desc_type; 236 237 } mptsas_target_t; 238 239 /* 240 * If you change this structure, be sure that mptsas_smp_target_copy() 241 * does the right thing. 242 */ 243 typedef struct mptsas_smp { 244 mptsas_target_addr_t m_addr; 245 refhash_link_t m_link; 246 uint16_t m_devhdl; 247 uint32_t m_deviceinfo; 248 uint16_t m_pdevhdl; 249 uint32_t m_pdevinfo; 250 } mptsas_smp_t; 251 252 typedef struct mptsas_cache_frames { 253 ddi_dma_handle_t m_dma_hdl; 254 ddi_acc_handle_t m_acc_hdl; 255 caddr_t m_frames_addr; 256 uint32_t m_phys_addr; 257 } mptsas_cache_frames_t; 258 259 typedef struct mptsas_cmd { 260 uint_t cmd_flags; /* flags from scsi_init_pkt */ 261 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 262 ddi_dma_cookie_t cmd_cookie; 263 uint_t cmd_cookiec; 264 uint_t cmd_winindex; 265 uint_t cmd_nwin; 266 uint_t cmd_cur_cookie; 267 off_t cmd_dma_offset; 268 size_t cmd_dma_len; 269 uint32_t cmd_totaldmacount; 270 271 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 272 ddi_dma_cookie_t cmd_arqcookie; 273 struct buf *cmd_arq_buf; 274 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 275 ddi_dma_cookie_t cmd_ext_arqcookie; 276 struct buf *cmd_ext_arq_buf; 277 278 int cmd_pkt_flags; 279 280 /* pending expiration time for command in active slot */ 281 hrtime_t cmd_active_expiration; 282 TAILQ_ENTRY(mptsas_cmd) cmd_active_link; 283 284 struct scsi_pkt *cmd_pkt; 285 struct scsi_arq_status cmd_scb; 286 uchar_t cmd_cdblen; /* length of cdb */ 287 uchar_t cmd_rqslen; /* len of requested rqsense */ 288 uchar_t cmd_privlen; 289 uint_t cmd_scblen; 290 uint32_t cmd_dmacount; 291 uint64_t cmd_dma_addr; 292 uchar_t cmd_age; 293 ushort_t cmd_qfull_retries; 294 uchar_t cmd_queued; /* true if queued */ 295 struct mptsas_cmd *cmd_linkp; 296 mptti_t *cmd_sg; /* Scatter/Gather structure */ 297 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 298 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 299 uint32_t cmd_slot; 300 uint32_t ioc_cmd_slot; 301 302 mptsas_cache_frames_t *cmd_extra_frames; 303 304 uint32_t cmd_rfm; 305 mptsas_target_t *cmd_tgt_addr; 306 } mptsas_cmd_t; 307 308 /* 309 * These are the defined cmd_flags for this structure. 310 */ 311 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 312 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 313 #define CFLAG_FINISHED 0x000004 /* command completed */ 314 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 315 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 316 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 317 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 318 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 319 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 320 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 321 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 322 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 323 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 324 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 325 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 326 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 327 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 328 #define CFLAG_FREE 0x010000 /* packet is on free list */ 329 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 330 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 331 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 332 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 333 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 334 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 335 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 336 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 337 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 338 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 339 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 340 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 341 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 342 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 343 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 344 345 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 347 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 356 357 #define MPTSAS_HASH_ARRAY_SIZE 16 358 /* 359 * hash table definition 360 */ 361 362 #define MPTSAS_HASH_FIRST 0xffff 363 #define MPTSAS_HASH_NEXT 0x0000 364 365 typedef struct mptsas_dma_alloc_state 366 { 367 ddi_dma_handle_t handle; 368 caddr_t memp; 369 size_t size; 370 ddi_acc_handle_t accessp; 371 ddi_dma_cookie_t cookie; 372 } mptsas_dma_alloc_state_t; 373 374 /* 375 * passthrough request structure 376 */ 377 typedef struct mptsas_pt_request { 378 uint8_t *request; 379 uint32_t request_size; 380 uint32_t data_size; 381 uint32_t dataout_size; 382 uint32_t direction; 383 uint8_t simple; 384 uint16_t sgl_offset; 385 ddi_dma_cookie_t data_cookie; 386 ddi_dma_cookie_t dataout_cookie; 387 } mptsas_pt_request_t; 388 389 /* 390 * config page request structure 391 */ 392 typedef struct mptsas_config_request { 393 uint32_t page_address; 394 uint8_t action; 395 uint8_t page_type; 396 uint8_t page_number; 397 uint8_t page_length; 398 uint8_t page_version; 399 uint8_t ext_page_type; 400 uint16_t ext_page_length; 401 } mptsas_config_request_t; 402 403 typedef struct mptsas_fw_diagnostic_buffer { 404 mptsas_dma_alloc_state_t buffer_data; 405 uint8_t extended_type; 406 uint8_t buffer_type; 407 uint8_t force_release; 408 uint32_t product_specific[23]; 409 uint8_t immediate; 410 uint8_t enabled; 411 uint8_t valid_data; 412 uint8_t owned_by_firmware; 413 uint32_t unique_id; 414 } mptsas_fw_diagnostic_buffer_t; 415 416 /* 417 * FW diag request structure 418 */ 419 typedef struct mptsas_diag_request { 420 mptsas_fw_diagnostic_buffer_t *pBuffer; 421 uint8_t function; 422 } mptsas_diag_request_t; 423 424 typedef struct mptsas_hash_node { 425 void *data; 426 struct mptsas_hash_node *next; 427 } mptsas_hash_node_t; 428 429 typedef struct mptsas_hash_table { 430 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 431 /* 432 * last position in traverse 433 */ 434 struct mptsas_hash_node *cur; 435 uint16_t line; 436 437 } mptsas_hash_table_t; 438 439 /* 440 * RAID volume information 441 */ 442 typedef struct mptsas_raidvol { 443 ushort_t m_israid; 444 uint16_t m_raidhandle; 445 uint64_t m_raidwwid; 446 uint8_t m_state; 447 uint32_t m_statusflags; 448 uint32_t m_settings; 449 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 450 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 451 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 452 uint64_t m_raidsize; 453 int m_raidlevel; 454 int m_ndisks; 455 mptsas_target_t *m_raidtgt; 456 } mptsas_raidvol_t; 457 458 /* 459 * RAID configurations 460 */ 461 typedef struct mptsas_raidconfig { 462 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 463 uint16_t m_physdisk_devhdl[ 464 MPTSAS_MAX_DISKS_IN_CONFIG]; 465 uint8_t m_native; 466 } m_raidconfig_t; 467 468 /* 469 * Track outstanding commands. The index into the m_slot array is the SMID 470 * (system message ID) of the outstanding command. SMID 0 is reserved by the 471 * software/firmware protocol and is never used for any command we generate; 472 * as such, the assertion m_slot[0] == NULL is universally true. The last 473 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 474 * task management commands. No normal SCSI or ATA command will ever occupy 475 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 476 * time that a consistent view of the target array is obtainable. 477 * 478 * As such, m_n_normal is the maximum number of slots available to ordinary 479 * commands, and the relationship: 480 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 481 * always holds after initialisation. 482 */ 483 typedef struct mptsas_slots { 484 size_t m_size; /* size of struct, bytes */ 485 uint_t m_n_normal; /* see above */ 486 uint_t m_rotor; /* next slot idx to consider */ 487 mptsas_cmd_t *m_slot[1]; 488 } mptsas_slots_t; 489 490 /* 491 * Structure to hold command and packets for event ack 492 * and task management commands. 493 */ 494 typedef struct m_event_struct { 495 struct mptsas_cmd m_event_cmd; 496 struct m_event_struct *m_event_linkp; 497 /* 498 * event member record the failure event and eventcntx 499 * event member would be used in send ack pending process 500 */ 501 uint32_t m_event; 502 uint32_t m_eventcntx; 503 uint_t in_use; 504 struct scsi_pkt m_event_pkt; /* must be last */ 505 /* ... scsi_pkt_size() */ 506 } m_event_struct_t; 507 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 508 sizeof (struct scsi_pkt) + scsi_pkt_size()) 509 510 #define MAX_IOC_COMMANDS 8 511 512 /* 513 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 514 * A new event ack command requests mptsas_cmd and scsi_pkt structures 515 * from this pool, and returns it back when done. 516 */ 517 518 typedef struct m_replyh_arg { 519 void *mpt; 520 uint32_t rfm; 521 } m_replyh_arg_t; 522 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 523 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 524 525 /* 526 * Flags for DR handler topology change 527 */ 528 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 529 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 530 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 531 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 532 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 533 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 534 535 typedef struct mptsas_topo_change_list { 536 void *mpt; 537 uint_t event; 538 union { 539 uint8_t physport; 540 mptsas_phymask_t phymask; 541 } un; 542 uint16_t devhdl; 543 void *object; 544 uint8_t flags; 545 struct mptsas_topo_change_list *next; 546 } mptsas_topo_change_list_t; 547 548 549 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 550 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 551 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 552 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 553 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 554 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 555 556 /* 557 * Status types when calling mptsas_get_target_device_info 558 */ 559 #define DEV_INFO_SUCCESS 0x0 560 #define DEV_INFO_FAIL_PAGE0 0x1 561 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 562 #define DEV_INFO_PHYS_DISK 0x3 563 #define DEV_INFO_FAIL_ALLOC 0x4 564 565 /* 566 * mpt hotplug event defines 567 */ 568 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 569 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 570 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 571 572 /* 573 * SMP target hotplug events 574 */ 575 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 576 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 577 #define MPTSAS_DR_EVENT_MASK 0x3F 578 579 /* 580 * mpt hotplug status definition for m_dr_flag 581 */ 582 583 /* 584 * MPTSAS_DR_INACTIVE 585 * 586 * The target is in a normal operating state. 587 * No dynamic reconfiguration operation is in progress. 588 */ 589 #define MPTSAS_DR_INACTIVE 0x0 590 /* 591 * MPTSAS_DR_INTRANSITION 592 * 593 * The target is in a transition mode since 594 * hotplug event happens and offline procedure has not 595 * been finished 596 */ 597 #define MPTSAS_DR_INTRANSITION 0x1 598 599 typedef struct mptsas_tgt_private { 600 int t_lun; 601 struct mptsas_target *t_private; 602 } mptsas_tgt_private_t; 603 604 /* 605 * The following defines are used in mptsas_set_init_mode to track the current 606 * state as we progress through reprogramming the HBA from target mode into 607 * initiator mode. 608 */ 609 610 #define IOUC_READ_PAGE0 0x00000100 611 #define IOUC_READ_PAGE1 0x00000200 612 #define IOUC_WRITE_PAGE1 0x00000400 613 #define IOUC_DONE 0x00000800 614 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 615 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 616 617 /* 618 * Last allocated slot is used for TM requests. Since only m_max_requests 619 * frames are allocated, the last SMID will be m_max_requests - 1. 620 */ 621 #define MPTSAS_SLOTS_SIZE(mpt) \ 622 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 623 mpt->m_max_requests)) 624 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 625 626 /* 627 * Macro for phy_flags 628 */ 629 630 typedef struct smhba_info { 631 kmutex_t phy_mutex; 632 uint8_t phy_id; 633 uint64_t sas_addr; 634 char path[8]; 635 uint16_t owner_devhdl; 636 uint16_t attached_devhdl; 637 uint8_t attached_phy_identify; 638 uint32_t attached_phy_info; 639 uint8_t programmed_link_rate; 640 uint8_t hw_link_rate; 641 uint8_t change_count; 642 uint32_t phy_info; 643 uint8_t negotiated_link_rate; 644 uint8_t port_num; 645 kstat_t *phy_stats; 646 uint32_t invalid_dword_count; 647 uint32_t running_disparity_error_count; 648 uint32_t loss_of_dword_sync_count; 649 uint32_t phy_reset_problem_count; 650 void *mpt; 651 } smhba_info_t; 652 653 typedef struct mptsas_phy_info { 654 uint8_t port_num; 655 uint8_t port_flags; 656 uint16_t ctrl_devhdl; 657 uint32_t phy_device_type; 658 uint16_t attached_devhdl; 659 mptsas_phymask_t phy_mask; 660 smhba_info_t smhba_info; 661 } mptsas_phy_info_t; 662 663 664 typedef struct mptsas_doneq_thread_arg { 665 void *mpt; 666 uint64_t t; 667 } mptsas_doneq_thread_arg_t; 668 669 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 670 typedef struct mptsas_doneq_thread_list { 671 mptsas_cmd_t *doneq; 672 mptsas_cmd_t **donetail; 673 kthread_t *threadp; 674 kcondvar_t cv; 675 ushort_t reserv1; 676 uint32_t reserv2; 677 kmutex_t mutex; 678 uint32_t flag; 679 uint32_t len; 680 mptsas_doneq_thread_arg_t arg; 681 } mptsas_doneq_thread_list_t; 682 683 typedef struct mptsas { 684 int m_instance; 685 686 struct mptsas *m_next; 687 688 scsi_hba_tran_t *m_tran; 689 smp_hba_tran_t *m_smptran; 690 kmutex_t m_mutex; 691 kmutex_t m_passthru_mutex; 692 kcondvar_t m_cv; 693 kcondvar_t m_passthru_cv; 694 kcondvar_t m_fw_cv; 695 kcondvar_t m_config_cv; 696 kcondvar_t m_fw_diag_cv; 697 dev_info_t *m_dip; 698 699 /* 700 * soft state flags 701 */ 702 uint_t m_softstate; 703 704 refhash_t *m_targets; 705 refhash_t *m_smp_targets; 706 707 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 708 uint8_t m_num_raid_configs; 709 710 struct mptsas_slots *m_active; /* outstanding cmds */ 711 712 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 713 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 714 715 kmutex_t m_tx_waitq_mutex; 716 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 717 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 718 int m_tx_draining; /* TX queue draining flag */ 719 720 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 721 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 722 723 /* 724 * variables for helper threads (fan-out interrupts) 725 */ 726 mptsas_doneq_thread_list_t *m_doneq_thread_id; 727 uint32_t m_doneq_thread_n; 728 uint32_t m_doneq_thread_threshold; 729 uint32_t m_doneq_length_threshold; 730 uint32_t m_doneq_len; 731 kcondvar_t m_doneq_thread_cv; 732 kmutex_t m_doneq_mutex; 733 734 int m_ncmds; /* number of outstanding commands */ 735 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 736 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 737 738 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 739 740 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 741 742 ushort_t m_devid; /* device id of chip. */ 743 uchar_t m_revid; /* revision of chip. */ 744 uint16_t m_svid; /* subsystem Vendor ID of chip */ 745 uint16_t m_ssid; /* subsystem Device ID of chip */ 746 747 uchar_t m_sync_offset; /* default offset for this chip. */ 748 749 timeout_id_t m_quiesce_timeid; 750 751 ddi_dma_handle_t m_dma_req_frame_hdl; 752 ddi_acc_handle_t m_acc_req_frame_hdl; 753 ddi_dma_handle_t m_dma_reply_frame_hdl; 754 ddi_acc_handle_t m_acc_reply_frame_hdl; 755 ddi_dma_handle_t m_dma_free_queue_hdl; 756 ddi_acc_handle_t m_acc_free_queue_hdl; 757 ddi_dma_handle_t m_dma_post_queue_hdl; 758 ddi_acc_handle_t m_acc_post_queue_hdl; 759 760 /* 761 * list of reset notification requests 762 */ 763 struct scsi_reset_notify_entry *m_reset_notify_listf; 764 765 /* 766 * qfull handling 767 */ 768 timeout_id_t m_restart_cmd_timeid; 769 770 /* 771 * scsi reset delay per bus 772 */ 773 uint_t m_scsi_reset_delay; 774 775 int m_pm_idle_delay; 776 777 uchar_t m_polled_intr; /* intr was polled. */ 778 uchar_t m_suspended; /* true if driver is suspended */ 779 780 struct kmem_cache *m_kmem_cache; 781 struct kmem_cache *m_cache_frames; 782 783 /* 784 * hba options. 785 */ 786 uint_t m_options; 787 788 int m_in_callback; 789 790 int m_power_level; /* current power level */ 791 792 int m_busy; /* power management busy state */ 793 794 off_t m_pmcsr_offset; /* PMCSR offset */ 795 796 ddi_acc_handle_t m_config_handle; 797 798 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 799 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 800 ddi_device_acc_attr_t m_dev_acc_attr; 801 ddi_device_acc_attr_t m_reg_acc_attr; 802 803 /* 804 * request/reply variables 805 */ 806 caddr_t m_req_frame; 807 uint64_t m_req_frame_dma_addr; 808 caddr_t m_reply_frame; 809 uint64_t m_reply_frame_dma_addr; 810 caddr_t m_free_queue; 811 uint64_t m_free_queue_dma_addr; 812 caddr_t m_post_queue; 813 uint64_t m_post_queue_dma_addr; 814 815 m_replyh_arg_t *m_replyh_args; 816 817 uint16_t m_max_requests; 818 uint16_t m_req_frame_size; 819 820 /* 821 * Max frames per request reprted in IOC Facts 822 */ 823 uint8_t m_max_chain_depth; 824 /* 825 * Max frames per request which is used in reality. It's adjusted 826 * according DMA SG length attribute, and shall not exceed the 827 * m_max_chain_depth. 828 */ 829 uint8_t m_max_request_frames; 830 831 uint16_t m_free_queue_depth; 832 uint16_t m_post_queue_depth; 833 uint16_t m_max_replies; 834 uint32_t m_free_index; 835 uint32_t m_post_index; 836 uint8_t m_reply_frame_size; 837 uint32_t m_ioc_capabilities; 838 839 /* 840 * indicates if the firmware was upload by the driver 841 * at boot time 842 */ 843 ushort_t m_fwupload; 844 845 uint16_t m_productid; 846 847 /* 848 * per instance data structures for dma memory resources for 849 * MPI handshake protocol. only one handshake cmd can run at a time. 850 */ 851 ddi_dma_handle_t m_hshk_dma_hdl; 852 ddi_acc_handle_t m_hshk_acc_hdl; 853 caddr_t m_hshk_memp; 854 size_t m_hshk_dma_size; 855 856 /* Firmware version on the card at boot time */ 857 uint32_t m_fwversion; 858 859 /* MSI specific fields */ 860 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 861 int m_intr_type; /* What type of interrupt */ 862 int m_intr_cnt; /* # of intrs count returned */ 863 size_t m_intr_size; /* Size of intr array */ 864 uint_t m_intr_pri; /* Interrupt priority */ 865 int m_intr_cap; /* Interrupt capabilities */ 866 ddi_taskq_t *m_event_taskq; 867 868 /* SAS specific information */ 869 870 union { 871 uint64_t m_base_wwid; /* Base WWID */ 872 struct { 873 #ifdef _BIG_ENDIAN 874 uint32_t m_base_wwid_hi; 875 uint32_t m_base_wwid_lo; 876 #else 877 uint32_t m_base_wwid_lo; 878 uint32_t m_base_wwid_hi; 879 #endif 880 } sasaddr; 881 } un; 882 883 uint8_t m_num_phys; /* # of PHYs */ 884 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 885 uint8_t m_port_chng; /* initiator port changes */ 886 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 887 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 888 889 /* FMA Capabilities */ 890 int m_fm_capabilities; 891 ddi_taskq_t *m_dr_taskq; 892 int m_mpxio_enable; 893 uint8_t m_done_traverse_dev; 894 uint8_t m_done_traverse_smp; 895 int m_diag_action_in_progress; 896 uint16_t m_dev_handle; 897 uint16_t m_smp_devhdl; 898 899 /* 900 * Event recording 901 */ 902 uint8_t m_event_index; 903 uint32_t m_event_number; 904 uint32_t m_event_mask[4]; 905 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 906 907 /* 908 * FW diag Buffer List 909 */ 910 mptsas_fw_diagnostic_buffer_t 911 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 912 913 /* GEN3 support */ 914 uint8_t m_MPI25; 915 916 /* 917 * Event Replay flag (MUR support) 918 */ 919 uint8_t m_event_replay; 920 921 /* 922 * IR Capable flag 923 */ 924 uint8_t m_ir_capable; 925 926 /* 927 * Is HBA processing a diag reset? 928 */ 929 uint8_t m_in_reset; 930 931 /* 932 * per instance cmd data structures for task management cmds 933 */ 934 m_event_struct_t m_event_task_mgmt; /* must be last */ 935 /* ... scsi_pkt_size */ 936 } mptsas_t; 937 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 938 sizeof (struct scsi_pkt) + scsi_pkt_size()) 939 /* 940 * Only one of below two conditions is satisfied, we 941 * think the target is associated to the iport and 942 * allow call into mptsas_probe_lun(). 943 * 1. physicalsport == physport 944 * 2. (phymask & (1 << physport)) == 0 945 * The condition #2 is because LSI uses lowest PHY 946 * number as the value of physical port when auto port 947 * configuration. 948 */ 949 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 950 ((physicalport == physport) || (dynamicport && (phymask & \ 951 (1 << physport)))) 952 953 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 954 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 955 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 956 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 957 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 958 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 959 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 960 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 961 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 962 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 963 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 964 965 /* 966 * These should eventually migrate into the mpt header files 967 * that may become the /kernel/misc/mpt module... 968 */ 969 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 970 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 971 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 972 mptsas_put_msg_Function(hdl, mp, Function); \ 973 mptsas_put_msg_Lun(hdl, mp, Lun) 974 975 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 976 ddi_put16(hdl, &(mp)->DevHandle, (val)) 977 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 978 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 979 #define mptsas_put_msg_Function(hdl, mp, val) \ 980 ddi_put8(hdl, &(mp)->Function, (val)) 981 #define mptsas_put_msg_Lun(hdl, mp, val) \ 982 ddi_put8(hdl, &(mp)->LUN[1], (val)) 983 984 #define mptsas_get_msg_Function(hdl, mp) \ 985 ddi_get8(hdl, &(mp)->Function) 986 987 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 988 ddi_get8(hdl, &(mp)->MsgFlags) 989 990 #define MPTSAS_ENABLE_DRWE(hdl) \ 991 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 992 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 993 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 994 MPI2_WRSEQ_1ST_KEY_VALUE); \ 995 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 996 MPI2_WRSEQ_2ND_KEY_VALUE); \ 997 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 998 MPI2_WRSEQ_3RD_KEY_VALUE); \ 999 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1000 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1001 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1002 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1003 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1004 MPI2_WRSEQ_6TH_KEY_VALUE); 1005 1006 /* 1007 * m_options flags 1008 */ 1009 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1010 1011 /* 1012 * m_softstate flags 1013 */ 1014 #define MPTSAS_SS_DRAINING 0x02 1015 #define MPTSAS_SS_QUIESCED 0x04 1016 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1017 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1018 1019 /* 1020 * regspec defines. 1021 */ 1022 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1023 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1024 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1025 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1026 1027 /* 1028 * Handy constants 1029 */ 1030 #define FALSE 0 1031 #define TRUE 1 1032 #define UNDEFINED -1 1033 #define FAILED -2 1034 1035 /* 1036 * power management. 1037 */ 1038 #define MPTSAS_POWER_ON(mpt) { \ 1039 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1040 PCI_PMCSR_D0); \ 1041 delay(drv_usectohz(10000)); \ 1042 (void) pci_restore_config_regs(mpt->m_dip); \ 1043 mptsas_setup_cmd_reg(mpt); \ 1044 } 1045 1046 #define MPTSAS_POWER_OFF(mpt) { \ 1047 (void) pci_save_config_regs(mpt->m_dip); \ 1048 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1049 PCI_PMCSR_D3HOT); \ 1050 mpt->m_power_level = PM_LEVEL_D3; \ 1051 } 1052 1053 /* 1054 * inq_dtype: 1055 * Bits 5 through 7 are the Peripheral Device Qualifier 1056 * 001b: device not connected to the LUN 1057 * Bits 0 through 4 are the Peripheral Device Type 1058 * 1fh: Unknown or no device type 1059 * 1060 * Although the inquiry may return success, the following value 1061 * means no valid LUN connected. 1062 */ 1063 #define MPTSAS_VALID_LUN(sd_inq) \ 1064 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1065 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1066 1067 /* 1068 * Default is to have 10 retries on receiving QFULL status and 1069 * each retry to be after 100 ms. 1070 */ 1071 #define QFULL_RETRIES 10 1072 #define QFULL_RETRY_INTERVAL 100 1073 1074 /* 1075 * Handy macros 1076 */ 1077 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1078 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1079 1080 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1081 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1082 1083 /* 1084 * poll time for mptsas_pollret() and mptsas_wait_intr() 1085 */ 1086 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1087 1088 /* 1089 * default time for mptsas_do_passthru 1090 */ 1091 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1092 1093 /* 1094 * macro to return the effective address of a given per-target field 1095 */ 1096 #define EFF_ADDR(start, offset) ((start) + (offset)) 1097 1098 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1099 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1100 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1101 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1102 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1103 1104 1105 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1106 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1107 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1108 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1109 1110 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1111 1112 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1113 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1114 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1115 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1116 1117 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1118 &(mpt)->m_reg->HostInterruptStatus)) 1119 1120 #define MPTSAS_SET_SIGP(P) \ 1121 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1122 1123 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1124 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1125 1126 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1127 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1128 1129 1130 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1131 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1132 req_desc_lo);\ 1133 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1134 req_desc_hi); 1135 1136 #define INTPENDING(mpt) \ 1137 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1138 1139 /* 1140 * Mask all interrupts to disable 1141 */ 1142 #define MPTSAS_DISABLE_INTR(mpt) \ 1143 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1144 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1145 1146 /* 1147 * Mask Doorbell and Reset interrupts to enable reply desc int. 1148 */ 1149 #define MPTSAS_ENABLE_INTR(mpt) \ 1150 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1151 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1152 1153 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1154 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1155 1156 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1157 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1158 1159 #define ClrSetBits32(hdl, reg, clr, set) \ 1160 ddi_put32(hdl, (reg), \ 1161 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1162 1163 #define ClrSetBits(reg, clr, set) \ 1164 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1165 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1166 1167 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1168 if ((cmdp = mpt->m_waitq) != NULL) { \ 1169 /* If the queue is now empty fix the tail pointer */ \ 1170 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1171 mpt->m_waitqtail = &mpt->m_waitq; \ 1172 cmdp->cmd_linkp = NULL; \ 1173 cmdp->cmd_queued = FALSE; \ 1174 } 1175 1176 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1177 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1178 /* If the queue is now empty fix the tail pointer */ \ 1179 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1180 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1181 cmdp->cmd_linkp = NULL; \ 1182 cmdp->cmd_queued = FALSE; \ 1183 } 1184 1185 /* 1186 * defaults for the global properties 1187 */ 1188 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1189 #define DEFAULT_TAG_AGE_LIMIT 2 1190 #define DEFAULT_WD_TICK 1 1191 1192 /* 1193 * invalid hostid. 1194 */ 1195 #define MPTSAS_INVALID_HOSTID -1 1196 1197 /* 1198 * Get/Set hostid from SCSI port configuration page 1199 */ 1200 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1201 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1202 1203 /* 1204 * Config space. 1205 */ 1206 #define MPTSAS_LATENCY_TIMER 0x40 1207 1208 /* 1209 * Offset to firmware version 1210 */ 1211 #define MPTSAS_FW_VERSION_OFFSET 9 1212 1213 /* 1214 * Offset and masks to get at the ProductId field 1215 */ 1216 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1217 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1218 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1219 1220 /* 1221 * Subsystem ID for HBAs. 1222 */ 1223 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1224 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1225 1226 /* 1227 * reset delay tick 1228 */ 1229 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1230 1231 /* 1232 * Ioc reset return values 1233 */ 1234 #define MPTSAS_RESET_FAIL -1 1235 #define MPTSAS_NO_RESET 0 1236 #define MPTSAS_SUCCESS_HARDRESET 1 1237 #define MPTSAS_SUCCESS_MUR 2 1238 1239 /* 1240 * throttle support. 1241 */ 1242 #define MAX_THROTTLE 32 1243 #define HOLD_THROTTLE 0 1244 #define DRAIN_THROTTLE -1 1245 #define QFULL_THROTTLE -2 1246 1247 /* 1248 * Passthrough/config request flags 1249 */ 1250 #define MPTSAS_DATA_ALLOCATED 0x0001 1251 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1252 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1253 #define MPTSAS_ADDRESS_REPLY 0x0008 1254 #define MPTSAS_CMD_TIMEOUT 0x0010 1255 1256 /* 1257 * response code tlr flag 1258 */ 1259 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1260 1261 /* 1262 * System Events 1263 */ 1264 #ifndef DDI_VENDOR_LSI 1265 #define DDI_VENDOR_LSI "LSI" 1266 #endif /* DDI_VENDOR_LSI */ 1267 1268 /* 1269 * Shared functions 1270 */ 1271 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1272 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1273 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1274 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1275 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1276 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1277 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1278 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1279 uint8_t pageversion, uint8_t pagelength, uint32_t 1280 SGEflagslength, uint32_t SGEaddress32); 1281 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1282 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1283 uint8_t pageversion, uint16_t extpagelength, 1284 uint32_t SGEflagslength, uint32_t SGEaddress32); 1285 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1286 uint8_t type, int mode); 1287 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1288 uint8_t type, int mode); 1289 int mptsas_download_firmware(); 1290 int mptsas_can_download_firmware(); 1291 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1292 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1293 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1294 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1295 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1296 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1297 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1298 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1299 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1300 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1301 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1302 1303 /* 1304 * impl functions 1305 */ 1306 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1307 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1308 int mptsas_ioc_reset(mptsas_t *mpt, int); 1309 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1310 ddi_acc_handle_t accessp); 1311 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1312 ddi_acc_handle_t accessp); 1313 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1314 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1315 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1316 uint32_t SGEaddress32); 1317 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1318 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1319 uint8_t pageversion, uint16_t extpagelength, 1320 uint32_t SGEflagslength, uint32_t SGEaddress32); 1321 1322 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1323 struct scsi_pkt **pkt); 1324 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1325 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1326 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1327 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1328 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1329 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1330 1331 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1332 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1333 int mode); 1334 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1335 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1336 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1337 int mptsas_restart_ioc(mptsas_t *mpt); 1338 void mptsas_update_driver_data(struct mptsas *mpt); 1339 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1340 1341 /* 1342 * init functions 1343 */ 1344 int mptsas_ioc_get_facts(mptsas_t *mpt); 1345 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1346 int mptsas_ioc_enable_port(mptsas_t *mpt); 1347 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1348 int mptsas_ioc_init(mptsas_t *mpt); 1349 1350 /* 1351 * configuration pages operation 1352 */ 1353 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1354 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1355 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1356 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags); 1357 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1358 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1359 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1360 mptsas_smp_t *info); 1361 int mptsas_set_ioc_params(mptsas_t *mpt); 1362 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1363 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1364 uint64_t *sas_wwn, uint8_t *portwidth); 1365 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1366 int 1367 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1368 smhba_info_t *info); 1369 int 1370 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1371 smhba_info_t *info); 1372 int 1373 mptsas_get_manufacture_page0(mptsas_t *mpt); 1374 void 1375 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1376 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1377 int mptsas_smhba_phy_init(mptsas_t *mpt); 1378 /* 1379 * RAID functions 1380 */ 1381 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1382 int mptsas_get_raid_info(mptsas_t *mpt); 1383 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1384 uint8_t physdisknum); 1385 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1386 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1387 1388 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1389 /* 1390 * debugging. 1391 */ 1392 #if defined(MPTSAS_DEBUG) 1393 1394 void mptsas_printf(char *fmt, ...); 1395 1396 #define MPTSAS_DBGPR(m, args) \ 1397 if (mptsas_debug_flags & (m)) \ 1398 mptsas_printf args 1399 #else /* ! defined(MPTSAS_DEBUG) */ 1400 #define MPTSAS_DBGPR(m, args) 1401 #endif /* defined(MPTSAS_DEBUG) */ 1402 1403 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1404 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1405 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1406 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1407 1408 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1409 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1410 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1411 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1412 1413 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1414 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1415 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1416 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1417 1418 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1419 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1420 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1421 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */ 1422 1423 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1424 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1425 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1426 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1427 1428 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1429 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1430 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1431 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1432 1433 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1434 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1435 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1436 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1437 1438 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1439 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1440 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1441 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1442 1443 /* 1444 * auto request sense 1445 */ 1446 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1447 (pkt)->pkt_flags = (flag), \ 1448 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1449 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1450 (pkt)->pkt_address.a_lun 1451 1452 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1453 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1454 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1455 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1456 1457 1458 #ifdef __cplusplus 1459 } 1460 #endif 1461 1462 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1463