1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved. 26 */ 27 28 /* 29 * Copyright (c) 2000 to 2010, LSI Corporation. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms of all code within 33 * this file that is exclusively owned by LSI, with or without 34 * modification, is permitted provided that, in addition to the CDDL 1.0 35 * License requirements, the following conditions are met: 36 * 37 * Neither the name of the author nor the names of its contributors may be 38 * used to endorse or promote products derived from this software without 39 * specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 52 * DAMAGE. 53 */ 54 55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 57 58 #include <sys/byteorder.h> 59 #include <sys/isa_defs.h> 60 #include <sys/sunmdi.h> 61 #include <sys/mdi_impldefs.h> 62 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 63 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 64 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 65 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 66 67 #ifdef __cplusplus 68 extern "C" { 69 #endif 70 71 /* 72 * Compile options 73 */ 74 #ifdef DEBUG 75 #define MPTSAS_DEBUG /* turn on debugging code */ 76 #endif /* DEBUG */ 77 78 #define MPTSAS_INITIAL_SOFT_SPACE 4 79 80 #define MAX_MPI_PORTS 16 81 82 /* 83 * Note below macro definition and data type definition 84 * are used for phy mask handling, it should be changed 85 * simultaneously. 86 */ 87 #define MPTSAS_MAX_PHYS 16 88 typedef uint16_t mptsas_phymask_t; 89 90 #define MPTSAS_INVALID_DEVHDL 0xffff 91 #define MPTSAS_SATA_GUID "sata-guid" 92 93 /* 94 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 95 * targets. There's no need to go overboard here, as the ordinary paths for 96 * I/O do not normally require hashed target lookups. These should be good 97 * enough and then some for any fabric within the hardware's capabilities. 98 */ 99 #define MPTSAS_SMP_BUCKET_COUNT 23 100 #define MPTSAS_TARGET_BUCKET_COUNT 97 101 102 /* 103 * MPT HW defines 104 */ 105 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 106 #define MPTSAS_MAX_DISKS_IN_VOL 10 107 #define MPTSAS_MAX_HOTSPARES 2 108 #define MPTSAS_MAX_RAIDVOLS 2 109 #define MPTSAS_MAX_RAIDCONFIGS 5 110 111 /* 112 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 113 * plus two means the prefix 'w' and end of the string '\0'. 114 */ 115 #define MPTSAS_WWN_STRLEN (16 + 2) 116 #define MPTSAS_MAX_GUID_LEN 64 117 118 /* 119 * DMA routine flags 120 */ 121 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 122 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 123 #define MPTSAS_DMA_HANDLE_BOUND 0x8 124 125 /* 126 * If the HBA supports DMA or bus-mastering, you may have your own 127 * scatter-gather list for physically non-contiguous memory in one 128 * I/O operation; if so, there's probably a size for that list. 129 * It must be placed in the ddi_dma_lim_t structure, so that the system 130 * DMA-support routines can use it to break up the I/O request, so we 131 * define it here. 132 */ 133 #if defined(__sparc) 134 #define MPTSAS_MAX_DMA_SEGS 1 135 #define MPTSAS_MAX_CMD_SEGS 1 136 #else 137 #define MPTSAS_MAX_DMA_SEGS 256 138 #define MPTSAS_MAX_CMD_SEGS 257 139 #endif 140 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 141 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 142 143 /* 144 * Caculating how many 64-bit DMA simple elements can be stored in the first 145 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 146 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 147 * size. 148 */ 149 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 150 ((mpt->m_req_frame_size - \ 151 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 152 153 /* 154 * Scatter-gather list structure defined by HBA hardware 155 */ 156 typedef struct NcrTableIndirect { /* Table Indirect entries */ 157 uint32_t count; /* 24 bit count */ 158 union { 159 uint32_t address32; /* 32 bit address */ 160 struct { 161 uint32_t Low; 162 uint32_t High; 163 } address64; /* 64 bit address */ 164 } addr; 165 } mptti_t; 166 167 /* 168 * preferred pkt_private length in 64-bit quantities 169 */ 170 #ifdef _LP64 171 #define PKT_PRIV_SIZE 2 172 #define PKT_PRIV_LEN 16 /* in bytes */ 173 #else /* _ILP32 */ 174 #define PKT_PRIV_SIZE 1 175 #define PKT_PRIV_LEN 8 /* in bytes */ 176 #endif 177 178 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 179 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 180 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 181 182 /* 183 * get offset of item in structure 184 */ 185 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 186 187 /* 188 * WWID provided by LSI firmware is generated by firmware but the WWID is not 189 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 190 * address. According LSI's confirmation, the top nibble of RAID WWID is 191 * meanless, so the consensus between Solaris and OBP is to replace top nibble 192 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 193 * format unit address. 194 */ 195 #define MPTSAS_RAID_WWID(wwid) \ 196 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 197 198 typedef struct mptsas_target_addr { 199 uint64_t mta_wwn; 200 mptsas_phymask_t mta_phymask; 201 } mptsas_target_addr_t; 202 203 typedef struct mptsas_target { 204 mptsas_target_addr_t m_addr; 205 refhash_link_t m_link; 206 uint8_t m_dr_flag; 207 uint16_t m_devhdl; 208 uint32_t m_deviceinfo; 209 uint8_t m_phynum; 210 uint32_t m_dups; 211 int32_t m_timeout; 212 int32_t m_timebase; 213 int32_t m_t_throttle; 214 int32_t m_t_ncmds; 215 int32_t m_reset_delay; 216 int32_t m_t_nwait; 217 218 uint16_t m_qfull_retry_interval; 219 uint8_t m_qfull_retries; 220 uint16_t m_enclosure; 221 uint16_t m_slot_num; 222 uint32_t m_tgt_unconfigured; 223 uint8_t m_led_status; 224 225 } mptsas_target_t; 226 227 /* 228 * If you change this structure, be sure that mptsas_smp_target_copy() 229 * does the right thing. 230 */ 231 typedef struct mptsas_smp { 232 mptsas_target_addr_t m_addr; 233 refhash_link_t m_link; 234 uint16_t m_devhdl; 235 uint32_t m_deviceinfo; 236 uint16_t m_pdevhdl; 237 uint32_t m_pdevinfo; 238 } mptsas_smp_t; 239 240 typedef struct mptsas_cache_frames { 241 ddi_dma_handle_t m_dma_hdl; 242 ddi_acc_handle_t m_acc_hdl; 243 caddr_t m_frames_addr; 244 uint32_t m_phys_addr; 245 } mptsas_cache_frames_t; 246 247 typedef struct mptsas_cmd { 248 uint_t cmd_flags; /* flags from scsi_init_pkt */ 249 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 250 ddi_dma_cookie_t cmd_cookie; 251 uint_t cmd_cookiec; 252 uint_t cmd_winindex; 253 uint_t cmd_nwin; 254 uint_t cmd_cur_cookie; 255 off_t cmd_dma_offset; 256 size_t cmd_dma_len; 257 uint32_t cmd_totaldmacount; 258 259 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 260 ddi_dma_cookie_t cmd_arqcookie; 261 struct buf *cmd_arq_buf; 262 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 263 ddi_dma_cookie_t cmd_ext_arqcookie; 264 struct buf *cmd_ext_arq_buf; 265 266 int cmd_pkt_flags; 267 268 /* timer for command in active slot */ 269 int cmd_active_timeout; 270 271 struct scsi_pkt *cmd_pkt; 272 struct scsi_arq_status cmd_scb; 273 uchar_t cmd_cdblen; /* length of cdb */ 274 uchar_t cmd_rqslen; /* len of requested rqsense */ 275 uchar_t cmd_privlen; 276 uint_t cmd_scblen; 277 uint32_t cmd_dmacount; 278 uint64_t cmd_dma_addr; 279 uchar_t cmd_age; 280 ushort_t cmd_qfull_retries; 281 uchar_t cmd_queued; /* true if queued */ 282 struct mptsas_cmd *cmd_linkp; 283 mptti_t *cmd_sg; /* Scatter/Gather structure */ 284 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 285 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 286 uint32_t cmd_slot; 287 uint32_t ioc_cmd_slot; 288 289 mptsas_cache_frames_t *cmd_extra_frames; 290 291 uint32_t cmd_rfm; 292 mptsas_target_t *cmd_tgt_addr; 293 } mptsas_cmd_t; 294 295 /* 296 * These are the defined cmd_flags for this structure. 297 */ 298 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 299 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 300 #define CFLAG_FINISHED 0x000004 /* command completed */ 301 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 302 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 303 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 304 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 305 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 306 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 307 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 308 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 309 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 310 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 311 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 312 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 313 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 314 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 315 #define CFLAG_FREE 0x010000 /* packet is on free list */ 316 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 317 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 318 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 319 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 320 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 321 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 322 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 323 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 324 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 325 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 326 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 327 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 328 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 329 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 330 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 331 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 343 344 #define MPTSAS_HASH_ARRAY_SIZE 16 345 /* 346 * hash table definition 347 */ 348 349 #define MPTSAS_HASH_FIRST 0xffff 350 #define MPTSAS_HASH_NEXT 0x0000 351 352 typedef struct mptsas_dma_alloc_state 353 { 354 ddi_dma_handle_t handle; 355 caddr_t memp; 356 size_t size; 357 ddi_acc_handle_t accessp; 358 ddi_dma_cookie_t cookie; 359 } mptsas_dma_alloc_state_t; 360 361 /* 362 * passthrough request structure 363 */ 364 typedef struct mptsas_pt_request { 365 uint8_t *request; 366 uint32_t request_size; 367 uint32_t data_size; 368 uint32_t dataout_size; 369 uint32_t direction; 370 ddi_dma_cookie_t data_cookie; 371 ddi_dma_cookie_t dataout_cookie; 372 } mptsas_pt_request_t; 373 374 /* 375 * config page request structure 376 */ 377 typedef struct mptsas_config_request { 378 uint32_t page_address; 379 uint8_t action; 380 uint8_t page_type; 381 uint8_t page_number; 382 uint8_t page_length; 383 uint8_t page_version; 384 uint8_t ext_page_type; 385 uint16_t ext_page_length; 386 } mptsas_config_request_t; 387 388 typedef struct mptsas_fw_diagnostic_buffer { 389 mptsas_dma_alloc_state_t buffer_data; 390 uint8_t extended_type; 391 uint8_t buffer_type; 392 uint8_t force_release; 393 uint32_t product_specific[23]; 394 uint8_t immediate; 395 uint8_t enabled; 396 uint8_t valid_data; 397 uint8_t owned_by_firmware; 398 uint32_t unique_id; 399 } mptsas_fw_diagnostic_buffer_t; 400 401 /* 402 * FW diag request structure 403 */ 404 typedef struct mptsas_diag_request { 405 mptsas_fw_diagnostic_buffer_t *pBuffer; 406 uint8_t function; 407 } mptsas_diag_request_t; 408 409 typedef struct mptsas_hash_node { 410 void *data; 411 struct mptsas_hash_node *next; 412 } mptsas_hash_node_t; 413 414 typedef struct mptsas_hash_table { 415 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 416 /* 417 * last position in traverse 418 */ 419 struct mptsas_hash_node *cur; 420 uint16_t line; 421 422 } mptsas_hash_table_t; 423 424 /* 425 * RAID volume information 426 */ 427 typedef struct mptsas_raidvol { 428 ushort_t m_israid; 429 uint16_t m_raidhandle; 430 uint64_t m_raidwwid; 431 uint8_t m_state; 432 uint32_t m_statusflags; 433 uint32_t m_settings; 434 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 435 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 436 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 437 uint64_t m_raidsize; 438 int m_raidlevel; 439 int m_ndisks; 440 mptsas_target_t *m_raidtgt; 441 } mptsas_raidvol_t; 442 443 /* 444 * RAID configurations 445 */ 446 typedef struct mptsas_raidconfig { 447 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 448 uint16_t m_physdisk_devhdl[ 449 MPTSAS_MAX_DISKS_IN_CONFIG]; 450 uint8_t m_native; 451 } m_raidconfig_t; 452 453 /* 454 * Track outstanding commands. The index into the m_slot array is the SMID 455 * (system message ID) of the outstanding command. SMID 0 is reserved by the 456 * software/firmware protocol and is never used for any command we generate; 457 * as such, the assertion m_slot[0] == NULL is universally true. The last 458 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 459 * task management commands. No normal SCSI or ATA command will ever occupy 460 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 461 * time that a consistent view of the target array is obtainable. 462 * 463 * As such, m_n_normal is the maximum number of slots available to ordinary 464 * commands, and the relationship: 465 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 466 * always holds after initialisation. 467 */ 468 typedef struct mptsas_slots { 469 size_t m_size; /* size of struct, bytes */ 470 uint_t m_n_normal; /* see above */ 471 uint_t m_rotor; /* next slot idx to consider */ 472 mptsas_cmd_t *m_slot[1]; 473 } mptsas_slots_t; 474 475 /* 476 * Structure to hold command and packets for event ack 477 * and task management commands. 478 */ 479 typedef struct m_event_struct { 480 struct mptsas_cmd m_event_cmd; 481 struct m_event_struct *m_event_linkp; 482 /* 483 * event member record the failure event and eventcntx 484 * event member would be used in send ack pending process 485 */ 486 uint32_t m_event; 487 uint32_t m_eventcntx; 488 uint_t in_use; 489 struct scsi_pkt m_event_pkt; /* must be last */ 490 /* ... scsi_pkt_size() */ 491 } m_event_struct_t; 492 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 493 sizeof (struct scsi_pkt) + scsi_pkt_size()) 494 495 #define MAX_IOC_COMMANDS 8 496 497 /* 498 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 499 * A new event ack command requests mptsas_cmd and scsi_pkt structures 500 * from this pool, and returns it back when done. 501 */ 502 503 typedef struct m_replyh_arg { 504 void *mpt; 505 uint32_t rfm; 506 } m_replyh_arg_t; 507 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 508 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 509 510 /* 511 * Flags for DR handler topology change 512 */ 513 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 514 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 515 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 516 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 517 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 518 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 519 520 typedef struct mptsas_topo_change_list { 521 void *mpt; 522 uint_t event; 523 union { 524 uint8_t physport; 525 mptsas_phymask_t phymask; 526 } un; 527 uint16_t devhdl; 528 void *object; 529 uint8_t flags; 530 struct mptsas_topo_change_list *next; 531 } mptsas_topo_change_list_t; 532 533 534 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 535 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 536 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 537 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 538 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 539 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 540 541 /* 542 * Status types when calling mptsas_get_target_device_info 543 */ 544 #define DEV_INFO_SUCCESS 0x0 545 #define DEV_INFO_FAIL_PAGE0 0x1 546 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 547 #define DEV_INFO_PHYS_DISK 0x3 548 #define DEV_INFO_FAIL_ALLOC 0x4 549 550 /* 551 * mpt hotplug event defines 552 */ 553 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 554 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 555 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 556 557 /* 558 * SMP target hotplug events 559 */ 560 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 561 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 562 #define MPTSAS_DR_EVENT_MASK 0x3F 563 564 /* 565 * mpt hotplug status definition for m_dr_flag 566 */ 567 568 /* 569 * MPTSAS_DR_INACTIVE 570 * 571 * The target is in a normal operating state. 572 * No dynamic reconfiguration operation is in progress. 573 */ 574 #define MPTSAS_DR_INACTIVE 0x0 575 /* 576 * MPTSAS_DR_INTRANSITION 577 * 578 * The target is in a transition mode since 579 * hotplug event happens and offline procedure has not 580 * been finished 581 */ 582 #define MPTSAS_DR_INTRANSITION 0x1 583 584 typedef struct mptsas_tgt_private { 585 int t_lun; 586 struct mptsas_target *t_private; 587 } mptsas_tgt_private_t; 588 589 /* 590 * The following defines are used in mptsas_set_init_mode to track the current 591 * state as we progress through reprogramming the HBA from target mode into 592 * initiator mode. 593 */ 594 595 #define IOUC_READ_PAGE0 0x00000100 596 #define IOUC_READ_PAGE1 0x00000200 597 #define IOUC_WRITE_PAGE1 0x00000400 598 #define IOUC_DONE 0x00000800 599 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 600 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 601 602 /* 603 * Last allocated slot is used for TM requests. Since only m_max_requests 604 * frames are allocated, the last SMID will be m_max_requests - 1. 605 */ 606 #define MPTSAS_SLOTS_SIZE(mpt) \ 607 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 608 mpt->m_max_requests)) 609 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 610 611 /* 612 * Macro for phy_flags 613 */ 614 615 typedef struct smhba_info { 616 kmutex_t phy_mutex; 617 uint8_t phy_id; 618 uint64_t sas_addr; 619 char path[8]; 620 uint16_t owner_devhdl; 621 uint16_t attached_devhdl; 622 uint8_t attached_phy_identify; 623 uint32_t attached_phy_info; 624 uint8_t programmed_link_rate; 625 uint8_t hw_link_rate; 626 uint8_t change_count; 627 uint32_t phy_info; 628 uint8_t negotiated_link_rate; 629 uint8_t port_num; 630 kstat_t *phy_stats; 631 uint32_t invalid_dword_count; 632 uint32_t running_disparity_error_count; 633 uint32_t loss_of_dword_sync_count; 634 uint32_t phy_reset_problem_count; 635 void *mpt; 636 } smhba_info_t; 637 638 typedef struct mptsas_phy_info { 639 uint8_t port_num; 640 uint8_t port_flags; 641 uint16_t ctrl_devhdl; 642 uint32_t phy_device_type; 643 uint16_t attached_devhdl; 644 mptsas_phymask_t phy_mask; 645 smhba_info_t smhba_info; 646 } mptsas_phy_info_t; 647 648 649 typedef struct mptsas_doneq_thread_arg { 650 void *mpt; 651 uint64_t t; 652 } mptsas_doneq_thread_arg_t; 653 654 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 655 typedef struct mptsas_doneq_thread_list { 656 mptsas_cmd_t *doneq; 657 mptsas_cmd_t **donetail; 658 kthread_t *threadp; 659 kcondvar_t cv; 660 ushort_t reserv1; 661 uint32_t reserv2; 662 kmutex_t mutex; 663 uint32_t flag; 664 uint32_t len; 665 mptsas_doneq_thread_arg_t arg; 666 } mptsas_doneq_thread_list_t; 667 668 typedef struct mptsas { 669 int m_instance; 670 671 struct mptsas *m_next; 672 673 scsi_hba_tran_t *m_tran; 674 smp_hba_tran_t *m_smptran; 675 kmutex_t m_mutex; 676 kmutex_t m_passthru_mutex; 677 kcondvar_t m_cv; 678 kcondvar_t m_passthru_cv; 679 kcondvar_t m_fw_cv; 680 kcondvar_t m_config_cv; 681 kcondvar_t m_fw_diag_cv; 682 dev_info_t *m_dip; 683 684 /* 685 * soft state flags 686 */ 687 uint_t m_softstate; 688 689 refhash_t *m_targets; 690 refhash_t *m_smp_targets; 691 692 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 693 uint8_t m_num_raid_configs; 694 695 struct mptsas_slots *m_active; /* outstanding cmds */ 696 697 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 698 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 699 700 kmutex_t m_tx_waitq_mutex; 701 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 702 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 703 int m_tx_draining; /* TX queue draining flag */ 704 705 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 706 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 707 708 /* 709 * variables for helper threads (fan-out interrupts) 710 */ 711 mptsas_doneq_thread_list_t *m_doneq_thread_id; 712 uint32_t m_doneq_thread_n; 713 uint32_t m_doneq_thread_threshold; 714 uint32_t m_doneq_length_threshold; 715 uint32_t m_doneq_len; 716 kcondvar_t m_doneq_thread_cv; 717 kmutex_t m_doneq_mutex; 718 719 int m_ncmds; /* number of outstanding commands */ 720 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 721 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 722 723 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 724 725 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 726 727 ushort_t m_devid; /* device id of chip. */ 728 uchar_t m_revid; /* revision of chip. */ 729 uint16_t m_svid; /* subsystem Vendor ID of chip */ 730 uint16_t m_ssid; /* subsystem Device ID of chip */ 731 732 uchar_t m_sync_offset; /* default offset for this chip. */ 733 734 timeout_id_t m_quiesce_timeid; 735 736 ddi_dma_handle_t m_dma_req_frame_hdl; 737 ddi_acc_handle_t m_acc_req_frame_hdl; 738 ddi_dma_handle_t m_dma_reply_frame_hdl; 739 ddi_acc_handle_t m_acc_reply_frame_hdl; 740 ddi_dma_handle_t m_dma_free_queue_hdl; 741 ddi_acc_handle_t m_acc_free_queue_hdl; 742 ddi_dma_handle_t m_dma_post_queue_hdl; 743 ddi_acc_handle_t m_acc_post_queue_hdl; 744 745 /* 746 * list of reset notification requests 747 */ 748 struct scsi_reset_notify_entry *m_reset_notify_listf; 749 750 /* 751 * qfull handling 752 */ 753 timeout_id_t m_restart_cmd_timeid; 754 755 /* 756 * scsi reset delay per bus 757 */ 758 uint_t m_scsi_reset_delay; 759 760 int m_pm_idle_delay; 761 762 uchar_t m_polled_intr; /* intr was polled. */ 763 uchar_t m_suspended; /* true if driver is suspended */ 764 765 struct kmem_cache *m_kmem_cache; 766 struct kmem_cache *m_cache_frames; 767 768 /* 769 * hba options. 770 */ 771 uint_t m_options; 772 773 int m_in_callback; 774 775 int m_power_level; /* current power level */ 776 777 int m_busy; /* power management busy state */ 778 779 off_t m_pmcsr_offset; /* PMCSR offset */ 780 781 ddi_acc_handle_t m_config_handle; 782 783 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 784 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 785 ddi_device_acc_attr_t m_dev_acc_attr; 786 ddi_device_acc_attr_t m_reg_acc_attr; 787 788 /* 789 * request/reply variables 790 */ 791 caddr_t m_req_frame; 792 uint64_t m_req_frame_dma_addr; 793 caddr_t m_reply_frame; 794 uint64_t m_reply_frame_dma_addr; 795 caddr_t m_free_queue; 796 uint64_t m_free_queue_dma_addr; 797 caddr_t m_post_queue; 798 uint64_t m_post_queue_dma_addr; 799 800 m_replyh_arg_t *m_replyh_args; 801 802 uint16_t m_max_requests; 803 uint16_t m_req_frame_size; 804 805 /* 806 * Max frames per request reprted in IOC Facts 807 */ 808 uint8_t m_max_chain_depth; 809 /* 810 * Max frames per request which is used in reality. It's adjusted 811 * according DMA SG length attribute, and shall not exceed the 812 * m_max_chain_depth. 813 */ 814 uint8_t m_max_request_frames; 815 816 uint16_t m_free_queue_depth; 817 uint16_t m_post_queue_depth; 818 uint16_t m_max_replies; 819 uint32_t m_free_index; 820 uint32_t m_post_index; 821 uint8_t m_reply_frame_size; 822 uint32_t m_ioc_capabilities; 823 824 /* 825 * indicates if the firmware was upload by the driver 826 * at boot time 827 */ 828 ushort_t m_fwupload; 829 830 uint16_t m_productid; 831 832 /* 833 * per instance data structures for dma memory resources for 834 * MPI handshake protocol. only one handshake cmd can run at a time. 835 */ 836 ddi_dma_handle_t m_hshk_dma_hdl; 837 ddi_acc_handle_t m_hshk_acc_hdl; 838 caddr_t m_hshk_memp; 839 size_t m_hshk_dma_size; 840 841 /* Firmware version on the card at boot time */ 842 uint32_t m_fwversion; 843 844 /* MSI specific fields */ 845 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 846 int m_intr_type; /* What type of interrupt */ 847 int m_intr_cnt; /* # of intrs count returned */ 848 size_t m_intr_size; /* Size of intr array */ 849 uint_t m_intr_pri; /* Interrupt priority */ 850 int m_intr_cap; /* Interrupt capabilities */ 851 ddi_taskq_t *m_event_taskq; 852 853 /* SAS specific information */ 854 855 union { 856 uint64_t m_base_wwid; /* Base WWID */ 857 struct { 858 #ifdef _BIG_ENDIAN 859 uint32_t m_base_wwid_hi; 860 uint32_t m_base_wwid_lo; 861 #else 862 uint32_t m_base_wwid_lo; 863 uint32_t m_base_wwid_hi; 864 #endif 865 } sasaddr; 866 } un; 867 868 uint8_t m_num_phys; /* # of PHYs */ 869 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 870 uint8_t m_port_chng; /* initiator port changes */ 871 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 872 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 873 874 /* FMA Capabilities */ 875 int m_fm_capabilities; 876 ddi_taskq_t *m_dr_taskq; 877 int m_mpxio_enable; 878 uint8_t m_done_traverse_dev; 879 uint8_t m_done_traverse_smp; 880 int m_diag_action_in_progress; 881 uint16_t m_dev_handle; 882 uint16_t m_smp_devhdl; 883 884 /* 885 * Event recording 886 */ 887 uint8_t m_event_index; 888 uint32_t m_event_number; 889 uint32_t m_event_mask[4]; 890 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 891 892 /* 893 * FW diag Buffer List 894 */ 895 mptsas_fw_diagnostic_buffer_t 896 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 897 898 /* 899 * Event Replay flag (MUR support) 900 */ 901 uint8_t m_event_replay; 902 903 /* 904 * IR Capable flag 905 */ 906 uint8_t m_ir_capable; 907 908 /* 909 * Is HBA processing a diag reset? 910 */ 911 uint8_t m_in_reset; 912 913 /* 914 * per instance cmd data structures for task management cmds 915 */ 916 m_event_struct_t m_event_task_mgmt; /* must be last */ 917 /* ... scsi_pkt_size */ 918 } mptsas_t; 919 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 920 sizeof (struct scsi_pkt) + scsi_pkt_size()) 921 /* 922 * Only one of below two conditions is satisfied, we 923 * think the target is associated to the iport and 924 * allow call into mptsas_probe_lun(). 925 * 1. physicalsport == physport 926 * 2. (phymask & (1 << physport)) == 0 927 * The condition #2 is because LSI uses lowest PHY 928 * number as the value of physical port when auto port 929 * configuration. 930 */ 931 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 932 ((physicalport == physport) || (dynamicport && (phymask & \ 933 (1 << physport)))) 934 935 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 936 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 937 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 938 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 939 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 940 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 941 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 942 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 943 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 944 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 945 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 946 947 /* 948 * These should eventually migrate into the mpt header files 949 * that may become the /kernel/misc/mpt module... 950 */ 951 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 952 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 953 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 954 mptsas_put_msg_Function(hdl, mp, Function); \ 955 mptsas_put_msg_Lun(hdl, mp, Lun) 956 957 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 958 ddi_put16(hdl, &(mp)->DevHandle, (val)) 959 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 960 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 961 #define mptsas_put_msg_Function(hdl, mp, val) \ 962 ddi_put8(hdl, &(mp)->Function, (val)) 963 #define mptsas_put_msg_Lun(hdl, mp, val) \ 964 ddi_put8(hdl, &(mp)->LUN[1], (val)) 965 966 #define mptsas_get_msg_Function(hdl, mp) \ 967 ddi_get8(hdl, &(mp)->Function) 968 969 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 970 ddi_get8(hdl, &(mp)->MsgFlags) 971 972 #define MPTSAS_ENABLE_DRWE(hdl) \ 973 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 974 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 975 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 976 MPI2_WRSEQ_1ST_KEY_VALUE); \ 977 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 978 MPI2_WRSEQ_2ND_KEY_VALUE); \ 979 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 980 MPI2_WRSEQ_3RD_KEY_VALUE); \ 981 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 982 MPI2_WRSEQ_4TH_KEY_VALUE); \ 983 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 984 MPI2_WRSEQ_5TH_KEY_VALUE); \ 985 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 986 MPI2_WRSEQ_6TH_KEY_VALUE); 987 988 /* 989 * m_options flags 990 */ 991 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 992 993 /* 994 * m_softstate flags 995 */ 996 #define MPTSAS_SS_DRAINING 0x02 997 #define MPTSAS_SS_QUIESCED 0x04 998 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 999 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1000 1001 /* 1002 * regspec defines. 1003 */ 1004 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1005 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1006 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1007 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1008 1009 /* 1010 * Handy constants 1011 */ 1012 #define FALSE 0 1013 #define TRUE 1 1014 #define UNDEFINED -1 1015 #define FAILED -2 1016 1017 /* 1018 * power management. 1019 */ 1020 #define MPTSAS_POWER_ON(mpt) { \ 1021 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1022 PCI_PMCSR_D0); \ 1023 delay(drv_usectohz(10000)); \ 1024 (void) pci_restore_config_regs(mpt->m_dip); \ 1025 mptsas_setup_cmd_reg(mpt); \ 1026 } 1027 1028 #define MPTSAS_POWER_OFF(mpt) { \ 1029 (void) pci_save_config_regs(mpt->m_dip); \ 1030 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1031 PCI_PMCSR_D3HOT); \ 1032 mpt->m_power_level = PM_LEVEL_D3; \ 1033 } 1034 1035 /* 1036 * inq_dtype: 1037 * Bits 5 through 7 are the Peripheral Device Qualifier 1038 * 001b: device not connected to the LUN 1039 * Bits 0 through 4 are the Peripheral Device Type 1040 * 1fh: Unknown or no device type 1041 * 1042 * Although the inquiry may return success, the following value 1043 * means no valid LUN connected. 1044 */ 1045 #define MPTSAS_VALID_LUN(sd_inq) \ 1046 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1047 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1048 1049 /* 1050 * Default is to have 10 retries on receiving QFULL status and 1051 * each retry to be after 100 ms. 1052 */ 1053 #define QFULL_RETRIES 10 1054 #define QFULL_RETRY_INTERVAL 100 1055 1056 /* 1057 * Handy macros 1058 */ 1059 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1060 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1061 1062 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1063 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1064 1065 /* 1066 * poll time for mptsas_pollret() and mptsas_wait_intr() 1067 */ 1068 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1069 1070 /* 1071 * default time for mptsas_do_passthru 1072 */ 1073 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1074 1075 /* 1076 * macro to return the effective address of a given per-target field 1077 */ 1078 #define EFF_ADDR(start, offset) ((start) + (offset)) 1079 1080 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1081 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1082 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1083 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1084 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1085 1086 1087 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1088 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1089 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1090 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1091 1092 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1093 1094 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1095 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1096 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1097 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1098 1099 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1100 &(mpt)->m_reg->HostInterruptStatus)) 1101 1102 #define MPTSAS_SET_SIGP(P) \ 1103 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1104 1105 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1106 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1107 1108 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1109 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1110 1111 1112 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1113 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1114 req_desc_lo);\ 1115 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1116 req_desc_hi); 1117 1118 #define INTPENDING(mpt) \ 1119 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1120 1121 /* 1122 * Mask all interrupts to disable 1123 */ 1124 #define MPTSAS_DISABLE_INTR(mpt) \ 1125 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1126 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1127 1128 /* 1129 * Mask Doorbell and Reset interrupts to enable reply desc int. 1130 */ 1131 #define MPTSAS_ENABLE_INTR(mpt) \ 1132 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1133 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1134 1135 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1136 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1137 1138 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1139 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1140 1141 #define ClrSetBits32(hdl, reg, clr, set) \ 1142 ddi_put32(hdl, (reg), \ 1143 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1144 1145 #define ClrSetBits(reg, clr, set) \ 1146 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1147 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1148 1149 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1150 if ((cmdp = mpt->m_waitq) != NULL) { \ 1151 /* If the queue is now empty fix the tail pointer */ \ 1152 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1153 mpt->m_waitqtail = &mpt->m_waitq; \ 1154 cmdp->cmd_linkp = NULL; \ 1155 cmdp->cmd_queued = FALSE; \ 1156 } 1157 1158 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1159 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1160 /* If the queue is now empty fix the tail pointer */ \ 1161 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1162 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1163 cmdp->cmd_linkp = NULL; \ 1164 cmdp->cmd_queued = FALSE; \ 1165 } 1166 1167 /* 1168 * defaults for the global properties 1169 */ 1170 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1171 #define DEFAULT_TAG_AGE_LIMIT 2 1172 #define DEFAULT_WD_TICK 10 1173 1174 /* 1175 * invalid hostid. 1176 */ 1177 #define MPTSAS_INVALID_HOSTID -1 1178 1179 /* 1180 * Get/Set hostid from SCSI port configuration page 1181 */ 1182 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1183 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1184 1185 /* 1186 * Config space. 1187 */ 1188 #define MPTSAS_LATENCY_TIMER 0x40 1189 1190 /* 1191 * Offset to firmware version 1192 */ 1193 #define MPTSAS_FW_VERSION_OFFSET 9 1194 1195 /* 1196 * Offset and masks to get at the ProductId field 1197 */ 1198 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1199 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1200 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1201 1202 /* 1203 * Subsystem ID for HBAs. 1204 */ 1205 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1206 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1207 1208 /* 1209 * reset delay tick 1210 */ 1211 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1212 1213 /* 1214 * Ioc reset return values 1215 */ 1216 #define MPTSAS_RESET_FAIL -1 1217 #define MPTSAS_NO_RESET 0 1218 #define MPTSAS_SUCCESS_HARDRESET 1 1219 #define MPTSAS_SUCCESS_MUR 2 1220 1221 /* 1222 * throttle support. 1223 */ 1224 #define MAX_THROTTLE 32 1225 #define HOLD_THROTTLE 0 1226 #define DRAIN_THROTTLE -1 1227 #define QFULL_THROTTLE -2 1228 1229 /* 1230 * Passthrough/config request flags 1231 */ 1232 #define MPTSAS_DATA_ALLOCATED 0x0001 1233 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1234 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1235 #define MPTSAS_ADDRESS_REPLY 0x0008 1236 #define MPTSAS_CMD_TIMEOUT 0x0010 1237 1238 /* 1239 * response code tlr flag 1240 */ 1241 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1242 1243 /* 1244 * System Events 1245 */ 1246 #ifndef DDI_VENDOR_LSI 1247 #define DDI_VENDOR_LSI "LSI" 1248 #endif /* DDI_VENDOR_LSI */ 1249 1250 /* 1251 * Shared functions 1252 */ 1253 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1254 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1255 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1256 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1257 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1258 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1259 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1260 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1261 uint8_t pageversion, uint8_t pagelength, uint32_t 1262 SGEflagslength, uint32_t SGEaddress32); 1263 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1264 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1265 uint8_t pageversion, uint16_t extpagelength, 1266 uint32_t SGEflagslength, uint32_t SGEaddress32); 1267 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1268 uint8_t type, int mode); 1269 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1270 uint8_t type, int mode); 1271 int mptsas_download_firmware(); 1272 int mptsas_can_download_firmware(); 1273 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1274 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1275 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1276 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1277 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1278 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1279 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1280 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1281 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1282 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1283 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1284 1285 /* 1286 * impl functions 1287 */ 1288 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1289 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1290 int mptsas_ioc_reset(mptsas_t *mpt, int); 1291 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1292 ddi_acc_handle_t accessp); 1293 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1294 ddi_acc_handle_t accessp); 1295 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1296 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1297 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1298 uint32_t SGEaddress32); 1299 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1300 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1301 uint8_t pageversion, uint16_t extpagelength, 1302 uint32_t SGEflagslength, uint32_t SGEaddress32); 1303 1304 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1305 struct scsi_pkt **pkt); 1306 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1307 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1308 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1309 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1310 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1311 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1312 1313 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1314 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1315 int mode); 1316 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1317 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1318 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1319 int mptsas_restart_ioc(mptsas_t *mpt); 1320 void mptsas_update_driver_data(struct mptsas *mpt); 1321 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1322 1323 /* 1324 * init functions 1325 */ 1326 int mptsas_ioc_get_facts(mptsas_t *mpt); 1327 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1328 int mptsas_ioc_enable_port(mptsas_t *mpt); 1329 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1330 int mptsas_ioc_init(mptsas_t *mpt); 1331 1332 /* 1333 * configuration pages operation 1334 */ 1335 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1336 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1337 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1338 uint16_t *slot_num, uint16_t *enclosure); 1339 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1340 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1341 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1342 mptsas_smp_t *info); 1343 int mptsas_set_ioc_params(mptsas_t *mpt); 1344 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1345 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1346 uint64_t *sas_wwn, uint8_t *portwidth); 1347 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1348 int 1349 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1350 smhba_info_t *info); 1351 int 1352 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1353 smhba_info_t *info); 1354 int 1355 mptsas_get_manufacture_page0(mptsas_t *mpt); 1356 void 1357 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1358 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1359 int mptsas_smhba_phy_init(mptsas_t *mpt); 1360 /* 1361 * RAID functions 1362 */ 1363 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1364 int mptsas_get_raid_info(mptsas_t *mpt); 1365 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1366 uint8_t physdisknum); 1367 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1368 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1369 1370 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1371 /* 1372 * debugging. 1373 */ 1374 #if defined(MPTSAS_DEBUG) 1375 1376 void mptsas_printf(char *fmt, ...); 1377 1378 #define MPTSAS_DBGPR(m, args) \ 1379 if (mptsas_debug_flags & (m)) \ 1380 mptsas_printf args 1381 #else /* ! defined(MPTSAS_DEBUG) */ 1382 #define MPTSAS_DBGPR(m, args) 1383 #endif /* defined(MPTSAS_DEBUG) */ 1384 1385 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1386 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1387 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1388 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1389 1390 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1391 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1392 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1393 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1394 1395 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1396 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1397 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1398 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1399 1400 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1401 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1402 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1403 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1404 1405 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1406 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1407 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1408 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1409 1410 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1411 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1412 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1413 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1414 1415 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1416 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1417 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1418 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1419 1420 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1421 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1422 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1423 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1424 1425 /* 1426 * auto request sense 1427 */ 1428 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1429 (pkt)->pkt_flags = (flag), \ 1430 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1431 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1432 (pkt)->pkt_address.a_lun 1433 1434 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1435 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1436 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1437 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1438 1439 1440 #ifdef __cplusplus 1441 } 1442 #endif 1443 1444 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1445