1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2014 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved. 26 */ 27 28 /* 29 * Copyright (c) 2000 to 2010, LSI Corporation. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms of all code within 33 * this file that is exclusively owned by LSI, with or without 34 * modification, is permitted provided that, in addition to the CDDL 1.0 35 * License requirements, the following conditions are met: 36 * 37 * Neither the name of the author nor the names of its contributors may be 38 * used to endorse or promote products derived from this software without 39 * specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 52 * DAMAGE. 53 */ 54 55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 57 58 #include <sys/byteorder.h> 59 #include <sys/queue.h> 60 #include <sys/isa_defs.h> 61 #include <sys/sunmdi.h> 62 #include <sys/mdi_impldefs.h> 63 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 64 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 65 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 /* 73 * Compile options 74 */ 75 #ifdef DEBUG 76 #define MPTSAS_DEBUG /* turn on debugging code */ 77 #endif /* DEBUG */ 78 79 #define MPTSAS_INITIAL_SOFT_SPACE 4 80 81 #define MAX_MPI_PORTS 16 82 83 /* 84 * Note below macro definition and data type definition 85 * are used for phy mask handling, it should be changed 86 * simultaneously. 87 */ 88 #define MPTSAS_MAX_PHYS 16 89 typedef uint16_t mptsas_phymask_t; 90 91 #define MPTSAS_INVALID_DEVHDL 0xffff 92 #define MPTSAS_SATA_GUID "sata-guid" 93 94 /* 95 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 96 * targets. There's no need to go overboard here, as the ordinary paths for 97 * I/O do not normally require hashed target lookups. These should be good 98 * enough and then some for any fabric within the hardware's capabilities. 99 */ 100 #define MPTSAS_SMP_BUCKET_COUNT 23 101 #define MPTSAS_TARGET_BUCKET_COUNT 97 102 103 /* 104 * MPT HW defines 105 */ 106 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 107 #define MPTSAS_MAX_DISKS_IN_VOL 10 108 #define MPTSAS_MAX_HOTSPARES 2 109 #define MPTSAS_MAX_RAIDVOLS 2 110 #define MPTSAS_MAX_RAIDCONFIGS 5 111 112 /* 113 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 114 * plus two means the prefix 'w' and end of the string '\0'. 115 */ 116 #define MPTSAS_WWN_STRLEN (16 + 2) 117 #define MPTSAS_MAX_GUID_LEN 64 118 119 /* 120 * DMA routine flags 121 */ 122 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 123 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 124 #define MPTSAS_DMA_HANDLE_BOUND 0x8 125 126 /* 127 * If the HBA supports DMA or bus-mastering, you may have your own 128 * scatter-gather list for physically non-contiguous memory in one 129 * I/O operation; if so, there's probably a size for that list. 130 * It must be placed in the ddi_dma_lim_t structure, so that the system 131 * DMA-support routines can use it to break up the I/O request, so we 132 * define it here. 133 */ 134 #if defined(__sparc) 135 #define MPTSAS_MAX_DMA_SEGS 1 136 #define MPTSAS_MAX_CMD_SEGS 1 137 #else 138 #define MPTSAS_MAX_DMA_SEGS 256 139 #define MPTSAS_MAX_CMD_SEGS 257 140 #endif 141 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 142 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 143 144 /* 145 * Caculating how many 64-bit DMA simple elements can be stored in the first 146 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 147 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 148 * size. 149 */ 150 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 151 ((mpt->m_req_frame_size - \ 152 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 153 154 /* 155 * Scatter-gather list structure defined by HBA hardware 156 */ 157 typedef struct NcrTableIndirect { /* Table Indirect entries */ 158 uint32_t count; /* 24 bit count */ 159 union { 160 uint32_t address32; /* 32 bit address */ 161 struct { 162 uint32_t Low; 163 uint32_t High; 164 } address64; /* 64 bit address */ 165 } addr; 166 } mptti_t; 167 168 /* 169 * preferred pkt_private length in 64-bit quantities 170 */ 171 #ifdef _LP64 172 #define PKT_PRIV_SIZE 2 173 #define PKT_PRIV_LEN 16 /* in bytes */ 174 #else /* _ILP32 */ 175 #define PKT_PRIV_SIZE 1 176 #define PKT_PRIV_LEN 8 /* in bytes */ 177 #endif 178 179 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 180 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 181 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 182 183 /* 184 * get offset of item in structure 185 */ 186 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 187 188 /* 189 * WWID provided by LSI firmware is generated by firmware but the WWID is not 190 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 191 * address. According LSI's confirmation, the top nibble of RAID WWID is 192 * meanless, so the consensus between Solaris and OBP is to replace top nibble 193 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 194 * format unit address. 195 */ 196 #define MPTSAS_RAID_WWID(wwid) \ 197 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 198 199 typedef struct mptsas_target_addr { 200 uint64_t mta_wwn; 201 mptsas_phymask_t mta_phymask; 202 } mptsas_target_addr_t; 203 204 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd); 205 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t; 206 207 typedef struct mptsas_target { 208 mptsas_target_addr_t m_addr; 209 refhash_link_t m_link; 210 uint8_t m_dr_flag; 211 uint16_t m_devhdl; 212 uint32_t m_deviceinfo; 213 uint8_t m_phynum; 214 uint32_t m_dups; 215 mptsas_active_cmdq_t m_active_cmdq; 216 int32_t m_t_throttle; 217 int32_t m_t_ncmds; 218 int32_t m_reset_delay; 219 int32_t m_t_nwait; 220 221 uint16_t m_qfull_retry_interval; 222 uint8_t m_qfull_retries; 223 uint16_t m_enclosure; 224 uint16_t m_slot_num; 225 uint32_t m_tgt_unconfigured; 226 uint8_t m_led_status; 227 228 } mptsas_target_t; 229 230 /* 231 * If you change this structure, be sure that mptsas_smp_target_copy() 232 * does the right thing. 233 */ 234 typedef struct mptsas_smp { 235 mptsas_target_addr_t m_addr; 236 refhash_link_t m_link; 237 uint16_t m_devhdl; 238 uint32_t m_deviceinfo; 239 uint16_t m_pdevhdl; 240 uint32_t m_pdevinfo; 241 } mptsas_smp_t; 242 243 typedef struct mptsas_cache_frames { 244 ddi_dma_handle_t m_dma_hdl; 245 ddi_acc_handle_t m_acc_hdl; 246 caddr_t m_frames_addr; 247 uint32_t m_phys_addr; 248 } mptsas_cache_frames_t; 249 250 typedef struct mptsas_cmd { 251 uint_t cmd_flags; /* flags from scsi_init_pkt */ 252 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 253 ddi_dma_cookie_t cmd_cookie; 254 uint_t cmd_cookiec; 255 uint_t cmd_winindex; 256 uint_t cmd_nwin; 257 uint_t cmd_cur_cookie; 258 off_t cmd_dma_offset; 259 size_t cmd_dma_len; 260 uint32_t cmd_totaldmacount; 261 262 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 263 ddi_dma_cookie_t cmd_arqcookie; 264 struct buf *cmd_arq_buf; 265 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 266 ddi_dma_cookie_t cmd_ext_arqcookie; 267 struct buf *cmd_ext_arq_buf; 268 269 int cmd_pkt_flags; 270 271 /* pending expiration time for command in active slot */ 272 hrtime_t cmd_active_expiration; 273 TAILQ_ENTRY(mptsas_cmd) cmd_active_link; 274 275 struct scsi_pkt *cmd_pkt; 276 struct scsi_arq_status cmd_scb; 277 uchar_t cmd_cdblen; /* length of cdb */ 278 uchar_t cmd_rqslen; /* len of requested rqsense */ 279 uchar_t cmd_privlen; 280 uint_t cmd_scblen; 281 uint32_t cmd_dmacount; 282 uint64_t cmd_dma_addr; 283 uchar_t cmd_age; 284 ushort_t cmd_qfull_retries; 285 uchar_t cmd_queued; /* true if queued */ 286 struct mptsas_cmd *cmd_linkp; 287 mptti_t *cmd_sg; /* Scatter/Gather structure */ 288 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 289 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 290 uint32_t cmd_slot; 291 uint32_t ioc_cmd_slot; 292 293 mptsas_cache_frames_t *cmd_extra_frames; 294 295 uint32_t cmd_rfm; 296 mptsas_target_t *cmd_tgt_addr; 297 } mptsas_cmd_t; 298 299 /* 300 * These are the defined cmd_flags for this structure. 301 */ 302 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 303 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 304 #define CFLAG_FINISHED 0x000004 /* command completed */ 305 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 306 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 307 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 308 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 309 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 310 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 311 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 312 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 313 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 314 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 315 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 316 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 317 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 318 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 319 #define CFLAG_FREE 0x010000 /* packet is on free list */ 320 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 321 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 322 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 323 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 324 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 325 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 326 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 327 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 328 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 329 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 330 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 331 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 332 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 333 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 334 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 335 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 345 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 347 348 #define MPTSAS_HASH_ARRAY_SIZE 16 349 /* 350 * hash table definition 351 */ 352 353 #define MPTSAS_HASH_FIRST 0xffff 354 #define MPTSAS_HASH_NEXT 0x0000 355 356 typedef struct mptsas_dma_alloc_state 357 { 358 ddi_dma_handle_t handle; 359 caddr_t memp; 360 size_t size; 361 ddi_acc_handle_t accessp; 362 ddi_dma_cookie_t cookie; 363 } mptsas_dma_alloc_state_t; 364 365 /* 366 * passthrough request structure 367 */ 368 typedef struct mptsas_pt_request { 369 uint8_t *request; 370 uint32_t request_size; 371 uint32_t data_size; 372 uint32_t dataout_size; 373 uint32_t direction; 374 ddi_dma_cookie_t data_cookie; 375 ddi_dma_cookie_t dataout_cookie; 376 } mptsas_pt_request_t; 377 378 /* 379 * config page request structure 380 */ 381 typedef struct mptsas_config_request { 382 uint32_t page_address; 383 uint8_t action; 384 uint8_t page_type; 385 uint8_t page_number; 386 uint8_t page_length; 387 uint8_t page_version; 388 uint8_t ext_page_type; 389 uint16_t ext_page_length; 390 } mptsas_config_request_t; 391 392 typedef struct mptsas_fw_diagnostic_buffer { 393 mptsas_dma_alloc_state_t buffer_data; 394 uint8_t extended_type; 395 uint8_t buffer_type; 396 uint8_t force_release; 397 uint32_t product_specific[23]; 398 uint8_t immediate; 399 uint8_t enabled; 400 uint8_t valid_data; 401 uint8_t owned_by_firmware; 402 uint32_t unique_id; 403 } mptsas_fw_diagnostic_buffer_t; 404 405 /* 406 * FW diag request structure 407 */ 408 typedef struct mptsas_diag_request { 409 mptsas_fw_diagnostic_buffer_t *pBuffer; 410 uint8_t function; 411 } mptsas_diag_request_t; 412 413 typedef struct mptsas_hash_node { 414 void *data; 415 struct mptsas_hash_node *next; 416 } mptsas_hash_node_t; 417 418 typedef struct mptsas_hash_table { 419 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 420 /* 421 * last position in traverse 422 */ 423 struct mptsas_hash_node *cur; 424 uint16_t line; 425 426 } mptsas_hash_table_t; 427 428 /* 429 * RAID volume information 430 */ 431 typedef struct mptsas_raidvol { 432 ushort_t m_israid; 433 uint16_t m_raidhandle; 434 uint64_t m_raidwwid; 435 uint8_t m_state; 436 uint32_t m_statusflags; 437 uint32_t m_settings; 438 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 439 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 440 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 441 uint64_t m_raidsize; 442 int m_raidlevel; 443 int m_ndisks; 444 mptsas_target_t *m_raidtgt; 445 } mptsas_raidvol_t; 446 447 /* 448 * RAID configurations 449 */ 450 typedef struct mptsas_raidconfig { 451 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 452 uint16_t m_physdisk_devhdl[ 453 MPTSAS_MAX_DISKS_IN_CONFIG]; 454 uint8_t m_native; 455 } m_raidconfig_t; 456 457 /* 458 * Track outstanding commands. The index into the m_slot array is the SMID 459 * (system message ID) of the outstanding command. SMID 0 is reserved by the 460 * software/firmware protocol and is never used for any command we generate; 461 * as such, the assertion m_slot[0] == NULL is universally true. The last 462 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 463 * task management commands. No normal SCSI or ATA command will ever occupy 464 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 465 * time that a consistent view of the target array is obtainable. 466 * 467 * As such, m_n_normal is the maximum number of slots available to ordinary 468 * commands, and the relationship: 469 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 470 * always holds after initialisation. 471 */ 472 typedef struct mptsas_slots { 473 size_t m_size; /* size of struct, bytes */ 474 uint_t m_n_normal; /* see above */ 475 uint_t m_rotor; /* next slot idx to consider */ 476 mptsas_cmd_t *m_slot[1]; 477 } mptsas_slots_t; 478 479 /* 480 * Structure to hold command and packets for event ack 481 * and task management commands. 482 */ 483 typedef struct m_event_struct { 484 struct mptsas_cmd m_event_cmd; 485 struct m_event_struct *m_event_linkp; 486 /* 487 * event member record the failure event and eventcntx 488 * event member would be used in send ack pending process 489 */ 490 uint32_t m_event; 491 uint32_t m_eventcntx; 492 uint_t in_use; 493 struct scsi_pkt m_event_pkt; /* must be last */ 494 /* ... scsi_pkt_size() */ 495 } m_event_struct_t; 496 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 497 sizeof (struct scsi_pkt) + scsi_pkt_size()) 498 499 #define MAX_IOC_COMMANDS 8 500 501 /* 502 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 503 * A new event ack command requests mptsas_cmd and scsi_pkt structures 504 * from this pool, and returns it back when done. 505 */ 506 507 typedef struct m_replyh_arg { 508 void *mpt; 509 uint32_t rfm; 510 } m_replyh_arg_t; 511 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 512 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 513 514 /* 515 * Flags for DR handler topology change 516 */ 517 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 518 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 519 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 520 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 521 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 522 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 523 524 typedef struct mptsas_topo_change_list { 525 void *mpt; 526 uint_t event; 527 union { 528 uint8_t physport; 529 mptsas_phymask_t phymask; 530 } un; 531 uint16_t devhdl; 532 void *object; 533 uint8_t flags; 534 struct mptsas_topo_change_list *next; 535 } mptsas_topo_change_list_t; 536 537 538 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 539 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 540 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 541 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 542 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 543 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 544 545 /* 546 * Status types when calling mptsas_get_target_device_info 547 */ 548 #define DEV_INFO_SUCCESS 0x0 549 #define DEV_INFO_FAIL_PAGE0 0x1 550 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 551 #define DEV_INFO_PHYS_DISK 0x3 552 #define DEV_INFO_FAIL_ALLOC 0x4 553 554 /* 555 * mpt hotplug event defines 556 */ 557 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 558 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 559 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 560 561 /* 562 * SMP target hotplug events 563 */ 564 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 565 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 566 #define MPTSAS_DR_EVENT_MASK 0x3F 567 568 /* 569 * mpt hotplug status definition for m_dr_flag 570 */ 571 572 /* 573 * MPTSAS_DR_INACTIVE 574 * 575 * The target is in a normal operating state. 576 * No dynamic reconfiguration operation is in progress. 577 */ 578 #define MPTSAS_DR_INACTIVE 0x0 579 /* 580 * MPTSAS_DR_INTRANSITION 581 * 582 * The target is in a transition mode since 583 * hotplug event happens and offline procedure has not 584 * been finished 585 */ 586 #define MPTSAS_DR_INTRANSITION 0x1 587 588 typedef struct mptsas_tgt_private { 589 int t_lun; 590 struct mptsas_target *t_private; 591 } mptsas_tgt_private_t; 592 593 /* 594 * The following defines are used in mptsas_set_init_mode to track the current 595 * state as we progress through reprogramming the HBA from target mode into 596 * initiator mode. 597 */ 598 599 #define IOUC_READ_PAGE0 0x00000100 600 #define IOUC_READ_PAGE1 0x00000200 601 #define IOUC_WRITE_PAGE1 0x00000400 602 #define IOUC_DONE 0x00000800 603 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 604 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 605 606 /* 607 * Last allocated slot is used for TM requests. Since only m_max_requests 608 * frames are allocated, the last SMID will be m_max_requests - 1. 609 */ 610 #define MPTSAS_SLOTS_SIZE(mpt) \ 611 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 612 mpt->m_max_requests)) 613 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 614 615 /* 616 * Macro for phy_flags 617 */ 618 619 typedef struct smhba_info { 620 kmutex_t phy_mutex; 621 uint8_t phy_id; 622 uint64_t sas_addr; 623 char path[8]; 624 uint16_t owner_devhdl; 625 uint16_t attached_devhdl; 626 uint8_t attached_phy_identify; 627 uint32_t attached_phy_info; 628 uint8_t programmed_link_rate; 629 uint8_t hw_link_rate; 630 uint8_t change_count; 631 uint32_t phy_info; 632 uint8_t negotiated_link_rate; 633 uint8_t port_num; 634 kstat_t *phy_stats; 635 uint32_t invalid_dword_count; 636 uint32_t running_disparity_error_count; 637 uint32_t loss_of_dword_sync_count; 638 uint32_t phy_reset_problem_count; 639 void *mpt; 640 } smhba_info_t; 641 642 typedef struct mptsas_phy_info { 643 uint8_t port_num; 644 uint8_t port_flags; 645 uint16_t ctrl_devhdl; 646 uint32_t phy_device_type; 647 uint16_t attached_devhdl; 648 mptsas_phymask_t phy_mask; 649 smhba_info_t smhba_info; 650 } mptsas_phy_info_t; 651 652 653 typedef struct mptsas_doneq_thread_arg { 654 void *mpt; 655 uint64_t t; 656 } mptsas_doneq_thread_arg_t; 657 658 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 659 typedef struct mptsas_doneq_thread_list { 660 mptsas_cmd_t *doneq; 661 mptsas_cmd_t **donetail; 662 kthread_t *threadp; 663 kcondvar_t cv; 664 ushort_t reserv1; 665 uint32_t reserv2; 666 kmutex_t mutex; 667 uint32_t flag; 668 uint32_t len; 669 mptsas_doneq_thread_arg_t arg; 670 } mptsas_doneq_thread_list_t; 671 672 typedef struct mptsas { 673 int m_instance; 674 675 struct mptsas *m_next; 676 677 scsi_hba_tran_t *m_tran; 678 smp_hba_tran_t *m_smptran; 679 kmutex_t m_mutex; 680 kmutex_t m_passthru_mutex; 681 kcondvar_t m_cv; 682 kcondvar_t m_passthru_cv; 683 kcondvar_t m_fw_cv; 684 kcondvar_t m_config_cv; 685 kcondvar_t m_fw_diag_cv; 686 dev_info_t *m_dip; 687 688 /* 689 * soft state flags 690 */ 691 uint_t m_softstate; 692 693 refhash_t *m_targets; 694 refhash_t *m_smp_targets; 695 696 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 697 uint8_t m_num_raid_configs; 698 699 struct mptsas_slots *m_active; /* outstanding cmds */ 700 701 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 702 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 703 704 kmutex_t m_tx_waitq_mutex; 705 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 706 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 707 int m_tx_draining; /* TX queue draining flag */ 708 709 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 710 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 711 712 /* 713 * variables for helper threads (fan-out interrupts) 714 */ 715 mptsas_doneq_thread_list_t *m_doneq_thread_id; 716 uint32_t m_doneq_thread_n; 717 uint32_t m_doneq_thread_threshold; 718 uint32_t m_doneq_length_threshold; 719 uint32_t m_doneq_len; 720 kcondvar_t m_doneq_thread_cv; 721 kmutex_t m_doneq_mutex; 722 723 int m_ncmds; /* number of outstanding commands */ 724 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 725 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 726 727 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 728 729 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 730 731 ushort_t m_devid; /* device id of chip. */ 732 uchar_t m_revid; /* revision of chip. */ 733 uint16_t m_svid; /* subsystem Vendor ID of chip */ 734 uint16_t m_ssid; /* subsystem Device ID of chip */ 735 736 uchar_t m_sync_offset; /* default offset for this chip. */ 737 738 timeout_id_t m_quiesce_timeid; 739 740 ddi_dma_handle_t m_dma_req_frame_hdl; 741 ddi_acc_handle_t m_acc_req_frame_hdl; 742 ddi_dma_handle_t m_dma_reply_frame_hdl; 743 ddi_acc_handle_t m_acc_reply_frame_hdl; 744 ddi_dma_handle_t m_dma_free_queue_hdl; 745 ddi_acc_handle_t m_acc_free_queue_hdl; 746 ddi_dma_handle_t m_dma_post_queue_hdl; 747 ddi_acc_handle_t m_acc_post_queue_hdl; 748 749 /* 750 * list of reset notification requests 751 */ 752 struct scsi_reset_notify_entry *m_reset_notify_listf; 753 754 /* 755 * qfull handling 756 */ 757 timeout_id_t m_restart_cmd_timeid; 758 759 /* 760 * scsi reset delay per bus 761 */ 762 uint_t m_scsi_reset_delay; 763 764 int m_pm_idle_delay; 765 766 uchar_t m_polled_intr; /* intr was polled. */ 767 uchar_t m_suspended; /* true if driver is suspended */ 768 769 struct kmem_cache *m_kmem_cache; 770 struct kmem_cache *m_cache_frames; 771 772 /* 773 * hba options. 774 */ 775 uint_t m_options; 776 777 int m_in_callback; 778 779 int m_power_level; /* current power level */ 780 781 int m_busy; /* power management busy state */ 782 783 off_t m_pmcsr_offset; /* PMCSR offset */ 784 785 ddi_acc_handle_t m_config_handle; 786 787 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 788 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 789 ddi_device_acc_attr_t m_dev_acc_attr; 790 ddi_device_acc_attr_t m_reg_acc_attr; 791 792 /* 793 * request/reply variables 794 */ 795 caddr_t m_req_frame; 796 uint64_t m_req_frame_dma_addr; 797 caddr_t m_reply_frame; 798 uint64_t m_reply_frame_dma_addr; 799 caddr_t m_free_queue; 800 uint64_t m_free_queue_dma_addr; 801 caddr_t m_post_queue; 802 uint64_t m_post_queue_dma_addr; 803 804 m_replyh_arg_t *m_replyh_args; 805 806 uint16_t m_max_requests; 807 uint16_t m_req_frame_size; 808 809 /* 810 * Max frames per request reprted in IOC Facts 811 */ 812 uint8_t m_max_chain_depth; 813 /* 814 * Max frames per request which is used in reality. It's adjusted 815 * according DMA SG length attribute, and shall not exceed the 816 * m_max_chain_depth. 817 */ 818 uint8_t m_max_request_frames; 819 820 uint16_t m_free_queue_depth; 821 uint16_t m_post_queue_depth; 822 uint16_t m_max_replies; 823 uint32_t m_free_index; 824 uint32_t m_post_index; 825 uint8_t m_reply_frame_size; 826 uint32_t m_ioc_capabilities; 827 828 /* 829 * indicates if the firmware was upload by the driver 830 * at boot time 831 */ 832 ushort_t m_fwupload; 833 834 uint16_t m_productid; 835 836 /* 837 * per instance data structures for dma memory resources for 838 * MPI handshake protocol. only one handshake cmd can run at a time. 839 */ 840 ddi_dma_handle_t m_hshk_dma_hdl; 841 ddi_acc_handle_t m_hshk_acc_hdl; 842 caddr_t m_hshk_memp; 843 size_t m_hshk_dma_size; 844 845 /* Firmware version on the card at boot time */ 846 uint32_t m_fwversion; 847 848 /* MSI specific fields */ 849 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 850 int m_intr_type; /* What type of interrupt */ 851 int m_intr_cnt; /* # of intrs count returned */ 852 size_t m_intr_size; /* Size of intr array */ 853 uint_t m_intr_pri; /* Interrupt priority */ 854 int m_intr_cap; /* Interrupt capabilities */ 855 ddi_taskq_t *m_event_taskq; 856 857 /* SAS specific information */ 858 859 union { 860 uint64_t m_base_wwid; /* Base WWID */ 861 struct { 862 #ifdef _BIG_ENDIAN 863 uint32_t m_base_wwid_hi; 864 uint32_t m_base_wwid_lo; 865 #else 866 uint32_t m_base_wwid_lo; 867 uint32_t m_base_wwid_hi; 868 #endif 869 } sasaddr; 870 } un; 871 872 uint8_t m_num_phys; /* # of PHYs */ 873 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 874 uint8_t m_port_chng; /* initiator port changes */ 875 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 876 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 877 878 /* FMA Capabilities */ 879 int m_fm_capabilities; 880 ddi_taskq_t *m_dr_taskq; 881 int m_mpxio_enable; 882 uint8_t m_done_traverse_dev; 883 uint8_t m_done_traverse_smp; 884 int m_diag_action_in_progress; 885 uint16_t m_dev_handle; 886 uint16_t m_smp_devhdl; 887 888 /* 889 * Event recording 890 */ 891 uint8_t m_event_index; 892 uint32_t m_event_number; 893 uint32_t m_event_mask[4]; 894 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 895 896 /* 897 * FW diag Buffer List 898 */ 899 mptsas_fw_diagnostic_buffer_t 900 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 901 902 /* 903 * Event Replay flag (MUR support) 904 */ 905 uint8_t m_event_replay; 906 907 /* 908 * IR Capable flag 909 */ 910 uint8_t m_ir_capable; 911 912 /* 913 * Is HBA processing a diag reset? 914 */ 915 uint8_t m_in_reset; 916 917 /* 918 * per instance cmd data structures for task management cmds 919 */ 920 m_event_struct_t m_event_task_mgmt; /* must be last */ 921 /* ... scsi_pkt_size */ 922 } mptsas_t; 923 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 924 sizeof (struct scsi_pkt) + scsi_pkt_size()) 925 /* 926 * Only one of below two conditions is satisfied, we 927 * think the target is associated to the iport and 928 * allow call into mptsas_probe_lun(). 929 * 1. physicalsport == physport 930 * 2. (phymask & (1 << physport)) == 0 931 * The condition #2 is because LSI uses lowest PHY 932 * number as the value of physical port when auto port 933 * configuration. 934 */ 935 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 936 ((physicalport == physport) || (dynamicport && (phymask & \ 937 (1 << physport)))) 938 939 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 940 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 941 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 942 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 943 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 944 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 945 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 946 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 947 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 948 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 949 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 950 951 /* 952 * These should eventually migrate into the mpt header files 953 * that may become the /kernel/misc/mpt module... 954 */ 955 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 956 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 957 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 958 mptsas_put_msg_Function(hdl, mp, Function); \ 959 mptsas_put_msg_Lun(hdl, mp, Lun) 960 961 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 962 ddi_put16(hdl, &(mp)->DevHandle, (val)) 963 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 964 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 965 #define mptsas_put_msg_Function(hdl, mp, val) \ 966 ddi_put8(hdl, &(mp)->Function, (val)) 967 #define mptsas_put_msg_Lun(hdl, mp, val) \ 968 ddi_put8(hdl, &(mp)->LUN[1], (val)) 969 970 #define mptsas_get_msg_Function(hdl, mp) \ 971 ddi_get8(hdl, &(mp)->Function) 972 973 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 974 ddi_get8(hdl, &(mp)->MsgFlags) 975 976 #define MPTSAS_ENABLE_DRWE(hdl) \ 977 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 978 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 979 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 980 MPI2_WRSEQ_1ST_KEY_VALUE); \ 981 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 982 MPI2_WRSEQ_2ND_KEY_VALUE); \ 983 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 984 MPI2_WRSEQ_3RD_KEY_VALUE); \ 985 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 986 MPI2_WRSEQ_4TH_KEY_VALUE); \ 987 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 988 MPI2_WRSEQ_5TH_KEY_VALUE); \ 989 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 990 MPI2_WRSEQ_6TH_KEY_VALUE); 991 992 /* 993 * m_options flags 994 */ 995 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 996 997 /* 998 * m_softstate flags 999 */ 1000 #define MPTSAS_SS_DRAINING 0x02 1001 #define MPTSAS_SS_QUIESCED 0x04 1002 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1003 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1004 1005 /* 1006 * regspec defines. 1007 */ 1008 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1009 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1010 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1011 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1012 1013 /* 1014 * Handy constants 1015 */ 1016 #define FALSE 0 1017 #define TRUE 1 1018 #define UNDEFINED -1 1019 #define FAILED -2 1020 1021 /* 1022 * power management. 1023 */ 1024 #define MPTSAS_POWER_ON(mpt) { \ 1025 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1026 PCI_PMCSR_D0); \ 1027 delay(drv_usectohz(10000)); \ 1028 (void) pci_restore_config_regs(mpt->m_dip); \ 1029 mptsas_setup_cmd_reg(mpt); \ 1030 } 1031 1032 #define MPTSAS_POWER_OFF(mpt) { \ 1033 (void) pci_save_config_regs(mpt->m_dip); \ 1034 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1035 PCI_PMCSR_D3HOT); \ 1036 mpt->m_power_level = PM_LEVEL_D3; \ 1037 } 1038 1039 /* 1040 * inq_dtype: 1041 * Bits 5 through 7 are the Peripheral Device Qualifier 1042 * 001b: device not connected to the LUN 1043 * Bits 0 through 4 are the Peripheral Device Type 1044 * 1fh: Unknown or no device type 1045 * 1046 * Although the inquiry may return success, the following value 1047 * means no valid LUN connected. 1048 */ 1049 #define MPTSAS_VALID_LUN(sd_inq) \ 1050 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1051 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1052 1053 /* 1054 * Default is to have 10 retries on receiving QFULL status and 1055 * each retry to be after 100 ms. 1056 */ 1057 #define QFULL_RETRIES 10 1058 #define QFULL_RETRY_INTERVAL 100 1059 1060 /* 1061 * Handy macros 1062 */ 1063 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1064 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1065 1066 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1067 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1068 1069 /* 1070 * poll time for mptsas_pollret() and mptsas_wait_intr() 1071 */ 1072 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1073 1074 /* 1075 * default time for mptsas_do_passthru 1076 */ 1077 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1078 1079 /* 1080 * macro to return the effective address of a given per-target field 1081 */ 1082 #define EFF_ADDR(start, offset) ((start) + (offset)) 1083 1084 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1085 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1086 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1087 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1088 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1089 1090 1091 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1092 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1093 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1094 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1095 1096 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1097 1098 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1099 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1100 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1101 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1102 1103 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1104 &(mpt)->m_reg->HostInterruptStatus)) 1105 1106 #define MPTSAS_SET_SIGP(P) \ 1107 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1108 1109 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1110 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1111 1112 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1113 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1114 1115 1116 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1117 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1118 req_desc_lo);\ 1119 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1120 req_desc_hi); 1121 1122 #define INTPENDING(mpt) \ 1123 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1124 1125 /* 1126 * Mask all interrupts to disable 1127 */ 1128 #define MPTSAS_DISABLE_INTR(mpt) \ 1129 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1130 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1131 1132 /* 1133 * Mask Doorbell and Reset interrupts to enable reply desc int. 1134 */ 1135 #define MPTSAS_ENABLE_INTR(mpt) \ 1136 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1137 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1138 1139 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1140 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1141 1142 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1143 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1144 1145 #define ClrSetBits32(hdl, reg, clr, set) \ 1146 ddi_put32(hdl, (reg), \ 1147 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1148 1149 #define ClrSetBits(reg, clr, set) \ 1150 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1151 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1152 1153 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1154 if ((cmdp = mpt->m_waitq) != NULL) { \ 1155 /* If the queue is now empty fix the tail pointer */ \ 1156 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1157 mpt->m_waitqtail = &mpt->m_waitq; \ 1158 cmdp->cmd_linkp = NULL; \ 1159 cmdp->cmd_queued = FALSE; \ 1160 } 1161 1162 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1163 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1164 /* If the queue is now empty fix the tail pointer */ \ 1165 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1166 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1167 cmdp->cmd_linkp = NULL; \ 1168 cmdp->cmd_queued = FALSE; \ 1169 } 1170 1171 /* 1172 * defaults for the global properties 1173 */ 1174 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1175 #define DEFAULT_TAG_AGE_LIMIT 2 1176 #define DEFAULT_WD_TICK 1 1177 1178 /* 1179 * invalid hostid. 1180 */ 1181 #define MPTSAS_INVALID_HOSTID -1 1182 1183 /* 1184 * Get/Set hostid from SCSI port configuration page 1185 */ 1186 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1187 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1188 1189 /* 1190 * Config space. 1191 */ 1192 #define MPTSAS_LATENCY_TIMER 0x40 1193 1194 /* 1195 * Offset to firmware version 1196 */ 1197 #define MPTSAS_FW_VERSION_OFFSET 9 1198 1199 /* 1200 * Offset and masks to get at the ProductId field 1201 */ 1202 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1203 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1204 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1205 1206 /* 1207 * Subsystem ID for HBAs. 1208 */ 1209 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1210 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1211 1212 /* 1213 * reset delay tick 1214 */ 1215 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1216 1217 /* 1218 * Ioc reset return values 1219 */ 1220 #define MPTSAS_RESET_FAIL -1 1221 #define MPTSAS_NO_RESET 0 1222 #define MPTSAS_SUCCESS_HARDRESET 1 1223 #define MPTSAS_SUCCESS_MUR 2 1224 1225 /* 1226 * throttle support. 1227 */ 1228 #define MAX_THROTTLE 32 1229 #define HOLD_THROTTLE 0 1230 #define DRAIN_THROTTLE -1 1231 #define QFULL_THROTTLE -2 1232 1233 /* 1234 * Passthrough/config request flags 1235 */ 1236 #define MPTSAS_DATA_ALLOCATED 0x0001 1237 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1238 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1239 #define MPTSAS_ADDRESS_REPLY 0x0008 1240 #define MPTSAS_CMD_TIMEOUT 0x0010 1241 1242 /* 1243 * response code tlr flag 1244 */ 1245 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1246 1247 /* 1248 * System Events 1249 */ 1250 #ifndef DDI_VENDOR_LSI 1251 #define DDI_VENDOR_LSI "LSI" 1252 #endif /* DDI_VENDOR_LSI */ 1253 1254 /* 1255 * Shared functions 1256 */ 1257 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1258 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1259 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1260 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1261 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1262 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1263 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1264 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1265 uint8_t pageversion, uint8_t pagelength, uint32_t 1266 SGEflagslength, uint32_t SGEaddress32); 1267 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1268 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1269 uint8_t pageversion, uint16_t extpagelength, 1270 uint32_t SGEflagslength, uint32_t SGEaddress32); 1271 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1272 uint8_t type, int mode); 1273 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1274 uint8_t type, int mode); 1275 int mptsas_download_firmware(); 1276 int mptsas_can_download_firmware(); 1277 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1278 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1279 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1280 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1281 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1282 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1283 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1284 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1285 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1286 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1287 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1288 1289 /* 1290 * impl functions 1291 */ 1292 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1293 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1294 int mptsas_ioc_reset(mptsas_t *mpt, int); 1295 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1296 ddi_acc_handle_t accessp); 1297 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1298 ddi_acc_handle_t accessp); 1299 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1300 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1301 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1302 uint32_t SGEaddress32); 1303 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1304 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1305 uint8_t pageversion, uint16_t extpagelength, 1306 uint32_t SGEflagslength, uint32_t SGEaddress32); 1307 1308 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1309 struct scsi_pkt **pkt); 1310 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1311 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1312 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1313 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1314 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1315 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1316 1317 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1318 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1319 int mode); 1320 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1321 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1322 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1323 int mptsas_restart_ioc(mptsas_t *mpt); 1324 void mptsas_update_driver_data(struct mptsas *mpt); 1325 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1326 1327 /* 1328 * init functions 1329 */ 1330 int mptsas_ioc_get_facts(mptsas_t *mpt); 1331 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1332 int mptsas_ioc_enable_port(mptsas_t *mpt); 1333 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1334 int mptsas_ioc_init(mptsas_t *mpt); 1335 1336 /* 1337 * configuration pages operation 1338 */ 1339 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1340 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1341 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1342 uint16_t *slot_num, uint16_t *enclosure); 1343 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1344 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1345 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1346 mptsas_smp_t *info); 1347 int mptsas_set_ioc_params(mptsas_t *mpt); 1348 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1349 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1350 uint64_t *sas_wwn, uint8_t *portwidth); 1351 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1352 int 1353 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1354 smhba_info_t *info); 1355 int 1356 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1357 smhba_info_t *info); 1358 int 1359 mptsas_get_manufacture_page0(mptsas_t *mpt); 1360 void 1361 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1362 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1363 int mptsas_smhba_phy_init(mptsas_t *mpt); 1364 /* 1365 * RAID functions 1366 */ 1367 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1368 int mptsas_get_raid_info(mptsas_t *mpt); 1369 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1370 uint8_t physdisknum); 1371 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1372 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1373 1374 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1375 /* 1376 * debugging. 1377 */ 1378 #if defined(MPTSAS_DEBUG) 1379 1380 void mptsas_printf(char *fmt, ...); 1381 1382 #define MPTSAS_DBGPR(m, args) \ 1383 if (mptsas_debug_flags & (m)) \ 1384 mptsas_printf args 1385 #else /* ! defined(MPTSAS_DEBUG) */ 1386 #define MPTSAS_DBGPR(m, args) 1387 #endif /* defined(MPTSAS_DEBUG) */ 1388 1389 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1390 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1391 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1392 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1393 1394 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1395 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1396 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1397 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1398 1399 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1400 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1401 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1402 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1403 1404 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1405 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1406 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1407 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1408 1409 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1410 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1411 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1412 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1413 1414 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1415 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1416 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1417 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1418 1419 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1420 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1421 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1422 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1423 1424 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1425 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1426 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1427 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1428 1429 /* 1430 * auto request sense 1431 */ 1432 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1433 (pkt)->pkt_flags = (flag), \ 1434 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1435 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1436 (pkt)->pkt_address.a_lun 1437 1438 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1439 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1440 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1441 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1442 1443 1444 #ifdef __cplusplus 1445 } 1446 #endif 1447 1448 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1449