1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved. 26 */ 27 28 /* 29 * Copyright (c) 2000 to 2010, LSI Corporation. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms of all code within 33 * this file that is exclusively owned by LSI, with or without 34 * modification, is permitted provided that, in addition to the CDDL 1.0 35 * License requirements, the following conditions are met: 36 * 37 * Neither the name of the author nor the names of its contributors may be 38 * used to endorse or promote products derived from this software without 39 * specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 52 * DAMAGE. 53 */ 54 55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 57 58 #include <sys/byteorder.h> 59 #include <sys/isa_defs.h> 60 #include <sys/sunmdi.h> 61 #include <sys/mdi_impldefs.h> 62 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 63 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 64 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 65 66 #ifdef __cplusplus 67 extern "C" { 68 #endif 69 70 /* 71 * Compile options 72 */ 73 #ifdef DEBUG 74 #define MPTSAS_DEBUG /* turn on debugging code */ 75 #endif /* DEBUG */ 76 77 #define MPTSAS_INITIAL_SOFT_SPACE 4 78 79 #define MAX_MPI_PORTS 16 80 81 /* 82 * Note below macro definition and data type definition 83 * are used for phy mask handling, it should be changed 84 * simultaneously. 85 */ 86 #define MPTSAS_MAX_PHYS 16 87 typedef uint16_t mptsas_phymask_t; 88 89 #define MPTSAS_INVALID_DEVHDL 0xffff 90 #define MPTSAS_SATA_GUID "sata-guid" 91 92 /* 93 * MPT HW defines 94 */ 95 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 96 #define MPTSAS_MAX_DISKS_IN_VOL 10 97 #define MPTSAS_MAX_HOTSPARES 2 98 #define MPTSAS_MAX_RAIDVOLS 2 99 #define MPTSAS_MAX_RAIDCONFIGS 5 100 101 /* 102 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 103 * plus two means the prefix 'w' and end of the string '\0'. 104 */ 105 #define MPTSAS_WWN_STRLEN (16 + 2) 106 #define MPTSAS_MAX_GUID_LEN 64 107 108 /* 109 * DMA routine flags 110 */ 111 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 112 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 113 #define MPTSAS_DMA_HANDLE_BOUND 0x8 114 115 /* 116 * If the HBA supports DMA or bus-mastering, you may have your own 117 * scatter-gather list for physically non-contiguous memory in one 118 * I/O operation; if so, there's probably a size for that list. 119 * It must be placed in the ddi_dma_lim_t structure, so that the system 120 * DMA-support routines can use it to break up the I/O request, so we 121 * define it here. 122 */ 123 #if defined(__sparc) 124 #define MPTSAS_MAX_DMA_SEGS 1 125 #define MPTSAS_MAX_CMD_SEGS 1 126 #else 127 #define MPTSAS_MAX_DMA_SEGS 256 128 #define MPTSAS_MAX_CMD_SEGS 257 129 #endif 130 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 131 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 132 133 /* 134 * Caculating how many 64-bit DMA simple elements can be stored in the first 135 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 136 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 137 * size. 138 */ 139 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 140 ((mpt->m_req_frame_size - \ 141 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 142 143 /* 144 * Scatter-gather list structure defined by HBA hardware 145 */ 146 typedef struct NcrTableIndirect { /* Table Indirect entries */ 147 uint32_t count; /* 24 bit count */ 148 union { 149 uint32_t address32; /* 32 bit address */ 150 struct { 151 uint32_t Low; 152 uint32_t High; 153 } address64; /* 64 bit address */ 154 } addr; 155 } mptti_t; 156 157 /* 158 * preferred pkt_private length in 64-bit quantities 159 */ 160 #ifdef _LP64 161 #define PKT_PRIV_SIZE 2 162 #define PKT_PRIV_LEN 16 /* in bytes */ 163 #else /* _ILP32 */ 164 #define PKT_PRIV_SIZE 1 165 #define PKT_PRIV_LEN 8 /* in bytes */ 166 #endif 167 168 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 169 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 170 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 171 172 /* 173 * get offset of item in structure 174 */ 175 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 176 177 /* 178 * WWID provided by LSI firmware is generated by firmware but the WWID is not 179 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 180 * address. According LSI's confirmation, the top nibble of RAID WWID is 181 * meanless, so the consensus between Solaris and OBP is to replace top nibble 182 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 183 * format unit address. 184 */ 185 #define MPTSAS_RAID_WWID(wwid) \ 186 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 187 188 typedef struct mptsas_target { 189 uint64_t m_sas_wwn; /* hash key1 */ 190 mptsas_phymask_t m_phymask; /* hash key2 */ 191 /* 192 * m_dr_flag is a flag for DR, make sure the member 193 * take the place of dr_flag of mptsas_hash_data. 194 */ 195 uint8_t m_dr_flag; /* dr_flag */ 196 uint16_t m_devhdl; 197 uint32_t m_deviceinfo; 198 uint8_t m_phynum; 199 uint32_t m_dups; 200 int32_t m_timeout; 201 int32_t m_timebase; 202 int32_t m_t_throttle; 203 int32_t m_t_ncmds; 204 int32_t m_reset_delay; 205 int32_t m_t_nwait; 206 207 uint16_t m_qfull_retry_interval; 208 uint8_t m_qfull_retries; 209 uint16_t m_enclosure; 210 uint16_t m_slot_num; 211 uint32_t m_tgt_unconfigured; 212 uint8_t m_led_status; 213 214 } mptsas_target_t; 215 216 typedef struct mptsas_smp { 217 uint64_t m_sasaddr; /* hash key1 */ 218 mptsas_phymask_t m_phymask; /* hash key2 */ 219 uint8_t reserved1; 220 uint16_t m_devhdl; 221 uint32_t m_deviceinfo; 222 uint16_t m_pdevhdl; 223 uint32_t m_pdevinfo; 224 } mptsas_smp_t; 225 226 typedef struct mptsas_hash_data { 227 uint64_t key1; 228 mptsas_phymask_t key2; 229 uint8_t dr_flag; 230 uint16_t devhdl; 231 uint32_t device_info; 232 } mptsas_hash_data_t; 233 234 typedef struct mptsas_cache_frames { 235 ddi_dma_handle_t m_dma_hdl; 236 ddi_acc_handle_t m_acc_hdl; 237 caddr_t m_frames_addr; 238 uint32_t m_phys_addr; 239 } mptsas_cache_frames_t; 240 241 typedef struct mptsas_cmd { 242 uint_t cmd_flags; /* flags from scsi_init_pkt */ 243 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 244 ddi_dma_cookie_t cmd_cookie; 245 uint_t cmd_cookiec; 246 uint_t cmd_winindex; 247 uint_t cmd_nwin; 248 uint_t cmd_cur_cookie; 249 off_t cmd_dma_offset; 250 size_t cmd_dma_len; 251 uint32_t cmd_totaldmacount; 252 253 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 254 ddi_dma_cookie_t cmd_arqcookie; 255 struct buf *cmd_arq_buf; 256 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 257 ddi_dma_cookie_t cmd_ext_arqcookie; 258 struct buf *cmd_ext_arq_buf; 259 260 int cmd_pkt_flags; 261 262 /* timer for command in active slot */ 263 int cmd_active_timeout; 264 265 struct scsi_pkt *cmd_pkt; 266 struct scsi_arq_status cmd_scb; 267 uchar_t cmd_cdblen; /* length of cdb */ 268 uchar_t cmd_rqslen; /* len of requested rqsense */ 269 uchar_t cmd_privlen; 270 uint_t cmd_scblen; 271 uint32_t cmd_dmacount; 272 uint64_t cmd_dma_addr; 273 uchar_t cmd_age; 274 ushort_t cmd_qfull_retries; 275 uchar_t cmd_queued; /* true if queued */ 276 struct mptsas_cmd *cmd_linkp; 277 mptti_t *cmd_sg; /* Scatter/Gather structure */ 278 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 279 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 280 uint32_t cmd_slot; 281 uint32_t ioc_cmd_slot; 282 283 mptsas_cache_frames_t *cmd_extra_frames; 284 285 uint32_t cmd_rfm; 286 mptsas_target_t *cmd_tgt_addr; 287 } mptsas_cmd_t; 288 289 /* 290 * These are the defined cmd_flags for this structure. 291 */ 292 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 293 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 294 #define CFLAG_FINISHED 0x000004 /* command completed */ 295 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 296 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 297 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 298 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 299 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 300 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 301 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 302 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 303 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 304 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 305 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 306 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 307 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 308 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 309 #define CFLAG_FREE 0x010000 /* packet is on free list */ 310 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 311 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 312 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 313 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 314 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 315 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 316 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 317 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 318 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 319 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 320 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 321 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 322 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 323 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 324 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 325 326 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 327 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 328 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 329 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 330 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 331 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 337 338 #define MPTSAS_HASH_ARRAY_SIZE 16 339 /* 340 * hash table definition 341 */ 342 343 #define MPTSAS_HASH_FIRST 0xffff 344 #define MPTSAS_HASH_NEXT 0x0000 345 346 typedef struct mptsas_dma_alloc_state 347 { 348 ddi_dma_handle_t handle; 349 caddr_t memp; 350 size_t size; 351 ddi_acc_handle_t accessp; 352 ddi_dma_cookie_t cookie; 353 } mptsas_dma_alloc_state_t; 354 355 /* 356 * passthrough request structure 357 */ 358 typedef struct mptsas_pt_request { 359 uint8_t *request; 360 uint32_t request_size; 361 uint32_t data_size; 362 uint32_t dataout_size; 363 uint32_t direction; 364 ddi_dma_cookie_t data_cookie; 365 ddi_dma_cookie_t dataout_cookie; 366 } mptsas_pt_request_t; 367 368 /* 369 * config page request structure 370 */ 371 typedef struct mptsas_config_request { 372 uint32_t page_address; 373 uint8_t action; 374 uint8_t page_type; 375 uint8_t page_number; 376 uint8_t page_length; 377 uint8_t page_version; 378 uint8_t ext_page_type; 379 uint16_t ext_page_length; 380 } mptsas_config_request_t; 381 382 typedef struct mptsas_fw_diagnostic_buffer { 383 mptsas_dma_alloc_state_t buffer_data; 384 uint8_t extended_type; 385 uint8_t buffer_type; 386 uint8_t force_release; 387 uint32_t product_specific[23]; 388 uint8_t immediate; 389 uint8_t enabled; 390 uint8_t valid_data; 391 uint8_t owned_by_firmware; 392 uint32_t unique_id; 393 } mptsas_fw_diagnostic_buffer_t; 394 395 /* 396 * FW diag request structure 397 */ 398 typedef struct mptsas_diag_request { 399 mptsas_fw_diagnostic_buffer_t *pBuffer; 400 uint8_t function; 401 } mptsas_diag_request_t; 402 403 typedef struct mptsas_hash_node { 404 void *data; 405 struct mptsas_hash_node *next; 406 } mptsas_hash_node_t; 407 408 typedef struct mptsas_hash_table { 409 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 410 /* 411 * last position in traverse 412 */ 413 struct mptsas_hash_node *cur; 414 uint16_t line; 415 416 } mptsas_hash_table_t; 417 418 /* 419 * RAID volume information 420 */ 421 typedef struct mptsas_raidvol { 422 ushort_t m_israid; 423 uint16_t m_raidhandle; 424 uint64_t m_raidwwid; 425 uint8_t m_state; 426 uint32_t m_statusflags; 427 uint32_t m_settings; 428 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 429 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 430 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 431 uint64_t m_raidsize; 432 int m_raidlevel; 433 int m_ndisks; 434 mptsas_target_t *m_raidtgt; 435 } mptsas_raidvol_t; 436 437 /* 438 * RAID configurations 439 */ 440 typedef struct mptsas_raidconfig { 441 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 442 uint16_t m_physdisk_devhdl[ 443 MPTSAS_MAX_DISKS_IN_CONFIG]; 444 uint8_t m_native; 445 } m_raidconfig_t; 446 447 /* 448 * Structure to hold active outstanding cmds. Also, keep 449 * timeout on a per target basis. 450 */ 451 typedef struct mptsas_slots { 452 mptsas_hash_table_t m_tgttbl; 453 mptsas_hash_table_t m_smptbl; 454 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 455 uint8_t m_num_raid_configs; 456 uint16_t m_tags; 457 size_t m_size; 458 uint16_t m_n_slots; 459 mptsas_cmd_t *m_slot[1]; 460 } mptsas_slots_t; 461 462 /* 463 * Structure to hold command and packets for event ack 464 * and task management commands. 465 */ 466 typedef struct m_event_struct { 467 struct mptsas_cmd m_event_cmd; 468 struct m_event_struct *m_event_linkp; 469 /* 470 * event member record the failure event and eventcntx 471 * event member would be used in send ack pending process 472 */ 473 uint32_t m_event; 474 uint32_t m_eventcntx; 475 uint_t in_use; 476 struct scsi_pkt m_event_pkt; /* must be last */ 477 /* ... scsi_pkt_size() */ 478 } m_event_struct_t; 479 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 480 sizeof (struct scsi_pkt) + scsi_pkt_size()) 481 482 #define MAX_IOC_COMMANDS 8 483 484 /* 485 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 486 * A new event ack command requests mptsas_cmd and scsi_pkt structures 487 * from this pool, and returns it back when done. 488 */ 489 490 typedef struct m_replyh_arg { 491 void *mpt; 492 uint32_t rfm; 493 } m_replyh_arg_t; 494 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 495 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 496 497 /* 498 * Flags for DR handler topology change 499 */ 500 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 501 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 502 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 503 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 504 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 505 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 506 507 typedef struct mptsas_topo_change_list { 508 void *mpt; 509 uint_t event; 510 union { 511 uint8_t physport; 512 mptsas_phymask_t phymask; 513 } un; 514 uint16_t devhdl; 515 void *object; 516 uint8_t flags; 517 struct mptsas_topo_change_list *next; 518 } mptsas_topo_change_list_t; 519 520 521 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 522 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 523 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 524 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 525 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 526 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 527 528 /* 529 * Status types when calling mptsas_get_target_device_info 530 */ 531 #define DEV_INFO_SUCCESS 0x0 532 #define DEV_INFO_FAIL_PAGE0 0x1 533 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 534 #define DEV_INFO_PHYS_DISK 0x3 535 #define DEV_INFO_FAIL_ALLOC 0x4 536 537 /* 538 * mpt hotplug event defines 539 */ 540 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 541 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 542 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 543 544 /* 545 * SMP target hotplug events 546 */ 547 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 548 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 549 #define MPTSAS_DR_EVENT_MASK 0x3F 550 551 /* 552 * mpt hotplug status definition for m_dr_flag 553 */ 554 555 /* 556 * MPTSAS_DR_INACTIVE 557 * 558 * The target is in a normal operating state. 559 * No dynamic reconfiguration operation is in progress. 560 */ 561 #define MPTSAS_DR_INACTIVE 0x0 562 /* 563 * MPTSAS_DR_INTRANSITION 564 * 565 * The target is in a transition mode since 566 * hotplug event happens and offline procedure has not 567 * been finished 568 */ 569 #define MPTSAS_DR_INTRANSITION 0x1 570 571 typedef struct mptsas_tgt_private { 572 int t_lun; 573 struct mptsas_target *t_private; 574 } mptsas_tgt_private_t; 575 576 /* 577 * The following defines are used in mptsas_set_init_mode to track the current 578 * state as we progress through reprogramming the HBA from target mode into 579 * initiator mode. 580 */ 581 582 #define IOUC_READ_PAGE0 0x00000100 583 #define IOUC_READ_PAGE1 0x00000200 584 #define IOUC_WRITE_PAGE1 0x00000400 585 #define IOUC_DONE 0x00000800 586 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 587 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 588 589 /* 590 * Last allocated slot is used for TM requests. Since only m_max_requests 591 * frames are allocated, the last SMID will be m_max_requests - 1. 592 */ 593 #define MPTSAS_SLOTS_SIZE(mpt) \ 594 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 595 mpt->m_max_requests)) 596 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 597 598 /* 599 * Macro for phy_flags 600 */ 601 602 typedef struct smhba_info { 603 kmutex_t phy_mutex; 604 uint8_t phy_id; 605 uint64_t sas_addr; 606 char path[8]; 607 uint16_t owner_devhdl; 608 uint16_t attached_devhdl; 609 uint8_t attached_phy_identify; 610 uint32_t attached_phy_info; 611 uint8_t programmed_link_rate; 612 uint8_t hw_link_rate; 613 uint8_t change_count; 614 uint32_t phy_info; 615 uint8_t negotiated_link_rate; 616 uint8_t port_num; 617 kstat_t *phy_stats; 618 uint32_t invalid_dword_count; 619 uint32_t running_disparity_error_count; 620 uint32_t loss_of_dword_sync_count; 621 uint32_t phy_reset_problem_count; 622 void *mpt; 623 } smhba_info_t; 624 625 typedef struct mptsas_phy_info { 626 uint8_t port_num; 627 uint8_t port_flags; 628 uint16_t ctrl_devhdl; 629 uint32_t phy_device_type; 630 uint16_t attached_devhdl; 631 mptsas_phymask_t phy_mask; 632 smhba_info_t smhba_info; 633 } mptsas_phy_info_t; 634 635 636 typedef struct mptsas_doneq_thread_arg { 637 void *mpt; 638 uint64_t t; 639 } mptsas_doneq_thread_arg_t; 640 641 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 642 typedef struct mptsas_doneq_thread_list { 643 mptsas_cmd_t *doneq; 644 mptsas_cmd_t **donetail; 645 kthread_t *threadp; 646 kcondvar_t cv; 647 ushort_t reserv1; 648 uint32_t reserv2; 649 kmutex_t mutex; 650 uint32_t flag; 651 uint32_t len; 652 mptsas_doneq_thread_arg_t arg; 653 } mptsas_doneq_thread_list_t; 654 655 typedef struct mptsas { 656 int m_instance; 657 658 struct mptsas *m_next; 659 660 scsi_hba_tran_t *m_tran; 661 smp_hba_tran_t *m_smptran; 662 kmutex_t m_mutex; 663 kmutex_t m_passthru_mutex; 664 kcondvar_t m_cv; 665 kcondvar_t m_passthru_cv; 666 kcondvar_t m_fw_cv; 667 kcondvar_t m_config_cv; 668 kcondvar_t m_fw_diag_cv; 669 dev_info_t *m_dip; 670 671 /* 672 * soft state flags 673 */ 674 uint_t m_softstate; 675 676 struct mptsas_slots *m_active; /* outstanding cmds */ 677 678 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 679 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 680 681 kmutex_t m_tx_waitq_mutex; 682 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 683 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 684 int m_tx_draining; /* TX queue draining flag */ 685 686 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 687 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 688 689 /* 690 * variables for helper threads (fan-out interrupts) 691 */ 692 mptsas_doneq_thread_list_t *m_doneq_thread_id; 693 uint32_t m_doneq_thread_n; 694 uint32_t m_doneq_thread_threshold; 695 uint32_t m_doneq_length_threshold; 696 uint32_t m_doneq_len; 697 kcondvar_t m_doneq_thread_cv; 698 kmutex_t m_doneq_mutex; 699 700 int m_ncmds; /* number of outstanding commands */ 701 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 702 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 703 704 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 705 706 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 707 708 ushort_t m_devid; /* device id of chip. */ 709 uchar_t m_revid; /* revision of chip. */ 710 uint16_t m_svid; /* subsystem Vendor ID of chip */ 711 uint16_t m_ssid; /* subsystem Device ID of chip */ 712 713 uchar_t m_sync_offset; /* default offset for this chip. */ 714 715 timeout_id_t m_quiesce_timeid; 716 717 ddi_dma_handle_t m_dma_req_frame_hdl; 718 ddi_acc_handle_t m_acc_req_frame_hdl; 719 ddi_dma_handle_t m_dma_reply_frame_hdl; 720 ddi_acc_handle_t m_acc_reply_frame_hdl; 721 ddi_dma_handle_t m_dma_free_queue_hdl; 722 ddi_acc_handle_t m_acc_free_queue_hdl; 723 ddi_dma_handle_t m_dma_post_queue_hdl; 724 ddi_acc_handle_t m_acc_post_queue_hdl; 725 726 /* 727 * list of reset notification requests 728 */ 729 struct scsi_reset_notify_entry *m_reset_notify_listf; 730 731 /* 732 * qfull handling 733 */ 734 timeout_id_t m_restart_cmd_timeid; 735 736 /* 737 * scsi reset delay per bus 738 */ 739 uint_t m_scsi_reset_delay; 740 741 int m_pm_idle_delay; 742 743 uchar_t m_polled_intr; /* intr was polled. */ 744 uchar_t m_suspended; /* true if driver is suspended */ 745 746 struct kmem_cache *m_kmem_cache; 747 struct kmem_cache *m_cache_frames; 748 749 /* 750 * hba options. 751 */ 752 uint_t m_options; 753 754 int m_in_callback; 755 756 int m_power_level; /* current power level */ 757 758 int m_busy; /* power management busy state */ 759 760 off_t m_pmcsr_offset; /* PMCSR offset */ 761 762 ddi_acc_handle_t m_config_handle; 763 764 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 765 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 766 ddi_device_acc_attr_t m_dev_acc_attr; 767 ddi_device_acc_attr_t m_reg_acc_attr; 768 769 /* 770 * request/reply variables 771 */ 772 caddr_t m_req_frame; 773 uint64_t m_req_frame_dma_addr; 774 caddr_t m_reply_frame; 775 uint64_t m_reply_frame_dma_addr; 776 caddr_t m_free_queue; 777 uint64_t m_free_queue_dma_addr; 778 caddr_t m_post_queue; 779 uint64_t m_post_queue_dma_addr; 780 781 m_replyh_arg_t *m_replyh_args; 782 783 uint16_t m_max_requests; 784 uint16_t m_req_frame_size; 785 786 /* 787 * Max frames per request reprted in IOC Facts 788 */ 789 uint8_t m_max_chain_depth; 790 /* 791 * Max frames per request which is used in reality. It's adjusted 792 * according DMA SG length attribute, and shall not exceed the 793 * m_max_chain_depth. 794 */ 795 uint8_t m_max_request_frames; 796 797 uint16_t m_free_queue_depth; 798 uint16_t m_post_queue_depth; 799 uint16_t m_max_replies; 800 uint32_t m_free_index; 801 uint32_t m_post_index; 802 uint8_t m_reply_frame_size; 803 uint32_t m_ioc_capabilities; 804 805 /* 806 * indicates if the firmware was upload by the driver 807 * at boot time 808 */ 809 ushort_t m_fwupload; 810 811 uint16_t m_productid; 812 813 /* 814 * per instance data structures for dma memory resources for 815 * MPI handshake protocol. only one handshake cmd can run at a time. 816 */ 817 ddi_dma_handle_t m_hshk_dma_hdl; 818 ddi_acc_handle_t m_hshk_acc_hdl; 819 caddr_t m_hshk_memp; 820 size_t m_hshk_dma_size; 821 822 /* Firmware version on the card at boot time */ 823 uint32_t m_fwversion; 824 825 /* MSI specific fields */ 826 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 827 int m_intr_type; /* What type of interrupt */ 828 int m_intr_cnt; /* # of intrs count returned */ 829 size_t m_intr_size; /* Size of intr array */ 830 uint_t m_intr_pri; /* Interrupt priority */ 831 int m_intr_cap; /* Interrupt capabilities */ 832 ddi_taskq_t *m_event_taskq; 833 834 /* SAS specific information */ 835 836 union { 837 uint64_t m_base_wwid; /* Base WWID */ 838 struct { 839 #ifdef _BIG_ENDIAN 840 uint32_t m_base_wwid_hi; 841 uint32_t m_base_wwid_lo; 842 #else 843 uint32_t m_base_wwid_lo; 844 uint32_t m_base_wwid_hi; 845 #endif 846 } sasaddr; 847 } un; 848 849 uint8_t m_num_phys; /* # of PHYs */ 850 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 851 uint8_t m_port_chng; /* initiator port changes */ 852 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 853 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 854 855 /* FMA Capabilities */ 856 int m_fm_capabilities; 857 ddi_taskq_t *m_dr_taskq; 858 int m_mpxio_enable; 859 uint8_t m_done_traverse_dev; 860 uint8_t m_done_traverse_smp; 861 int m_diag_action_in_progress; 862 uint16_t m_dev_handle; 863 uint16_t m_smp_devhdl; 864 865 /* 866 * Event recording 867 */ 868 uint8_t m_event_index; 869 uint32_t m_event_number; 870 uint32_t m_event_mask[4]; 871 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 872 873 /* 874 * FW diag Buffer List 875 */ 876 mptsas_fw_diagnostic_buffer_t 877 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 878 879 /* 880 * Event Replay flag (MUR support) 881 */ 882 uint8_t m_event_replay; 883 884 /* 885 * IR Capable flag 886 */ 887 uint8_t m_ir_capable; 888 889 /* 890 * Is HBA processing a diag reset? 891 */ 892 uint8_t m_in_reset; 893 894 /* 895 * per instance cmd data structures for task management cmds 896 */ 897 m_event_struct_t m_event_task_mgmt; /* must be last */ 898 /* ... scsi_pkt_size */ 899 } mptsas_t; 900 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 901 sizeof (struct scsi_pkt) + scsi_pkt_size()) 902 /* 903 * Only one of below two conditions is satisfied, we 904 * think the target is associated to the iport and 905 * allow call into mptsas_probe_lun(). 906 * 1. physicalsport == physport 907 * 2. (phymask & (1 << physport)) == 0 908 * The condition #2 is because LSI uses lowest PHY 909 * number as the value of physical port when auto port 910 * configuration. 911 */ 912 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 913 ((physicalport == physport) || (dynamicport && (phymask & \ 914 (1 << physport)))) 915 916 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 917 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 918 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 919 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 920 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 921 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 922 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 923 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 924 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 925 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 926 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 927 928 /* 929 * These should eventually migrate into the mpt header files 930 * that may become the /kernel/misc/mpt module... 931 */ 932 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 933 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 934 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 935 mptsas_put_msg_Function(hdl, mp, Function); \ 936 mptsas_put_msg_Lun(hdl, mp, Lun) 937 938 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 939 ddi_put16(hdl, &(mp)->DevHandle, (val)) 940 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 941 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 942 #define mptsas_put_msg_Function(hdl, mp, val) \ 943 ddi_put8(hdl, &(mp)->Function, (val)) 944 #define mptsas_put_msg_Lun(hdl, mp, val) \ 945 ddi_put8(hdl, &(mp)->LUN[1], (val)) 946 947 #define mptsas_get_msg_Function(hdl, mp) \ 948 ddi_get8(hdl, &(mp)->Function) 949 950 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 951 ddi_get8(hdl, &(mp)->MsgFlags) 952 953 #define MPTSAS_ENABLE_DRWE(hdl) \ 954 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 955 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 956 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 957 MPI2_WRSEQ_1ST_KEY_VALUE); \ 958 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 959 MPI2_WRSEQ_2ND_KEY_VALUE); \ 960 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 961 MPI2_WRSEQ_3RD_KEY_VALUE); \ 962 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 963 MPI2_WRSEQ_4TH_KEY_VALUE); \ 964 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 965 MPI2_WRSEQ_5TH_KEY_VALUE); \ 966 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 967 MPI2_WRSEQ_6TH_KEY_VALUE); 968 969 /* 970 * m_options flags 971 */ 972 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 973 974 /* 975 * m_softstate flags 976 */ 977 #define MPTSAS_SS_DRAINING 0x02 978 #define MPTSAS_SS_QUIESCED 0x04 979 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 980 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 981 982 /* 983 * regspec defines. 984 */ 985 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 986 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 987 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 988 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 989 990 /* 991 * Handy constants 992 */ 993 #define FALSE 0 994 #define TRUE 1 995 #define UNDEFINED -1 996 #define FAILED -2 997 998 /* 999 * power management. 1000 */ 1001 #define MPTSAS_POWER_ON(mpt) { \ 1002 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1003 PCI_PMCSR_D0); \ 1004 delay(drv_usectohz(10000)); \ 1005 (void) pci_restore_config_regs(mpt->m_dip); \ 1006 mptsas_setup_cmd_reg(mpt); \ 1007 } 1008 1009 #define MPTSAS_POWER_OFF(mpt) { \ 1010 (void) pci_save_config_regs(mpt->m_dip); \ 1011 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1012 PCI_PMCSR_D3HOT); \ 1013 mpt->m_power_level = PM_LEVEL_D3; \ 1014 } 1015 1016 /* 1017 * inq_dtype: 1018 * Bits 5 through 7 are the Peripheral Device Qualifier 1019 * 001b: device not connected to the LUN 1020 * Bits 0 through 4 are the Peripheral Device Type 1021 * 1fh: Unknown or no device type 1022 * 1023 * Although the inquiry may return success, the following value 1024 * means no valid LUN connected. 1025 */ 1026 #define MPTSAS_VALID_LUN(sd_inq) \ 1027 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1028 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1029 1030 /* 1031 * Default is to have 10 retries on receiving QFULL status and 1032 * each retry to be after 100 ms. 1033 */ 1034 #define QFULL_RETRIES 10 1035 #define QFULL_RETRY_INTERVAL 100 1036 1037 /* 1038 * Handy macros 1039 */ 1040 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1041 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1042 1043 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1044 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1045 1046 /* 1047 * poll time for mptsas_pollret() and mptsas_wait_intr() 1048 */ 1049 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1050 1051 /* 1052 * default time for mptsas_do_passthru 1053 */ 1054 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1055 1056 /* 1057 * macro to return the effective address of a given per-target field 1058 */ 1059 #define EFF_ADDR(start, offset) ((start) + (offset)) 1060 1061 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1062 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1063 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1064 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1065 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1066 1067 1068 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1069 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1070 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1071 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1072 1073 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1074 1075 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1076 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1077 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1078 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1079 1080 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1081 &(mpt)->m_reg->HostInterruptStatus)) 1082 1083 #define MPTSAS_SET_SIGP(P) \ 1084 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1085 1086 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1087 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1088 1089 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1090 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1091 1092 1093 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1094 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1095 req_desc_lo);\ 1096 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1097 req_desc_hi); 1098 1099 #define INTPENDING(mpt) \ 1100 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1101 1102 /* 1103 * Mask all interrupts to disable 1104 */ 1105 #define MPTSAS_DISABLE_INTR(mpt) \ 1106 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1107 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1108 1109 /* 1110 * Mask Doorbell and Reset interrupts to enable reply desc int. 1111 */ 1112 #define MPTSAS_ENABLE_INTR(mpt) \ 1113 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1114 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1115 1116 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1117 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1118 1119 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1120 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1121 1122 #define ClrSetBits32(hdl, reg, clr, set) \ 1123 ddi_put32(hdl, (reg), \ 1124 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1125 1126 #define ClrSetBits(reg, clr, set) \ 1127 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1128 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1129 1130 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1131 if ((cmdp = mpt->m_waitq) != NULL) { \ 1132 /* If the queue is now empty fix the tail pointer */ \ 1133 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1134 mpt->m_waitqtail = &mpt->m_waitq; \ 1135 cmdp->cmd_linkp = NULL; \ 1136 cmdp->cmd_queued = FALSE; \ 1137 } 1138 1139 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1140 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1141 /* If the queue is now empty fix the tail pointer */ \ 1142 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1143 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1144 cmdp->cmd_linkp = NULL; \ 1145 cmdp->cmd_queued = FALSE; \ 1146 } 1147 1148 /* 1149 * defaults for the global properties 1150 */ 1151 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1152 #define DEFAULT_TAG_AGE_LIMIT 2 1153 #define DEFAULT_WD_TICK 10 1154 1155 /* 1156 * invalid hostid. 1157 */ 1158 #define MPTSAS_INVALID_HOSTID -1 1159 1160 /* 1161 * Get/Set hostid from SCSI port configuration page 1162 */ 1163 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1164 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1165 1166 /* 1167 * Config space. 1168 */ 1169 #define MPTSAS_LATENCY_TIMER 0x40 1170 1171 /* 1172 * Offset to firmware version 1173 */ 1174 #define MPTSAS_FW_VERSION_OFFSET 9 1175 1176 /* 1177 * Offset and masks to get at the ProductId field 1178 */ 1179 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1180 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1181 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1182 1183 /* 1184 * Subsystem ID for HBAs. 1185 */ 1186 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1187 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1188 1189 /* 1190 * reset delay tick 1191 */ 1192 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1193 1194 /* 1195 * Ioc reset return values 1196 */ 1197 #define MPTSAS_RESET_FAIL -1 1198 #define MPTSAS_NO_RESET 0 1199 #define MPTSAS_SUCCESS_HARDRESET 1 1200 #define MPTSAS_SUCCESS_MUR 2 1201 1202 /* 1203 * throttle support. 1204 */ 1205 #define MAX_THROTTLE 32 1206 #define HOLD_THROTTLE 0 1207 #define DRAIN_THROTTLE -1 1208 #define QFULL_THROTTLE -2 1209 1210 /* 1211 * Passthrough/config request flags 1212 */ 1213 #define MPTSAS_DATA_ALLOCATED 0x0001 1214 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1215 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1216 #define MPTSAS_ADDRESS_REPLY 0x0008 1217 #define MPTSAS_CMD_TIMEOUT 0x0010 1218 1219 /* 1220 * response code tlr flag 1221 */ 1222 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1223 1224 /* 1225 * System Events 1226 */ 1227 #ifndef DDI_VENDOR_LSI 1228 #define DDI_VENDOR_LSI "LSI" 1229 #endif /* DDI_VENDOR_LSI */ 1230 1231 /* 1232 * Shared functions 1233 */ 1234 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1235 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1236 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1237 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1238 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1239 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1240 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1241 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1242 uint8_t pageversion, uint8_t pagelength, uint32_t 1243 SGEflagslength, uint32_t SGEaddress32); 1244 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1245 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1246 uint8_t pageversion, uint16_t extpagelength, 1247 uint32_t SGEflagslength, uint32_t SGEaddress32); 1248 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1249 uint8_t type, int mode); 1250 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1251 uint8_t type, int mode); 1252 int mptsas_download_firmware(); 1253 int mptsas_can_download_firmware(); 1254 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1255 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1256 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1257 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1258 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1259 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1260 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1261 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1262 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1263 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1264 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1265 1266 /* 1267 * impl functions 1268 */ 1269 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1270 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1271 int mptsas_ioc_reset(mptsas_t *mpt, int); 1272 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1273 ddi_acc_handle_t accessp); 1274 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1275 ddi_acc_handle_t accessp); 1276 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1277 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1278 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1279 uint32_t SGEaddress32); 1280 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1281 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1282 uint8_t pageversion, uint16_t extpagelength, 1283 uint32_t SGEflagslength, uint32_t SGEaddress32); 1284 1285 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1286 struct scsi_pkt **pkt); 1287 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1288 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1289 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1290 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1291 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1292 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1293 1294 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1295 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1296 int mode); 1297 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1298 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1299 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1300 int mptsas_restart_ioc(mptsas_t *mpt); 1301 void mptsas_update_driver_data(struct mptsas *mpt); 1302 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1303 1304 /* 1305 * init functions 1306 */ 1307 int mptsas_ioc_get_facts(mptsas_t *mpt); 1308 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1309 int mptsas_ioc_enable_port(mptsas_t *mpt); 1310 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1311 int mptsas_ioc_init(mptsas_t *mpt); 1312 1313 /* 1314 * configuration pages operation 1315 */ 1316 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1317 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1318 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1319 uint16_t *slot_num, uint16_t *enclosure); 1320 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1321 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1322 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1323 mptsas_smp_t *info); 1324 int mptsas_set_ioc_params(mptsas_t *mpt); 1325 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1326 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1327 uint64_t *sas_wwn, uint8_t *portwidth); 1328 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1329 int 1330 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1331 smhba_info_t *info); 1332 int 1333 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1334 smhba_info_t *info); 1335 int 1336 mptsas_get_manufacture_page0(mptsas_t *mpt); 1337 void 1338 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1339 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1340 int mptsas_smhba_phy_init(mptsas_t *mpt); 1341 /* 1342 * RAID functions 1343 */ 1344 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1345 int mptsas_get_raid_info(mptsas_t *mpt); 1346 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1347 uint8_t physdisknum); 1348 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1349 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1350 1351 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1352 /* 1353 * debugging. 1354 */ 1355 #if defined(MPTSAS_DEBUG) 1356 1357 void mptsas_printf(char *fmt, ...); 1358 1359 #define MPTSAS_DBGPR(m, args) \ 1360 if (mptsas_debug_flags & (m)) \ 1361 mptsas_printf args 1362 #else /* ! defined(MPTSAS_DEBUG) */ 1363 #define MPTSAS_DBGPR(m, args) 1364 #endif /* defined(MPTSAS_DEBUG) */ 1365 1366 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1367 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1368 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1369 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1370 1371 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1372 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1373 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1374 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1375 1376 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1377 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1378 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1379 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1380 1381 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1382 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1383 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1384 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1385 1386 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1387 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1388 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1389 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1390 1391 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1392 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1393 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1394 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1395 1396 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1397 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1398 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1399 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1400 1401 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1402 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1403 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1404 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1405 1406 /* 1407 * auto request sense 1408 */ 1409 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1410 (pkt)->pkt_flags = (flag), \ 1411 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1412 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1413 (pkt)->pkt_address.a_lun 1414 1415 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1416 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1417 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1418 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1419 1420 1421 #ifdef __cplusplus 1422 } 1423 #endif 1424 1425 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1426