1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2000 to 2010, LSI Corporation. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms of all code within 32 * this file that is exclusively owned by LSI, with or without 33 * modification, is permitted provided that, in addition to the CDDL 1.0 34 * License requirements, the following conditions are met: 35 * 36 * Neither the name of the author nor the names of its contributors may be 37 * used to endorse or promote products derived from this software without 38 * specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 51 * DAMAGE. 52 */ 53 54 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 55 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 56 57 #include <sys/byteorder.h> 58 #include <sys/isa_defs.h> 59 #include <sys/sunmdi.h> 60 #include <sys/mdi_impldefs.h> 61 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 62 63 #ifdef __cplusplus 64 extern "C" { 65 #endif 66 67 /* 68 * Compile options 69 */ 70 #ifdef DEBUG 71 #define MPTSAS_DEBUG /* turn on debugging code */ 72 #endif /* DEBUG */ 73 74 #define MPTSAS_INITIAL_SOFT_SPACE 4 75 76 #define MAX_MPI_PORTS 16 77 78 /* 79 * Note below macro definition and data type definition 80 * are used for phy mask handling, it should be changed 81 * simultaneously. 82 */ 83 #define MPTSAS_MAX_PHYS 16 84 typedef uint16_t mptsas_phymask_t; 85 86 #define MPTSAS_INVALID_DEVHDL 0xffff 87 88 /* 89 * MPT HW defines 90 */ 91 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 92 #define MPTSAS_MAX_DISKS_IN_VOL 10 93 #define MPTSAS_MAX_HOTSPARES 2 94 #define MPTSAS_MAX_RAIDVOLS 2 95 #define MPTSAS_MAX_RAIDCONFIGS 5 96 97 /* 98 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 99 * plus one means the end of the string '\0'. 100 */ 101 #define MPTSAS_WWN_STRLEN 16 + 1 102 #define MPTSAS_MAX_GUID_LEN 64 103 104 /* 105 * DMA routine flags 106 */ 107 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 108 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 109 #define MPTSAS_DMA_HANDLE_BOUND 0x8 110 111 /* 112 * If the HBA supports DMA or bus-mastering, you may have your own 113 * scatter-gather list for physically non-contiguous memory in one 114 * I/O operation; if so, there's probably a size for that list. 115 * It must be placed in the ddi_dma_lim_t structure, so that the system 116 * DMA-support routines can use it to break up the I/O request, so we 117 * define it here. 118 */ 119 #if defined(__sparc) 120 #define MPTSAS_MAX_DMA_SEGS 1 121 #define MPTSAS_MAX_CMD_SEGS 1 122 #else 123 #define MPTSAS_MAX_DMA_SEGS 256 124 #define MPTSAS_MAX_CMD_SEGS 257 125 #endif 126 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 127 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 128 129 /* 130 * Caculating how many 64-bit DMA simple elements can be stored in the first 131 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 132 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 133 * size. 134 */ 135 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 136 ((mpt->m_req_frame_size - \ 137 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 138 139 /* 140 * Scatter-gather list structure defined by HBA hardware 141 */ 142 typedef struct NcrTableIndirect { /* Table Indirect entries */ 143 uint32_t count; /* 24 bit count */ 144 union { 145 uint32_t address32; /* 32 bit address */ 146 struct { 147 uint32_t Low; 148 uint32_t High; 149 } address64; /* 64 bit address */ 150 } addr; 151 } mptti_t; 152 153 /* 154 * preferred pkt_private length in 64-bit quantities 155 */ 156 #ifdef _LP64 157 #define PKT_PRIV_SIZE 2 158 #define PKT_PRIV_LEN 16 /* in bytes */ 159 #else /* _ILP32 */ 160 #define PKT_PRIV_SIZE 1 161 #define PKT_PRIV_LEN 8 /* in bytes */ 162 #endif 163 164 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 165 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 166 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 167 168 /* 169 * get offset of item in structure 170 */ 171 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 172 173 /* 174 * WWID provided by LSI firmware is generated by firmware but the WWID is not 175 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 176 * address. According LSI's confirmation, the top nibble of RAID WWID is 177 * meanless, so the consensus between Solaris and OBP is to replace top nibble 178 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 179 * format unit address. 180 */ 181 #define MPTSAS_RAID_WWID(wwid) \ 182 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 183 184 typedef struct mptsas_target { 185 uint64_t m_sas_wwn; /* hash key1 */ 186 mptsas_phymask_t m_phymask; /* hash key2 */ 187 /* 188 * m_dr_flag is a flag for DR, make sure the member 189 * take the place of dr_flag of mptsas_hash_data. 190 */ 191 uint8_t m_dr_flag; /* dr_flag */ 192 uint16_t m_devhdl; 193 uint32_t m_deviceinfo; 194 uint8_t m_phynum; 195 uint32_t m_dups; 196 int32_t m_timeout; 197 int32_t m_timebase; 198 int32_t m_t_throttle; 199 int32_t m_t_ncmds; 200 int32_t m_reset_delay; 201 int32_t m_t_nwait; 202 203 uint16_t m_qfull_retry_interval; 204 uint8_t m_qfull_retries; 205 206 } mptsas_target_t; 207 208 typedef struct mptsas_smp { 209 uint64_t m_sasaddr; /* hash key1 */ 210 mptsas_phymask_t m_phymask; /* hash key2 */ 211 uint8_t reserved1; 212 uint16_t m_devhdl; 213 uint32_t m_deviceinfo; 214 } mptsas_smp_t; 215 216 typedef struct mptsas_hash_data { 217 uint64_t key1; 218 mptsas_phymask_t key2; 219 uint8_t dr_flag; 220 uint16_t devhdl; 221 uint32_t device_info; 222 } mptsas_hash_data_t; 223 224 typedef struct mptsas_cache_frames { 225 ddi_dma_handle_t m_dma_hdl; 226 ddi_acc_handle_t m_acc_hdl; 227 caddr_t m_frames_addr; 228 uint32_t m_phys_addr; 229 } mptsas_cache_frames_t; 230 231 typedef struct mptsas_cmd { 232 uint_t cmd_flags; /* flags from scsi_init_pkt */ 233 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 234 ddi_dma_cookie_t cmd_cookie; 235 uint_t cmd_cookiec; 236 uint_t cmd_winindex; 237 uint_t cmd_nwin; 238 uint_t cmd_cur_cookie; 239 off_t cmd_dma_offset; 240 size_t cmd_dma_len; 241 uint32_t cmd_totaldmacount; 242 243 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 244 ddi_dma_cookie_t cmd_arqcookie; 245 struct buf *cmd_arq_buf; 246 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 247 ddi_dma_cookie_t cmd_ext_arqcookie; 248 struct buf *cmd_ext_arq_buf; 249 250 int cmd_pkt_flags; 251 252 /* timer for command in active slot */ 253 int cmd_active_timeout; 254 255 struct scsi_pkt *cmd_pkt; 256 struct scsi_arq_status cmd_scb; 257 uchar_t cmd_cdblen; /* length of cdb */ 258 uchar_t cmd_rqslen; /* len of requested rqsense */ 259 uchar_t cmd_privlen; 260 uint_t cmd_scblen; 261 uint32_t cmd_dmacount; 262 uint64_t cmd_dma_addr; 263 uchar_t cmd_age; 264 ushort_t cmd_qfull_retries; 265 uchar_t cmd_queued; /* true if queued */ 266 struct mptsas_cmd *cmd_linkp; 267 mptti_t *cmd_sg; /* Scatter/Gather structure */ 268 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 269 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 270 uint32_t cmd_slot; 271 uint32_t ioc_cmd_slot; 272 273 mptsas_cache_frames_t *cmd_extra_frames; 274 275 uint32_t cmd_rfm; 276 mptsas_target_t *cmd_tgt_addr; 277 } mptsas_cmd_t; 278 279 /* 280 * These are the defined cmd_flags for this structure. 281 */ 282 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 283 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 284 #define CFLAG_FINISHED 0x000004 /* command completed */ 285 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 286 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 287 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 288 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 289 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 290 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 291 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 292 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 293 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 294 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 295 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 296 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 297 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 298 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 299 #define CFLAG_FREE 0x010000 /* packet is on free list */ 300 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 301 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 302 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 303 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 304 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 305 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 306 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 307 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 308 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 309 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 310 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 311 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 312 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 313 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 314 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 315 316 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 317 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 318 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 319 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 320 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 321 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 322 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 323 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 324 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 325 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 326 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 327 328 #define MPTSAS_HASH_ARRAY_SIZE 16 329 /* 330 * hash table definition 331 */ 332 333 #define MPTSAS_HASH_FIRST 0xffff 334 #define MPTSAS_HASH_NEXT 0x0000 335 336 typedef struct mptsas_dma_alloc_state 337 { 338 ddi_dma_handle_t handle; 339 caddr_t memp; 340 size_t size; 341 ddi_acc_handle_t accessp; 342 ddi_dma_cookie_t cookie; 343 } mptsas_dma_alloc_state_t; 344 345 /* 346 * passthrough request structure 347 */ 348 typedef struct mptsas_pt_request { 349 uint8_t *request; 350 uint32_t request_size; 351 uint32_t data_size; 352 uint32_t dataout_size; 353 uint32_t direction; 354 ddi_dma_cookie_t data_cookie; 355 ddi_dma_cookie_t dataout_cookie; 356 } mptsas_pt_request_t; 357 358 /* 359 * config page request structure 360 */ 361 typedef struct mptsas_config_request { 362 uint32_t page_address; 363 uint8_t action; 364 uint8_t page_type; 365 uint8_t page_number; 366 uint8_t page_length; 367 uint8_t page_version; 368 uint8_t ext_page_type; 369 uint16_t ext_page_length; 370 } mptsas_config_request_t; 371 372 typedef struct mptsas_fw_diagnostic_buffer { 373 mptsas_dma_alloc_state_t buffer_data; 374 uint8_t extended_type; 375 uint8_t buffer_type; 376 uint8_t force_release; 377 uint32_t product_specific[23]; 378 uint8_t immediate; 379 uint8_t enabled; 380 uint8_t valid_data; 381 uint8_t owned_by_firmware; 382 uint32_t unique_id; 383 } mptsas_fw_diagnostic_buffer_t; 384 385 /* 386 * FW diag request structure 387 */ 388 typedef struct mptsas_diag_request { 389 mptsas_fw_diagnostic_buffer_t *pBuffer; 390 uint8_t function; 391 } mptsas_diag_request_t; 392 393 typedef struct mptsas_hash_node { 394 void *data; 395 struct mptsas_hash_node *next; 396 } mptsas_hash_node_t; 397 398 typedef struct mptsas_hash_table { 399 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 400 /* 401 * last position in traverse 402 */ 403 struct mptsas_hash_node *cur; 404 uint16_t line; 405 406 } mptsas_hash_table_t; 407 408 /* 409 * RAID volume information 410 */ 411 typedef struct mptsas_raidvol { 412 ushort_t m_israid; 413 uint16_t m_raidhandle; 414 uint64_t m_raidwwid; 415 uint8_t m_state; 416 uint32_t m_statusflags; 417 uint32_t m_settings; 418 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 419 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 420 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 421 uint64_t m_raidsize; 422 int m_raidlevel; 423 int m_ndisks; 424 mptsas_target_t *m_raidtgt; 425 } mptsas_raidvol_t; 426 427 /* 428 * RAID configurations 429 */ 430 typedef struct mptsas_raidconfig { 431 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 432 uint16_t m_physdisk_devhdl[ 433 MPTSAS_MAX_DISKS_IN_CONFIG]; 434 uint8_t m_native; 435 } m_raidconfig_t; 436 437 /* 438 * Structure to hold active outstanding cmds. Also, keep 439 * timeout on a per target basis. 440 */ 441 typedef struct mptsas_slots { 442 mptsas_hash_table_t m_tgttbl; 443 mptsas_hash_table_t m_smptbl; 444 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 445 uint8_t m_num_raid_configs; 446 uint16_t m_tags; 447 size_t m_size; 448 uint16_t m_n_slots; 449 mptsas_cmd_t *m_slot[1]; 450 } mptsas_slots_t; 451 452 /* 453 * Structure to hold command and packets for event ack 454 * and task management commands. 455 */ 456 typedef struct m_event_struct { 457 struct mptsas_cmd m_event_cmd; 458 struct m_event_struct *m_event_linkp; 459 /* 460 * event member record the failure event and eventcntx 461 * event member would be used in send ack pending process 462 */ 463 uint32_t m_event; 464 uint32_t m_eventcntx; 465 uint_t in_use; 466 struct scsi_pkt m_event_pkt; /* must be last */ 467 /* ... scsi_pkt_size() */ 468 } m_event_struct_t; 469 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 470 sizeof (struct scsi_pkt) + scsi_pkt_size()) 471 472 #define MAX_IOC_COMMANDS 8 473 474 /* 475 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 476 * A new event ack command requests mptsas_cmd and scsi_pkt structures 477 * from this pool, and returns it back when done. 478 */ 479 480 typedef struct m_replyh_arg { 481 void *mpt; 482 uint32_t rfm; 483 } m_replyh_arg_t; 484 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 485 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 486 487 /* 488 * Flags for DR handler topology change 489 */ 490 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 491 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 492 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 493 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 494 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 495 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 496 497 typedef struct mptsas_topo_change_list { 498 void *mpt; 499 uint_t event; 500 union { 501 uint8_t physport; 502 mptsas_phymask_t phymask; 503 } un; 504 uint16_t devhdl; 505 void *object; 506 uint8_t flags; 507 struct mptsas_topo_change_list *next; 508 } mptsas_topo_change_list_t; 509 510 511 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 512 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 513 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 514 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 515 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 516 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 517 518 /* 519 * Status types when calling mptsas_get_target_device_info 520 */ 521 #define DEV_INFO_SUCCESS 0x0 522 #define DEV_INFO_FAIL_PAGE0 0x1 523 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 524 #define DEV_INFO_PHYS_DISK 0x3 525 #define DEV_INFO_FAIL_ALLOC 0x4 526 527 /* 528 * mpt hotplug event defines 529 */ 530 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 531 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 532 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 533 534 /* 535 * SMP target hotplug events 536 */ 537 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 538 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 539 #define MPTSAS_DR_EVENT_MASK 0x3F 540 541 /* 542 * mpt hotplug status definition for m_dr_flag 543 */ 544 545 /* 546 * MPTSAS_DR_INACTIVE 547 * 548 * The target is in a normal operating state. 549 * No dynamic reconfiguration operation is in progress. 550 */ 551 #define MPTSAS_DR_INACTIVE 0x0 552 /* 553 * MPTSAS_DR_INTRANSITION 554 * 555 * The target is in a transition mode since 556 * hotplug event happens and offline procedure has not 557 * been finished 558 */ 559 #define MPTSAS_DR_INTRANSITION 0x1 560 561 typedef struct mptsas_tgt_private { 562 int t_lun; 563 struct mptsas_target *t_private; 564 } mptsas_tgt_private_t; 565 566 /* 567 * The following defines are used in mptsas_set_init_mode to track the current 568 * state as we progress through reprogramming the HBA from target mode into 569 * initiator mode. 570 */ 571 572 #define IOUC_READ_PAGE0 0x00000100 573 #define IOUC_READ_PAGE1 0x00000200 574 #define IOUC_WRITE_PAGE1 0x00000400 575 #define IOUC_DONE 0x00000800 576 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 577 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 578 579 /* 580 * Last allocated slot is used for TM requests. Since only m_max_requests 581 * frames are allocated, the last SMID will be m_max_requests - 1. 582 */ 583 #define MPTSAS_SLOTS_SIZE(mpt) \ 584 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 585 mpt->m_max_requests)) 586 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 587 588 /* 589 * Macro for phy_flags 590 */ 591 typedef struct mptsas_phy_info { 592 uint8_t port_num; 593 uint8_t port_flags; 594 uint16_t ctrl_devhdl; 595 uint32_t phy_device_type; 596 uint16_t attached_devhdl; 597 mptsas_phymask_t phy_mask; 598 } mptsas_phy_info_t; 599 600 typedef struct mptsas_doneq_thread_arg { 601 void *mpt; 602 uint64_t t; 603 } mptsas_doneq_thread_arg_t; 604 605 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 606 typedef struct mptsas_doneq_thread_list { 607 mptsas_cmd_t *doneq; 608 mptsas_cmd_t **donetail; 609 kthread_t *threadp; 610 kcondvar_t cv; 611 ushort_t reserv1; 612 uint32_t reserv2; 613 kmutex_t mutex; 614 uint32_t flag; 615 uint32_t len; 616 mptsas_doneq_thread_arg_t arg; 617 } mptsas_doneq_thread_list_t; 618 619 typedef struct mptsas { 620 int m_instance; 621 622 struct mptsas *m_next; 623 624 scsi_hba_tran_t *m_tran; 625 smp_hba_tran_t *m_smptran; 626 kmutex_t m_mutex; 627 kcondvar_t m_cv; 628 kcondvar_t m_passthru_cv; 629 kcondvar_t m_fw_cv; 630 kcondvar_t m_config_cv; 631 kcondvar_t m_fw_diag_cv; 632 dev_info_t *m_dip; 633 634 /* 635 * soft state flags 636 */ 637 uint_t m_softstate; 638 639 struct mptsas_slots *m_active; /* outstanding cmds */ 640 641 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 642 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 643 644 kmutex_t m_tx_waitq_mutex; 645 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 646 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 647 int m_tx_draining; /* TX queue draining flag */ 648 649 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 650 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 651 652 /* 653 * variables for helper threads (fan-out interrupts) 654 */ 655 mptsas_doneq_thread_list_t *m_doneq_thread_id; 656 uint32_t m_doneq_thread_n; 657 uint32_t m_doneq_thread_threshold; 658 uint32_t m_doneq_length_threshold; 659 uint32_t m_doneq_len; 660 kcondvar_t m_doneq_thread_cv; 661 kmutex_t m_doneq_mutex; 662 663 int m_ncmds; /* number of outstanding commands */ 664 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 665 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 666 667 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 668 669 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 670 671 ushort_t m_devid; /* device id of chip. */ 672 uchar_t m_revid; /* revision of chip. */ 673 uint16_t m_svid; /* subsystem Vendor ID of chip */ 674 uint16_t m_ssid; /* subsystem Device ID of chip */ 675 676 uchar_t m_sync_offset; /* default offset for this chip. */ 677 678 timeout_id_t m_quiesce_timeid; 679 timeout_id_t m_pm_timeid; 680 681 ddi_dma_handle_t m_dma_req_frame_hdl; 682 ddi_acc_handle_t m_acc_req_frame_hdl; 683 ddi_dma_handle_t m_dma_reply_frame_hdl; 684 ddi_acc_handle_t m_acc_reply_frame_hdl; 685 ddi_dma_handle_t m_dma_free_queue_hdl; 686 ddi_acc_handle_t m_acc_free_queue_hdl; 687 ddi_dma_handle_t m_dma_post_queue_hdl; 688 ddi_acc_handle_t m_acc_post_queue_hdl; 689 690 /* 691 * list of reset notification requests 692 */ 693 struct scsi_reset_notify_entry *m_reset_notify_listf; 694 695 /* 696 * qfull handling 697 */ 698 timeout_id_t m_restart_cmd_timeid; 699 700 /* 701 * scsi reset delay per bus 702 */ 703 uint_t m_scsi_reset_delay; 704 705 int m_pm_idle_delay; 706 707 uchar_t m_polled_intr; /* intr was polled. */ 708 uchar_t m_suspended; /* true if driver is suspended */ 709 710 struct kmem_cache *m_kmem_cache; 711 struct kmem_cache *m_cache_frames; 712 713 /* 714 * hba options. 715 */ 716 uint_t m_options; 717 718 int m_in_callback; 719 720 int m_power_level; /* current power level */ 721 722 int m_busy; /* power management busy state */ 723 724 off_t m_pmcsr_offset; /* PMCSR offset */ 725 726 ddi_acc_handle_t m_config_handle; 727 728 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 729 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 730 ddi_device_acc_attr_t m_dev_acc_attr; 731 ddi_device_acc_attr_t m_reg_acc_attr; 732 733 /* 734 * request/reply variables 735 */ 736 caddr_t m_req_frame; 737 uint64_t m_req_frame_dma_addr; 738 caddr_t m_reply_frame; 739 uint64_t m_reply_frame_dma_addr; 740 caddr_t m_free_queue; 741 uint64_t m_free_queue_dma_addr; 742 caddr_t m_post_queue; 743 uint64_t m_post_queue_dma_addr; 744 745 m_replyh_arg_t *m_replyh_args; 746 747 uint16_t m_max_requests; 748 uint16_t m_req_frame_size; 749 750 /* 751 * Max frames per request reprted in IOC Facts 752 */ 753 uint8_t m_max_chain_depth; 754 /* 755 * Max frames per request which is used in reality. It's adjusted 756 * according DMA SG length attribute, and shall not exceed the 757 * m_max_chain_depth. 758 */ 759 uint8_t m_max_request_frames; 760 761 uint16_t m_free_queue_depth; 762 uint16_t m_post_queue_depth; 763 uint16_t m_max_replies; 764 uint32_t m_free_index; 765 uint32_t m_post_index; 766 uint8_t m_reply_frame_size; 767 uint32_t m_ioc_capabilities; 768 769 /* 770 * indicates if the firmware was upload by the driver 771 * at boot time 772 */ 773 ushort_t m_fwupload; 774 775 uint16_t m_productid; 776 777 /* 778 * per instance data structures for dma memory resources for 779 * MPI handshake protocol. only one handshake cmd can run at a time. 780 */ 781 ddi_dma_handle_t m_hshk_dma_hdl; 782 783 ddi_acc_handle_t m_hshk_acc_hdl; 784 785 caddr_t m_hshk_memp; 786 787 size_t m_hshk_dma_size; 788 789 /* Firmware version on the card at boot time */ 790 uint32_t m_fwversion; 791 792 /* MSI specific fields */ 793 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 794 int m_intr_type; /* What type of interrupt */ 795 int m_intr_cnt; /* # of intrs count returned */ 796 size_t m_intr_size; /* Size of intr array */ 797 uint_t m_intr_pri; /* Interrupt priority */ 798 int m_intr_cap; /* Interrupt capabilities */ 799 ddi_taskq_t *m_event_taskq; 800 801 /* SAS specific information */ 802 803 union { 804 uint64_t m_base_wwid; /* Base WWID */ 805 struct { 806 #ifdef _BIG_ENDIAN 807 uint32_t m_base_wwid_hi; 808 uint32_t m_base_wwid_lo; 809 #else 810 uint32_t m_base_wwid_lo; 811 uint32_t m_base_wwid_hi; 812 #endif 813 } sasaddr; 814 } un; 815 816 uint8_t m_num_phys; /* # of PHYs */ 817 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 818 uint8_t m_port_chng; /* initiator port changes */ 819 820 /* FMA Capabilities */ 821 int m_fm_capabilities; 822 ddi_taskq_t *m_dr_taskq; 823 int m_mpxio_enable; 824 uint8_t m_done_traverse_dev; 825 uint8_t m_done_traverse_smp; 826 int m_passthru_in_progress; 827 int m_diag_action_in_progress; 828 uint16_t m_dev_handle; 829 uint16_t m_smp_devhdl; 830 831 /* 832 * Event recording 833 */ 834 uint8_t m_event_index; 835 uint32_t m_event_number; 836 uint32_t m_event_mask[4]; 837 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 838 839 /* 840 * FW diag Buffer List 841 */ 842 mptsas_fw_diagnostic_buffer_t 843 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 844 845 /* 846 * Event Replay flag (MUR support) 847 */ 848 uint8_t m_event_replay; 849 850 /* 851 * IR Capable flag 852 */ 853 uint8_t m_ir_capable; 854 855 /* 856 * Is HBA processing a diag reset? 857 */ 858 uint8_t m_in_reset; 859 860 /* 861 * per instance cmd data structures for task management cmds 862 */ 863 m_event_struct_t m_event_task_mgmt; /* must be last */ 864 /* ... scsi_pkt_size */ 865 } mptsas_t; 866 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 867 sizeof (struct scsi_pkt) + scsi_pkt_size()) 868 /* 869 * Only one of below two conditions is satisfied, we 870 * think the target is associated to the iport and 871 * allow call into mptsas_probe_lun(). 872 * 1. physicalsport == physport 873 * 2. (phymask & (1 << physport)) == 0 874 * The condition #2 is because LSI uses lowest PHY 875 * number as the value of physical port when auto port 876 * configuration. 877 */ 878 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 879 ((physicalport == physport) || (dynamicport && (phymask & \ 880 (1 << physport)))) 881 882 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 883 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 884 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 885 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 886 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 887 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 888 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 889 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 890 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 891 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 892 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 893 894 /* 895 * These should eventually migrate into the mpt header files 896 * that may become the /kernel/misc/mpt module... 897 */ 898 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 899 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 900 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 901 mptsas_put_msg_Function(hdl, mp, Function); \ 902 mptsas_put_msg_Lun(hdl, mp, Lun) 903 904 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 905 ddi_put16(hdl, &(mp)->DevHandle, (val)) 906 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 907 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 908 #define mptsas_put_msg_Function(hdl, mp, val) \ 909 ddi_put8(hdl, &(mp)->Function, (val)) 910 #define mptsas_put_msg_Lun(hdl, mp, val) \ 911 ddi_put8(hdl, &(mp)->LUN[1], (val)) 912 913 #define mptsas_get_msg_Function(hdl, mp) \ 914 ddi_get8(hdl, &(mp)->Function) 915 916 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 917 ddi_get8(hdl, &(mp)->MsgFlags) 918 919 #define MPTSAS_ENABLE_DRWE(hdl) \ 920 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 921 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 922 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 923 MPI2_WRSEQ_1ST_KEY_VALUE); \ 924 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 925 MPI2_WRSEQ_2ND_KEY_VALUE); \ 926 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 927 MPI2_WRSEQ_3RD_KEY_VALUE); \ 928 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 929 MPI2_WRSEQ_4TH_KEY_VALUE); \ 930 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 931 MPI2_WRSEQ_5TH_KEY_VALUE); \ 932 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 933 MPI2_WRSEQ_6TH_KEY_VALUE); 934 935 /* 936 * m_options flags 937 */ 938 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 939 940 /* 941 * m_softstate flags 942 */ 943 #define MPTSAS_SS_DRAINING 0x02 944 #define MPTSAS_SS_QUIESCED 0x04 945 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 946 947 /* 948 * regspec defines. 949 */ 950 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 951 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 952 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 953 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 954 955 /* 956 * Handy constants 957 */ 958 #define FALSE 0 959 #define TRUE 1 960 #define UNDEFINED -1 961 #define FAILED -2 962 963 /* 964 * power management. 965 */ 966 #define MPTSAS_POWER_ON(mpt) { \ 967 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 968 PCI_PMCSR_D0); \ 969 delay(drv_usectohz(10000)); \ 970 (void) pci_restore_config_regs(mpt->m_dip); \ 971 mptsas_setup_cmd_reg(mpt); \ 972 } 973 974 #define MPTSAS_POWER_OFF(mpt) { \ 975 (void) pci_save_config_regs(mpt->m_dip); \ 976 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 977 PCI_PMCSR_D3HOT); \ 978 mpt->m_power_level = PM_LEVEL_D3; \ 979 } 980 981 /* 982 * inq_dtype: 983 * Bits 5 through 7 are the Peripheral Device Qualifier 984 * 001b: device not connected to the LUN 985 * Bits 0 through 4 are the Peripheral Device Type 986 * 1fh: Unknown or no device type 987 * 988 * Although the inquiry may return success, the following value 989 * means no valid LUN connected. 990 */ 991 #define MPTSAS_VALID_LUN(sd_inq) \ 992 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 993 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 994 995 /* 996 * Default is to have 10 retries on receiving QFULL status and 997 * each retry to be after 100 ms. 998 */ 999 #define QFULL_RETRIES 10 1000 #define QFULL_RETRY_INTERVAL 100 1001 1002 /* 1003 * Handy macros 1004 */ 1005 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1006 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1007 1008 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1009 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1010 1011 /* 1012 * poll time for mptsas_pollret() and mptsas_wait_intr() 1013 */ 1014 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1015 1016 /* 1017 * default time for mptsas_do_passthru 1018 */ 1019 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1020 1021 /* 1022 * macro to return the effective address of a given per-target field 1023 */ 1024 #define EFF_ADDR(start, offset) ((start) + (offset)) 1025 1026 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1027 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1028 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1029 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1030 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1031 1032 1033 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1034 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1035 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1036 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1037 1038 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1039 1040 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1041 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1042 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1043 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1044 1045 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1046 &(mpt)->m_reg->HostInterruptStatus)) 1047 1048 #define MPTSAS_SET_SIGP(P) \ 1049 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1050 1051 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1052 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1053 1054 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1055 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1056 1057 1058 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1059 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1060 req_desc_lo);\ 1061 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1062 req_desc_hi); 1063 1064 #define INTPENDING(mpt) \ 1065 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1066 1067 /* 1068 * Mask all interrupts to disable 1069 */ 1070 #define MPTSAS_DISABLE_INTR(mpt) \ 1071 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1072 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1073 1074 /* 1075 * Mask Doorbell and Reset interrupts to enable reply desc int. 1076 */ 1077 #define MPTSAS_ENABLE_INTR(mpt) \ 1078 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1079 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1080 1081 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1082 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1083 1084 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1085 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1086 1087 #define ClrSetBits32(hdl, reg, clr, set) \ 1088 ddi_put32(hdl, (reg), \ 1089 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1090 1091 #define ClrSetBits(reg, clr, set) \ 1092 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1093 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1094 1095 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1096 if ((cmdp = mpt->m_waitq) != NULL) { \ 1097 /* If the queue is now empty fix the tail pointer */ \ 1098 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1099 mpt->m_waitqtail = &mpt->m_waitq; \ 1100 cmdp->cmd_linkp = NULL; \ 1101 cmdp->cmd_queued = FALSE; \ 1102 } 1103 1104 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1105 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1106 /* If the queue is now empty fix the tail pointer */ \ 1107 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1108 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1109 cmdp->cmd_linkp = NULL; \ 1110 cmdp->cmd_queued = FALSE; \ 1111 } 1112 1113 /* 1114 * defaults for the global properties 1115 */ 1116 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1117 #define DEFAULT_TAG_AGE_LIMIT 2 1118 #define DEFAULT_WD_TICK 10 1119 1120 /* 1121 * invalid hostid. 1122 */ 1123 #define MPTSAS_INVALID_HOSTID -1 1124 1125 /* 1126 * Get/Set hostid from SCSI port configuration page 1127 */ 1128 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1129 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1130 1131 /* 1132 * Config space. 1133 */ 1134 #define MPTSAS_LATENCY_TIMER 0x40 1135 1136 /* 1137 * Offset to firmware version 1138 */ 1139 #define MPTSAS_FW_VERSION_OFFSET 9 1140 1141 /* 1142 * Offset and masks to get at the ProductId field 1143 */ 1144 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1145 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1146 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1147 1148 /* 1149 * Subsystem ID for HBAs. 1150 */ 1151 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1152 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1153 1154 /* 1155 * reset delay tick 1156 */ 1157 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1158 1159 /* 1160 * Ioc reset return values 1161 */ 1162 #define MPTSAS_RESET_FAIL -1 1163 #define MPTSAS_NO_RESET 0 1164 #define MPTSAS_SUCCESS_HARDRESET 1 1165 1166 /* 1167 * throttle support. 1168 */ 1169 #define MAX_THROTTLE 32 1170 #define HOLD_THROTTLE 0 1171 #define DRAIN_THROTTLE -1 1172 #define QFULL_THROTTLE -2 1173 1174 /* 1175 * Passthrough/config request flags 1176 */ 1177 #define MPTSAS_DATA_ALLOCATED 0x0001 1178 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1179 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1180 #define MPTSAS_ADDRESS_REPLY 0x0008 1181 #define MPTSAS_CMD_TIMEOUT 0x0010 1182 1183 /* 1184 * response code tlr flag 1185 */ 1186 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1187 1188 /* 1189 * System Events 1190 */ 1191 #ifndef DDI_VENDOR_LSI 1192 #define DDI_VENDOR_LSI "LSI" 1193 #endif /* DDI_VENDOR_LSI */ 1194 1195 /* 1196 * Shared functions 1197 */ 1198 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1199 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1200 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1201 int mptsas_config_space_init(struct mptsas *mpt); 1202 int mptsas_init_chip(mptsas_t *mpt, int first_time); 1203 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1204 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1205 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1206 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1207 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1208 uint8_t pageversion, uint8_t pagelength, uint32_t 1209 SGEflagslength, uint32_t SGEaddress32); 1210 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1211 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1212 uint8_t pageversion, uint16_t extpagelength, 1213 uint32_t SGEflagslength, uint32_t SGEaddress32); 1214 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1215 uint8_t type, int mode); 1216 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1217 uint8_t type, int mode); 1218 int mptsas_download_firmware(); 1219 int mptsas_can_download_firmware(); 1220 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1221 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1222 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1223 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1224 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1225 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1226 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1227 1228 /* 1229 * impl functions 1230 */ 1231 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1232 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1233 int mptsas_ioc_reset(mptsas_t *mpt); 1234 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1235 ddi_acc_handle_t accessp); 1236 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1237 ddi_acc_handle_t accessp); 1238 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1239 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1240 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1241 uint32_t SGEaddress32); 1242 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1243 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1244 uint8_t pageversion, uint16_t extpagelength, 1245 uint32_t SGEflagslength, uint32_t SGEaddress32); 1246 1247 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1248 struct scsi_pkt **pkt); 1249 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1250 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1251 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1252 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1253 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1254 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1255 1256 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1257 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1258 int mode); 1259 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1260 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1261 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1262 int mptsas_restart_ioc(mptsas_t *mpt); 1263 void mptsas_update_driver_data(struct mptsas *mpt); 1264 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1265 1266 /* 1267 * init functions 1268 */ 1269 int mptsas_ioc_get_facts(mptsas_t *mpt); 1270 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1271 int mptsas_ioc_enable_port(mptsas_t *mpt); 1272 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1273 int mptsas_ioc_init(mptsas_t *mpt); 1274 1275 /* 1276 * configuration pages operation 1277 */ 1278 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1279 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1280 uint8_t *physport, uint8_t *phynum); 1281 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1282 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1283 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1284 mptsas_smp_t *info); 1285 int mptsas_set_ioc_params(mptsas_t *mpt); 1286 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1287 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1288 uint64_t *sas_wwn, uint8_t *portwidth); 1289 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1290 1291 /* 1292 * RAID functions 1293 */ 1294 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1295 int mptsas_get_raid_info(mptsas_t *mpt); 1296 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1297 uint8_t physdisknum); 1298 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1299 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1300 1301 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1302 /* 1303 * debugging. 1304 */ 1305 #if defined(MPTSAS_DEBUG) 1306 1307 void mptsas_printf(char *fmt, ...); 1308 1309 #define MPTSAS_DBGPR(m, args) \ 1310 if (mptsas_debug_flags & (m)) \ 1311 mptsas_printf args 1312 #else /* ! defined(MPTSAS_DEBUG) */ 1313 #define MPTSAS_DBGPR(m, args) 1314 #endif /* defined(MPTSAS_DEBUG) */ 1315 1316 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1317 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1318 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1319 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1320 1321 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1322 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1323 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1324 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1325 1326 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1327 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1328 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1329 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1330 1331 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1332 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1333 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) 1334 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1335 1336 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1337 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1338 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1339 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1340 1341 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1342 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1343 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1344 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1345 1346 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1347 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1348 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1349 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1350 1351 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1352 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1353 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1354 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1355 1356 /* 1357 * auto request sense 1358 */ 1359 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1360 (pkt)->pkt_flags = (flag), \ 1361 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1362 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1363 (pkt)->pkt_address.a_lun 1364 1365 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1366 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1367 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1368 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1369 1370 1371 #ifdef __cplusplus 1372 } 1373 #endif 1374 1375 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1376