1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2000 to 2010, LSI Corporation. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms of all code within 32 * this file that is exclusively owned by LSI, with or without 33 * modification, is permitted provided that, in addition to the CDDL 1.0 34 * License requirements, the following conditions are met: 35 * 36 * Neither the name of the author nor the names of its contributors may be 37 * used to endorse or promote products derived from this software without 38 * specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 51 * DAMAGE. 52 */ 53 54 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 55 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 56 57 #include <sys/byteorder.h> 58 #include <sys/isa_defs.h> 59 #include <sys/sunmdi.h> 60 #include <sys/mdi_impldefs.h> 61 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 62 63 #ifdef __cplusplus 64 extern "C" { 65 #endif 66 67 /* 68 * Compile options 69 */ 70 #ifdef DEBUG 71 #define MPTSAS_DEBUG /* turn on debugging code */ 72 #endif /* DEBUG */ 73 74 #define MPTSAS_INITIAL_SOFT_SPACE 4 75 76 #define MAX_MPI_PORTS 16 77 78 #define MPTSAS_MAX_PHYS 8 79 80 #define MPTSAS_INVALID_DEVHDL 0xffff 81 82 /* 83 * MPT HW defines 84 */ 85 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 86 #define MPTSAS_MAX_DISKS_IN_VOL 10 87 #define MPTSAS_MAX_HOTSPARES 2 88 #define MPTSAS_MAX_RAIDVOLS 2 89 #define MPTSAS_MAX_RAIDCONFIGS 5 90 91 /* 92 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 93 * plus one means the end of the string '\0'. 94 */ 95 #define MPTSAS_WWN_STRLEN 16 + 1 96 #define MPTSAS_MAX_GUID_LEN 64 97 98 /* 99 * DMA routine flags 100 */ 101 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 102 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 103 #define MPTSAS_DMA_HANDLE_BOUND 0x8 104 105 /* 106 * If the HBA supports DMA or bus-mastering, you may have your own 107 * scatter-gather list for physically non-contiguous memory in one 108 * I/O operation; if so, there's probably a size for that list. 109 * It must be placed in the ddi_dma_lim_t structure, so that the system 110 * DMA-support routines can use it to break up the I/O request, so we 111 * define it here. 112 */ 113 #if defined(__sparc) 114 #define MPTSAS_MAX_DMA_SEGS 1 115 #define MPTSAS_MAX_CMD_SEGS 1 116 #else 117 #define MPTSAS_MAX_DMA_SEGS 256 118 #define MPTSAS_MAX_CMD_SEGS 257 119 #endif 120 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 121 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 122 123 /* 124 * Caculating how many 64-bit DMA simple elements can be stored in the first 125 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 126 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 127 * size. 128 */ 129 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 130 ((mpt->m_req_frame_size - \ 131 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 132 133 /* 134 * Scatter-gather list structure defined by HBA hardware 135 */ 136 typedef struct NcrTableIndirect { /* Table Indirect entries */ 137 uint32_t count; /* 24 bit count */ 138 union { 139 uint32_t address32; /* 32 bit address */ 140 struct { 141 uint32_t Low; 142 uint32_t High; 143 } address64; /* 64 bit address */ 144 } addr; 145 } mptti_t; 146 147 /* 148 * preferred pkt_private length in 64-bit quantities 149 */ 150 #ifdef _LP64 151 #define PKT_PRIV_SIZE 2 152 #define PKT_PRIV_LEN 16 /* in bytes */ 153 #else /* _ILP32 */ 154 #define PKT_PRIV_SIZE 1 155 #define PKT_PRIV_LEN 8 /* in bytes */ 156 #endif 157 158 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 159 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 160 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 161 162 /* 163 * get offset of item in structure 164 */ 165 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 166 167 /* 168 * WWID provided by LSI firmware is generated by firmware but the WWID is not 169 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 170 * address. According LSI's confirmation, the top nibble of RAID WWID is 171 * meanless, so the consensus between Solaris and OBP is to replace top nibble 172 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 173 * format unit address. 174 */ 175 #define MPTSAS_RAID_WWID(wwid) \ 176 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 177 178 typedef struct mptsas_target { 179 uint64_t m_sas_wwn; /* hash key1 */ 180 uint8_t m_phymask; /* hash key2 */ 181 /* 182 * m_dr_flag is a flag for DR, make sure the member 183 * take the place of dr_flag of mptsas_hash_data. 184 */ 185 uint8_t m_dr_flag; /* dr_flag */ 186 uint16_t m_devhdl; 187 uint32_t m_deviceinfo; 188 uint8_t m_phynum; 189 uint32_t m_dups; 190 int32_t m_timeout; 191 int32_t m_timebase; 192 int32_t m_t_throttle; 193 int32_t m_t_ncmds; 194 int32_t m_reset_delay; 195 int32_t m_t_nwait; 196 197 uint16_t m_qfull_retry_interval; 198 uint8_t m_qfull_retries; 199 200 } mptsas_target_t; 201 202 typedef struct mptsas_smp { 203 uint64_t m_sasaddr; /* hash key1 */ 204 uint8_t m_phymask; /* hash key2 */ 205 uint8_t reserved1; 206 uint16_t m_devhdl; 207 uint32_t m_deviceinfo; 208 } mptsas_smp_t; 209 210 typedef struct mptsas_hash_data { 211 uint64_t key1; 212 uint8_t key2; 213 uint8_t dr_flag; 214 uint16_t devhdl; 215 uint32_t device_info; 216 } mptsas_hash_data_t; 217 218 typedef struct mptsas_cache_frames { 219 ddi_dma_handle_t m_dma_hdl; 220 ddi_acc_handle_t m_acc_hdl; 221 caddr_t m_frames_addr; 222 uint32_t m_phys_addr; 223 } mptsas_cache_frames_t; 224 225 typedef struct mptsas_cmd { 226 uint_t cmd_flags; /* flags from scsi_init_pkt */ 227 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 228 ddi_dma_cookie_t cmd_cookie; 229 uint_t cmd_cookiec; 230 uint_t cmd_winindex; 231 uint_t cmd_nwin; 232 uint_t cmd_cur_cookie; 233 off_t cmd_dma_offset; 234 size_t cmd_dma_len; 235 uint32_t cmd_totaldmacount; 236 237 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 238 ddi_dma_cookie_t cmd_arqcookie; 239 struct buf *cmd_arq_buf; 240 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 241 ddi_dma_cookie_t cmd_ext_arqcookie; 242 struct buf *cmd_ext_arq_buf; 243 244 int cmd_pkt_flags; 245 246 /* timer for command in active slot */ 247 int cmd_active_timeout; 248 249 struct scsi_pkt *cmd_pkt; 250 struct scsi_arq_status cmd_scb; 251 uchar_t cmd_cdblen; /* length of cdb */ 252 uchar_t cmd_rqslen; /* len of requested rqsense */ 253 uchar_t cmd_privlen; 254 uint_t cmd_scblen; 255 uint32_t cmd_dmacount; 256 uint64_t cmd_dma_addr; 257 uchar_t cmd_age; 258 ushort_t cmd_qfull_retries; 259 uchar_t cmd_queued; /* true if queued */ 260 struct mptsas_cmd *cmd_linkp; 261 mptti_t *cmd_sg; /* Scatter/Gather structure */ 262 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 263 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 264 uint32_t cmd_slot; 265 uint32_t ioc_cmd_slot; 266 267 mptsas_cache_frames_t *cmd_extra_frames; 268 269 uint32_t cmd_rfm; 270 mptsas_target_t *cmd_tgt_addr; 271 } mptsas_cmd_t; 272 273 /* 274 * These are the defined cmd_flags for this structure. 275 */ 276 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 277 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 278 #define CFLAG_FINISHED 0x000004 /* command completed */ 279 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 280 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 281 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 282 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 283 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 284 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 285 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 286 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 287 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 288 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 289 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 290 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 291 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 292 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 293 #define CFLAG_FREE 0x010000 /* packet is on free list */ 294 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 295 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 296 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 297 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 298 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 299 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 300 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 301 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 302 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 303 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 304 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 305 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 306 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 307 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 308 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 309 310 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 311 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 312 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 313 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 314 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 315 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 316 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 317 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 318 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 319 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 320 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 321 322 #define MPTSAS_HASH_ARRAY_SIZE 16 323 /* 324 * hash table definition 325 */ 326 327 #define MPTSAS_HASH_FIRST 0xffff 328 #define MPTSAS_HASH_NEXT 0x0000 329 330 typedef struct mptsas_dma_alloc_state 331 { 332 ddi_dma_handle_t handle; 333 caddr_t memp; 334 size_t size; 335 ddi_acc_handle_t accessp; 336 ddi_dma_cookie_t cookie; 337 } mptsas_dma_alloc_state_t; 338 339 /* 340 * passthrough request structure 341 */ 342 typedef struct mptsas_pt_request { 343 uint8_t *request; 344 uint32_t request_size; 345 uint32_t data_size; 346 uint32_t dataout_size; 347 uint32_t direction; 348 ddi_dma_cookie_t data_cookie; 349 ddi_dma_cookie_t dataout_cookie; 350 } mptsas_pt_request_t; 351 352 /* 353 * config page request structure 354 */ 355 typedef struct mptsas_config_request { 356 uint32_t page_address; 357 uint8_t action; 358 uint8_t page_type; 359 uint8_t page_number; 360 uint8_t page_length; 361 uint8_t page_version; 362 uint8_t ext_page_type; 363 uint16_t ext_page_length; 364 } mptsas_config_request_t; 365 366 typedef struct mptsas_fw_diagnostic_buffer { 367 mptsas_dma_alloc_state_t buffer_data; 368 uint8_t extended_type; 369 uint8_t buffer_type; 370 uint8_t force_release; 371 uint32_t product_specific[23]; 372 uint8_t immediate; 373 uint8_t enabled; 374 uint8_t valid_data; 375 uint8_t owned_by_firmware; 376 uint32_t unique_id; 377 } mptsas_fw_diagnostic_buffer_t; 378 379 /* 380 * FW diag request structure 381 */ 382 typedef struct mptsas_diag_request { 383 mptsas_fw_diagnostic_buffer_t *pBuffer; 384 uint8_t function; 385 } mptsas_diag_request_t; 386 387 typedef struct mptsas_hash_node { 388 void *data; 389 struct mptsas_hash_node *next; 390 } mptsas_hash_node_t; 391 392 typedef struct mptsas_hash_table { 393 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 394 /* 395 * last position in traverse 396 */ 397 struct mptsas_hash_node *cur; 398 uint16_t line; 399 400 } mptsas_hash_table_t; 401 402 /* 403 * RAID volume information 404 */ 405 typedef struct mptsas_raidvol { 406 ushort_t m_israid; 407 uint16_t m_raidhandle; 408 uint64_t m_raidwwid; 409 uint8_t m_state; 410 uint32_t m_statusflags; 411 uint32_t m_settings; 412 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 413 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 414 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 415 uint64_t m_raidsize; 416 int m_raidlevel; 417 int m_ndisks; 418 mptsas_target_t *m_raidtgt; 419 } mptsas_raidvol_t; 420 421 /* 422 * RAID configurations 423 */ 424 typedef struct mptsas_raidconfig { 425 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 426 uint16_t m_physdisk_devhdl[ 427 MPTSAS_MAX_DISKS_IN_CONFIG]; 428 uint8_t m_native; 429 } m_raidconfig_t; 430 431 /* 432 * Structure to hold active outstanding cmds. Also, keep 433 * timeout on a per target basis. 434 */ 435 typedef struct mptsas_slots { 436 mptsas_hash_table_t m_tgttbl; 437 mptsas_hash_table_t m_smptbl; 438 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 439 uint8_t m_num_raid_configs; 440 uint16_t m_tags; 441 size_t m_size; 442 uint16_t m_n_slots; 443 mptsas_cmd_t *m_slot[1]; 444 } mptsas_slots_t; 445 446 /* 447 * Structure to hold command and packets for event ack 448 * and task management commands. 449 */ 450 typedef struct m_event_struct { 451 struct mptsas_cmd m_event_cmd; 452 struct m_event_struct *m_event_linkp; 453 /* 454 * event member record the failure event and eventcntx 455 * event member would be used in send ack pending process 456 */ 457 uint32_t m_event; 458 uint32_t m_eventcntx; 459 uint_t in_use; 460 struct scsi_pkt m_event_pkt; /* must be last */ 461 /* ... scsi_pkt_size() */ 462 } m_event_struct_t; 463 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 464 sizeof (struct scsi_pkt) + scsi_pkt_size()) 465 466 #define MAX_IOC_COMMANDS 8 467 468 /* 469 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 470 * A new event ack command requests mptsas_cmd and scsi_pkt structures 471 * from this pool, and returns it back when done. 472 */ 473 474 typedef struct m_replyh_arg { 475 void *mpt; 476 uint32_t rfm; 477 } m_replyh_arg_t; 478 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 479 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 480 481 /* 482 * Flags for DR handler topology change 483 */ 484 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 485 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 486 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 487 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 488 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 489 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 490 491 typedef struct mptsas_topo_change_list { 492 void *mpt; 493 uint_t event; 494 union { 495 uint8_t physport; 496 uint8_t phymask; 497 } un; 498 uint16_t devhdl; 499 void *object; 500 uint8_t flags; 501 struct mptsas_topo_change_list *next; 502 } mptsas_topo_change_list_t; 503 504 505 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 506 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 507 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 508 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 509 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 510 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 511 512 /* 513 * Status types when calling mptsas_get_target_device_info 514 */ 515 #define DEV_INFO_SUCCESS 0x0 516 #define DEV_INFO_FAIL_PAGE0 0x1 517 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 518 #define DEV_INFO_PHYS_DISK 0x3 519 #define DEV_INFO_FAIL_ALLOC 0x4 520 521 /* 522 * mpt hotplug event defines 523 */ 524 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 525 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 526 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 527 528 /* 529 * SMP target hotplug events 530 */ 531 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 532 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 533 #define MPTSAS_DR_EVENT_MASK 0x3F 534 535 /* 536 * mpt hotplug status definition for m_dr_flag 537 */ 538 539 /* 540 * MPTSAS_DR_INACTIVE 541 * 542 * The target is in a normal operating state. 543 * No dynamic reconfiguration operation is in progress. 544 */ 545 #define MPTSAS_DR_INACTIVE 0x0 546 /* 547 * MPTSAS_DR_INTRANSITION 548 * 549 * The target is in a transition mode since 550 * hotplug event happens and offline procedure has not 551 * been finished 552 */ 553 #define MPTSAS_DR_INTRANSITION 0x1 554 555 typedef struct mptsas_tgt_private { 556 int t_lun; 557 struct mptsas_target *t_private; 558 } mptsas_tgt_private_t; 559 560 /* 561 * The following defines are used in mptsas_set_init_mode to track the current 562 * state as we progress through reprogramming the HBA from target mode into 563 * initiator mode. 564 */ 565 566 #define IOUC_READ_PAGE0 0x00000100 567 #define IOUC_READ_PAGE1 0x00000200 568 #define IOUC_WRITE_PAGE1 0x00000400 569 #define IOUC_DONE 0x00000800 570 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 571 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 572 573 /* 574 * Last allocated slot is used for TM requests. Since only m_max_requests 575 * frames are allocated, the last SMID will be m_max_requests - 1. 576 */ 577 #define MPTSAS_SLOTS_SIZE(mpt) \ 578 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 579 mpt->m_max_requests)) 580 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 581 582 /* 583 * Macro for phy_flags 584 */ 585 typedef struct mptsas_phy_info { 586 uint8_t port_num; 587 uint8_t port_flags; 588 uint16_t ctrl_devhdl; 589 uint32_t phy_device_type; 590 uint16_t attached_devhdl; 591 uint8_t phy_mask; 592 } mptsas_phy_info_t; 593 594 typedef struct mptsas_doneq_thread_arg { 595 void *mpt; 596 uint64_t t; 597 } mptsas_doneq_thread_arg_t; 598 599 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 600 typedef struct mptsas_doneq_thread_list { 601 mptsas_cmd_t *doneq; 602 mptsas_cmd_t **donetail; 603 kthread_t *threadp; 604 kcondvar_t cv; 605 ushort_t reserv1; 606 uint32_t reserv2; 607 kmutex_t mutex; 608 uint32_t flag; 609 uint32_t len; 610 mptsas_doneq_thread_arg_t arg; 611 } mptsas_doneq_thread_list_t; 612 613 typedef struct mptsas { 614 int m_instance; 615 616 struct mptsas *m_next; 617 618 scsi_hba_tran_t *m_tran; 619 smp_hba_tran_t *m_smptran; 620 kmutex_t m_mutex; 621 kcondvar_t m_cv; 622 kcondvar_t m_passthru_cv; 623 kcondvar_t m_fw_cv; 624 kcondvar_t m_config_cv; 625 kcondvar_t m_fw_diag_cv; 626 dev_info_t *m_dip; 627 628 /* 629 * soft state flags 630 */ 631 uint_t m_softstate; 632 633 struct mptsas_slots *m_active; /* outstanding cmds */ 634 635 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 636 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 637 638 kmutex_t m_tx_waitq_mutex; 639 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 640 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 641 int m_tx_draining; /* TX queue draining flag */ 642 643 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 644 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 645 646 /* 647 * variables for helper threads (fan-out interrupts) 648 */ 649 mptsas_doneq_thread_list_t *m_doneq_thread_id; 650 uint32_t m_doneq_thread_n; 651 uint32_t m_doneq_thread_threshold; 652 uint32_t m_doneq_length_threshold; 653 uint32_t m_doneq_len; 654 kcondvar_t m_doneq_thread_cv; 655 kmutex_t m_doneq_mutex; 656 657 int m_ncmds; /* number of outstanding commands */ 658 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 659 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 660 661 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 662 663 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 664 665 ushort_t m_devid; /* device id of chip. */ 666 uchar_t m_revid; /* revision of chip. */ 667 uint16_t m_svid; /* subsystem Vendor ID of chip */ 668 uint16_t m_ssid; /* subsystem Device ID of chip */ 669 670 uchar_t m_sync_offset; /* default offset for this chip. */ 671 672 timeout_id_t m_quiesce_timeid; 673 timeout_id_t m_pm_timeid; 674 675 ddi_dma_handle_t m_dma_req_frame_hdl; 676 ddi_acc_handle_t m_acc_req_frame_hdl; 677 ddi_dma_handle_t m_dma_reply_frame_hdl; 678 ddi_acc_handle_t m_acc_reply_frame_hdl; 679 ddi_dma_handle_t m_dma_free_queue_hdl; 680 ddi_acc_handle_t m_acc_free_queue_hdl; 681 ddi_dma_handle_t m_dma_post_queue_hdl; 682 ddi_acc_handle_t m_acc_post_queue_hdl; 683 684 /* 685 * list of reset notification requests 686 */ 687 struct scsi_reset_notify_entry *m_reset_notify_listf; 688 689 /* 690 * qfull handling 691 */ 692 timeout_id_t m_restart_cmd_timeid; 693 694 /* 695 * scsi reset delay per bus 696 */ 697 uint_t m_scsi_reset_delay; 698 699 int m_pm_idle_delay; 700 701 uchar_t m_polled_intr; /* intr was polled. */ 702 uchar_t m_suspended; /* true if driver is suspended */ 703 704 struct kmem_cache *m_kmem_cache; 705 struct kmem_cache *m_cache_frames; 706 707 /* 708 * hba options. 709 */ 710 uint_t m_options; 711 712 int m_in_callback; 713 714 int m_power_level; /* current power level */ 715 716 int m_busy; /* power management busy state */ 717 718 off_t m_pmcsr_offset; /* PMCSR offset */ 719 720 ddi_acc_handle_t m_config_handle; 721 722 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 723 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 724 ddi_device_acc_attr_t m_dev_acc_attr; 725 ddi_device_acc_attr_t m_reg_acc_attr; 726 727 /* 728 * request/reply variables 729 */ 730 caddr_t m_req_frame; 731 uint64_t m_req_frame_dma_addr; 732 caddr_t m_reply_frame; 733 uint64_t m_reply_frame_dma_addr; 734 caddr_t m_free_queue; 735 uint64_t m_free_queue_dma_addr; 736 caddr_t m_post_queue; 737 uint64_t m_post_queue_dma_addr; 738 739 m_replyh_arg_t *m_replyh_args; 740 741 uint16_t m_max_requests; 742 uint16_t m_req_frame_size; 743 744 /* 745 * Max frames per request reprted in IOC Facts 746 */ 747 uint8_t m_max_chain_depth; 748 /* 749 * Max frames per request which is used in reality. It's adjusted 750 * according DMA SG length attribute, and shall not exceed the 751 * m_max_chain_depth. 752 */ 753 uint8_t m_max_request_frames; 754 755 uint16_t m_free_queue_depth; 756 uint16_t m_post_queue_depth; 757 uint16_t m_max_replies; 758 uint32_t m_free_index; 759 uint32_t m_post_index; 760 uint8_t m_reply_frame_size; 761 uint32_t m_ioc_capabilities; 762 763 /* 764 * indicates if the firmware was upload by the driver 765 * at boot time 766 */ 767 ushort_t m_fwupload; 768 769 uint16_t m_productid; 770 771 /* 772 * per instance data structures for dma memory resources for 773 * MPI handshake protocol. only one handshake cmd can run at a time. 774 */ 775 ddi_dma_handle_t m_hshk_dma_hdl; 776 777 ddi_acc_handle_t m_hshk_acc_hdl; 778 779 caddr_t m_hshk_memp; 780 781 size_t m_hshk_dma_size; 782 783 /* Firmware version on the card at boot time */ 784 uint32_t m_fwversion; 785 786 /* MSI specific fields */ 787 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 788 int m_intr_type; /* What type of interrupt */ 789 int m_intr_cnt; /* # of intrs count returned */ 790 size_t m_intr_size; /* Size of intr array */ 791 uint_t m_intr_pri; /* Interrupt priority */ 792 int m_intr_cap; /* Interrupt capabilities */ 793 ddi_taskq_t *m_event_taskq; 794 795 /* SAS specific information */ 796 797 union { 798 uint64_t m_base_wwid; /* Base WWID */ 799 struct { 800 #ifdef _BIG_ENDIAN 801 uint32_t m_base_wwid_hi; 802 uint32_t m_base_wwid_lo; 803 #else 804 uint32_t m_base_wwid_lo; 805 uint32_t m_base_wwid_hi; 806 #endif 807 } sasaddr; 808 } un; 809 810 uint8_t m_num_phys; /* # of PHYs */ 811 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 812 uint8_t m_port_chng; /* initiator port changes */ 813 814 /* FMA Capabilities */ 815 int m_fm_capabilities; 816 ddi_taskq_t *m_dr_taskq; 817 int m_mpxio_enable; 818 uint8_t m_done_traverse_dev; 819 uint8_t m_done_traverse_smp; 820 int m_passthru_in_progress; 821 int m_diag_action_in_progress; 822 uint16_t m_dev_handle; 823 uint16_t m_smp_devhdl; 824 825 /* 826 * Event recording 827 */ 828 uint8_t m_event_index; 829 uint32_t m_event_number; 830 uint32_t m_event_mask[4]; 831 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 832 833 /* 834 * FW diag Buffer List 835 */ 836 mptsas_fw_diagnostic_buffer_t 837 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 838 839 /* 840 * Event Replay flag (MUR support) 841 */ 842 uint8_t m_event_replay; 843 844 /* 845 * IR Capable flag 846 */ 847 uint8_t m_ir_capable; 848 849 /* 850 * Is HBA processing a diag reset? 851 */ 852 uint8_t m_in_reset; 853 854 /* 855 * per instance cmd data structures for task management cmds 856 */ 857 m_event_struct_t m_event_task_mgmt; /* must be last */ 858 /* ... scsi_pkt_size */ 859 } mptsas_t; 860 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 861 sizeof (struct scsi_pkt) + scsi_pkt_size()) 862 /* 863 * Only one of below two conditions is satisfied, we 864 * think the target is associated to the iport and 865 * allow call into mptsas_probe_lun(). 866 * 1. physicalsport == physport 867 * 2. (phymask & (1 << physport)) == 0 868 * The condition #2 is because LSI uses lowest PHY 869 * number as the value of physical port when auto port 870 * configuration. 871 */ 872 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 873 ((physicalport == physport) || (dynamicport && (phymask & \ 874 (1 << physport)))) 875 876 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 877 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 878 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 879 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 880 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 881 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 882 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 883 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 884 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 885 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 886 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 887 888 /* 889 * These should eventually migrate into the mpt header files 890 * that may become the /kernel/misc/mpt module... 891 */ 892 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 893 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 894 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 895 mptsas_put_msg_Function(hdl, mp, Function); \ 896 mptsas_put_msg_Lun(hdl, mp, Lun) 897 898 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 899 ddi_put16(hdl, &(mp)->DevHandle, (val)) 900 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 901 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 902 #define mptsas_put_msg_Function(hdl, mp, val) \ 903 ddi_put8(hdl, &(mp)->Function, (val)) 904 #define mptsas_put_msg_Lun(hdl, mp, val) \ 905 ddi_put8(hdl, &(mp)->LUN[1], (val)) 906 907 #define mptsas_get_msg_Function(hdl, mp) \ 908 ddi_get8(hdl, &(mp)->Function) 909 910 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 911 ddi_get8(hdl, &(mp)->MsgFlags) 912 913 #define MPTSAS_ENABLE_DRWE(hdl) \ 914 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 915 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 916 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 917 MPI2_WRSEQ_1ST_KEY_VALUE); \ 918 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 919 MPI2_WRSEQ_2ND_KEY_VALUE); \ 920 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 921 MPI2_WRSEQ_3RD_KEY_VALUE); \ 922 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 923 MPI2_WRSEQ_4TH_KEY_VALUE); \ 924 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 925 MPI2_WRSEQ_5TH_KEY_VALUE); \ 926 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 927 MPI2_WRSEQ_6TH_KEY_VALUE); 928 929 /* 930 * m_options flags 931 */ 932 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 933 934 /* 935 * m_softstate flags 936 */ 937 #define MPTSAS_SS_DRAINING 0x02 938 #define MPTSAS_SS_QUIESCED 0x04 939 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 940 941 /* 942 * regspec defines. 943 */ 944 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 945 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 946 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 947 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 948 949 /* 950 * Handy constants 951 */ 952 #define FALSE 0 953 #define TRUE 1 954 #define UNDEFINED -1 955 #define FAILED -2 956 957 /* 958 * power management. 959 */ 960 #define MPTSAS_POWER_ON(mpt) { \ 961 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 962 PCI_PMCSR_D0); \ 963 delay(drv_usectohz(10000)); \ 964 (void) pci_restore_config_regs(mpt->m_dip); \ 965 mptsas_setup_cmd_reg(mpt); \ 966 } 967 968 #define MPTSAS_POWER_OFF(mpt) { \ 969 (void) pci_save_config_regs(mpt->m_dip); \ 970 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 971 PCI_PMCSR_D3HOT); \ 972 mpt->m_power_level = PM_LEVEL_D3; \ 973 } 974 975 /* 976 * inq_dtype: 977 * Bits 5 through 7 are the Peripheral Device Qualifier 978 * 001b: device not connected to the LUN 979 * Bits 0 through 4 are the Peripheral Device Type 980 * 1fh: Unknown or no device type 981 * 982 * Although the inquiry may return success, the following value 983 * means no valid LUN connected. 984 */ 985 #define MPTSAS_VALID_LUN(sd_inq) \ 986 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 987 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 988 989 /* 990 * Default is to have 10 retries on receiving QFULL status and 991 * each retry to be after 100 ms. 992 */ 993 #define QFULL_RETRIES 10 994 #define QFULL_RETRY_INTERVAL 100 995 996 /* 997 * Handy macros 998 */ 999 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1000 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1001 1002 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1003 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1004 1005 /* 1006 * poll time for mptsas_pollret() and mptsas_wait_intr() 1007 */ 1008 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1009 1010 /* 1011 * default time for mptsas_do_passthru 1012 */ 1013 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1014 1015 /* 1016 * macro to return the effective address of a given per-target field 1017 */ 1018 #define EFF_ADDR(start, offset) ((start) + (offset)) 1019 1020 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1021 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1022 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1023 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1024 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1025 1026 1027 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1028 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1029 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1030 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1031 1032 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1033 1034 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1035 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1036 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1037 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1038 1039 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1040 &(mpt)->m_reg->HostInterruptStatus)) 1041 1042 #define MPTSAS_SET_SIGP(P) \ 1043 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1044 1045 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1046 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1047 1048 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1049 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1050 1051 1052 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1053 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1054 req_desc_lo);\ 1055 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1056 req_desc_hi); 1057 1058 #define INTPENDING(mpt) \ 1059 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1060 1061 /* 1062 * Mask all interrupts to disable 1063 */ 1064 #define MPTSAS_DISABLE_INTR(mpt) \ 1065 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1066 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1067 1068 /* 1069 * Mask Doorbell and Reset interrupts to enable reply desc int. 1070 */ 1071 #define MPTSAS_ENABLE_INTR(mpt) \ 1072 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1073 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1074 1075 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1076 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1077 1078 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1079 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1080 1081 #define ClrSetBits32(hdl, reg, clr, set) \ 1082 ddi_put32(hdl, (reg), \ 1083 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1084 1085 #define ClrSetBits(reg, clr, set) \ 1086 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1087 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1088 1089 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1090 if ((cmdp = mpt->m_waitq) != NULL) { \ 1091 /* If the queue is now empty fix the tail pointer */ \ 1092 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1093 mpt->m_waitqtail = &mpt->m_waitq; \ 1094 cmdp->cmd_linkp = NULL; \ 1095 cmdp->cmd_queued = FALSE; \ 1096 } 1097 1098 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1099 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1100 /* If the queue is now empty fix the tail pointer */ \ 1101 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1102 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1103 cmdp->cmd_linkp = NULL; \ 1104 cmdp->cmd_queued = FALSE; \ 1105 } 1106 1107 /* 1108 * defaults for the global properties 1109 */ 1110 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1111 #define DEFAULT_TAG_AGE_LIMIT 2 1112 #define DEFAULT_WD_TICK 10 1113 1114 /* 1115 * invalid hostid. 1116 */ 1117 #define MPTSAS_INVALID_HOSTID -1 1118 1119 /* 1120 * Get/Set hostid from SCSI port configuration page 1121 */ 1122 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1123 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1124 1125 /* 1126 * Config space. 1127 */ 1128 #define MPTSAS_LATENCY_TIMER 0x40 1129 1130 /* 1131 * Offset to firmware version 1132 */ 1133 #define MPTSAS_FW_VERSION_OFFSET 9 1134 1135 /* 1136 * Offset and masks to get at the ProductId field 1137 */ 1138 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1139 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1140 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1141 1142 /* 1143 * Subsystem ID for HBAs. 1144 */ 1145 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1146 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1147 1148 /* 1149 * reset delay tick 1150 */ 1151 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1152 1153 /* 1154 * Ioc reset return values 1155 */ 1156 #define MPTSAS_RESET_FAIL -1 1157 #define MPTSAS_NO_RESET 0 1158 #define MPTSAS_SUCCESS_HARDRESET 1 1159 1160 /* 1161 * throttle support. 1162 */ 1163 #define MAX_THROTTLE 32 1164 #define HOLD_THROTTLE 0 1165 #define DRAIN_THROTTLE -1 1166 #define QFULL_THROTTLE -2 1167 1168 /* 1169 * Passthrough/config request flags 1170 */ 1171 #define MPTSAS_DATA_ALLOCATED 0x0001 1172 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1173 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1174 #define MPTSAS_ADDRESS_REPLY 0x0008 1175 #define MPTSAS_CMD_TIMEOUT 0x0010 1176 1177 /* 1178 * response code tlr flag 1179 */ 1180 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1181 1182 /* 1183 * System Events 1184 */ 1185 #ifndef DDI_VENDOR_LSI 1186 #define DDI_VENDOR_LSI "LSI" 1187 #endif /* DDI_VENDOR_LSI */ 1188 1189 /* 1190 * Shared functions 1191 */ 1192 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1193 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1194 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1195 int mptsas_config_space_init(struct mptsas *mpt); 1196 int mptsas_init_chip(mptsas_t *mpt, int first_time); 1197 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1198 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1199 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1200 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1201 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1202 uint8_t pageversion, uint8_t pagelength, uint32_t 1203 SGEflagslength, uint32_t SGEaddress32); 1204 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1205 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1206 uint8_t pageversion, uint16_t extpagelength, 1207 uint32_t SGEflagslength, uint32_t SGEaddress32); 1208 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1209 uint8_t type, int mode); 1210 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1211 uint8_t type, int mode); 1212 int mptsas_download_firmware(); 1213 int mptsas_can_download_firmware(); 1214 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1215 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1216 uint8_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1217 uint8_t mptsas_phymask_to_physport(mptsas_t *mpt, uint8_t phymask); 1218 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1219 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1220 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1221 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1222 1223 /* 1224 * impl functions 1225 */ 1226 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1227 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1228 int mptsas_ioc_reset(mptsas_t *mpt); 1229 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1230 ddi_acc_handle_t accessp); 1231 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1232 ddi_acc_handle_t accessp); 1233 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1234 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1235 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1236 uint32_t SGEaddress32); 1237 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1238 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1239 uint8_t pageversion, uint16_t extpagelength, 1240 uint32_t SGEflagslength, uint32_t SGEaddress32); 1241 1242 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1243 struct scsi_pkt **pkt); 1244 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1245 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1246 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1247 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1248 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1249 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1250 1251 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1252 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1253 int mode); 1254 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1255 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1256 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1257 int mptsas_restart_ioc(mptsas_t *mpt); 1258 void mptsas_update_driver_data(struct mptsas *mpt); 1259 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1260 1261 /* 1262 * init functions 1263 */ 1264 int mptsas_ioc_get_facts(mptsas_t *mpt); 1265 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1266 int mptsas_ioc_enable_port(mptsas_t *mpt); 1267 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1268 int mptsas_ioc_init(mptsas_t *mpt); 1269 1270 /* 1271 * configuration pages operation 1272 */ 1273 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1274 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1275 uint8_t *physport, uint8_t *phynum); 1276 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1277 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1278 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1279 mptsas_smp_t *info); 1280 int mptsas_set_initiator_mode(mptsas_t *mpt); 1281 int mptsas_set_ioc_params(mptsas_t *mpt); 1282 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1283 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1284 uint64_t *sas_wwn, uint8_t *portwidth); 1285 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1286 1287 /* 1288 * RAID functions 1289 */ 1290 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1291 int mptsas_get_raid_info(mptsas_t *mpt); 1292 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1293 uint8_t physdisknum); 1294 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1295 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1296 1297 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1298 /* 1299 * debugging. 1300 */ 1301 #if defined(MPTSAS_DEBUG) 1302 1303 void mptsas_printf(char *fmt, ...); 1304 1305 #define MPTSAS_DBGPR(m, args) \ 1306 if (mptsas_debug_flags & (m)) \ 1307 mptsas_printf args 1308 #else /* ! defined(MPTSAS_DEBUG) */ 1309 #define MPTSAS_DBGPR(m, args) 1310 #endif /* defined(MPTSAS_DEBUG) */ 1311 1312 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1313 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1314 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1315 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1316 1317 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1318 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1319 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1320 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1321 1322 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1323 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1324 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1325 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1326 1327 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1328 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1329 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) 1330 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1331 1332 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1333 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1334 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1335 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1336 1337 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1338 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1339 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1340 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1341 1342 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1343 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1344 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1345 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1346 1347 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1348 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1349 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1350 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1351 1352 /* 1353 * auto request sense 1354 */ 1355 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1356 (pkt)->pkt_flags = (flag), \ 1357 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1358 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1359 (pkt)->pkt_address.a_lun 1360 1361 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1362 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1363 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1364 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1365 1366 1367 #ifdef __cplusplus 1368 } 1369 #endif 1370 1371 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1372