1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NV_SATA_H 28 #define _NV_SATA_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 37 38 typedef struct nv_port nv_port_t; 39 40 typedef struct nv_ctl { 41 /* 42 * Each of these are specific to the chipset in use. 43 */ 44 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 45 void (*nvc_reg_init)(struct nv_ctl *nvc, 46 ddi_acc_handle_t pci_conf_handle); 47 48 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 49 50 struct nv_port *nvc_port; /* array of pointers to port struct */ 51 52 /* 53 * handle and base address to register space. 54 * 55 * 0: port 0 task file 56 * 1: port 0 status 57 * 2: port 1 task file 58 * 3: port 1 status 59 * 4: bus master for both ports 60 * 5: extended registers for SATA features 61 */ 62 ddi_acc_handle_t nvc_bar_hdl[6]; 63 uchar_t *nvc_bar_addr[6]; 64 65 /* 66 * sata registers in bar 5 which are shared on all devices 67 * on the channel. 68 */ 69 uint32_t *nvc_mcp55_ctl; 70 uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */ 71 72 kmutex_t nvc_mutex; /* ctrl level lock */ 73 74 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 75 int nvc_intr_type; /* What type of interrupt */ 76 int nvc_intr_cnt; /* # of intrs count returned */ 77 size_t nvc_intr_size; /* Size of intr array to */ 78 uint_t nvc_intr_pri; /* Interrupt priority */ 79 int nvc_intr_cap; /* Interrupt capabilities */ 80 uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */ 81 82 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 83 84 /* 85 * enable/disable interrupts, controller specific 86 */ 87 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 88 int nvc_state; /* state flags of ctrl see below */ 89 uint8_t nvc_revid; /* PCI revid of device */ 90 } nv_ctl_t; 91 92 93 struct nv_port { 94 95 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 96 97 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 98 99 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 100 uint32_t nvp_signature; /* sig acquired from task file regs */ 101 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 102 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 103 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 104 105 ddi_acc_handle_t nvp_cmd_hdl; 106 uchar_t *nvp_data; /* data register */ 107 uchar_t *nvp_error; /* error register (read) */ 108 uchar_t *nvp_feature; /* features (write) */ 109 uchar_t *nvp_count; /* sector count */ 110 uchar_t *nvp_sect; /* sector number */ 111 uchar_t *nvp_lcyl; /* cylinder low byte */ 112 uchar_t *nvp_hcyl; /* cylinder high byte */ 113 uchar_t *nvp_drvhd; /* drive/head register */ 114 uchar_t *nvp_status; /* status/command register */ 115 uchar_t *nvp_cmd; /* status/command register */ 116 117 ddi_acc_handle_t nvp_ctl_hdl; 118 uchar_t *nvp_altstatus; /* alternate status (read) */ 119 uchar_t *nvp_devctl; /* device control (write) */ 120 121 ddi_acc_handle_t nvp_bm_hdl; 122 uchar_t *nvp_bmisx; 123 uint32_t *nvp_bmidtpx; 124 uchar_t *nvp_bmicx; 125 126 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 127 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 128 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 129 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 130 131 uint32_t *nvp_sstatus; 132 uint32_t *nvp_serror; 133 uint32_t *nvp_sctrl; 134 uint32_t *nvp_sactive; 135 136 kmutex_t nvp_mutex; /* main per port mutex */ 137 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 138 139 /* 140 * nvp_slot is a pointer to an array of nv_slot 141 */ 142 struct nv_slot *nvp_slot; 143 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 144 uint8_t nvp_queue_depth; 145 146 /* 147 * NCQ flow control. During NCQ operation, no other commands 148 * allowed. The following are used to enforce this. 149 */ 150 int nvp_ncq_run; 151 int nvp_non_ncq_run; 152 153 timeout_id_t nvp_timeout_id; 154 155 clock_t nvp_reset_time; /* time of last reset */ 156 clock_t nvp_probe_time; /* time when probe began */ 157 clock_t nvp_link_lost_time; /* time link lost was noticed */ 158 159 int nvp_state; /* state of port. flags defined below */ 160 161 uint16_t *nvp_mcp55_int_status; 162 uint16_t *nvp_mcp55_int_ctl; 163 }; 164 165 166 typedef struct nv_device_table { 167 ushort_t vendor_id; /* vendor id */ 168 ushort_t device_id; /* device id */ 169 ushort_t type; /* chipset type, mcp04 or mcp55 */ 170 } nv_device_table_t; 171 172 173 typedef struct nv_slot { 174 caddr_t nvslot_v_addr; /* I/O buffer address */ 175 size_t nvslot_byte_count; /* # bytes left to read/write */ 176 sata_pkt_t *nvslot_spkt; 177 clock_t nvslot_stime; 178 int (*nvslot_start)(nv_port_t *nvp, int queue); 179 void (*nvslot_intr)(nv_port_t *nvp, 180 struct nv_slot *nv_slotp); 181 uint32_t nvslot_flags; 182 } nv_slot_t; 183 184 185 /* 186 * nvslot_flags 187 */ 188 #define NVSLOT_COMPLETE 0x01 189 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 190 191 /* 192 * state values for nv_attach 193 */ 194 #define ATTACH_PROGRESS_NONE (1 << 0) 195 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 196 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 197 #define ATTACH_PROGRESS_BARS (1 << 3) 198 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 199 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 200 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 201 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 202 #define ATTACH_PROGRESS_COUNT (1 << 8) 203 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 204 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 205 206 #ifdef DEBUG 207 208 #define NV_DEBUG 1 209 210 #endif /* DEBUG */ 211 212 213 /* 214 * nv_debug_flags 215 */ 216 #define NVDBG_ALWAYS 0x0001 217 #define NVDBG_INIT 0x0002 218 #define NVDBG_ENTRY 0x0004 219 #define NVDBG_DELIVER 0x0008 220 #define NVDBG_EVENT 0x0010 221 #define NVDBG_SYNC 0x0020 222 #define NVDBG_PKTCOMP 0x0040 223 #define NVDBG_TIMEOUT 0x0080 224 #define NVDBG_INFO 0x0100 225 #define NVDBG_VERBOSE 0x0200 226 #define NVDBG_INTR 0x0400 227 #define NVDBG_ERRS 0x0800 228 #define NVDBG_COOKIES 0x1000 229 #define NVDBG_HOT 0x2000 230 #define NVDBG_PROBE 0x4000 231 232 #ifdef DEBUG 233 #define NVLOG(a) nv_log a 234 #else 235 #define NVLOG(a) 236 #endif 237 238 #define NV_SUCCESS 0 239 #define NV_FAILURE -1 240 241 /* 242 * indicates whether nv_wait functions can sleep or not. 243 */ 244 #define NV_SLEEP 1 245 #define NV_NOSLEEP 2 246 247 /* 248 * port offsets from base address ioaddr1 249 */ 250 #define NV_DATA 0x00 /* data register */ 251 #define NV_ERROR 0x01 /* error register (read) */ 252 #define NV_FEATURE 0x01 /* features (write) */ 253 #define NV_COUNT 0x02 /* sector count */ 254 #define NV_SECT 0x03 /* sector number */ 255 #define NV_LCYL 0x04 /* cylinder low byte */ 256 #define NV_HCYL 0x05 /* cylinder high byte */ 257 #define NV_DRVHD 0x06 /* drive/head register */ 258 #define NV_STATUS 0x07 /* status/command register */ 259 #define NV_CMD 0x07 /* status/command register */ 260 261 /* 262 * port offsets from base address ioaddr2 263 */ 264 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 265 #define NV_DEVCTL 0x02 /* device control (write) */ 266 267 /* 268 * device control register 269 */ 270 #define ATDC_NIEN 0x02 /* disable interrupts */ 271 #define ATDC_SRST 0x04 /* controller reset */ 272 #define ATDC_D3 0x08 /* mysterious bit */ 273 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 274 275 276 #define MCP55_CTL 0x400 /* queuing control */ 277 #define MCP55_INT_STATUS 0x440 /* status bits for interrupt */ 278 #define MCP55_INT_CTL 0x444 /* enable bits for interrupt */ 279 #define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */ 280 281 /* 282 * if either of these bits are set, when using NCQ, if no other commands are 283 * active while a new command is started, DMA engine can be programmed ahead 284 * of time to save extra interrupt. Presumably pre-programming is discarded 285 * if a subsequent command ends up finishing first. 286 */ 287 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 288 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 289 290 /* 291 * bit definitions to indicate which NCQ command requires 292 * DMA setup. 293 */ 294 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 295 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 296 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 297 298 299 /* 300 * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS 301 */ 302 #define MCP55_INT_SNOTIFY 0x200 /* snotification set */ 303 #define MCP55_INT_SERROR 0x100 /* serror set */ 304 #define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 305 #define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */ 306 #define MCP55_INT_SDB_FIS 0x20 /* SDB FIS */ 307 #define MCP55_INT_TX_BACKOUT 0x10 /* TX backout */ 308 #define MCP55_INT_REM 0x08 /* device removed */ 309 #define MCP55_INT_ADD 0x04 /* device added */ 310 #define MCP55_INT_PM 0x02 /* power changed */ 311 #define MCP55_INT_COMPLETE 0x01 /* device interrupt */ 312 313 /* 314 * Bits above that are not used for now. 315 */ 316 #define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\ 317 MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\ 318 MCP55_INT_SNOTIFY|MCP55_INT_SERROR) 319 320 /* 321 * Bits for MCP_SATA_AE_CTL 322 */ 323 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 324 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 325 326 #define NV_DELAY_NSEC(wait_ns) \ 327 { \ 328 hrtime_t start, end; \ 329 start = end = gethrtime(); \ 330 while ((end - start) < wait_ns) \ 331 end = gethrtime(); \ 332 } 333 334 /* 335 * signatures in task file registers after device reset 336 */ 337 #define NV_SIG_DISK 0x00000101 338 #define NV_SIG_ATAPI 0xeb140101 339 #define NV_SIG_PM 0x96690101 340 #define NV_SIG_NOTREADY 0x00000000 341 342 /* 343 * These bar5 offsets are common to mcp55/mcp04 and thus 344 * prefixed with NV. 345 */ 346 #define NV_SSTATUS 0x00 347 #define NV_SERROR 0x04 348 #define NV_SCTRL 0x08 349 #define NV_SACTIVE 0x0c 350 #define NV_SNOTIFICATION 0x10 351 352 #define CH0_SREG_OFFSET 0x0 353 #define CH1_SREG_OFFSET 0x40 354 355 356 /* 357 * The following config space offsets are needed to enable 358 * bar 5 register access in mcp04/mcp55 359 */ 360 #define NV_SATA_CFG_20 0x50 361 #define NV_BAR5_SPACE_EN 0x04 362 #define NV_40BIT_PRD 0x20 363 364 /* 365 * mcp04 interrupt status register 366 */ 367 368 /* 369 * offsets to bar 5 registers 370 */ 371 #define MCP04_SATA_INT_STATUS 0x440 372 #define MCP04_SATA_INT_EN 0x441 373 374 375 /* 376 * bit fields for int status and int enable 377 * registers 378 */ 379 #define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */ 380 #define MCP04_INT_PDEV_PM 0x02 /* power change */ 381 #define MCP04_INT_PDEV_ADD 0x04 /* hot plug */ 382 #define MCP04_INT_PDEV_REM 0x08 /* hot remove */ 383 #define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM 384 385 #define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */ 386 #define MCP04_INT_SDEV_PM 0x20 /* power change */ 387 #define MCP04_INT_SDEV_ADD 0x40 /* hot plug */ 388 #define MCP04_INT_SDEV_REM 0x80 /* hot remove */ 389 #define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM 390 391 #define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\ 392 MCP04_INT_PDEV_PM 393 #define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\ 394 MCP04_INT_SDEV_PM 395 396 /* 397 * config space offset 42 398 */ 399 #define NV_SATA_CFG_42 0xac 400 401 /* 402 * bit in CFG_42 which delays hotplug interrupt until 403 * PHY ready 404 */ 405 #define MCP04_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 406 407 408 /* 409 * bar 5 offsets for SATA registers in ck804 410 */ 411 #define MCP04_CH1_SSTATUS 0x00 412 #define MCP04_CH1_SERROR 0x04 413 #define MCP04_CH1_SCTRL 0x08 414 #define MCP04_CH1_SACTIVE 0x0c 415 #define MCP04_CH1_SNOTIFICATION 0x10 416 417 #define MCP04_CH2_SSTATUS 0x40 418 #define MCP04_CH2_SERROR 0x44 419 #define MCP04_CH2_SCTRL 0x48 420 #define MCP04_CH2_SACTIVE 0x4c 421 #define MCP04_CH2_SNOTIFICATION 0x50 422 423 424 /* 425 * bar 5 offsets for ADMACTL settings for both mcp04/mcp55 426 */ 427 #define NV_ADMACTL_X 0x4C0 428 #define NV_ADMACTL_Y 0x5C0 429 430 /* 431 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 432 */ 433 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 434 #define NV_CH_RST 0x04 /* reset channel */ 435 436 437 /* 438 * bar 5 offset for ADMASTAT regs for mcp04 439 */ 440 #define MCP04_ADMASTAT_X 0x4C4 441 #define MCP04_ADMASTAT_Y 0x5C4 442 443 /* 444 * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y 445 */ 446 #define MCP04_HPIRQ 0x4 447 #define MCP05_HUIRQ 0x2 448 449 450 /* 451 * bar 4 offset to bus master command registers 452 */ 453 #define BMICX_REG 0 454 455 /* 456 * bit definitions for BMICX_REG 457 */ 458 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 459 /* 1=Start (Enable) */ 460 /* 0=Start (Disable) */ 461 462 /* 463 * NOTE: "read" and "write" are the actions of the DMA engine 464 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 465 * command, program the DMA engine to "write to memory" mode 466 * (and vice versa). 467 */ 468 #define BMICX_RWCON 0x08 /* Read/Write Control */ 469 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 470 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 471 472 /* 473 * BMICX bits to preserve during updates 474 */ 475 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 476 477 /* 478 * bar 4 offset to bus master status register 479 */ 480 #define BMISX_REG 2 481 482 /* 483 * bit fields for bus master status register 484 */ 485 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 486 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 487 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 488 489 /* 490 * bus master status register bits to preserve 491 */ 492 #define BMISX_MASK 0xf8 493 494 /* 495 * bar4 offset to bus master PRD descriptor table 496 */ 497 #define BMIDTPX_REG 4 498 499 500 /* 501 * structure for a single entry in the PRD table 502 * (physical region descriptor table) 503 */ 504 typedef struct prde { 505 uint32_t p_address; /* physical address */ 506 uint32_t p_count; /* byte count, EOT in high order bit */ 507 } prde_t; 508 509 510 #define PRDE_EOT ((uint_t)0x80000000) 511 512 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 513 514 /* 515 * ck804 and mcp55 both have 2 ports per controller 516 */ 517 #define NV_NUM_CPORTS 2 518 519 /* 520 * Number of slots to allocate in data nv_sata structures to handle 521 * multiple commands at once. This does not reflect the capability of 522 * the drive or the hardware, and in many cases will not match. 523 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 524 * enabled but the drive doesn't support it, or supports fewer than 525 * 32 slots, here may be an over allocation of memory. 526 */ 527 #ifdef NCQ 528 #define NV_QUEUE_SLOTS 32 529 #else 530 #define NV_QUEUE_SLOTS 1 531 #endif 532 533 /* 534 * wait 30 seconds for signature 535 */ 536 #define NV_SIG_TIMEOUT 45 537 538 #define NV_BM_64K_BOUNDARY 0x10000ull 539 540 /* 541 * every 1 second 542 */ 543 #define NV_ONE_SEC 1000000 544 545 546 /* 547 * the amount of time link can be down during 548 * reset without taking action. 549 */ 550 #define NV_LINK_LOST_OK 2 551 552 /* 553 * nv_reset() flags 554 */ 555 #define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */ 556 #define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */ 557 558 559 560 #define NV_RESET_ATTEMPTS 3 561 562 /* 563 * nvp_state flags 564 */ 565 #define NV_PORT_INACTIVE 0x001 566 #define NV_PORT_ABORTING 0x002 567 #define NV_PORT_HOTREMOVED 0x004 568 #define NV_PORT_INIT 0x008 569 #define NV_PORT_FAILED 0x010 570 #define NV_PORT_RESET 0x020 571 #define NV_PORT_RESET_PROBE 0x040 572 #define NV_PORT_RESTORE 0x080 573 574 /* 575 * nvc_state flags 576 */ 577 #define NV_CTRL_SUSPEND 0x1 578 579 580 /* 581 * flags for mcp04_set_intr/mcp55_set_intr 582 */ 583 #define NV_INTR_DISABLE 0x1 584 #define NV_INTR_ENABLE 0x2 585 #define NV_INTR_CLEAR_ALL 0x4 586 587 /* 588 * sizes of strings to allocate 589 */ 590 #define NV_STRING_10 10 591 #define NV_STRING_512 512 592 593 #define NV_BYTES_PER_SEC 512 594 595 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 596 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 597 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 598 #define MCP55_INT_CLEAR 0xffff /* clear all interrupts */ 599 600 /* 601 * definition labels for the BAR registers 602 */ 603 #define NV_BAR_0 0 /* chan 0 task file regs */ 604 #define NV_BAR_1 1 /* chan 0 status reg */ 605 #define NV_BAR_2 2 /* chan 1 task file regs */ 606 #define NV_BAR_3 3 /* chan 1 status reg */ 607 #define NV_BAR_4 4 /* bus master regs */ 608 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 609 610 /* 611 * transform seconds to microseconds 612 */ 613 #define NV_SEC2USEC(x) x * MICROSEC 614 615 616 /* 617 * ck804 maps in task file regs into bar 5. These are 618 * only used to identify ck804, therefore only this reg is 619 * listed here. 620 */ 621 #define NV_BAR5_TRAN_LEN_CH_X 0x518 622 623 /* 624 * if after this many iterations through the interrupt 625 * processing loop, declare the interrupt wedged and 626 * disable. 627 */ 628 #define NV_MAX_INTR_LOOP 10 629 630 /* 631 * flag values for nv_copy_regs_out 632 */ 633 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 634 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 635 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 636 637 638 #ifdef __cplusplus 639 } 640 #endif 641 642 #endif /* _NV_SATA_H */ 643