1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NV_SATA_H 28 #define _NV_SATA_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 37 38 typedef struct nv_port nv_port_t; 39 40 typedef struct nv_ctl { 41 /* 42 * Each of these are specific to the chipset in use. 43 */ 44 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 45 void (*nvc_reg_init)(struct nv_ctl *nvc, 46 ddi_acc_handle_t pci_conf_handle); 47 48 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 49 50 struct nv_port *nvc_port; /* array of pointers to port struct */ 51 52 /* 53 * handle and base address to register space. 54 * 55 * 0: port 0 task file 56 * 1: port 0 status 57 * 2: port 1 task file 58 * 3: port 1 status 59 * 4: bus master for both ports 60 * 5: extended registers for SATA features 61 */ 62 ddi_acc_handle_t nvc_bar_hdl[6]; 63 uchar_t *nvc_bar_addr[6]; 64 65 /* 66 * sata registers in bar 5 which are shared on all devices 67 * on the channel. 68 */ 69 uint32_t *nvc_mcp55_ctl; 70 uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */ 71 72 kmutex_t nvc_mutex; /* ctrl level lock */ 73 74 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 75 int nvc_intr_type; /* What type of interrupt */ 76 int nvc_intr_cnt; /* # of intrs count returned */ 77 size_t nvc_intr_size; /* Size of intr array to */ 78 uint_t nvc_intr_pri; /* Interrupt priority */ 79 int nvc_intr_cap; /* Interrupt capabilities */ 80 uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */ 81 82 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 83 84 /* 85 * enable/disable interrupts, controller specific 86 */ 87 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 88 int nvc_state; /* state flags of ctrl see below */ 89 uint8_t nvc_revid; /* PCI revid of device */ 90 } nv_ctl_t; 91 92 93 struct nv_port { 94 95 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 96 97 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 98 99 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 100 uint32_t nvp_signature; /* sig acquired from task file regs */ 101 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 102 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 103 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 104 105 ddi_acc_handle_t nvp_cmd_hdl; 106 uchar_t *nvp_data; /* data register */ 107 uchar_t *nvp_error; /* error register (read) */ 108 uchar_t *nvp_feature; /* features (write) */ 109 uchar_t *nvp_count; /* sector count */ 110 uchar_t *nvp_sect; /* sector number */ 111 uchar_t *nvp_lcyl; /* cylinder low byte */ 112 uchar_t *nvp_hcyl; /* cylinder high byte */ 113 uchar_t *nvp_drvhd; /* drive/head register */ 114 uchar_t *nvp_status; /* status/command register */ 115 uchar_t *nvp_cmd; /* status/command register */ 116 117 ddi_acc_handle_t nvp_ctl_hdl; 118 uchar_t *nvp_altstatus; /* alternate status (read) */ 119 uchar_t *nvp_devctl; /* device control (write) */ 120 121 ddi_acc_handle_t nvp_bm_hdl; 122 uchar_t *nvp_bmisx; 123 uint32_t *nvp_bmidtpx; 124 uchar_t *nvp_bmicx; 125 126 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 127 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 128 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 129 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 130 131 uint32_t *nvp_sstatus; 132 uint32_t *nvp_serror; 133 uint32_t *nvp_sctrl; 134 uint32_t *nvp_sactive; 135 136 kmutex_t nvp_mutex; /* main per port mutex */ 137 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 138 139 /* 140 * nvp_slot is a pointer to an array of nv_slot 141 */ 142 struct nv_slot *nvp_slot; 143 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 144 uint8_t nvp_queue_depth; 145 146 /* 147 * NCQ flow control. During NCQ operation, no other commands 148 * allowed. The following are used to enforce this. 149 */ 150 int nvp_ncq_run; 151 int nvp_non_ncq_run; 152 153 timeout_id_t nvp_timeout_id; 154 155 clock_t nvp_reset_time; /* time of last reset */ 156 clock_t nvp_probe_time; /* time when probe began */ 157 clock_t nvp_link_lost_time; /* time link lost was noticed */ 158 159 int nvp_state; /* state of port. flags defined below */ 160 161 uint16_t *nvp_mcp55_int_status; 162 uint16_t *nvp_mcp55_int_ctl; 163 }; 164 165 166 typedef struct nv_device_table { 167 ushort_t vendor_id; /* vendor id */ 168 ushort_t device_id; /* device id */ 169 ushort_t type; /* chipset type, mcp04 or mcp55 */ 170 } nv_device_table_t; 171 172 173 typedef struct nv_slot { 174 caddr_t nvslot_v_addr; /* I/O buffer address */ 175 size_t nvslot_byte_count; /* # bytes left to read/write */ 176 sata_pkt_t *nvslot_spkt; 177 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 178 clock_t nvslot_stime; 179 int (*nvslot_start)(nv_port_t *nvp, int queue); 180 void (*nvslot_intr)(nv_port_t *nvp, 181 struct nv_slot *nv_slotp); 182 uint32_t nvslot_flags; 183 } nv_slot_t; 184 185 186 /* 187 * nvslot_flags 188 */ 189 #define NVSLOT_COMPLETE 0x01 190 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 191 #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 192 193 /* 194 * state values for nv_attach 195 */ 196 #define ATTACH_PROGRESS_NONE (1 << 0) 197 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 198 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 199 #define ATTACH_PROGRESS_BARS (1 << 3) 200 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 201 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 202 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 203 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 204 #define ATTACH_PROGRESS_COUNT (1 << 8) 205 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 206 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 207 208 #ifdef DEBUG 209 210 #define NV_DEBUG 1 211 212 #endif /* DEBUG */ 213 214 215 /* 216 * nv_debug_flags 217 */ 218 #define NVDBG_ALWAYS 0x0001 219 #define NVDBG_INIT 0x0002 220 #define NVDBG_ENTRY 0x0004 221 #define NVDBG_DELIVER 0x0008 222 #define NVDBG_EVENT 0x0010 223 #define NVDBG_SYNC 0x0020 224 #define NVDBG_PKTCOMP 0x0040 225 #define NVDBG_TIMEOUT 0x0080 226 #define NVDBG_INFO 0x0100 227 #define NVDBG_VERBOSE 0x0200 228 #define NVDBG_INTR 0x0400 229 #define NVDBG_ERRS 0x0800 230 #define NVDBG_COOKIES 0x1000 231 #define NVDBG_HOT 0x2000 232 #define NVDBG_PROBE 0x4000 233 #define NVDBG_ATAPI 0x8000 234 235 #ifdef DEBUG 236 #define NVLOG(a) nv_log a 237 #else 238 #define NVLOG(a) 239 #endif 240 241 #define NV_SUCCESS 0 242 #define NV_FAILURE -1 243 244 /* 245 * indicates whether nv_wait functions can sleep or not. 246 */ 247 #define NV_SLEEP 1 248 #define NV_NOSLEEP 2 249 250 /* 251 * port offsets from base address ioaddr1 252 */ 253 #define NV_DATA 0x00 /* data register */ 254 #define NV_ERROR 0x01 /* error register (read) */ 255 #define NV_FEATURE 0x01 /* features (write) */ 256 #define NV_COUNT 0x02 /* sector count */ 257 #define NV_SECT 0x03 /* sector number */ 258 #define NV_LCYL 0x04 /* cylinder low byte */ 259 #define NV_HCYL 0x05 /* cylinder high byte */ 260 #define NV_DRVHD 0x06 /* drive/head register */ 261 #define NV_STATUS 0x07 /* status/command register */ 262 #define NV_CMD 0x07 /* status/command register */ 263 264 /* 265 * port offsets from base address ioaddr2 266 */ 267 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 268 #define NV_DEVCTL 0x02 /* device control (write) */ 269 270 /* 271 * device control register 272 */ 273 #define ATDC_NIEN 0x02 /* disable interrupts */ 274 #define ATDC_SRST 0x04 /* controller reset */ 275 #define ATDC_D3 0x08 /* mysterious bit */ 276 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 277 278 279 #define MCP55_CTL 0x400 /* queuing control */ 280 #define MCP55_INT_STATUS 0x440 /* status bits for interrupt */ 281 #define MCP55_INT_CTL 0x444 /* enable bits for interrupt */ 282 #define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */ 283 284 /* 285 * if either of these bits are set, when using NCQ, if no other commands are 286 * active while a new command is started, DMA engine can be programmed ahead 287 * of time to save extra interrupt. Presumably pre-programming is discarded 288 * if a subsequent command ends up finishing first. 289 */ 290 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 291 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 292 293 /* 294 * bit definitions to indicate which NCQ command requires 295 * DMA setup. 296 */ 297 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 298 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 299 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 300 301 302 /* 303 * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS 304 */ 305 #define MCP55_INT_SNOTIFY 0x200 /* snotification set */ 306 #define MCP55_INT_SERROR 0x100 /* serror set */ 307 #define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 308 #define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */ 309 #define MCP55_INT_SDB_FIS 0x20 /* SDB FIS */ 310 #define MCP55_INT_TX_BACKOUT 0x10 /* TX backout */ 311 #define MCP55_INT_REM 0x08 /* device removed */ 312 #define MCP55_INT_ADD 0x04 /* device added */ 313 #define MCP55_INT_PM 0x02 /* power changed */ 314 #define MCP55_INT_COMPLETE 0x01 /* device interrupt */ 315 316 /* 317 * Bits above that are not used for now. 318 */ 319 #define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\ 320 MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\ 321 MCP55_INT_SNOTIFY|MCP55_INT_SERROR) 322 323 /* 324 * Bits for MCP_SATA_AE_CTL 325 */ 326 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 327 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 328 329 #define NV_DELAY_NSEC(wait_ns) \ 330 { \ 331 hrtime_t start, end; \ 332 start = end = gethrtime(); \ 333 while ((end - start) < wait_ns) \ 334 end = gethrtime(); \ 335 } 336 337 /* 338 * signatures in task file registers after device reset 339 */ 340 #define NV_SIG_DISK 0x00000101 341 #define NV_SIG_ATAPI 0xeb140101 342 #define NV_SIG_PM 0x96690101 343 #define NV_SIG_NOTREADY 0x00000000 344 345 /* 346 * These bar5 offsets are common to mcp55/mcp04 and thus 347 * prefixed with NV. 348 */ 349 #define NV_SSTATUS 0x00 350 #define NV_SERROR 0x04 351 #define NV_SCTRL 0x08 352 #define NV_SACTIVE 0x0c 353 #define NV_SNOTIFICATION 0x10 354 355 #define CH0_SREG_OFFSET 0x0 356 #define CH1_SREG_OFFSET 0x40 357 358 359 /* 360 * The following config space offsets are needed to enable 361 * bar 5 register access in mcp04/mcp55 362 */ 363 #define NV_SATA_CFG_20 0x50 364 #define NV_BAR5_SPACE_EN 0x04 365 #define NV_40BIT_PRD 0x20 366 367 /* 368 * mcp04 interrupt status register 369 */ 370 371 /* 372 * offsets to bar 5 registers 373 */ 374 #define MCP04_SATA_INT_STATUS 0x440 375 #define MCP04_SATA_INT_EN 0x441 376 377 378 /* 379 * bit fields for int status and int enable 380 * registers 381 */ 382 #define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */ 383 #define MCP04_INT_PDEV_PM 0x02 /* power change */ 384 #define MCP04_INT_PDEV_ADD 0x04 /* hot plug */ 385 #define MCP04_INT_PDEV_REM 0x08 /* hot remove */ 386 #define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM 387 388 #define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */ 389 #define MCP04_INT_SDEV_PM 0x20 /* power change */ 390 #define MCP04_INT_SDEV_ADD 0x40 /* hot plug */ 391 #define MCP04_INT_SDEV_REM 0x80 /* hot remove */ 392 #define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM 393 394 #define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\ 395 MCP04_INT_PDEV_PM 396 #define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\ 397 MCP04_INT_SDEV_PM 398 399 /* 400 * config space offset 42 401 */ 402 #define NV_SATA_CFG_42 0xac 403 404 /* 405 * bit in CFG_42 which delays hotplug interrupt until 406 * PHY ready 407 */ 408 #define MCP04_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 409 410 411 /* 412 * bar 5 offsets for SATA registers in ck804 413 */ 414 #define MCP04_CH1_SSTATUS 0x00 415 #define MCP04_CH1_SERROR 0x04 416 #define MCP04_CH1_SCTRL 0x08 417 #define MCP04_CH1_SACTIVE 0x0c 418 #define MCP04_CH1_SNOTIFICATION 0x10 419 420 #define MCP04_CH2_SSTATUS 0x40 421 #define MCP04_CH2_SERROR 0x44 422 #define MCP04_CH2_SCTRL 0x48 423 #define MCP04_CH2_SACTIVE 0x4c 424 #define MCP04_CH2_SNOTIFICATION 0x50 425 426 427 /* 428 * bar 5 offsets for ADMACTL settings for both mcp04/mcp55 429 */ 430 #define NV_ADMACTL_X 0x4C0 431 #define NV_ADMACTL_Y 0x5C0 432 433 /* 434 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 435 */ 436 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 437 #define NV_CH_RST 0x04 /* reset channel */ 438 439 440 /* 441 * bar 5 offset for ADMASTAT regs for mcp04 442 */ 443 #define MCP04_ADMASTAT_X 0x4C4 444 #define MCP04_ADMASTAT_Y 0x5C4 445 446 /* 447 * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y 448 */ 449 #define MCP04_HPIRQ 0x4 450 #define MCP05_HUIRQ 0x2 451 452 453 /* 454 * bar 4 offset to bus master command registers 455 */ 456 #define BMICX_REG 0 457 458 /* 459 * bit definitions for BMICX_REG 460 */ 461 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 462 /* 1=Start (Enable) */ 463 /* 0=Start (Disable) */ 464 465 /* 466 * NOTE: "read" and "write" are the actions of the DMA engine 467 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 468 * command, program the DMA engine to "write to memory" mode 469 * (and vice versa). 470 */ 471 #define BMICX_RWCON 0x08 /* Read/Write Control */ 472 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 473 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 474 475 /* 476 * BMICX bits to preserve during updates 477 */ 478 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 479 480 /* 481 * bar 4 offset to bus master status register 482 */ 483 #define BMISX_REG 2 484 485 /* 486 * bit fields for bus master status register 487 */ 488 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 489 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 490 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 491 492 /* 493 * bus master status register bits to preserve 494 */ 495 #define BMISX_MASK 0xf8 496 497 /* 498 * bar4 offset to bus master PRD descriptor table 499 */ 500 #define BMIDTPX_REG 4 501 502 503 /* 504 * structure for a single entry in the PRD table 505 * (physical region descriptor table) 506 */ 507 typedef struct prde { 508 uint32_t p_address; /* physical address */ 509 uint32_t p_count; /* byte count, EOT in high order bit */ 510 } prde_t; 511 512 513 #define PRDE_EOT ((uint_t)0x80000000) 514 515 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 516 517 /* 518 * ck804 and mcp55 both have 2 ports per controller 519 */ 520 #define NV_NUM_CPORTS 2 521 522 /* 523 * Number of slots to allocate in data nv_sata structures to handle 524 * multiple commands at once. This does not reflect the capability of 525 * the drive or the hardware, and in many cases will not match. 526 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 527 * enabled but the drive doesn't support it, or supports fewer than 528 * 32 slots, here may be an over allocation of memory. 529 */ 530 #ifdef NCQ 531 #define NV_QUEUE_SLOTS 32 532 #else 533 #define NV_QUEUE_SLOTS 1 534 #endif 535 536 /* 537 * wait 30 seconds for signature 538 */ 539 #define NV_SIG_TIMEOUT 45 540 541 #define NV_BM_64K_BOUNDARY 0x10000ull 542 543 /* 544 * every 1 second 545 */ 546 #define NV_ONE_SEC 1000000 547 548 549 /* 550 * the amount of time link can be down during 551 * reset without taking action. 552 */ 553 #define NV_LINK_LOST_OK 2 554 555 /* 556 * nv_reset() flags 557 */ 558 #define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */ 559 #define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */ 560 561 562 563 #define NV_RESET_ATTEMPTS 3 564 565 /* 566 * nvp_state flags 567 */ 568 #define NV_PORT_INACTIVE 0x001 569 #define NV_PORT_ABORTING 0x002 570 #define NV_PORT_HOTREMOVED 0x004 571 #define NV_PORT_INIT 0x008 572 #define NV_PORT_FAILED 0x010 573 #define NV_PORT_RESET 0x020 574 #define NV_PORT_RESET_PROBE 0x040 575 #define NV_PORT_RESTORE 0x080 576 577 /* 578 * nvc_state flags 579 */ 580 #define NV_CTRL_SUSPEND 0x1 581 582 583 /* 584 * flags for mcp04_set_intr/mcp55_set_intr 585 */ 586 #define NV_INTR_DISABLE 0x1 587 #define NV_INTR_ENABLE 0x2 588 #define NV_INTR_CLEAR_ALL 0x4 589 590 /* 591 * sizes of strings to allocate 592 */ 593 #define NV_STRING_10 10 594 #define NV_STRING_512 512 595 596 #define NV_BYTES_PER_SEC 512 597 598 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 599 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 600 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 601 #define MCP55_INT_CLEAR 0xffff /* clear all interrupts */ 602 603 /* 604 * definition labels for the BAR registers 605 */ 606 #define NV_BAR_0 0 /* chan 0 task file regs */ 607 #define NV_BAR_1 1 /* chan 0 status reg */ 608 #define NV_BAR_2 2 /* chan 1 task file regs */ 609 #define NV_BAR_3 3 /* chan 1 status reg */ 610 #define NV_BAR_4 4 /* bus master regs */ 611 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 612 613 /* 614 * transform seconds to microseconds 615 */ 616 #define NV_SEC2USEC(x) x * MICROSEC 617 618 619 /* 620 * ck804 maps in task file regs into bar 5. These are 621 * only used to identify ck804, therefore only this reg is 622 * listed here. 623 */ 624 #define NV_BAR5_TRAN_LEN_CH_X 0x518 625 626 /* 627 * if after this many iterations through the interrupt 628 * processing loop, declare the interrupt wedged and 629 * disable. 630 */ 631 #define NV_MAX_INTR_LOOP 10 632 633 /* 634 * flag values for nv_copy_regs_out 635 */ 636 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 637 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 638 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 639 640 641 #ifdef __cplusplus 642 } 643 #endif 644 645 #endif /* _NV_SATA_H */ 646