1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #ifndef _AHCIVAR_H 29 #define _AHCIVAR_H 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Type for argument of event handler */ 38 typedef struct ahci_event_arg { 39 void *ahciea_ctlp; 40 void *ahciea_portp; 41 uint32_t ahciea_event; 42 } ahci_event_arg_t; 43 44 /* Warlock annotation */ 45 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp)) 46 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp)) 47 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event)) 48 49 /* 50 * flags for ahciport_flags 51 * 52 * AHCI_PORT_FLAG_SPINUP: this flag will be set when a HBA which supports 53 * staggered spin-up needs to do a spin-up. 54 * 55 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped, 56 * and all the outstanding commands need to be aborted and sent to upper 57 * layers. 58 * 59 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is 60 * disabled, and the command is executed in POLLING mode. 61 * 62 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which 63 * is used to retrieve sense data is being executed. 64 * 65 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started, 66 * that is PxCMD.ST is set with '1', and be cleared when the port is put into 67 * idle, that is PxCMD.ST is changed from '1' to '0'. 68 * 69 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which 70 * is used to retrieve NCQ failure context is being executed. 71 * 72 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone 73 * during ahci_restart_port_wait_till_ready process. 74 */ 75 #define AHCI_PORT_FLAG_SPINUP 0x01 76 #define AHCI_PORT_FLAG_MOPPING 0x02 77 #define AHCI_PORT_FLAG_POLLING 0x04 78 #define AHCI_PORT_FLAG_RQSENSE 0x08 79 #define AHCI_PORT_FLAG_STARTED 0x10 80 #define AHCI_PORT_FLAG_RDLOGEXT 0x20 81 #define AHCI_PORT_FLAG_NODEV 0x40 82 83 typedef struct ahci_port { 84 /* The physical port number */ 85 uint8_t ahciport_port_num; 86 87 /* Type of the device attached to the port */ 88 uint8_t ahciport_device_type; 89 /* State of the port */ 90 uint32_t ahciport_port_state; 91 92 /* 93 * AHCI_PORT_FLAG_SPINUP 94 * AHCI_PORT_FLAG_MOPPING 95 * AHCI_PORT_FLAG_POLLING 96 * AHCI_PORT_FLAG_RQSENSE 97 * AHCI_PORT_FLAG_STARTED 98 * AHCI_PORT_FLAG_RDLOGEXT 99 * AHCI_PORT_FLAG_NODEV 100 */ 101 int ahciport_flags; 102 103 /* Pointer to received FIS structure */ 104 ahci_rcvd_fis_t *ahciport_rcvd_fis; 105 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; 106 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; 107 108 /* Pointer to command list structure */ 109 ahci_cmd_header_t *ahciport_cmd_list; 110 ddi_dma_handle_t ahciport_cmd_list_dma_handle; 111 ddi_acc_handle_t ahciport_cmd_list_acc_handle; 112 113 /* Pointer to cmmand table structure */ 114 ahci_cmd_table_t \ 115 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; 116 ddi_dma_handle_t \ 117 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; 118 ddi_acc_handle_t \ 119 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; 120 121 /* Condition variable used for sync mode commands */ 122 kcondvar_t ahciport_cv; 123 124 /* The whole mutex for the port structure */ 125 kmutex_t ahciport_mutex; 126 127 /* The maximum number of tags for native queuing command transfers */ 128 int ahciport_max_ncq_tags; 129 130 /* Keep the tags of all pending non-ncq commands */ 131 uint32_t ahciport_pending_tags; 132 133 /* 134 * Keep the tags of all pending ncq commands 135 * (READ/WRITE FPDMA QUEUED) 136 */ 137 uint32_t ahciport_pending_ncq_tags; 138 139 /* Keep all the pending sata packets */ 140 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; 141 142 /* Keep the error retrieval sata packet */ 143 sata_pkt_t *ahciport_err_retri_pkt; 144 145 /* 146 * SATA HBA driver is supposed to remember and maintain device 147 * reset state. While the reset is in progress, it doesn't accept 148 * any more commands until receiving the command with 149 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. 150 */ 151 int ahciport_reset_in_progress; 152 153 /* This is for error recovery handler */ 154 ahci_event_arg_t *ahciport_event_args; 155 156 /* This is to calculate how many mops are in progress */ 157 int ahciport_mop_in_progress; 158 } ahci_port_t; 159 160 /* Warlock annotation */ 161 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) 162 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) 163 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) 164 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 165 ahci_port_t::ahciport_device_type)) 166 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 167 ahci_port_t::ahciport_port_state)) 168 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 169 ahci_port_t::ahciport_flags)) 170 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 171 ahci_port_t::ahciport_pending_tags)) 172 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 173 ahci_port_t::ahciport_slot_pkts)) 174 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 175 ahci_port_t::ahciport_reset_in_progress)) 176 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 177 ahci_port_t::ahciport_mop_in_progress)) 178 179 typedef struct ahci_ctl { 180 dev_info_t *ahcictl_dip; 181 /* To map port number to cport number */ 182 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; 183 /* To map cport number to port number */ 184 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; 185 186 /* Number of controller ports */ 187 int ahcictl_num_ports; 188 /* Number of command slots */ 189 int ahcictl_num_cmd_slots; 190 /* Number of implemented ports */ 191 int ahcictl_num_implemented_ports; 192 /* Bit map to indicate which port is implemented */ 193 uint32_t ahcictl_ports_implemented; 194 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; 195 196 int ahcictl_flags; 197 int ahcictl_power_level; 198 off_t ahcictl_pmcsr_offset; 199 200 /* 201 * AHCI_CAP_PIO_MDRQ 202 * AHCI_CAP_NO_MCMDLIST_NONQUEUE 203 * AHCI_CAP_NCQ 204 */ 205 int ahcictl_cap; 206 207 /* Pci configuration space handle */ 208 ddi_acc_handle_t ahcictl_pci_conf_handle; 209 210 /* Mapping into bar 5 - AHCI base address */ 211 ddi_acc_handle_t ahcictl_ahci_acc_handle; 212 uintptr_t ahcictl_ahci_addr; 213 214 /* Pointer used for sata hba framework registration */ 215 struct sata_hba_tran *ahcictl_sata_hba_tran; 216 217 /* DMA attributes for the data buffer */ 218 ddi_dma_attr_t ahcictl_buffer_dma_attr; 219 /* DMA attributes for the rcvd FIS */ 220 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; 221 /* DMA attributes for the command list */ 222 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; 223 /* DMA attributes for command tables */ 224 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; 225 226 /* Used for watchdog handler */ 227 timeout_id_t ahcictl_timeout_id; 228 229 /* Per controller mutex */ 230 kmutex_t ahcictl_mutex; 231 232 /* Components for interrupt */ 233 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ 234 int ahcictl_intr_type; /* What type of interrupt */ 235 int ahcictl_intr_cnt; /* # of intrs returned */ 236 size_t ahcictl_intr_size; /* Size of intr array */ 237 uint_t ahcictl_intr_pri; /* Intr priority */ 238 int ahcictl_intr_cap; /* Intr capabilities */ 239 240 /* Taskq for handling event */ 241 ddi_taskq_t *ahcictl_event_taskq; 242 } ahci_ctl_t; 243 244 /* Warlock annotation */ 245 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) 246 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) 247 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) 248 249 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 250 ahci_ctl_t::ahcictl_power_level)) 251 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 252 ahci_ctl_t::ahcictl_flags)) 253 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 254 ahci_ctl_t::ahcictl_timeout_id)) 255 256 #define AHCI_SUCCESS (0) /* Successful return */ 257 #define AHCI_TIMEOUT (1) /* Timed out */ 258 #define AHCI_FAILURE (-1) /* Unsuccessful return */ 259 260 /* Flags for ahcictl_flags */ 261 #define AHCI_PM 0x1 262 #define AHCI_ATTACH 0x2 263 #define AHCI_DETACH 0x4 264 265 /* Values for ahcictl_cap */ 266 /* PIO Multiple DRQ Block */ 267 #define AHCI_CAP_PIO_MDRQ 0x1 268 /* 269 * Multiple command slots in the command list cannot be used for 270 * non-queued commands 271 */ 272 #define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2 273 /* Native Command Queuing (NCQ) */ 274 #define AHCI_CAP_NCQ 0x4 275 276 /* Flags controlling the restart port behavior */ 277 #define AHCI_PORT_RESET 0x0001 /* Reset the port */ 278 #define AHCI_PORT_INIT 0x0002 /* Initialize port */ 279 #define AHCI_RESET_NO_EVENTS_UP 0x0004 /* Don't send reset events up */ 280 281 #define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \ 282 (ahci_portp->ahciport_flags & \ 283 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT)) 284 285 #define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \ 286 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 287 ahci_portp->ahciport_pending_tags != 0 && \ 288 ahci_portp->ahciport_pending_ncq_tags == 0) 289 290 #define NCQ_CMD_IN_PROGRESS(ahci_portp) \ 291 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 292 ahci_portp->ahciport_pending_ncq_tags != 0) 293 294 /* Command type for ahci_claim_free_slot routine */ 295 #define AHCI_NON_NCQ_CMD 0x0 296 #define AHCI_NCQ_CMD 0x1 297 #define AHCI_ERR_RETRI_CMD 0x2 298 299 /* State values for ahci_attach */ 300 #define AHCI_ATTACH_STATE_NONE (0x1 << 0) 301 #define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) 302 #define AHCI_ATTACH_STATE_REG_MAP (0x1 << 2) 303 #define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 3) 304 #define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 4) 305 #define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 5) 306 #define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 6) 307 #define AHCI_ATTACH_STATE_ERR_RECV_TASKQ (0x1 << 7) 308 #define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8) 309 #define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9) 310 311 /* Interval used for delay */ 312 #define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 millisec */ 313 #define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 millisec */ 314 #define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 */ 315 #define AHCI_1MS_USECS (1000) /* usecs in 1 millisec */ 316 317 /* 318 * The following values are the numbers of times to retry polled requests. 319 */ 320 #define AHCI_POLLRATE_HBA_RESET 100 321 #define AHCI_POLLRATE_PORT_SSTATUS 10 322 #define AHCI_POLLRATE_PORT_TFD_ERROR 1100 323 #define AHCI_POLLRATE_PORT_IDLE 50 324 #define AHCI_POLLRATE_PORT_SOFTRESET 100 325 #define AHCI_POLLRATE_GET_SPKT 100 326 327 328 /* Clearing & setting the n'th bit in a given tag */ 329 #define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) 330 #define SET_BIT(tag, bit) (tag |= (0x1<<bit)) 331 332 333 #if DEBUG 334 335 #define AHCI_DEBUG 1 336 337 #define AHCIDBG_INIT 0x0001 338 #define AHCIDBG_ENTRY 0x0002 339 #define AHCIDBG_DUMP_PRB 0x0004 340 #define AHCIDBG_EVENT 0x0008 341 #define AHCIDBG_POLL_LOOP 0x0010 342 #define AHCIDBG_PKTCOMP 0x0020 343 #define AHCIDBG_TIMEOUT 0x0040 344 #define AHCIDBG_INFO 0x0080 345 #define AHCIDBG_VERBOSE 0x0100 346 #define AHCIDBG_INTR 0x0200 347 #define AHCIDBG_ERRS 0x0400 348 #define AHCIDBG_COOKIES 0x0800 349 #define AHCIDBG_POWER 0x1000 350 #define AHCIDBG_COMMAND 0x2000 351 #define AHCIDBG_SENSEDATA 0x4000 352 #define AHCIDBG_NCQ 0x8000 353 354 extern int ahci_debug_flag; 355 356 #define AHCIDBG0(flag, ahci_ctlp, format) \ 357 if (ahci_debug_flags & (flag)) { \ 358 ahci_log(ahci_ctlp, CE_WARN, format); \ 359 } 360 361 #define AHCIDBG1(flag, ahci_ctlp, format, arg1) \ 362 if (ahci_debug_flags & (flag)) { \ 363 ahci_log(ahci_ctlp, CE_WARN, format, arg1); \ 364 } 365 366 #define AHCIDBG2(flag, ahci_ctlp, format, arg1, arg2) \ 367 if (ahci_debug_flags & (flag)) { \ 368 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2); \ 369 } 370 371 #define AHCIDBG3(flag, ahci_ctlp, format, arg1, arg2, arg3) \ 372 if (ahci_debug_flags & (flag)) { \ 373 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3); \ 374 } 375 376 #define AHCIDBG4(flag, ahci_ctlp, format, arg1, arg2, arg3, arg4) \ 377 if (ahci_debug_flags & (flag)) { \ 378 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3, arg4); \ 379 } 380 381 #define AHCIDBG5(flag, ahci_ctlp, format, arg1, arg2, arg3, arg4, arg5) \ 382 if (ahci_debug_flags & (flag)) { \ 383 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, \ 384 arg3, arg4, arg5); \ 385 } 386 #else 387 388 #define AHCIDBG0(flag, dip, frmt) 389 #define AHCIDBG1(flag, dip, frmt, arg1) 390 #define AHCIDBG2(flag, dip, frmt, arg1, arg2) 391 #define AHCIDBG3(flag, dip, frmt, arg1, arg2, arg3) 392 #define AHCIDBG4(flag, dip, frmt, arg1, arg2, arg3, arg4) 393 #define AHCIDBG5(flag, dip, frmt, arg1, arg2, arg3, arg4, arg5) 394 395 #endif /* DEBUG */ 396 397 398 #ifdef __cplusplus 399 } 400 #endif 401 402 #endif /* _AHCIVAR_H */ 403