1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #ifndef _AHCIREG_H 29 #define _AHCIREG_H 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #define AHCI_MAX_PORTS 32 38 #define AHCI_PORT_MAX_CMD_SLOTS 32 39 40 #define VIA_VENID 0x1106 41 42 /* 43 * In AHCI spec, command table contains a list of 0 (no data transfer) 44 * to up to 65,535 scatter/gather entries for the data transfer. 45 */ 46 #define AHCI_MAX_PRDT_NUMBER 65535 47 #define AHCI_MIN_PRDT_NUMBER 1 48 49 /* 50 * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1 51 * if misaligned, and it's tuable by setting ahci_dma_prdt_number in 52 * /etc/system file. 53 */ 54 #define AHCI_PRDT_NUMBER 257 55 56 /* AHCI base address */ 57 #define AHCI_BASE_REG 6 /* BAR5 is the only useful register */ 58 59 /* various global HBA capability bits */ 60 #define AHCI_HBA_CAP_NP (0x1f << 0) /* number of ports */ 61 #define AHCI_HBA_CAP_SXS (0x1 << 5) /* external SATA */ 62 #define AHCI_HBA_CAP_EMS (0x1 << 6) /* enclosure management */ 63 #define AHCI_HBA_CAP_CCCS (0x1 << 7) /* command completed coalescing */ 64 #define AHCI_HBA_CAP_NCS (0x1f << 8) /* number of command slots */ 65 #define AHCI_HBA_CAP_PSC (0x1 << 13) /* partial state capable */ 66 #define AHCI_HBA_CAP_SSC (0x1 << 14) /* slumber state capable */ 67 #define AHCI_HBA_CAP_PMD (0x1 << 15) /* PIO multiple DRQ block */ 68 #define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */ 69 #define AHCI_HBA_CAP_SPM (0x1 << 17) /* port multiplier */ 70 #define AHCI_HBA_CAP_SAM (0x1 << 18) /* AHCI mode only */ 71 #define AHCI_HBA_CAP_SNZO (0x1 << 19) /* non-zero DMA offsets */ 72 #define AHCI_HBA_CAP_ISS (0xf << 20) /* interface speed support */ 73 #define AHCI_HBA_CAP_SCLO (0x1 << 24) /* command list override */ 74 #define AHCI_HBA_CAP_SAL (0x1 << 25) /* activity LED */ 75 #define AHCI_HBA_CAP_SALP (0x1 << 26) /* aggressive link power mgmt */ 76 #define AHCI_HBA_CAP_SSS (0x1 << 27) /* staggered spin-up */ 77 #define AHCI_HBA_CAP_SMPS (0x1 << 28) /* mechanical presence switch */ 78 #define AHCI_HBA_CAP_SSNTF (0x1 << 29) /* Snotification register */ 79 #define AHCI_HBA_CAP_SNCQ (0x1 << 30) /* Native Command Queuing */ 80 #define AHCI_HBA_CAP_S64A ((uint32_t)0x1 << 31) /* 64-bit addressing */ 81 #define AHCI_HBA_CAP_NCS_SHIFT 8 /* Number of command slots */ 82 #define AHCI_HBA_CAP_ISS_SHIFT 20 /* Interface speed support */ 83 84 /* various global HBA control bits */ 85 #define AHCI_HBA_GHC_HR (0x1 << 0) /* HBA Reset */ 86 #define AHCI_HBA_GHC_IE (0x1 << 1) /* Interrupt Enable */ 87 #define AHCI_HBA_GHC_MRSM (0x1 << 2) /* MSI Revert to Single Message */ 88 #define AHCI_HBA_GHC_AE ((uint32_t)0x1 << 31) /* AHCI Enable */ 89 90 /* various global HBA Command Completion Coalescing (CCC) control bits */ 91 #define AHCI_HBA_CCC_CTL_EN 0x00000001 /* Enable */ 92 #define AHCI_HBA_CCC_CTL_INT_MASK (0x1f << 3) /* Interrupt */ 93 #define AHCI_HBA_CCC_CTL_CC_MASK 0x0000ff00 /* Command Completions */ 94 #define AHCI_HBA_CCC_CTL_TV_MASK 0xffff0000 /* Timeout Value */ 95 #define AHCI_HBA_CCC_CTL_INT_SHIFT 3 96 #define AHCI_HBA_CCC_CTL_CC_SHIFT 8 97 #define AHCI_HBA_CCC_CTL_TV_SHIFT 16 98 99 /* global HBA Enclosure Management Location (EM_LOC) */ 100 #define AHCI_HBA_EM_LOC_SZ_MASK 0x0000ffff /* Buffer Size */ 101 #define AHCI_HBA_EM_LOC_OFST_MASK 0xffff0000 /* Offset */ 102 #define AHCI_HBA_EM_LOC_OFST_SHIFT 16 103 104 /* global HBA Enclosure Management Control (EM_CTL) bits */ 105 #define AHCI_HBA_EM_CTL_STS_MR (0x1 << 0) /* Message Received */ 106 #define AHCI_HBA_EM_CTL_CTL_TM (0x1 << 8) /* Transmit Message */ 107 #define AHCI_HBA_EM_CTL_CTL_RST (0x1 << 9) /* Reset */ 108 #define AHCI_HBA_EM_CTL_SUPP_LED (0x1 << 16) /* LED Message Types */ 109 #define AHCI_HBA_EM_CTL_SUPP_SAFTE (0x1 << 17) /* SAF-TE EM Messages */ 110 #define AHCI_HBA_EM_CTL_SUPP_SES2 (0x1 << 18) /* SES-2 EM Messages */ 111 #define AHCI_HBA_EM_CTL_SUPP_SGPIO (0x1 << 19) /* SGPIO EM Messages */ 112 #define AHCI_HBA_EM_CTL_ATTR_SMB (0x1 << 24) /* Single Message Buffer */ 113 #define AHCI_HBA_EM_CTL_ATTR_XMT (0x1 << 25) /* Transmit Only */ 114 #define AHCI_HBA_EM_CTL_ATTR_ALHD (0x1 << 26) /* Activity LED HW Driven */ 115 #define AHCI_HBA_EM_CTL_ATTR_PM (0x1 << 27) /* PM Support */ 116 117 118 /* global HBA registers definitions */ 119 #define AHCI_GLOBAL_OFFSET(ahci_ctlp) (ahci_ctlp->ahcictl_ahci_addr) 120 /* HBA Capabilities */ 121 #define AHCI_GLOBAL_CAP(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00) 122 /* Global HBA Control */ 123 #define AHCI_GLOBAL_GHC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04) 124 /* Interrupt Status Register */ 125 #define AHCI_GLOBAL_IS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08) 126 /* Ports Implemented */ 127 #define AHCI_GLOBAL_PI(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c) 128 /* AHCI Version */ 129 #define AHCI_GLOBAL_VS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10) 130 /* Command Completion Coalescing Control */ 131 #define AHCI_GLOBAL_CCC_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14) 132 /* Command Completion Coalescing Ports */ 133 #define AHCI_GLOBAL_CCC_PORTS(ahci_ctlp) \ 134 (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18) 135 /* Enclosure Management Location */ 136 #define AHCI_GLOBAL_EM_LOC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c) 137 /* Enclosure Management Control */ 138 #define AHCI_GLOBAL_EM_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20) 139 140 #define AHCI_PORT_IMPLEMENTED(ahci_ctlp, port) \ 141 ((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented) 142 143 /* various port interrupt bits */ 144 /* Device to Host Register FIS Interrupt */ 145 #define AHCI_INTR_STATUS_DHRS (0x1 << 0) 146 /* PIO Setup FIS Interrupt */ 147 #define AHCI_INTR_STATUS_PSS (0x1 << 1) 148 /* DMA Setup FIS Interrupt */ 149 #define AHCI_INTR_STATUS_DSS (0x1 << 2) 150 /* Set Device Bits Interrupt */ 151 #define AHCI_INTR_STATUS_SDBS (0x1 << 3) 152 /* Unknown FIS Interrupt */ 153 #define AHCI_INTR_STATUS_UFS (0x1 << 4) 154 /* Descriptor Processed */ 155 #define AHCI_INTR_STATUS_DPS (0x1 << 5) 156 /* Port Connect Change Status */ 157 #define AHCI_INTR_STATUS_PCS (0x1 << 6) 158 /* Device Mechanical Presence Status */ 159 #define AHCI_INTR_STATUS_DMPS (0x1 << 7) 160 /* PhyRdy Change Status */ 161 #define AHCI_INTR_STATUS_PRCS (0x1 << 22) 162 /* Incorrect Port Multiplier Status */ 163 #define AHCI_INTR_STATUS_IPMS (0x1 << 23) 164 /* Overflow Status */ 165 #define AHCI_INTR_STATUS_OFS (0x1 << 24) 166 /* Interface Non-fatal Error Status */ 167 #define AHCI_INTR_STATUS_INFS (0x1 << 26) 168 /* Interface Fatal Error Status */ 169 #define AHCI_INTR_STATUS_IFS (0x1 << 27) 170 /* Host Bus Data Error Status */ 171 #define AHCI_INTR_STATUS_HBDS (0x1 << 28) 172 /* Host Bus Fatal Error Status */ 173 #define AHCI_INTR_STATUS_HBFS (0x1 << 29) 174 /* Task File Error Status */ 175 #define AHCI_INTR_STATUS_TFES (0x1 << 30) 176 /* Cold Port Detect Status */ 177 #define AHCI_INTR_STATUS_CPDS ((uint32_t)0x1 << 31) 178 #define AHCI_PORT_INTR_MASK 0xfec000ff 179 180 /* port command and status bits */ 181 #define AHCI_CMD_STATUS_ST (0x1 << 0) /* Start */ 182 #define AHCI_CMD_STATUS_SUD (0x1 << 1) /* Spin-up device */ 183 #define AHCI_CMD_STATUS_POD (0x1 << 2) /* Power on device */ 184 #define AHCI_CMD_STATUS_CLO (0x1 << 3) /* Command list override */ 185 #define AHCI_CMD_STATUS_FRE (0x1 << 4) /* FIS receive enable */ 186 #define AHCI_CMD_STATUS_CCS (0x1f << 8) /* Current command slot */ 187 /* Mechanical presence switch state */ 188 #define AHCI_CMD_STATUS_MPSS (0x1 << 13) 189 #define AHCI_CMD_STATUS_FR (0x1 << 14) /* FIS receiving running */ 190 #define AHCI_CMD_STATUS_CR (0x1 << 15) /* Command list running */ 191 #define AHCI_CMD_STATUS_CPS (0x1 << 16) /* Cold presence state */ 192 #define AHCI_CMD_STATUS_PMA (0x1 << 17) /* Port multiplier attached */ 193 #define AHCI_CMD_STATUS_HPCP (0x1 << 18) /* Hot plug capable port */ 194 /* Mechanical presence switch attached to port */ 195 #define AHCI_CMD_STATUS_MPSP (0x1 << 19) 196 #define AHCI_CMD_STATUS_CPD (0x1 << 20) /* Cold presence detection */ 197 #define AHCI_CMD_STATUS_ESP (0x1 << 21) /* External SATA port */ 198 #define AHCI_CMD_STATUS_ATAPI (0x1 << 24) /* Device is ATAPI */ 199 #define AHCI_CMD_STATUS_DLAE (0x1 << 25) /* Drive LED on ATAPI enable */ 200 /* Aggressive link power magament enable */ 201 #define AHCI_CMD_STATUS_ALPE (0x1 << 26) 202 #define AHCI_CMD_STATUS_ASP (0x1 << 27) /* Aggressive slumber/partial */ 203 /* Interface communication control */ 204 #define AHCI_CMD_STATUS_ICC (0xf << 28) 205 #define AHCI_CMD_STATUS_CCS_SHIFT 8 206 #define AHCI_CMD_STATUS_ICC_SHIFT 28 207 208 /* port task file data bits */ 209 #define AHCI_TFD_STS_MASK 0x000000ff 210 #define AHCI_TFD_ERR_MASK 0x0000ff00 211 #define AHCI_TFD_STS_BSY (0x1 << 7) 212 #define AHCI_TFD_STS_DRQ (0x1 << 3) 213 #define AHCI_TFD_STS_ERR (0x1 << 0) 214 #define AHCI_TFD_ERR_SHIFT 8 215 216 #define AHCI_SERROR_CLEAR_ALL 0xffffffff 217 218 /* per port registers offset */ 219 #define AHCI_PORT_OFFSET(ahci_ctlp, port) \ 220 (ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80))) 221 /* Command List Base Address */ 222 #define AHCI_PORT_PxCLB(ahci_ctlp, port) \ 223 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00) 224 /* Command List Base Address Upper 32-Bits */ 225 #define AHCI_PORT_PxCLBU(ahci_ctlp, port) \ 226 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04) 227 /* FIS Base Address */ 228 #define AHCI_PORT_PxFB(ahci_ctlp, port) \ 229 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08) 230 /* FIS Base Address Upper 32-Bits */ 231 #define AHCI_PORT_PxFBU(ahci_ctlp, port) \ 232 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c) 233 /* Interrupt Status */ 234 #define AHCI_PORT_PxIS(ahci_ctlp, port) \ 235 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10) 236 /* Interrupt Enable */ 237 #define AHCI_PORT_PxIE(ahci_ctlp, port) \ 238 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14) 239 /* Command and Status */ 240 #define AHCI_PORT_PxCMD(ahci_ctlp, port) \ 241 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18) 242 /* Task File Data */ 243 #define AHCI_PORT_PxTFD(ahci_ctlp, port) \ 244 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20) 245 /* Signature */ 246 #define AHCI_PORT_PxSIG(ahci_ctlp, port) \ 247 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24) 248 /* Serial ATA Status (SCR0:SStatus) */ 249 #define AHCI_PORT_PxSSTS(ahci_ctlp, port) \ 250 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28) 251 /* Serial ATA Control (SCR2:SControl) */ 252 #define AHCI_PORT_PxSCTL(ahci_ctlp, port) \ 253 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c) 254 /* Serial ATA Error (SCR1:SError) */ 255 #define AHCI_PORT_PxSERR(ahci_ctlp, port) \ 256 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30) 257 /* Serial ATA Active (SCR3:SActive) */ 258 #define AHCI_PORT_PxSACT(ahci_ctlp, port) \ 259 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34) 260 /* Command Issue */ 261 #define AHCI_PORT_PxCI(ahci_ctlp, port) \ 262 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38) 263 /* SNotification */ 264 #define AHCI_PORT_PxSNTF(ahci_ctlp, port) \ 265 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c) 266 267 #define AHCI_SLOT_MASK(ahci_ctlp) \ 268 ((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \ 269 0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1)) 270 #define AHCI_NCQ_SLOT_MASK(ahci_portp) \ 271 ((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \ 272 0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1)) 273 274 /* Device signatures */ 275 #define AHCI_SIGNATURE_PORT_MULTIPLIER 0x96690101 276 #define AHCI_SIGNATURE_ATAPI 0xeb140101 277 #define AHCI_SIGNATURE_DISK 0x00000101 278 279 /* 280 * The address of the control port for the port multiplier, which is 281 * used for control and status communication with the port multiplier 282 * itself. 283 */ 284 #define AHCI_PORTMULT_CONTROL_PORT 0x0f 285 286 #define AHCI_H2D_REGISTER_FIS_TYPE 0x27 287 #define AHCI_H2D_REGISTER_FIS_LENGTH 5 288 289 #define AHCI_CMDHEAD_ATAPI 0x1 /* set to 1 for ATAPI command */ 290 #define AHCI_CMDHEAD_DATA_WRITE 0x1 /* From system memory to device */ 291 #define AHCI_CMDHEAD_DATA_READ 0x0 /* From device to system memory */ 292 #define AHCI_CMDHEAD_PREFETCHABLE 0x1 /* if set, HBA prefetch PRDs */ 293 294 /* Register - Host to Device FIS (from SATA spec) */ 295 typedef struct ahci_fis_h2d_register { 296 /* offset 0x00 */ 297 uint32_t ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features; 298 299 #define SET_FIS_TYPE(fis, type) \ 300 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff)) 301 302 #define SET_FIS_PMP(fis, pmp) \ 303 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 304 ((pmp & 0xf) << 8)) 305 306 #define SET_FIS_CDMDEVCTL(fis, cmddevctl) \ 307 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 308 ((cmddevctl & 0x1) << 15)) 309 310 #define GET_FIS_COMMAND(fis) \ 311 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff) 312 313 #define SET_FIS_COMMAND(fis, command) \ 314 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 315 ((command & 0xff) << 16)) 316 317 #define GET_FIS_FEATURES(fis) \ 318 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff) 319 320 #define SET_FIS_FEATURES(fis, features) \ 321 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 322 ((features & 0xff) << 24)) 323 324 /* offset 0x04 */ 325 uint32_t ahcifhr_sector_cyllow_cylhi_devhead; 326 327 #define GET_FIS_SECTOR(fis) \ 328 (fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff) 329 330 #define SET_FIS_SECTOR(fis, sector) \ 331 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff))) 332 333 #define GET_FIS_CYL_LOW(fis) \ 334 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 335 336 #define SET_FIS_CYL_LOW(fis, cyl_low) \ 337 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8)) 338 339 #define GET_FIS_CYL_HI(fis) \ 340 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 341 342 #define SET_FIS_CYL_HI(fis, cyl_hi) \ 343 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16)) 344 345 #define GET_FIS_DEV_HEAD(fis) \ 346 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 347 348 #define SET_FIS_DEV_HEAD(fis, dev_head) \ 349 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24)) 350 351 /* offset 0x08 */ 352 uint32_t ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp; 353 354 #define GET_FIS_SECTOR_EXP(fis) \ 355 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp & 0xff) 356 357 #define SET_FIS_SECTOR_EXP(fis, sectorexp) \ 358 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 359 ((sectorexp & 0xff))) 360 361 #define GET_FIS_CYL_LOW_EXP(fis) \ 362 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff) 363 364 #define SET_FIS_CYL_LOW_EXP(fis, cyllowexp) \ 365 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 366 ((cyllowexp & 0xff) << 8)) 367 368 #define GET_FIS_CYL_HI_EXP(fis) \ 369 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff) 370 371 #define SET_FIS_CYL_HI_EXP(fis, cylhiexp) \ 372 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 373 ((cylhiexp & 0xff) << 16)) 374 375 #define SET_FIS_FEATURES_EXP(fis, features_exp) \ 376 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 377 ((features_exp & 0xff) << 24)) 378 379 /* offset 0x0c */ 380 uint32_t ahcifhr_sectcount_sectcountexp_rsvd_devctl; 381 382 #define GET_FIS_SECTOR_COUNT(fis) \ 383 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff) 384 385 #define SET_FIS_SECTOR_COUNT(fis, sector_count) \ 386 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 387 ((sector_count & 0xff))) 388 389 #define GET_FIS_SECTOR_COUNT_EXP(fis) \ 390 ((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff) 391 392 #define SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp) \ 393 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 394 ((sector_count_exp & 0xff) << 8)) 395 396 #define SET_FIS_DEVCTL(fis, devctl) \ 397 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 398 ((devctl & 0xff) << 24)) 399 400 /* offset 0x10 */ 401 uint32_t ahcifhr_rsvd3[1]; /* should be zero */ 402 } ahci_fis_h2d_register_t; 403 404 /* Register - Device to Host FIS (from SATA spec) */ 405 typedef struct ahci_fis_d2h_register { 406 /* offset 0x00 */ 407 uint32_t ahcifdr_type_intr_rsvd_status_error; 408 409 #define GET_RFIS_STATUS(fis) \ 410 ((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff) 411 412 #define GET_RFIS_ERROR(fis) \ 413 ((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff) 414 415 /* offset 0x04 */ 416 uint32_t ahcifdr_sector_cyllow_cylhi_devhead; 417 418 #define GET_RFIS_CYL_LOW(fis) \ 419 (fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff) 420 421 #define GET_RFIS_CYL_MID(fis) \ 422 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 423 424 #define GET_RFIS_CYL_HI(fis) \ 425 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 426 427 #define GET_RFIS_DEV_HEAD(fis) \ 428 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 429 430 /* offset 0x08 */ 431 uint32_t ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd; 432 433 #define GET_RFIS_CYL_LOW_EXP(fis) \ 434 (fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd & 0xff) 435 436 #define GET_RFIS_CYL_MID_EXP(fis) \ 437 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff) 438 439 #define GET_RFIS_CYL_HI_EXP(fis) \ 440 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff) 441 442 /* offset 0x0c */ 443 uint32_t ahcifdr_sectcount_sectcountexp_rsvd; 444 445 #define GET_RFIS_SECTOR_COUNT(fis) \ 446 (fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff) 447 448 #define GET_RFIS_SECTOR_COUNT_EXP(fis) \ 449 ((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff) 450 451 /* offset 0x10 */ 452 uint32_t ahcifdr_rsvd; 453 } ahci_fis_d2h_register_t; 454 455 /* Set Device Bits - Device to Host FIS (from SATA spec) */ 456 typedef struct ahci_fis_set_device_bits { 457 /* offset 0x00 */ 458 uint32_t ahcifsdb_type_rsvd_intr_status_error; 459 460 #define GET_N_BIT_OF_SET_DEV_BITS(fis) \ 461 ((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1) 462 463 /* offset 0x04 */ 464 uint32_t ahcifsdb_rsvd; 465 } ahci_fis_set_device_bits_t; 466 467 /* DMA Setup - Device to Host or Host to Device (from SATA spec) */ 468 typedef struct ahci_fis_dma_setup { 469 /* offset 0x00 */ 470 uint32_t ahcifds_type_rsvd_direction_intr_rsvd; 471 472 /* offset 0x04 */ 473 uint32_t ahcifds_dma_buffer_identifier_low; 474 475 /* offset 0x08 */ 476 uint32_t ahcifds_dma_buffer_identifier_high; 477 478 /* offset 0x0c */ 479 uint32_t ahcifds_rsvd1; 480 481 /* offset 0x10 */ 482 uint32_t ahcifds_dma_buffer_offset; 483 484 /* offset 0x14 */ 485 uint32_t ahcifds_dma_transfer_count; 486 487 /* offset 0x18 */ 488 uint32_t ahcifds_rsvd2; 489 } ahci_fis_dma_setup_t; 490 491 /* PIO Setup - Device to Host FIS (from SATA spec) */ 492 typedef struct ahci_fis_pio_setup { 493 /* offset 0x00 */ 494 uint32_t ahcifps_type_rsvd_direction_intr_status_error; 495 496 /* offset 0x04 */ 497 uint32_t ahcifps_sector_cyllow_cylhi_devhead; 498 499 /* offset 0x08 */ 500 uint32_t ahcifps_sectexp_cyllowexp_cylhiexp_rsvd; 501 502 /* offset 0x0c */ 503 uint32_t ahcifps_sectcount_sectcountexp_rsvd_e_status; 504 505 /* offset 0x10 */ 506 uint32_t ahcifps_transfer_count_rsvd; 507 } ahci_fis_pio_setup_t; 508 509 /* BIST Active - Host to Device or Device to Host (from SATA spec) */ 510 typedef struct ahci_fis_bist_active { 511 /* offset 0x00 */ 512 uint32_t ahcifba_type_rsvd_pattern_rsvd; 513 514 /* offset 0x04 */ 515 uint32_t ahcifba_data1; 516 517 /* offset 0x08 */ 518 uint32_t ahcifba_data2; 519 } ahci_fis_bist_active_t; 520 521 /* Up to 64 bytes */ 522 typedef struct ahci_fis_unknown { 523 uint32_t ahcifu_first_dword; 524 uint32_t ahcifu_dword[15]; 525 } ahci_fis_unknown_t; 526 527 /* 528 * This is a software constructed FIS. For data transfer, 529 * this is the H2D Register FIS format as specified in 530 * the Serial ATA 1.0a specification. Valid Command FIS 531 * length are 2 to 16 Dwords. 532 */ 533 typedef struct ahci_fis_command { 534 union { 535 ahci_fis_h2d_register_t ahcifc_h2d_register; 536 ahci_fis_bist_active_t ahcifc_bist_active; 537 } ahcifc_fis; 538 uint32_t ahcifc_rsvd3[11]; /* should be zero */ 539 } ahci_fis_command_t; 540 541 /* Received FISes structure - size 100h */ 542 typedef struct ahci_rcvd_fis { 543 /* offset 0x00 - DMA Setup FIS */ 544 ahci_fis_dma_setup_t ahcirf_dma_setup_fis; 545 uint32_t ahcirf_fis_rsvd1; 546 547 /* offset 0x20 - PIO Setup FIS */ 548 ahci_fis_pio_setup_t ahcirf_pio_setup_fis; 549 uint32_t ahcirf_fis_rsvd2[3]; 550 551 /* offset 0x40 - D2H Register FIS */ 552 ahci_fis_d2h_register_t ahcirf_d2h_register_fis; 553 uint32_t ahcirf_fis_rsvd3; 554 555 /* offset 0x58 - Set Device Bits FIS */ 556 ahci_fis_set_device_bits_t ahcirf_set_device_bits_fis; 557 558 /* offset 0x60 - Unknown FIS */ 559 ahci_fis_unknown_t ahcirf_unknown_fis; 560 561 /* offset 0xa0h - Reserved */ 562 uint32_t ahcirf_fis_rsvd4[15]; 563 } ahci_rcvd_fis_t; 564 565 /* physical region description table (PRDT) item structure */ 566 typedef struct ahci_prdt_item { 567 /* DW 0 - Data Base Address */ 568 uint32_t ahcipi_data_base_addr; 569 570 /* DW 1 - Data Base Address Upper */ 571 uint32_t ahcipi_data_base_addr_upper; 572 573 /* DW 2 - Reserved */ 574 uint32_t ahcipi_rsvd; 575 576 /* DW 3 - Description Information */ 577 uint32_t ahcipi_descr_info; 578 579 #define GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item) \ 580 ((prdt_item.ahcipi_descr_info >> 31) & 0x01) 581 582 #define GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item) \ 583 (prdt_item.ahcipi_descr_info & 0x3fffff) 584 585 } ahci_prdt_item_t; 586 587 /* command table structure */ 588 typedef struct ahci_cmd_table { 589 /* offset 0x00 - Command FIS */ 590 ahci_fis_command_t ahcict_command_fis; 591 592 /* offset 0x40 - ATAPI Command */ 593 uint8_t ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN]; 594 595 /* offset 0x50 - Reserved */ 596 uint32_t ahcict_rsvd[12]; 597 598 /* offset 0x80 - Physical Region Description Table */ 599 ahci_prdt_item_t ahcict_prdt[AHCI_PRDT_NUMBER]; 600 } ahci_cmd_table_t; 601 602 /* command head structure - size 20h */ 603 typedef struct ahci_cmd_header { 604 /* DW 0 - Description Information */ 605 uint32_t ahcich_descr_info; 606 607 #define BZERO_DESCR_INFO(cmd_header) \ 608 (cmd_header->ahcich_descr_info = 0) 609 610 #define GET_PRD_TABLE_LENGTH(cmd_header) \ 611 ((cmd_header->ahcich_descr_info >> 16) & 0xffff) 612 613 #define SET_PRD_TABLE_LENGTH(cmd_header, length) \ 614 (cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16)) 615 616 #define GET_PORT_MULTI_PORT(cmd_header) \ 617 ((cmd_header->ahcich_descr_info >> 12) & 0x0f) 618 619 #define SET_PORT_MULTI_PORT(cmd_header, flags) \ 620 (cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12)) 621 622 #define GET_CLEAR_BUSY_UPON_R_OK(cmd_header) \ 623 ((cmd_header->ahcich_descr_info >> 10) & 0x01) 624 625 #define SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags) \ 626 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10)) 627 628 #define GET_BIST(cmd_header) \ 629 ((cmd_header->ahcich_descr_info >> 9) & 0x01) 630 631 #define GET_RESET(cmd_header) \ 632 ((cmd_header->ahcich_descr_info >> 8) & 0x01) 633 634 #define SET_RESET(cmd_header, features_exp) \ 635 (cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8)) 636 637 #define GET_PREFETCHABLE(cmd_header) \ 638 ((cmd_header->ahcich_descr_info >> 7) & 0x01) 639 640 #define SET_PREFETCHABLE(cmd_header, flags) \ 641 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7)) 642 643 #define GET_WRITE(cmd_header) \ 644 ((cmd_header->ahcich_descr_info >> 6) & 0x01) 645 646 #define SET_WRITE(cmd_header, flags) \ 647 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6)) 648 649 #define GET_ATAPI(cmd_header) \ 650 ((cmd_header->ahcich_descr_info >> 5) & 0x01) 651 652 #define SET_ATAPI(cmd_header, flags) \ 653 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5)) 654 655 #define GET_COMMAND_FIS_LENGTH(cmd_header) \ 656 (cmd_header->ahcich_descr_info && 0x1f) 657 658 #define SET_COMMAND_FIS_LENGTH(cmd_header, length) \ 659 (cmd_header->ahcich_descr_info |= (length & 0x1f)) 660 661 /* DW 1 - Physical Region Descriptor Byte Count */ 662 uint32_t ahcich_prd_byte_count; 663 664 #define BZERO_PRD_BYTE_COUNT(cmd_header) \ 665 (cmd_header->ahcich_prd_byte_count = 0) 666 667 #define SET_PRD_BYTE_COUNT(cmd_header, count) \ 668 (cmd_header->ahcich_prd_byte_count = count) 669 670 /* DW 2 - Command Table Base Address */ 671 uint32_t ahcich_cmd_tab_base_addr; 672 673 #define SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address) \ 674 (cmd_header->ahcich_cmd_tab_base_addr = base_address) 675 676 /* DW 3 - Command Table Base Address Upper */ 677 uint32_t ahcich_cmd_tab_base_addr_upper; 678 679 #define SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \ 680 (cmd_header->ahcich_cmd_tab_base_addr_upper = base_address) 681 682 /* DW 4-7 - Reserved */ 683 uint32_t ahcich_rsvd[4]; 684 } ahci_cmd_header_t; 685 686 687 #ifdef __cplusplus 688 } 689 #endif 690 691 #endif /* _AHCIREG_H */ 692