1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #ifndef _AHCIREG_H 29 #define _AHCIREG_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define AHCI_MAX_PORTS 32 36 #define AHCI_PORT_MAX_CMD_SLOTS 32 37 38 #define VIA_VENID 0x1106 39 40 /* 41 * In AHCI spec, command table contains a list of 0 (no data transfer) 42 * to up to 65,535 scatter/gather entries for the data transfer. 43 */ 44 #define AHCI_MAX_PRDT_NUMBER 65535 45 #define AHCI_MIN_PRDT_NUMBER 1 46 47 /* 48 * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1 49 * if misaligned, and it's tuable by setting ahci_dma_prdt_number in 50 * /etc/system file. 51 */ 52 #define AHCI_PRDT_NUMBER 257 53 54 /* PCI header offset for AHCI Base Address */ 55 #define AHCI_PCI_RNUM 0x24 56 57 /* various global HBA capability bits */ 58 #define AHCI_HBA_CAP_NP (0x1f << 0) /* number of ports */ 59 #define AHCI_HBA_CAP_SXS (0x1 << 5) /* external SATA */ 60 #define AHCI_HBA_CAP_EMS (0x1 << 6) /* enclosure management */ 61 #define AHCI_HBA_CAP_CCCS (0x1 << 7) /* command completed coalescing */ 62 #define AHCI_HBA_CAP_NCS (0x1f << 8) /* number of command slots */ 63 #define AHCI_HBA_CAP_PSC (0x1 << 13) /* partial state capable */ 64 #define AHCI_HBA_CAP_SSC (0x1 << 14) /* slumber state capable */ 65 #define AHCI_HBA_CAP_PMD (0x1 << 15) /* PIO multiple DRQ block */ 66 #define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */ 67 #define AHCI_HBA_CAP_SPM (0x1 << 17) /* port multiplier */ 68 #define AHCI_HBA_CAP_SAM (0x1 << 18) /* AHCI mode only */ 69 #define AHCI_HBA_CAP_SNZO (0x1 << 19) /* non-zero DMA offsets */ 70 #define AHCI_HBA_CAP_ISS (0xf << 20) /* interface speed support */ 71 #define AHCI_HBA_CAP_SCLO (0x1 << 24) /* command list override */ 72 #define AHCI_HBA_CAP_SAL (0x1 << 25) /* activity LED */ 73 #define AHCI_HBA_CAP_SALP (0x1 << 26) /* aggressive link power mgmt */ 74 #define AHCI_HBA_CAP_SSS (0x1 << 27) /* staggered spin-up */ 75 #define AHCI_HBA_CAP_SMPS (0x1 << 28) /* mechanical presence switch */ 76 #define AHCI_HBA_CAP_SSNTF (0x1 << 29) /* Snotification register */ 77 #define AHCI_HBA_CAP_SNCQ (0x1 << 30) /* Native Command Queuing */ 78 #define AHCI_HBA_CAP_S64A ((uint32_t)0x1 << 31) /* 64-bit addressing */ 79 #define AHCI_HBA_CAP_NCS_SHIFT 8 /* Number of command slots */ 80 #define AHCI_HBA_CAP_ISS_SHIFT 20 /* Interface speed support */ 81 82 /* various global HBA control bits */ 83 #define AHCI_HBA_GHC_HR (0x1 << 0) /* HBA Reset */ 84 #define AHCI_HBA_GHC_IE (0x1 << 1) /* Interrupt Enable */ 85 #define AHCI_HBA_GHC_MRSM (0x1 << 2) /* MSI Revert to Single Message */ 86 #define AHCI_HBA_GHC_AE ((uint32_t)0x1 << 31) /* AHCI Enable */ 87 88 /* various global HBA Command Completion Coalescing (CCC) control bits */ 89 #define AHCI_HBA_CCC_CTL_EN 0x00000001 /* Enable */ 90 #define AHCI_HBA_CCC_CTL_INT_MASK (0x1f << 3) /* Interrupt */ 91 #define AHCI_HBA_CCC_CTL_CC_MASK 0x0000ff00 /* Command Completions */ 92 #define AHCI_HBA_CCC_CTL_TV_MASK 0xffff0000 /* Timeout Value */ 93 #define AHCI_HBA_CCC_CTL_INT_SHIFT 3 94 #define AHCI_HBA_CCC_CTL_CC_SHIFT 8 95 #define AHCI_HBA_CCC_CTL_TV_SHIFT 16 96 97 /* global HBA Enclosure Management Location (EM_LOC) */ 98 #define AHCI_HBA_EM_LOC_SZ_MASK 0x0000ffff /* Buffer Size */ 99 #define AHCI_HBA_EM_LOC_OFST_MASK 0xffff0000 /* Offset */ 100 #define AHCI_HBA_EM_LOC_OFST_SHIFT 16 101 102 /* global HBA Enclosure Management Control (EM_CTL) bits */ 103 #define AHCI_HBA_EM_CTL_STS_MR (0x1 << 0) /* Message Received */ 104 #define AHCI_HBA_EM_CTL_CTL_TM (0x1 << 8) /* Transmit Message */ 105 #define AHCI_HBA_EM_CTL_CTL_RST (0x1 << 9) /* Reset */ 106 #define AHCI_HBA_EM_CTL_SUPP_LED (0x1 << 16) /* LED Message Types */ 107 #define AHCI_HBA_EM_CTL_SUPP_SAFTE (0x1 << 17) /* SAF-TE EM Messages */ 108 #define AHCI_HBA_EM_CTL_SUPP_SES2 (0x1 << 18) /* SES-2 EM Messages */ 109 #define AHCI_HBA_EM_CTL_SUPP_SGPIO (0x1 << 19) /* SGPIO EM Messages */ 110 #define AHCI_HBA_EM_CTL_ATTR_SMB (0x1 << 24) /* Single Message Buffer */ 111 #define AHCI_HBA_EM_CTL_ATTR_XMT (0x1 << 25) /* Transmit Only */ 112 #define AHCI_HBA_EM_CTL_ATTR_ALHD (0x1 << 26) /* Activity LED HW Driven */ 113 #define AHCI_HBA_EM_CTL_ATTR_PM (0x1 << 27) /* PM Support */ 114 115 116 /* global HBA registers definitions */ 117 #define AHCI_GLOBAL_OFFSET(ahci_ctlp) (ahci_ctlp->ahcictl_ahci_addr) 118 /* HBA Capabilities */ 119 #define AHCI_GLOBAL_CAP(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00) 120 /* Global HBA Control */ 121 #define AHCI_GLOBAL_GHC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04) 122 /* Interrupt Status Register */ 123 #define AHCI_GLOBAL_IS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08) 124 /* Ports Implemented */ 125 #define AHCI_GLOBAL_PI(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c) 126 /* AHCI Version */ 127 #define AHCI_GLOBAL_VS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10) 128 /* Command Completion Coalescing Control */ 129 #define AHCI_GLOBAL_CCC_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14) 130 /* Command Completion Coalescing Ports */ 131 #define AHCI_GLOBAL_CCC_PORTS(ahci_ctlp) \ 132 (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18) 133 /* Enclosure Management Location */ 134 #define AHCI_GLOBAL_EM_LOC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c) 135 /* Enclosure Management Control */ 136 #define AHCI_GLOBAL_EM_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20) 137 138 #define AHCI_PORT_IMPLEMENTED(ahci_ctlp, port) \ 139 ((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented) 140 141 /* various port interrupt bits */ 142 /* Device to Host Register FIS Interrupt */ 143 #define AHCI_INTR_STATUS_DHRS (0x1 << 0) 144 /* PIO Setup FIS Interrupt */ 145 #define AHCI_INTR_STATUS_PSS (0x1 << 1) 146 /* DMA Setup FIS Interrupt */ 147 #define AHCI_INTR_STATUS_DSS (0x1 << 2) 148 /* Set Device Bits Interrupt */ 149 #define AHCI_INTR_STATUS_SDBS (0x1 << 3) 150 /* Unknown FIS Interrupt */ 151 #define AHCI_INTR_STATUS_UFS (0x1 << 4) 152 /* Descriptor Processed */ 153 #define AHCI_INTR_STATUS_DPS (0x1 << 5) 154 /* Port Connect Change Status */ 155 #define AHCI_INTR_STATUS_PCS (0x1 << 6) 156 /* Device Mechanical Presence Status */ 157 #define AHCI_INTR_STATUS_DMPS (0x1 << 7) 158 /* PhyRdy Change Status */ 159 #define AHCI_INTR_STATUS_PRCS (0x1 << 22) 160 /* Incorrect Port Multiplier Status */ 161 #define AHCI_INTR_STATUS_IPMS (0x1 << 23) 162 /* Overflow Status */ 163 #define AHCI_INTR_STATUS_OFS (0x1 << 24) 164 /* Interface Non-fatal Error Status */ 165 #define AHCI_INTR_STATUS_INFS (0x1 << 26) 166 /* Interface Fatal Error Status */ 167 #define AHCI_INTR_STATUS_IFS (0x1 << 27) 168 /* Host Bus Data Error Status */ 169 #define AHCI_INTR_STATUS_HBDS (0x1 << 28) 170 /* Host Bus Fatal Error Status */ 171 #define AHCI_INTR_STATUS_HBFS (0x1 << 29) 172 /* Task File Error Status */ 173 #define AHCI_INTR_STATUS_TFES (0x1 << 30) 174 /* Cold Port Detect Status */ 175 #define AHCI_INTR_STATUS_CPDS ((uint32_t)0x1 << 31) 176 #define AHCI_PORT_INTR_MASK 0xfec000ff 177 178 /* port command and status bits */ 179 #define AHCI_CMD_STATUS_ST (0x1 << 0) /* Start */ 180 #define AHCI_CMD_STATUS_SUD (0x1 << 1) /* Spin-up device */ 181 #define AHCI_CMD_STATUS_POD (0x1 << 2) /* Power on device */ 182 #define AHCI_CMD_STATUS_CLO (0x1 << 3) /* Command list override */ 183 #define AHCI_CMD_STATUS_FRE (0x1 << 4) /* FIS receive enable */ 184 #define AHCI_CMD_STATUS_CCS (0x1f << 8) /* Current command slot */ 185 /* Mechanical presence switch state */ 186 #define AHCI_CMD_STATUS_MPSS (0x1 << 13) 187 #define AHCI_CMD_STATUS_FR (0x1 << 14) /* FIS receiving running */ 188 #define AHCI_CMD_STATUS_CR (0x1 << 15) /* Command list running */ 189 #define AHCI_CMD_STATUS_CPS (0x1 << 16) /* Cold presence state */ 190 #define AHCI_CMD_STATUS_PMA (0x1 << 17) /* Port multiplier attached */ 191 #define AHCI_CMD_STATUS_HPCP (0x1 << 18) /* Hot plug capable port */ 192 /* Mechanical presence switch attached to port */ 193 #define AHCI_CMD_STATUS_MPSP (0x1 << 19) 194 #define AHCI_CMD_STATUS_CPD (0x1 << 20) /* Cold presence detection */ 195 #define AHCI_CMD_STATUS_ESP (0x1 << 21) /* External SATA port */ 196 #define AHCI_CMD_STATUS_ATAPI (0x1 << 24) /* Device is ATAPI */ 197 #define AHCI_CMD_STATUS_DLAE (0x1 << 25) /* Drive LED on ATAPI enable */ 198 /* Aggressive link power magament enable */ 199 #define AHCI_CMD_STATUS_ALPE (0x1 << 26) 200 #define AHCI_CMD_STATUS_ASP (0x1 << 27) /* Aggressive slumber/partial */ 201 /* Interface communication control */ 202 #define AHCI_CMD_STATUS_ICC (0xf << 28) 203 #define AHCI_CMD_STATUS_CCS_SHIFT 8 204 #define AHCI_CMD_STATUS_ICC_SHIFT 28 205 206 /* port task file data bits */ 207 #define AHCI_TFD_STS_MASK 0x000000ff 208 #define AHCI_TFD_ERR_MASK 0x0000ff00 209 #define AHCI_TFD_STS_BSY (0x1 << 7) 210 #define AHCI_TFD_STS_DRQ (0x1 << 3) 211 #define AHCI_TFD_STS_ERR (0x1 << 0) 212 #define AHCI_TFD_ERR_SHIFT 8 213 #define AHCI_TFD_ERR_SGS (0x1 << 0) /* DDR1: Send_good_status */ 214 215 #define AHCI_SERROR_CLEAR_ALL 0xffffffff 216 217 /* per port registers offset */ 218 #define AHCI_PORT_OFFSET(ahci_ctlp, port) \ 219 (ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80))) 220 /* Command List Base Address */ 221 #define AHCI_PORT_PxCLB(ahci_ctlp, port) \ 222 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00) 223 /* Command List Base Address Upper 32-Bits */ 224 #define AHCI_PORT_PxCLBU(ahci_ctlp, port) \ 225 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04) 226 /* FIS Base Address */ 227 #define AHCI_PORT_PxFB(ahci_ctlp, port) \ 228 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08) 229 /* FIS Base Address Upper 32-Bits */ 230 #define AHCI_PORT_PxFBU(ahci_ctlp, port) \ 231 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c) 232 /* Interrupt Status */ 233 #define AHCI_PORT_PxIS(ahci_ctlp, port) \ 234 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10) 235 /* Interrupt Enable */ 236 #define AHCI_PORT_PxIE(ahci_ctlp, port) \ 237 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14) 238 /* Command and Status */ 239 #define AHCI_PORT_PxCMD(ahci_ctlp, port) \ 240 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18) 241 /* Task File Data */ 242 #define AHCI_PORT_PxTFD(ahci_ctlp, port) \ 243 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20) 244 /* Signature */ 245 #define AHCI_PORT_PxSIG(ahci_ctlp, port) \ 246 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24) 247 /* Serial ATA Status (SCR0:SStatus) */ 248 #define AHCI_PORT_PxSSTS(ahci_ctlp, port) \ 249 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28) 250 /* Serial ATA Control (SCR2:SControl) */ 251 #define AHCI_PORT_PxSCTL(ahci_ctlp, port) \ 252 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c) 253 /* Serial ATA Error (SCR1:SError) */ 254 #define AHCI_PORT_PxSERR(ahci_ctlp, port) \ 255 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30) 256 /* Serial ATA Active (SCR3:SActive) */ 257 #define AHCI_PORT_PxSACT(ahci_ctlp, port) \ 258 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34) 259 /* Command Issue */ 260 #define AHCI_PORT_PxCI(ahci_ctlp, port) \ 261 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38) 262 /* SNotification */ 263 #define AHCI_PORT_PxSNTF(ahci_ctlp, port) \ 264 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c) 265 266 #define AHCI_SLOT_MASK(ahci_ctlp) \ 267 ((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \ 268 0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1)) 269 #define AHCI_NCQ_SLOT_MASK(ahci_portp) \ 270 ((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \ 271 0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1)) 272 273 /* Device signatures */ 274 #define AHCI_SIGNATURE_PORT_MULTIPLIER 0x96690101 275 #define AHCI_SIGNATURE_ATAPI 0xeb140101 276 #define AHCI_SIGNATURE_DISK 0x00000101 277 278 /* 279 * The address of the control port for the port multiplier, which is 280 * used for control and status communication with the port multiplier 281 * itself. 282 */ 283 #define AHCI_PORTMULT_CONTROL_PORT 0x0f 284 285 #define AHCI_H2D_REGISTER_FIS_TYPE 0x27 286 #define AHCI_H2D_REGISTER_FIS_LENGTH 5 287 288 #define AHCI_CMDHEAD_ATAPI 0x1 /* set to 1 for ATAPI command */ 289 #define AHCI_CMDHEAD_DATA_WRITE 0x1 /* From system memory to device */ 290 #define AHCI_CMDHEAD_DATA_READ 0x0 /* From device to system memory */ 291 #define AHCI_CMDHEAD_PREFETCHABLE 0x1 /* if set, HBA prefetch PRDs */ 292 293 /* Register - Host to Device FIS (from SATA spec) */ 294 typedef struct ahci_fis_h2d_register { 295 /* offset 0x00 */ 296 uint32_t ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features; 297 298 #define SET_FIS_TYPE(fis, type) \ 299 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff)) 300 301 #define SET_FIS_PMP(fis, pmp) \ 302 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 303 ((pmp & 0xf) << 8)) 304 305 #define SET_FIS_CDMDEVCTL(fis, cmddevctl) \ 306 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 307 ((cmddevctl & 0x1) << 15)) 308 309 #define GET_FIS_COMMAND(fis) \ 310 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff) 311 312 #define SET_FIS_COMMAND(fis, command) \ 313 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 314 ((command & 0xff) << 16)) 315 316 #define GET_FIS_FEATURES(fis) \ 317 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff) 318 319 #define SET_FIS_FEATURES(fis, features) \ 320 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 321 ((features & 0xff) << 24)) 322 323 /* offset 0x04 */ 324 uint32_t ahcifhr_sector_cyllow_cylhi_devhead; 325 326 #define GET_FIS_SECTOR(fis) \ 327 (fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff) 328 329 #define SET_FIS_SECTOR(fis, sector) \ 330 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff))) 331 332 #define GET_FIS_CYL_LOW(fis) \ 333 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 334 335 #define SET_FIS_CYL_LOW(fis, cyl_low) \ 336 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8)) 337 338 #define GET_FIS_CYL_HI(fis) \ 339 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 340 341 #define SET_FIS_CYL_HI(fis, cyl_hi) \ 342 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16)) 343 344 #define GET_FIS_DEV_HEAD(fis) \ 345 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 346 347 #define SET_FIS_DEV_HEAD(fis, dev_head) \ 348 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24)) 349 350 /* offset 0x08 */ 351 uint32_t ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp; 352 353 #define GET_FIS_SECTOR_EXP(fis) \ 354 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp & 0xff) 355 356 #define SET_FIS_SECTOR_EXP(fis, sectorexp) \ 357 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 358 ((sectorexp & 0xff))) 359 360 #define GET_FIS_CYL_LOW_EXP(fis) \ 361 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff) 362 363 #define SET_FIS_CYL_LOW_EXP(fis, cyllowexp) \ 364 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 365 ((cyllowexp & 0xff) << 8)) 366 367 #define GET_FIS_CYL_HI_EXP(fis) \ 368 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff) 369 370 #define SET_FIS_CYL_HI_EXP(fis, cylhiexp) \ 371 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 372 ((cylhiexp & 0xff) << 16)) 373 374 #define SET_FIS_FEATURES_EXP(fis, features_exp) \ 375 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 376 ((features_exp & 0xff) << 24)) 377 378 /* offset 0x0c */ 379 uint32_t ahcifhr_sectcount_sectcountexp_rsvd_devctl; 380 381 #define GET_FIS_SECTOR_COUNT(fis) \ 382 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff) 383 384 #define SET_FIS_SECTOR_COUNT(fis, sector_count) \ 385 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 386 ((sector_count & 0xff))) 387 388 #define GET_FIS_SECTOR_COUNT_EXP(fis) \ 389 ((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff) 390 391 #define SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp) \ 392 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 393 ((sector_count_exp & 0xff) << 8)) 394 395 #define SET_FIS_DEVCTL(fis, devctl) \ 396 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 397 ((devctl & 0xff) << 24)) 398 399 /* offset 0x10 */ 400 uint32_t ahcifhr_rsvd3[1]; /* should be zero */ 401 } ahci_fis_h2d_register_t; 402 403 /* Register - Device to Host FIS (from SATA spec) */ 404 typedef struct ahci_fis_d2h_register { 405 /* offset 0x00 */ 406 uint32_t ahcifdr_type_intr_rsvd_status_error; 407 408 #define GET_RFIS_STATUS(fis) \ 409 ((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff) 410 411 #define GET_RFIS_ERROR(fis) \ 412 ((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff) 413 414 /* offset 0x04 */ 415 uint32_t ahcifdr_sector_cyllow_cylhi_devhead; 416 417 #define GET_RFIS_CYL_LOW(fis) \ 418 (fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff) 419 420 #define GET_RFIS_CYL_MID(fis) \ 421 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 422 423 #define GET_RFIS_CYL_HI(fis) \ 424 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 425 426 #define GET_RFIS_DEV_HEAD(fis) \ 427 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 428 429 /* offset 0x08 */ 430 uint32_t ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd; 431 432 #define GET_RFIS_CYL_LOW_EXP(fis) \ 433 (fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd & 0xff) 434 435 #define GET_RFIS_CYL_MID_EXP(fis) \ 436 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff) 437 438 #define GET_RFIS_CYL_HI_EXP(fis) \ 439 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff) 440 441 /* offset 0x0c */ 442 uint32_t ahcifdr_sectcount_sectcountexp_rsvd; 443 444 #define GET_RFIS_SECTOR_COUNT(fis) \ 445 (fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff) 446 447 #define GET_RFIS_SECTOR_COUNT_EXP(fis) \ 448 ((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff) 449 450 /* offset 0x10 */ 451 uint32_t ahcifdr_rsvd; 452 } ahci_fis_d2h_register_t; 453 454 /* Set Device Bits - Device to Host FIS (from SATA spec) */ 455 typedef struct ahci_fis_set_device_bits { 456 /* offset 0x00 */ 457 uint32_t ahcifsdb_type_rsvd_intr_status_error; 458 459 #define GET_N_BIT_OF_SET_DEV_BITS(fis) \ 460 ((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1) 461 462 /* offset 0x04 */ 463 uint32_t ahcifsdb_rsvd; 464 } ahci_fis_set_device_bits_t; 465 466 /* DMA Setup - Device to Host or Host to Device (from SATA spec) */ 467 typedef struct ahci_fis_dma_setup { 468 /* offset 0x00 */ 469 uint32_t ahcifds_type_rsvd_direction_intr_rsvd; 470 471 /* offset 0x04 */ 472 uint32_t ahcifds_dma_buffer_identifier_low; 473 474 /* offset 0x08 */ 475 uint32_t ahcifds_dma_buffer_identifier_high; 476 477 /* offset 0x0c */ 478 uint32_t ahcifds_rsvd1; 479 480 /* offset 0x10 */ 481 uint32_t ahcifds_dma_buffer_offset; 482 483 /* offset 0x14 */ 484 uint32_t ahcifds_dma_transfer_count; 485 486 /* offset 0x18 */ 487 uint32_t ahcifds_rsvd2; 488 } ahci_fis_dma_setup_t; 489 490 /* PIO Setup - Device to Host FIS (from SATA spec) */ 491 typedef struct ahci_fis_pio_setup { 492 /* offset 0x00 */ 493 uint32_t ahcifps_type_rsvd_direction_intr_status_error; 494 495 /* offset 0x04 */ 496 uint32_t ahcifps_sector_cyllow_cylhi_devhead; 497 498 /* offset 0x08 */ 499 uint32_t ahcifps_sectexp_cyllowexp_cylhiexp_rsvd; 500 501 /* offset 0x0c */ 502 uint32_t ahcifps_sectcount_sectcountexp_rsvd_e_status; 503 504 /* offset 0x10 */ 505 uint32_t ahcifps_transfer_count_rsvd; 506 } ahci_fis_pio_setup_t; 507 508 /* BIST Active - Host to Device or Device to Host (from SATA spec) */ 509 typedef struct ahci_fis_bist_active { 510 /* offset 0x00 */ 511 uint32_t ahcifba_type_rsvd_pattern_rsvd; 512 513 /* offset 0x04 */ 514 uint32_t ahcifba_data1; 515 516 /* offset 0x08 */ 517 uint32_t ahcifba_data2; 518 } ahci_fis_bist_active_t; 519 520 /* Up to 64 bytes */ 521 typedef struct ahci_fis_unknown { 522 uint32_t ahcifu_first_dword; 523 uint32_t ahcifu_dword[15]; 524 } ahci_fis_unknown_t; 525 526 /* 527 * This is a software constructed FIS. For data transfer, 528 * this is the H2D Register FIS format as specified in 529 * the Serial ATA 1.0a specification. Valid Command FIS 530 * length are 2 to 16 Dwords. 531 */ 532 typedef struct ahci_fis_command { 533 union { 534 ahci_fis_h2d_register_t ahcifc_h2d_register; 535 ahci_fis_bist_active_t ahcifc_bist_active; 536 } ahcifc_fis; 537 uint32_t ahcifc_rsvd3[11]; /* should be zero */ 538 } ahci_fis_command_t; 539 540 /* Received FISes structure - size 100h */ 541 typedef struct ahci_rcvd_fis { 542 /* offset 0x00 - DMA Setup FIS */ 543 ahci_fis_dma_setup_t ahcirf_dma_setup_fis; 544 uint32_t ahcirf_fis_rsvd1; 545 546 /* offset 0x20 - PIO Setup FIS */ 547 ahci_fis_pio_setup_t ahcirf_pio_setup_fis; 548 uint32_t ahcirf_fis_rsvd2[3]; 549 550 /* offset 0x40 - D2H Register FIS */ 551 ahci_fis_d2h_register_t ahcirf_d2h_register_fis; 552 uint32_t ahcirf_fis_rsvd3; 553 554 /* offset 0x58 - Set Device Bits FIS */ 555 ahci_fis_set_device_bits_t ahcirf_set_device_bits_fis; 556 557 /* offset 0x60 - Unknown FIS */ 558 ahci_fis_unknown_t ahcirf_unknown_fis; 559 560 /* offset 0xa0h - Reserved */ 561 uint32_t ahcirf_fis_rsvd4[24]; 562 } ahci_rcvd_fis_t; 563 564 /* physical region description table (PRDT) item structure */ 565 typedef struct ahci_prdt_item { 566 /* DW 0 - Data Base Address */ 567 uint32_t ahcipi_data_base_addr; 568 569 /* DW 1 - Data Base Address Upper */ 570 uint32_t ahcipi_data_base_addr_upper; 571 572 /* DW 2 - Reserved */ 573 uint32_t ahcipi_rsvd; 574 575 /* DW 3 - Description Information */ 576 uint32_t ahcipi_descr_info; 577 578 #define GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item) \ 579 ((prdt_item.ahcipi_descr_info >> 31) & 0x01) 580 581 #define GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item) \ 582 (prdt_item.ahcipi_descr_info & 0x3fffff) 583 584 } ahci_prdt_item_t; 585 586 /* command table structure */ 587 typedef struct ahci_cmd_table { 588 /* offset 0x00 - Command FIS */ 589 ahci_fis_command_t ahcict_command_fis; 590 591 /* offset 0x40 - ATAPI Command */ 592 uint8_t ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN]; 593 594 /* offset 0x50 - Reserved */ 595 uint32_t ahcict_rsvd[12]; 596 597 /* offset 0x80 - Physical Region Description Table */ 598 ahci_prdt_item_t ahcict_prdt[AHCI_PRDT_NUMBER]; 599 } ahci_cmd_table_t; 600 601 /* command head structure - size 20h */ 602 typedef struct ahci_cmd_header { 603 /* DW 0 - Description Information */ 604 uint32_t ahcich_descr_info; 605 606 #define BZERO_DESCR_INFO(cmd_header) \ 607 (cmd_header->ahcich_descr_info = 0) 608 609 #define GET_PRD_TABLE_LENGTH(cmd_header) \ 610 ((cmd_header->ahcich_descr_info >> 16) & 0xffff) 611 612 #define SET_PRD_TABLE_LENGTH(cmd_header, length) \ 613 (cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16)) 614 615 #define GET_PORT_MULTI_PORT(cmd_header) \ 616 ((cmd_header->ahcich_descr_info >> 12) & 0x0f) 617 618 #define SET_PORT_MULTI_PORT(cmd_header, flags) \ 619 (cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12)) 620 621 #define GET_CLEAR_BUSY_UPON_R_OK(cmd_header) \ 622 ((cmd_header->ahcich_descr_info >> 10) & 0x01) 623 624 #define SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags) \ 625 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10)) 626 627 #define GET_BIST(cmd_header) \ 628 ((cmd_header->ahcich_descr_info >> 9) & 0x01) 629 630 #define GET_RESET(cmd_header) \ 631 ((cmd_header->ahcich_descr_info >> 8) & 0x01) 632 633 #define SET_RESET(cmd_header, features_exp) \ 634 (cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8)) 635 636 #define GET_PREFETCHABLE(cmd_header) \ 637 ((cmd_header->ahcich_descr_info >> 7) & 0x01) 638 639 #define SET_PREFETCHABLE(cmd_header, flags) \ 640 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7)) 641 642 #define GET_WRITE(cmd_header) \ 643 ((cmd_header->ahcich_descr_info >> 6) & 0x01) 644 645 #define SET_WRITE(cmd_header, flags) \ 646 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6)) 647 648 #define GET_ATAPI(cmd_header) \ 649 ((cmd_header->ahcich_descr_info >> 5) & 0x01) 650 651 #define SET_ATAPI(cmd_header, flags) \ 652 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5)) 653 654 #define GET_COMMAND_FIS_LENGTH(cmd_header) \ 655 (cmd_header->ahcich_descr_info && 0x1f) 656 657 #define SET_COMMAND_FIS_LENGTH(cmd_header, length) \ 658 (cmd_header->ahcich_descr_info |= (length & 0x1f)) 659 660 /* DW 1 - Physical Region Descriptor Byte Count */ 661 uint32_t ahcich_prd_byte_count; 662 663 #define BZERO_PRD_BYTE_COUNT(cmd_header) \ 664 (cmd_header->ahcich_prd_byte_count = 0) 665 666 /* DW 2 - Command Table Base Address */ 667 uint32_t ahcich_cmd_tab_base_addr; 668 669 #define SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address) \ 670 (cmd_header->ahcich_cmd_tab_base_addr = base_address) 671 672 /* DW 3 - Command Table Base Address Upper */ 673 uint32_t ahcich_cmd_tab_base_addr_upper; 674 675 #define SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \ 676 (cmd_header->ahcich_cmd_tab_base_addr_upper = base_address) 677 678 /* DW 4-7 - Reserved */ 679 uint32_t ahcich_rsvd[4]; 680 } ahci_cmd_header_t; 681 682 683 #ifdef __cplusplus 684 } 685 #endif 686 687 #endif /* _AHCIREG_H */ 688