1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019 Joyent, Inc. 24 * Copyright 2022 Oxide Computer Company 25 */ 26 27 #ifndef _SYS_PCIE_IMPL_H 28 #define _SYS_PCIE_IMPL_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/pcie.h> 35 #include <sys/pciev.h> 36 #include <sys/taskq_impl.h> 37 38 #define PCI_GET_BDF(dip) \ 39 PCIE_DIP2BUS(dip)->bus_bdf 40 #define PCI_GET_SEC_BUS(dip) \ 41 PCIE_DIP2BUS(dip)->bus_bdg_secbus 42 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 43 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus 44 45 #define DEVI_PORT_TYPE_PCI \ 46 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 47 PCI_BRIDGE_PCI_IF_PCI2PCI) 48 49 #define PCIE_DIP2BUS(dip) \ 50 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 51 PCIE_DIP2UPBUS(dip) : \ 52 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 53 PCIE_DIP2DOWNBUS(dip) : NULL) 54 55 #define PCIE_DIP2UPBUS(dip) \ 56 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 57 #define PCIE_DIP2DOWNBUS(dip) \ 58 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 59 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 60 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 61 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 62 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 63 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 64 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom 65 #define PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip)) 66 67 /* 68 * These macros depend on initialization of type related data in bus_p. 69 */ 70 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 71 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 72 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 73 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 74 /* IS_ROOT = is RC or RP */ 75 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 76 77 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 78 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 79 80 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 81 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 82 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 83 84 /* 85 * This is a pseudo pcie "device type", but it's needed to explain describe 86 * nodes such as PX and NPE, which aren't really PCI devices but do control or 87 * interaction with PCI error handling. 88 */ 89 #define PCIE_IS_RC(bus_p) \ 90 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 91 #define PCIE_IS_RP(bus_p) \ 92 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 93 PCIE_IS_PCIE(bus_p)) 94 #define PCIE_IS_SWU(bus_p) \ 95 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 96 #define PCIE_IS_SWD(bus_p) \ 97 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 98 #define PCIE_IS_SW(bus_p) \ 99 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 100 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 101 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 102 #define PCIE_IS_PCIE_BDG(bus_p) \ 103 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 104 #define PCIE_IS_PCI2PCIE(bus_p) \ 105 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 106 #define PCIE_IS_PCIE_SEC(bus_p) \ 107 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 108 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 109 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 110 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 111 112 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 113 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 114 115 /* PCIE Cap/AER shortcuts */ 116 #define PCIE_GET(sz, bus_p, off) \ 117 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 118 #define PCIE_PUT(sz, bus_p, off, val) \ 119 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 120 #define PCIE_CAP_GET(sz, bus_p, off) \ 121 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off) 122 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 123 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off, \ 124 val) 125 #define PCIE_AER_GET(sz, bus_p, off) \ 126 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off) 127 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 128 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off, \ 129 val) 130 #define PCIX_CAP_GET(sz, bus_p, off) \ 131 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off) 132 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 133 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off, \ 134 val) 135 136 /* Translate PF error return values to DDI_FM values */ 137 #define PF_ERR2DDIFM_ERR(sts) \ 138 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 139 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 140 141 /* 142 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 143 * This flag will be used both by px and pcieb nexus drivers. 144 */ 145 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 146 147 /* 148 * PCI(e/-X) structures used to to gather and report errors detected by 149 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 150 * Static data such as Capability Offsets and Version #s is saved in the parent 151 * private data. 152 */ 153 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 154 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 155 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 156 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 157 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 158 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 159 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 160 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 161 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 162 #define PCIE_ROOT_EH_SRC(pfd_p) pfd_p->pe_root_eh_src 163 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 164 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 165 #define PCIE_ADV_BDG_REG(pfd_p) \ 166 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 167 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 168 #define PCIE_ADV_RP_REG(pfd_p) \ 169 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 170 #define PCIE_SLOT_REG(pfd_p) pfd_p->pe_pcie_slot_regs 171 #define PFD_AFFECTED_DEV(pfd_p) pfd_p->pe_affected_dev 172 #define PFD_SET_AFFECTED_FLAG(pfd_p, aff_flag) \ 173 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = aff_flag 174 #define PFD_SET_AFFECTED_BDF(pfd_p, bdf) \ 175 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = bdf 176 177 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 178 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 179 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 180 181 /* bus_hp_mode field */ 182 typedef enum { 183 PCIE_NONE_HP_MODE = 0x0, 184 PCIE_ACPI_HP_MODE = 0x1, 185 PCIE_PCI_HP_MODE = 0x2, 186 PCIE_NATIVE_HP_MODE = 0x4 187 } pcie_hp_mode_t; 188 189 typedef struct pf_pci_bdg_err_regs { 190 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 191 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 192 } pf_pci_bdg_err_regs_t; 193 194 typedef struct pf_pci_err_regs { 195 uint16_t pci_err_status; /* pci status register */ 196 uint16_t pci_cfg_comm; /* pci command register */ 197 pf_pci_bdg_err_regs_t *pci_bdg_regs; 198 } pf_pci_err_regs_t; 199 200 typedef struct pf_pcix_ecc_regs { 201 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 202 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 203 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 204 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 205 } pf_pcix_ecc_regs_t; 206 207 typedef struct pf_pcix_err_regs { 208 uint16_t pcix_command; /* pcix command register */ 209 uint32_t pcix_status; /* pcix status register */ 210 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 211 } pf_pcix_err_regs_t; 212 213 typedef struct pf_pcix_bdg_err_regs { 214 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 215 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 216 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 217 } pf_pcix_bdg_err_regs_t; 218 219 typedef struct pf_pcie_adv_bdg_err_regs { 220 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 221 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 222 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 223 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 224 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 225 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 226 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 227 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 228 } pf_pcie_adv_bdg_err_regs_t; 229 230 typedef struct pf_pcie_adv_rp_err_regs { 231 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 232 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 233 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 234 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 235 } pf_pcie_adv_rp_err_regs_t; 236 237 typedef struct pf_pcie_adv_err_regs { 238 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 239 uint32_t pcie_ue_status; /* pcie ue error status reg */ 240 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 241 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 242 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 243 uint32_t pcie_ce_status; /* pcie ce error status reg */ 244 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 245 union { 246 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 247 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 248 } pcie_ext; 249 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 250 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 251 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 252 } pf_pcie_adv_err_regs_t; 253 254 typedef struct pf_pcie_rp_err_regs { 255 uint32_t pcie_rp_status; /* root complex status register */ 256 uint16_t pcie_rp_ctl; /* root complex control register */ 257 } pf_pcie_rp_err_regs_t; 258 259 typedef struct pf_pcie_err_regs { 260 uint16_t pcie_err_status; /* pcie device status register */ 261 uint16_t pcie_err_ctl; /* pcie error control register */ 262 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 263 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 264 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 265 } pf_pcie_err_regs_t; 266 267 /* 268 * Slot register values for hotplug-capable Downstream Ports or Root Ports with 269 * the Slot Implemented capability bit set. We gather these to help determine 270 * whether the slot's child device is physically present. 271 */ 272 typedef struct pf_pcie_slot_regs { 273 boolean_t pcie_slot_regs_valid; /* true if register values are valid */ 274 uint32_t pcie_slot_cap; /* pcie slot capabilities register */ 275 uint16_t pcie_slot_control; /* pcie slot control register */ 276 uint16_t pcie_slot_status; /* pcie slot status register */ 277 } pf_pcie_slot_regs_t; 278 279 typedef enum { 280 PF_INTR_TYPE_NONE = 0, 281 PF_INTR_TYPE_FABRIC = 1, /* Fabric Message */ 282 PF_INTR_TYPE_DATA, /* Data Access Failure, failed loads */ 283 PF_INTR_TYPE_AER, /* Root Port AER MSI */ 284 PF_INTR_TYPE_INTERNAL /* Chip specific internal errors */ 285 } pf_intr_type_t; 286 287 typedef struct pf_root_eh_src { 288 pf_intr_type_t intr_type; 289 void *intr_data; /* Interrupt Data */ 290 } pf_root_eh_src_t; 291 292 typedef struct pf_root_fault { 293 pcie_req_id_t scan_bdf; /* BDF from error logs */ 294 uint64_t scan_addr; /* Addr from error logs */ 295 boolean_t full_scan; /* Option to do a full scan */ 296 } pf_root_fault_t; 297 298 typedef struct pf_data pf_data_t; 299 300 typedef enum pcie_link_width { 301 PCIE_LINK_WIDTH_UNKNOWN, 302 PCIE_LINK_WIDTH_X1, 303 PCIE_LINK_WIDTH_X2, 304 PCIE_LINK_WIDTH_X4, 305 PCIE_LINK_WIDTH_X8, 306 PCIE_LINK_WIDTH_X12, 307 PCIE_LINK_WIDTH_X16, 308 PCIE_LINK_WIDTH_X32 309 } pcie_link_width_t; 310 311 /* 312 * Note, this member should always be treated as a bit field, as a device may 313 * support multiple speeds. 314 */ 315 typedef enum pcie_link_speed { 316 PCIE_LINK_SPEED_UNKNOWN = 0x00, 317 PCIE_LINK_SPEED_2_5 = 1 << 0, 318 PCIE_LINK_SPEED_5 = 1 << 1, 319 PCIE_LINK_SPEED_8 = 1 << 2, 320 PCIE_LINK_SPEED_16 = 1 << 3 321 } pcie_link_speed_t; 322 323 typedef enum pcie_link_flags { 324 PCIE_LINK_F_ADMIN_TARGET = 1 << 1 325 } pcie_link_flags_t; 326 327 typedef enum { 328 PCIE_LBW_S_ENABLED = 1 << 0, 329 PCIE_LBW_S_DISPATCHED = 1 << 1, 330 PCIE_LBW_S_RUNNING = 1 << 2 331 } pcie_lbw_state_t; 332 333 /* 334 * This structure is used to keep track of a given bus hierarchy and the set of 335 * PCIe tags that we have enabled on it. 336 */ 337 typedef enum { 338 PCIE_TAG_5B = 0, 339 PCIE_TAG_8B = 1 << 0, 340 PCIE_TAG_10B_COMP = 1 << 1, 341 PCIE_TAG_14B_COMP = 1 << 2 342 } pcie_tag_t; 343 344 #define PCIE_TAG_ALL (PCIE_TAG_8B | PCIE_TAG_10B_COMP | PCIE_TAG_14B_COMP) 345 346 typedef enum { 347 /* 348 * This flag is kept around for debugging and noticing that we're in the 349 * process of trying to perform a scan. 350 */ 351 PCIE_FABRIC_F_SCANNING = 1 << 0, 352 /* 353 * This is used to indicate that we have discovered a topology that is 354 * too complex for us to be able to set advanced settings on and 355 * therefore have to leave it at the bare minimum. 356 */ 357 PCIE_FABRIC_F_COMPLEX = 1 << 1, 358 /* 359 * Indicates that we found a hot-pluggable root port in the fabric. 360 */ 361 PCIE_FABRIC_F_RP_HP = 1 << 2 362 } pcie_fabric_flags_t; 363 364 /* 365 * This structure represents hierarchy wide settings that are used in a given 366 * PCIe fabric (what the spec calls a "hierarchy domain"). This keeps track of 367 * what we have found and enabled in the fabric as part of our initialization. 368 * For more information on this, please see the theory statement in 369 * uts/common/io/pciex/pcie.c. 370 */ 371 typedef struct pice_fabric_data { 372 pcie_fabric_flags_t pfd_flags; 373 uint16_t pfd_mps_found; 374 uint16_t pfd_mps_act; 375 pcie_tag_t pfd_tag_found; 376 pcie_tag_t pfd_tag_act; 377 } pcie_fabric_data_t; 378 379 /* 380 * For hot plugged device, these data are init'ed during during probe 381 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86), 382 * or in px_attach()(on sparc). 383 * 384 * For root complex the fields are initialized in pcie_rc_init_bus(); 385 * for others part of the fields are initialized in pcie_init_bus(), 386 * and part of fields initialized in pcie_post_init_bus(). See comments 387 * on top of respective functions for details. 388 */ 389 typedef struct pcie_bus { 390 /* Needed for PCI/PCIe fabric error handling */ 391 dev_info_t *bus_dip; 392 dev_info_t *bus_rp_dip; 393 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 394 uint_t bus_fm_flags; 395 uint_t bus_soft_state; 396 397 /* Static PCI/PCIe information */ 398 pcie_req_id_t bus_bdf; 399 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 400 uint32_t bus_dev_ven_id; /* device/vendor ID */ 401 uint8_t bus_rev_id; /* revision ID */ 402 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 403 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 404 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 405 uint8_t bus_pcie_vers; /* Version of the PCIe cap */ 406 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 407 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 408 uint16_t bus_dev3_off; /* PCIe Device 3 Capability */ 409 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 410 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 411 uint16_t bus_ecc_ver; /* PCIX ecc version */ 412 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 413 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 414 int bus_addr_entries; /* number of range prop */ 415 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 416 int bus_assigned_entries; /* number of prop entries */ 417 418 /* Cache of last fault data */ 419 pf_data_t *bus_pfd; 420 pcie_domain_t *bus_dom; 421 422 void *bus_plat_private; /* Platform specific */ 423 /* Hotplug specific fields */ 424 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 425 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 426 void *bus_hp_ctrl; /* HP bus ctrl data */ 427 int bus_ari; /* ARI device */ 428 429 /* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */ 430 pcie_req_id_t bus_pcie2pci_secbus; 431 432 /* 433 * Link speed specific fields. 434 */ 435 kmutex_t bus_speed_mutex; 436 pcie_link_flags_t bus_speed_flags; 437 pcie_link_width_t bus_max_width; 438 pcie_link_width_t bus_cur_width; 439 pcie_link_speed_t bus_sup_speed; 440 pcie_link_speed_t bus_max_speed; 441 pcie_link_speed_t bus_cur_speed; 442 pcie_link_speed_t bus_target_speed; 443 444 /* 445 * Link Bandwidth Monitoring 446 */ 447 kmutex_t bus_lbw_mutex; 448 kcondvar_t bus_lbw_cv; 449 pcie_lbw_state_t bus_lbw_state; 450 taskq_ent_t bus_lbw_ent; 451 uint64_t bus_lbw_nevents; 452 char *bus_lbw_pbuf; 453 char *bus_lbw_cbuf; 454 455 /* 456 * The following contains fabric wide settings and information that are 457 * used. This member is only valid on the root port. It is NULL on all 458 * other pcie_bus_t members who instead need to access this through the 459 * corresponding root port dip information. 460 */ 461 pcie_fabric_data_t *bus_fab; 462 } pcie_bus_t; 463 464 /* 465 * Data structure to log what devices are affected in relationship to the 466 * severity after all the errors bits have been analyzed. 467 */ 468 #define PF_AFFECTED_ROOT (1 << 0) /* RP/RC is affected */ 469 #define PF_AFFECTED_SELF (1 << 1) /* Reporting Device is affected */ 470 #define PF_AFFECTED_PARENT (1 << 2) /* Parent device is affected */ 471 #define PF_AFFECTED_CHILDREN (1 << 3) /* All children below are affected */ 472 #define PF_AFFECTED_BDF (1 << 4) /* See affected_bdf */ 473 #define PF_AFFECTED_AER (1 << 5) /* See AER Registers */ 474 #define PF_AFFECTED_SAER (1 << 6) /* See SAER Registers */ 475 #define PF_AFFECTED_ADDR (1 << 7) /* Device targeted by addr */ 476 477 #define PF_MAX_AFFECTED_FLAG PF_AFFECTED_ADDR 478 479 typedef struct pf_affected_dev { 480 uint16_t pe_affected_flags; 481 pcie_req_id_t pe_affected_bdf; 482 } pf_affected_dev_t; 483 484 struct pf_data { 485 boolean_t pe_lock; 486 boolean_t pe_valid; 487 uint32_t pe_severity_flags; /* Severity of error */ 488 uint32_t pe_severity_mask; 489 uint32_t pe_orig_severity_flags; /* Original severity */ 490 pf_affected_dev_t *pe_affected_dev; 491 pcie_bus_t *pe_bus_p; 492 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 493 pf_root_eh_src_t *pe_root_eh_src; /* Only valid for RC and RP */ 494 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 495 union { 496 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 497 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 498 } pe_ext; 499 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 500 pf_pcie_slot_regs_t *pe_pcie_slot_regs; /* PCIe slot regs */ 501 pf_data_t *pe_prev; /* Next error in queue */ 502 pf_data_t *pe_next; /* Next error in queue */ 503 boolean_t pe_rber_fatal; 504 }; 505 506 /* Information used while handling errors in the fabric. */ 507 typedef struct pf_impl { 508 ddi_fm_error_t *pf_derr; 509 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 510 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 511 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 512 uint32_t pf_total; /* total non RC pf_datas */ 513 } pf_impl_t; 514 515 /* bus_fm_flags field */ 516 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 517 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 518 #define PF_FM_IS_PASSTHRU (1 << 2) /* device is controlled by VM */ 519 520 /* 521 * PCIe fabric handle lookup address flags. Used to define what type of 522 * transaction the address is for. These same value are defined again in 523 * fabric-xlate FM module. Do not modify these variables, without modifying 524 * those. 525 */ 526 #define PF_ADDR_DMA (1 << 0) 527 #define PF_ADDR_PIO (1 << 1) 528 #define PF_ADDR_CFG (1 << 2) 529 530 /* PCIe fabric error scanning status flags */ 531 #define PF_SCAN_SUCCESS (1 << 0) 532 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 533 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 534 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 535 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 536 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 537 538 /* PCIe fabric error handling severity return flags */ 539 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 540 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 541 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 542 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 543 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 544 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 545 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 546 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 547 #define PF_ERR_BAD_RESPONSE (1 << 8) /* Device bad/no response */ 548 #define PF_ERR_MATCH_DOM (1 << 9) /* Error Handled By IO domain */ 549 550 #define PF_ERR_FATAL_FLAGS (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK) 551 552 #define PF_HDL_FOUND 1 553 #define PF_HDL_NOTFOUND 2 554 555 /* 556 * PCIe Capability Device Type Pseudo Definitions. 557 * 558 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 559 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 560 * Space access is usually frowned upon now in PCIe, but there for legacy 561 * purposes. 562 */ 563 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 564 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 565 566 #define PCIE_INVALID_BDF 0xFFFF 567 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 568 569 /* 570 * Default interrupt priority for all PCI and PCIe nexus drivers including 571 * hotplug interrupts. 572 */ 573 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 574 575 /* 576 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 577 * for non-standard PCI or PCI Express Hotplug Controllers. 578 */ 579 #define PCIE_ENABLE_ERRORS(dip) \ 580 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 581 pcie_enable_errors(dip); \ 582 (void) pcie_enable_ce(dip); \ 583 } 584 585 #define PCIE_DISABLE_ERRORS(dip) \ 586 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 587 pcie_disable_errors(dip); \ 588 } 589 590 /* 591 * pcie_init_buspcie_fini_bus specific flags 592 */ 593 #define PCIE_BUS_INITIAL 0x0001 594 #define PCIE_BUS_FINAL 0x0002 595 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL) 596 597 #ifdef DEBUG 598 #define PCIE_DBG pcie_dbg 599 /* Common Debugging shortcuts */ 600 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 601 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 602 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 603 PCIE_GET(sz, bus_p, off)) 604 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 605 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 606 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 607 PCIE_CAP_GET(sz, bus_p, off)) 608 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 609 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 610 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 611 PCIE_AER_GET(sz, bus_p, off)) 612 613 #else /* DEBUG */ 614 615 #define PCIE_DBG_CFG(...) (void)(0) 616 #define PCIE_DBG(...) (void)(0) 617 #define PCIE_ARI_DBG(...) (void)(0) 618 #define PCIE_DBG_CAP(...) (void)(0) 619 #define PCIE_DBG_AER(...) (void)(0) 620 621 #endif /* DEBUG */ 622 623 /* PCIe Friendly Functions */ 624 extern int pcie_init(dev_info_t *dip, caddr_t arg); 625 extern int pcie_uninit(dev_info_t *dip); 626 extern int pcie_hpintr_enable(dev_info_t *dip); 627 extern int pcie_hpintr_disable(dev_info_t *dip); 628 extern int pcie_intr(dev_info_t *dip); 629 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 630 cred_t *credp); 631 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 632 cred_t *credp); 633 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 634 int mode, cred_t *credp, int *rvalp); 635 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 636 int flags, char *name, caddr_t valuep, int *lengthp); 637 638 extern void pcie_fabric_setup(dev_info_t *dip); 639 extern int pcie_initchild(dev_info_t *dip); 640 extern void pcie_uninitchild(dev_info_t *dip); 641 extern int pcie_init_cfghdl(dev_info_t *dip); 642 extern void pcie_fini_cfghdl(dev_info_t *dip); 643 extern void pcie_clear_errors(dev_info_t *dip); 644 extern int pcie_postattach_child(dev_info_t *dip); 645 extern void pcie_enable_errors(dev_info_t *dip); 646 extern void pcie_disable_errors(dev_info_t *dip); 647 extern int pcie_enable_ce(dev_info_t *dip); 648 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 649 extern boolean_t pcie_is_pci_device(dev_info_t *dip); 650 651 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, 652 uint8_t flags); 653 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags); 654 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags); 655 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags); 656 extern void pcie_rc_init_bus(dev_info_t *dip); 657 extern void pcie_rc_fini_bus(dev_info_t *dip); 658 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 659 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 660 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 661 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 662 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 663 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 664 extern int pcie_dev(dev_info_t *dip); 665 extern int pcie_root_port(dev_info_t *dip); 666 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 667 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 668 669 extern uint32_t pcie_get_aer_uce_mask(); 670 extern uint32_t pcie_get_aer_ce_mask(); 671 extern uint32_t pcie_get_aer_suce_mask(); 672 extern uint32_t pcie_get_serr_mask(); 673 extern void pcie_set_aer_uce_mask(uint32_t mask); 674 extern void pcie_set_aer_ce_mask(uint32_t mask); 675 extern void pcie_set_aer_suce_mask(uint32_t mask); 676 extern void pcie_set_serr_mask(uint32_t mask); 677 extern void pcie_init_plat(dev_info_t *dip); 678 extern void pcie_fini_plat(dev_info_t *dip); 679 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 680 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 681 extern int pcie_ari_disable(dev_info_t *dip); 682 extern int pcie_ari_enable(dev_info_t *dip); 683 684 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 685 #define PCIE_ARI_FORW_SUPPORTED 1 686 687 extern int pcie_ari_supported(dev_info_t *dip); 688 689 #define PCIE_ARI_FORW_DISABLED 0 690 #define PCIE_ARI_FORW_ENABLED 1 691 692 extern int pcie_ari_is_enabled(dev_info_t *dip); 693 694 #define PCIE_NOT_ARI_DEVICE 0 695 #define PCIE_ARI_DEVICE 1 696 697 extern int pcie_ari_device(dev_info_t *dip); 698 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 699 700 /* PCIe error handling functions */ 701 extern void pf_eh_enter(pcie_bus_t *bus_p); 702 extern void pf_eh_exit(pcie_bus_t *bus_p); 703 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 704 pf_data_t *root_pfd_p); 705 extern void pf_set_passthru(dev_info_t *, boolean_t); 706 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 707 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 708 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 709 pcie_req_id_t); 710 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 711 extern void pcie_force_fullscan(); 712 713 #ifdef DEBUG 714 extern uint_t pcie_debug_flags; 715 extern void pcie_dbg(char *fmt, ...); 716 #endif /* DEBUG */ 717 718 /* PCIe IOV functions */ 719 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf); 720 721 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t); 722 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t); 723 extern int pf_pci_decode(pf_data_t *, uint16_t *); 724 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t); 725 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t); 726 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *); 727 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *); 728 729 extern int pciev_eh(pf_data_t *, pf_impl_t *); 730 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *, 731 uint16_t, uint16_t); 732 extern void pciev_eh_exit(pf_data_t *, uint_t); 733 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t); 734 735 /* Link Bandwidth Monitoring */ 736 extern boolean_t pcie_link_bw_supported(dev_info_t *); 737 extern int pcie_link_bw_enable(dev_info_t *); 738 extern int pcie_link_bw_disable(dev_info_t *); 739 740 /* Link Management */ 741 extern int pcie_link_set_target(dev_info_t *, pcie_link_speed_t); 742 extern int pcie_link_retrain(dev_info_t *); 743 744 #define PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP) 745 746 747 #ifdef __cplusplus 748 } 749 #endif 750 751 #endif /* _SYS_PCIE_IMPL_H */ 752