1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019 Joyent, Inc. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/pcie.h> 34 #include <sys/pciev.h> 35 #include <sys/taskq_impl.h> 36 37 #define PCI_GET_BDF(dip) \ 38 PCIE_DIP2BUS(dip)->bus_bdf 39 #define PCI_GET_SEC_BUS(dip) \ 40 PCIE_DIP2BUS(dip)->bus_bdg_secbus 41 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 42 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus 43 44 #define DEVI_PORT_TYPE_PCI \ 45 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 46 PCI_BRIDGE_PCI_IF_PCI2PCI) 47 48 #define PCIE_DIP2BUS(dip) \ 49 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 50 PCIE_DIP2UPBUS(dip) : \ 51 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 52 PCIE_DIP2DOWNBUS(dip) : NULL) 53 54 #define PCIE_DIP2UPBUS(dip) \ 55 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 56 #define PCIE_DIP2DOWNBUS(dip) \ 57 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 58 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 59 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 60 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 61 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 62 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 63 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom 64 #define PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip)) 65 66 /* 67 * These macros depend on initialization of type related data in bus_p. 68 */ 69 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 70 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 71 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 72 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 73 /* IS_ROOT = is RC or RP */ 74 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 75 76 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 77 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 78 79 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 80 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 81 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 82 83 /* 84 * This is a pseudo pcie "device type", but it's needed to explain describe 85 * nodes such as PX and NPE, which aren't really PCI devices but do control or 86 * interaction with PCI error handling. 87 */ 88 #define PCIE_IS_RC(bus_p) \ 89 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 90 #define PCIE_IS_RP(bus_p) \ 91 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 92 PCIE_IS_PCIE(bus_p)) 93 #define PCIE_IS_SWU(bus_p) \ 94 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 95 #define PCIE_IS_SWD(bus_p) \ 96 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 97 #define PCIE_IS_SW(bus_p) \ 98 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 99 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 100 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 101 #define PCIE_IS_PCIE_BDG(bus_p) \ 102 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 103 #define PCIE_IS_PCI2PCIE(bus_p) \ 104 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 105 #define PCIE_IS_PCIE_SEC(bus_p) \ 106 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 107 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 108 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 109 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 110 111 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 112 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 113 114 /* PCIE Cap/AER shortcuts */ 115 #define PCIE_GET(sz, bus_p, off) \ 116 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 117 #define PCIE_PUT(sz, bus_p, off, val) \ 118 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 119 #define PCIE_CAP_GET(sz, bus_p, off) \ 120 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off) 121 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 122 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off, \ 123 val) 124 #define PCIE_AER_GET(sz, bus_p, off) \ 125 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off) 126 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 127 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off, \ 128 val) 129 #define PCIX_CAP_GET(sz, bus_p, off) \ 130 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off) 131 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 132 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off, \ 133 val) 134 135 /* Translate PF error return values to DDI_FM values */ 136 #define PF_ERR2DDIFM_ERR(sts) \ 137 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 138 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 139 140 /* 141 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 142 * This flag will be used both by px and pcieb nexus drivers. 143 */ 144 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 145 146 /* 147 * PCI(e/-X) structures used to to gather and report errors detected by 148 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 149 * Static data such as Capability Offsets and Version #s is saved in the parent 150 * private data. 151 */ 152 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 153 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 154 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 155 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 156 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 157 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 158 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 159 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 160 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 161 #define PCIE_ROOT_EH_SRC(pfd_p) pfd_p->pe_root_eh_src 162 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 163 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 164 #define PCIE_ADV_BDG_REG(pfd_p) \ 165 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 166 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 167 #define PCIE_ADV_RP_REG(pfd_p) \ 168 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 169 #define PFD_AFFECTED_DEV(pfd_p) pfd_p->pe_affected_dev 170 #define PFD_SET_AFFECTED_FLAG(pfd_p, aff_flag) \ 171 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = aff_flag 172 #define PFD_SET_AFFECTED_BDF(pfd_p, bdf) \ 173 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = bdf 174 175 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 176 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 177 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 178 179 /* bus_hp_mode field */ 180 typedef enum { 181 PCIE_NONE_HP_MODE = 0x0, 182 PCIE_ACPI_HP_MODE = 0x1, 183 PCIE_PCI_HP_MODE = 0x2, 184 PCIE_NATIVE_HP_MODE = 0x4 185 } pcie_hp_mode_t; 186 187 typedef struct pf_pci_bdg_err_regs { 188 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 189 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 190 } pf_pci_bdg_err_regs_t; 191 192 typedef struct pf_pci_err_regs { 193 uint16_t pci_err_status; /* pci status register */ 194 uint16_t pci_cfg_comm; /* pci command register */ 195 pf_pci_bdg_err_regs_t *pci_bdg_regs; 196 } pf_pci_err_regs_t; 197 198 typedef struct pf_pcix_ecc_regs { 199 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 200 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 201 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 202 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 203 } pf_pcix_ecc_regs_t; 204 205 typedef struct pf_pcix_err_regs { 206 uint16_t pcix_command; /* pcix command register */ 207 uint32_t pcix_status; /* pcix status register */ 208 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 209 } pf_pcix_err_regs_t; 210 211 typedef struct pf_pcix_bdg_err_regs { 212 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 213 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 214 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 215 } pf_pcix_bdg_err_regs_t; 216 217 typedef struct pf_pcie_adv_bdg_err_regs { 218 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 219 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 220 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 221 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 222 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 223 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 224 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 225 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 226 } pf_pcie_adv_bdg_err_regs_t; 227 228 typedef struct pf_pcie_adv_rp_err_regs { 229 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 230 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 231 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 232 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 233 } pf_pcie_adv_rp_err_regs_t; 234 235 typedef struct pf_pcie_adv_err_regs { 236 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 237 uint32_t pcie_ue_status; /* pcie ue error status reg */ 238 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 239 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 240 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 241 uint32_t pcie_ce_status; /* pcie ce error status reg */ 242 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 243 union { 244 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 245 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 246 } pcie_ext; 247 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 248 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 249 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 250 } pf_pcie_adv_err_regs_t; 251 252 typedef struct pf_pcie_rp_err_regs { 253 uint32_t pcie_rp_status; /* root complex status register */ 254 uint16_t pcie_rp_ctl; /* root complex control register */ 255 } pf_pcie_rp_err_regs_t; 256 257 typedef struct pf_pcie_err_regs { 258 uint16_t pcie_err_status; /* pcie device status register */ 259 uint16_t pcie_err_ctl; /* pcie error control register */ 260 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 261 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 262 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 263 } pf_pcie_err_regs_t; 264 265 typedef enum { 266 PF_INTR_TYPE_NONE = 0, 267 PF_INTR_TYPE_FABRIC = 1, /* Fabric Message */ 268 PF_INTR_TYPE_DATA, /* Data Access Failure, failed loads */ 269 PF_INTR_TYPE_AER, /* Root Port AER MSI */ 270 PF_INTR_TYPE_INTERNAL /* Chip specific internal errors */ 271 } pf_intr_type_t; 272 273 typedef struct pf_root_eh_src { 274 pf_intr_type_t intr_type; 275 void *intr_data; /* Interrupt Data */ 276 } pf_root_eh_src_t; 277 278 typedef struct pf_root_fault { 279 pcie_req_id_t scan_bdf; /* BDF from error logs */ 280 uint64_t scan_addr; /* Addr from error logs */ 281 boolean_t full_scan; /* Option to do a full scan */ 282 } pf_root_fault_t; 283 284 typedef struct pf_data pf_data_t; 285 286 typedef enum pcie_link_width { 287 PCIE_LINK_WIDTH_UNKNOWN, 288 PCIE_LINK_WIDTH_X1, 289 PCIE_LINK_WIDTH_X2, 290 PCIE_LINK_WIDTH_X4, 291 PCIE_LINK_WIDTH_X8, 292 PCIE_LINK_WIDTH_X12, 293 PCIE_LINK_WIDTH_X16, 294 PCIE_LINK_WIDTH_X32 295 } pcie_link_width_t; 296 297 /* 298 * Note, this member should always be treated as a bit field, as a device may 299 * support multiple speeds. 300 */ 301 typedef enum pcie_link_speed { 302 PCIE_LINK_SPEED_UNKNOWN = 0x00, 303 PCIE_LINK_SPEED_2_5 = 1 << 0, 304 PCIE_LINK_SPEED_5 = 1 << 1, 305 PCIE_LINK_SPEED_8 = 1 << 2, 306 PCIE_LINK_SPEED_16 = 1 << 3 307 } pcie_link_speed_t; 308 309 typedef enum pcie_link_flags { 310 PCIE_LINK_F_ADMIN_TARGET = 1 << 1 311 } pcie_link_flags_t; 312 313 typedef enum { 314 PCIE_LBW_S_ENABLED = 1 << 0, 315 PCIE_LBW_S_DISPATCHED = 1 << 1, 316 PCIE_LBW_S_RUNNING = 1 << 2 317 } pcie_lbw_state_t; 318 319 /* 320 * For hot plugged device, these data are init'ed during during probe 321 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86), 322 * or in px_attach()(on sparc). 323 * 324 * For root complex the fields are initialized in pcie_rc_init_bus(); 325 * for others part of the fields are initialized in pcie_init_bus(), 326 * and part of fields initialized in pcie_post_init_bus(). See comments 327 * on top of respective functions for details. 328 */ 329 typedef struct pcie_bus { 330 /* Needed for PCI/PCIe fabric error handling */ 331 dev_info_t *bus_dip; 332 dev_info_t *bus_rp_dip; 333 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 334 uint_t bus_fm_flags; 335 uint_t bus_soft_state; 336 337 /* Static PCI/PCIe information */ 338 pcie_req_id_t bus_bdf; 339 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 340 uint32_t bus_dev_ven_id; /* device/vendor ID */ 341 uint8_t bus_rev_id; /* revision ID */ 342 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 343 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 344 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 345 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 346 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 347 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 348 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 349 uint16_t bus_ecc_ver; /* PCIX ecc version */ 350 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 351 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 352 int bus_addr_entries; /* number of range prop */ 353 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 354 int bus_assigned_entries; /* number of prop entries */ 355 356 /* Cache of last fault data */ 357 pf_data_t *bus_pfd; 358 pcie_domain_t *bus_dom; 359 360 int bus_mps; /* Maximum Payload Size */ 361 362 void *bus_plat_private; /* Platform specific */ 363 /* Hotplug specific fields */ 364 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 365 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 366 void *bus_hp_ctrl; /* HP bus ctrl data */ 367 int bus_ari; /* ARI device */ 368 369 uint64_t bus_cfgacc_base; /* config space base address */ 370 371 /* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */ 372 pcie_req_id_t bus_pcie2pci_secbus; 373 374 /* 375 * Link speed specific fields. 376 */ 377 kmutex_t bus_speed_mutex; 378 pcie_link_flags_t bus_speed_flags; 379 pcie_link_width_t bus_max_width; 380 pcie_link_width_t bus_cur_width; 381 pcie_link_speed_t bus_sup_speed; 382 pcie_link_speed_t bus_max_speed; 383 pcie_link_speed_t bus_cur_speed; 384 pcie_link_speed_t bus_target_speed; 385 386 /* 387 * Link Bandwidth Monitoring 388 */ 389 kmutex_t bus_lbw_mutex; 390 kcondvar_t bus_lbw_cv; 391 pcie_lbw_state_t bus_lbw_state; 392 taskq_ent_t bus_lbw_ent; 393 uint64_t bus_lbw_nevents; 394 char *bus_lbw_pbuf; 395 char *bus_lbw_cbuf; 396 } pcie_bus_t; 397 398 /* 399 * Data structure to log what devices are affected in relationship to the 400 * severity after all the errors bits have been analyzed. 401 */ 402 #define PF_AFFECTED_ROOT (1 << 0) /* RP/RC is affected */ 403 #define PF_AFFECTED_SELF (1 << 1) /* Reporting Device is affected */ 404 #define PF_AFFECTED_PARENT (1 << 2) /* Parent device is affected */ 405 #define PF_AFFECTED_CHILDREN (1 << 3) /* All children below are affected */ 406 #define PF_AFFECTED_BDF (1 << 4) /* See affected_bdf */ 407 #define PF_AFFECTED_AER (1 << 5) /* See AER Registers */ 408 #define PF_AFFECTED_SAER (1 << 6) /* See SAER Registers */ 409 #define PF_AFFECTED_ADDR (1 << 7) /* Device targeted by addr */ 410 411 #define PF_MAX_AFFECTED_FLAG PF_AFFECTED_ADDR 412 413 typedef struct pf_affected_dev { 414 uint16_t pe_affected_flags; 415 pcie_req_id_t pe_affected_bdf; 416 } pf_affected_dev_t; 417 418 struct pf_data { 419 boolean_t pe_lock; 420 boolean_t pe_valid; 421 uint32_t pe_severity_flags; /* Severity of error */ 422 uint32_t pe_severity_mask; 423 uint32_t pe_orig_severity_flags; /* Original severity */ 424 pf_affected_dev_t *pe_affected_dev; 425 pcie_bus_t *pe_bus_p; 426 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 427 pf_root_eh_src_t *pe_root_eh_src; /* Only valid for RC and RP */ 428 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 429 union { 430 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 431 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 432 } pe_ext; 433 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 434 pf_data_t *pe_prev; /* Next error in queue */ 435 pf_data_t *pe_next; /* Next error in queue */ 436 boolean_t pe_rber_fatal; 437 }; 438 439 /* Information used while handling errors in the fabric. */ 440 typedef struct pf_impl { 441 ddi_fm_error_t *pf_derr; 442 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 443 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 444 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 445 uint32_t pf_total; /* total non RC pf_datas */ 446 } pf_impl_t; 447 448 /* bus_fm_flags field */ 449 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 450 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 451 #define PF_FM_IS_PASSTHRU (1 << 2) /* device is controlled by VM */ 452 453 /* 454 * PCIe fabric handle lookup address flags. Used to define what type of 455 * transaction the address is for. These same value are defined again in 456 * fabric-xlate FM module. Do not modify these variables, without modifying 457 * those. 458 */ 459 #define PF_ADDR_DMA (1 << 0) 460 #define PF_ADDR_PIO (1 << 1) 461 #define PF_ADDR_CFG (1 << 2) 462 463 /* PCIe fabric error scanning status flags */ 464 #define PF_SCAN_SUCCESS (1 << 0) 465 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 466 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 467 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 468 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 469 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 470 471 /* PCIe fabric error handling severity return flags */ 472 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 473 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 474 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 475 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 476 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 477 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 478 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 479 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 480 #define PF_ERR_BAD_RESPONSE (1 << 8) /* Device bad/no response */ 481 #define PF_ERR_MATCH_DOM (1 << 9) /* Error Handled By IO domain */ 482 483 #define PF_ERR_FATAL_FLAGS (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK) 484 485 #define PF_HDL_FOUND 1 486 #define PF_HDL_NOTFOUND 2 487 488 /* 489 * PCIe Capability Device Type Pseudo Definitions. 490 * 491 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 492 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 493 * Space access is usually frowned upon now in PCIe, but there for legacy 494 * purposes. 495 */ 496 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 497 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 498 499 #define PCIE_INVALID_BDF 0xFFFF 500 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 501 502 typedef struct { 503 dev_info_t *dip; 504 int highest_common_mps; 505 } pcie_max_supported_t; 506 507 /* 508 * Default interrupt priority for all PCI and PCIe nexus drivers including 509 * hotplug interrupts. 510 */ 511 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 512 513 /* 514 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 515 * for non-standard PCI or PCI Express Hotplug Controllers. 516 */ 517 #define PCIE_ENABLE_ERRORS(dip) \ 518 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 519 pcie_enable_errors(dip); \ 520 (void) pcie_enable_ce(dip); \ 521 } 522 523 #define PCIE_DISABLE_ERRORS(dip) \ 524 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 525 pcie_disable_errors(dip); \ 526 } 527 528 /* 529 * pcie_init_buspcie_fini_bus specific flags 530 */ 531 #define PCIE_BUS_INITIAL 0x0001 532 #define PCIE_BUS_FINAL 0x0002 533 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL) 534 535 #ifdef DEBUG 536 #define PCIE_DBG pcie_dbg 537 /* Common Debugging shortcuts */ 538 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 539 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 540 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 541 PCIE_GET(sz, bus_p, off)) 542 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 543 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 544 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 545 PCIE_CAP_GET(sz, bus_p, off)) 546 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 547 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 548 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 549 PCIE_AER_GET(sz, bus_p, off)) 550 551 #else /* DEBUG */ 552 553 #define PCIE_DBG_CFG(...) (void)(0) 554 #define PCIE_DBG(...) (void)(0) 555 #define PCIE_ARI_DBG(...) (void)(0) 556 #define PCIE_DBG_CAP(...) (void)(0) 557 #define PCIE_DBG_AER(...) (void)(0) 558 559 #endif /* DEBUG */ 560 561 /* PCIe Friendly Functions */ 562 extern int pcie_init(dev_info_t *dip, caddr_t arg); 563 extern int pcie_uninit(dev_info_t *dip); 564 extern int pcie_hpintr_enable(dev_info_t *dip); 565 extern int pcie_hpintr_disable(dev_info_t *dip); 566 extern int pcie_intr(dev_info_t *dip); 567 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 568 cred_t *credp); 569 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 570 cred_t *credp); 571 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 572 int mode, cred_t *credp, int *rvalp); 573 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 574 int flags, char *name, caddr_t valuep, int *lengthp); 575 576 extern void pcie_init_root_port_mps(dev_info_t *dip); 577 extern int pcie_initchild(dev_info_t *dip); 578 extern void pcie_uninitchild(dev_info_t *dip); 579 extern int pcie_init_cfghdl(dev_info_t *dip); 580 extern void pcie_fini_cfghdl(dev_info_t *dip); 581 extern void pcie_clear_errors(dev_info_t *dip); 582 extern int pcie_postattach_child(dev_info_t *dip); 583 extern void pcie_enable_errors(dev_info_t *dip); 584 extern void pcie_disable_errors(dev_info_t *dip); 585 extern int pcie_enable_ce(dev_info_t *dip); 586 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 587 extern boolean_t pcie_is_pci_device(dev_info_t *dip); 588 589 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, 590 uint8_t flags); 591 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags); 592 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags); 593 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags); 594 extern void pcie_rc_init_bus(dev_info_t *dip); 595 extern void pcie_rc_fini_bus(dev_info_t *dip); 596 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 597 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 598 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 599 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 600 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 601 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 602 extern int pcie_dev(dev_info_t *dip); 603 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, 604 int *max_supported); 605 extern int pcie_root_port(dev_info_t *dip); 606 extern int pcie_initchild_mps(dev_info_t *dip); 607 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 608 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 609 610 extern uint32_t pcie_get_aer_uce_mask(); 611 extern uint32_t pcie_get_aer_ce_mask(); 612 extern uint32_t pcie_get_aer_suce_mask(); 613 extern uint32_t pcie_get_serr_mask(); 614 extern void pcie_set_aer_uce_mask(uint32_t mask); 615 extern void pcie_set_aer_ce_mask(uint32_t mask); 616 extern void pcie_set_aer_suce_mask(uint32_t mask); 617 extern void pcie_set_serr_mask(uint32_t mask); 618 extern void pcie_init_plat(dev_info_t *dip); 619 extern void pcie_fini_plat(dev_info_t *dip); 620 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 621 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 622 extern int pcie_ari_disable(dev_info_t *dip); 623 extern int pcie_ari_enable(dev_info_t *dip); 624 625 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 626 #define PCIE_ARI_FORW_SUPPORTED 1 627 628 extern int pcie_ari_supported(dev_info_t *dip); 629 630 #define PCIE_ARI_FORW_DISABLED 0 631 #define PCIE_ARI_FORW_ENABLED 1 632 633 extern int pcie_ari_is_enabled(dev_info_t *dip); 634 635 #define PCIE_NOT_ARI_DEVICE 0 636 #define PCIE_ARI_DEVICE 1 637 638 extern int pcie_ari_device(dev_info_t *dip); 639 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 640 641 /* PCIe error handling functions */ 642 extern void pf_eh_enter(pcie_bus_t *bus_p); 643 extern void pf_eh_exit(pcie_bus_t *bus_p); 644 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 645 pf_data_t *root_pfd_p); 646 extern void pf_set_passthru(dev_info_t *, boolean_t); 647 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 648 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 649 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 650 pcie_req_id_t); 651 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 652 extern void pcie_force_fullscan(); 653 654 #ifdef DEBUG 655 extern uint_t pcie_debug_flags; 656 extern void pcie_dbg(char *fmt, ...); 657 #endif /* DEBUG */ 658 659 /* PCIe IOV functions */ 660 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf); 661 662 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t); 663 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t); 664 extern int pf_pci_decode(pf_data_t *, uint16_t *); 665 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t); 666 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t); 667 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *); 668 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *); 669 670 extern int pciev_eh(pf_data_t *, pf_impl_t *); 671 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *, 672 uint16_t, uint16_t); 673 extern void pciev_eh_exit(pf_data_t *, uint_t); 674 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t); 675 676 /* Link Bandwidth Monitoring */ 677 extern boolean_t pcie_link_bw_supported(dev_info_t *); 678 extern int pcie_link_bw_enable(dev_info_t *); 679 extern int pcie_link_bw_disable(dev_info_t *); 680 681 /* Link Management */ 682 extern int pcie_link_set_target(dev_info_t *, pcie_link_speed_t); 683 extern int pcie_link_retrain(dev_info_t *); 684 685 #define PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP) 686 687 688 #ifdef __cplusplus 689 } 690 #endif 691 692 #endif /* _SYS_PCIE_IMPL_H */ 693