1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * Copyright 2018 Joyent, Inc. 25 * Copyright 2024 Oxide Computer Company 26 */ 27 28 #ifndef _SYS_PCI_IMPL_H 29 #define _SYS_PCI_IMPL_H 30 31 #include <sys/dditypes.h> 32 #include <sys/memlist.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined(__i386) || defined(__amd64) 39 40 /* 41 * There are two ways to access the PCI configuration space on X86 42 * Access method 2 is the older method 43 * Access method 1 is the newer method and is preferred because 44 * of the problems in trying to lock the configuration space 45 * for MP machines using method 2. See PCI Local BUS Specification 46 * Revision 2.0 section 3.6.4.1 for more details. 47 * 48 * In addition, on IBM Sandalfoot and a few related machines there's 49 * still another mechanism. See PReP 1.1 section 6.1.7. 50 */ 51 52 #define PCI_MECHANISM_UNKNOWN -1 53 #define PCI_MECHANISM_NONE 0 54 #if defined(__i386) || defined(__amd64) 55 #define PCI_MECHANISM_1 1 56 #define PCI_MECHANISM_2 2 57 #else 58 #error "Unknown processor type" 59 #endif 60 61 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 66 #ifndef TRUE 67 #define TRUE 1 68 #endif 69 70 #define PCI_FUNC_MASK 0x07 71 72 /* these macros apply to Configuration Mechanism #1 */ 73 #define PCI_CONFADD 0xcf8 74 #define PCI_PMC 0xcfb 75 #define PCI_CONFDATA 0xcfc 76 #define PCI_CONE 0x80000000 77 #define PCI_CADDR1(bus, device, function, reg) \ 78 (PCI_CONE | (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \ 79 | (((function) & 0x7) << 8) | ((reg) & 0xfc)) 80 81 /* these macros apply to Configuration Mechanism #2 */ 82 #define PCI_CSE_PORT 0xcf8 83 #define PCI_FORW_PORT 0xcfa 84 #define PCI_CADDR2(device, indx) \ 85 (0xc000 | (((device) & 0xf) << 8) | (indx)) 86 87 typedef struct pci_acc_cfblk { 88 uchar_t c_busnum; /* bus number */ 89 uchar_t c_devnum; /* device number */ 90 uchar_t c_funcnum; /* function number */ 91 uchar_t c_fill; /* reserve field */ 92 } pci_acc_cfblk_t; 93 94 struct pci_bus_resource { 95 struct memlist *io_avail; /* available free io res */ 96 struct memlist *io_used; /* used io res */ 97 struct memlist *mem_avail; /* available free mem res */ 98 struct memlist *mem_used; /* used mem res */ 99 struct memlist *pmem_avail; /* available free prefetchable mem res */ 100 struct memlist *pmem_used; /* used prefetchable mem res */ 101 struct memlist *bus_avail; /* available free bus res */ 102 /* bus_space_used not needed; can read from regs */ 103 dev_info_t *dip; /* devinfo node */ 104 void *privdata; /* private data for configuration */ 105 uchar_t par_bus; /* parent bus number */ 106 uchar_t sub_bus; /* highest bus number beyond this bridge */ 107 uchar_t root_addr; /* legacy peer bus address assignment */ 108 uchar_t num_cbb; /* # of CardBus Bridges on the bus */ 109 uchar_t num_bridge; /* number of bridges under this bus */ 110 boolean_t io_reprogram; /* need io reprog on this bus */ 111 boolean_t mem_reprogram; /* need mem reprog on this bus */ 112 boolean_t subtractive; /* subtractive PPB */ 113 uint64_t mem_size; /* existing children required MEM space size */ 114 uint64_t pmem_size; /* existing children required PMEM space size */ 115 uint64_t mem_buffer; /* memory available for proactively */ 116 /* allocating to bridges for hotplug */ 117 uint_t io_size; /* existing children required I/O space size */ 118 }; 119 120 extern struct pci_bus_resource *pci_bus_res; 121 122 extern struct memlist *pci_memlist_alloc(void); 123 extern void pci_memlist_free(struct memlist *); 124 extern void pci_memlist_free_all(struct memlist **); 125 extern void pci_memlist_insert(struct memlist **, uint64_t, uint64_t); 126 extern int pci_memlist_remove(struct memlist **, uint64_t, uint64_t); 127 extern uint64_t pci_memlist_find(struct memlist **, uint64_t, int); 128 extern uint64_t pci_memlist_find_with_startaddr(struct memlist **, uint64_t, 129 uint64_t, int); 130 extern void pci_memlist_dump(struct memlist *); 131 extern void pci_memlist_subsume(struct memlist **, struct memlist **); 132 extern void pci_memlist_merge(struct memlist **, struct memlist **); 133 extern struct memlist *pci_memlist_dup(struct memlist *); 134 extern int pci_memlist_count(struct memlist *); 135 136 #endif /* __i386 || __amd64 */ 137 138 /* Definitions for minor numbers */ 139 #define PCI_MINOR_NUM(x, y) (((uint_t)(x) << 8) | ((y) & 0xFF)) 140 #define PCI_MINOR_NUM_TO_PCI_DEVNUM(x) ((x) & 0xFF) 141 #define PCI_MINOR_NUM_TO_INSTANCE(x) ((x) >> 8) 142 #define PCI_DEVCTL_MINOR 0xFF 143 144 /* 145 * Minor numbers for dedicated pcitool nodes. 146 * Note that FF and FE minor numbers are used for other minor nodes. 147 */ 148 #define PCI_TOOL_REG_MINOR_NUM 0xFD 149 #define PCI_TOOL_INTR_MINOR_NUM 0xFC 150 151 /* pci devctl soft state flag */ 152 #define PCI_SOFT_STATE_CLOSED 0x0 153 #define PCI_SOFT_STATE_OPEN 0x1 154 #define PCI_SOFT_STATE_OPEN_EXCL 0x2 155 156 /* 157 * PCI capability related definitions. 158 */ 159 160 /* 161 * Minimum number of dwords to be saved. 162 */ 163 #define PCI_MSI_MIN_WORDS 3 164 #define PCI_PCIX_MIN_WORDS 2 165 #define PCI_PCIE_MIN_WORDS 5 166 167 /* 168 * Total number of dwords to be saved. 169 */ 170 #define PCI_PMCAP_NDWORDS 2 171 #define PCI_AGP_NDWORDS 3 172 #define PCI_SLOTID_NDWORDS 1 173 #define PCI_MSIX_NDWORDS 3 174 #define PCI_CAP_SZUNKNOWN 0 175 176 #define PCI_HTCAP_SLPRI_NDWORDS 7 177 #define PCI_HTCAP_HOSTSEC_NDWORDS 6 178 #define PCI_HTCAP_INTCONF_NDWORDS 2 179 #define PCI_HTCAP_REVID_NDWORDS 1 180 #define PCI_HTCAP_UNITID_CLUMP_NDWORDS 3 181 #define PCI_HTCAP_ECFG_NDWORDS 3 182 #define PCI_HTCAP_ADDRMAP_NDWORDS PCI_CAP_SZUNKNOWN /* variable */ 183 #define PCI_HTCAP_MSIMAP_NDWORDS 3 184 #define PCI_HTCAP_DIRROUTE_NDWORDS 3 185 #define PCI_HTCAP_VCSET_NDWORDS 3 186 #define PCI_HTCAP_RETRYMODE_NDWORDS 3 187 #define PCI_HTCAP_GEN3_NDWORDS 10 188 #define PCI_HTCAP_FUNCEXT_NDWORDS PCI_CAP_SZUNKNOWN /* variable */ 189 #define PCI_HTCAP_PM_NDWORDS 2 190 191 192 #define CAP_ID(confhdl, cap_ptr, xspace) \ 193 ((xspace) ? 0 : pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_ID)) 194 195 #define NEXT_CAP(confhdl, cap_ptr, xspace) \ 196 ((xspace) ? 0 : \ 197 pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_NEXT_PTR)) 198 199 extern int pci_resource_setup(dev_info_t *); 200 extern void pci_resource_destroy(dev_info_t *); 201 202 #ifdef __cplusplus 203 } 204 #endif 205 206 #endif /* _SYS_PCI_IMPL_H */ 207