1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_H 27 #define _SYS_PCI_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * PCI Configuration Header offsets 37 */ 38 #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 39 #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 40 #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 41 #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 42 #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 43 #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 44 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 45 #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 46 #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 47 #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ 48 #define PCI_CONF_HEADER 0xE /* header type, 1 byte */ 49 #define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */ 50 51 /* 52 * Header type 0 offsets 53 */ 54 #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ 55 #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ 56 #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ 57 #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ 58 #define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */ 59 #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ 60 #define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */ 61 #define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */ 62 #define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */ 63 #define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */ 64 #define PCI_CONF_CAP_PTR 0x34 /* capabilities pointer, 1 byte */ 65 #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */ 66 #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */ 67 #define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */ 68 #define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */ 69 70 /* 71 * PCI to PCI bridge configuration space header format 72 */ 73 #define PCI_BCNF_PRIBUS 0x18 /* primary bus number */ 74 #define PCI_BCNF_SECBUS 0x19 /* secondary bus number */ 75 #define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */ 76 #define PCI_BCNF_LATENCY_TIMER 0x1b 77 #define PCI_BCNF_IO_BASE_LOW 0x1c 78 #define PCI_BCNF_IO_LIMIT_LOW 0x1d 79 #define PCI_BCNF_SEC_STATUS 0x1e 80 #define PCI_BCNF_MEM_BASE 0x20 81 #define PCI_BCNF_MEM_LIMIT 0x22 82 #define PCI_BCNF_PF_BASE_LOW 0x24 83 #define PCI_BCNF_PF_LIMIT_LOW 0x26 84 #define PCI_BCNF_PF_BASE_HIGH 0x28 85 #define PCI_BCNF_PF_LIMIT_HIGH 0x2c 86 #define PCI_BCNF_IO_BASE_HI 0x30 87 #define PCI_BCNF_IO_LIMIT_HI 0x32 88 #define PCI_BCNF_CAP_PTR 0x34 89 #define PCI_BCNF_ROM 0x38 90 #define PCI_BCNF_ILINE 0x3c 91 #define PCI_BCNF_IPIN 0x3d 92 #define PCI_BCNF_BCNTRL 0x3e 93 94 #define PCI_BCNF_BASE_NUM 0x2 95 96 /* 97 * PCI to PCI bridge control register (0x3e) format 98 */ 99 #define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1 100 #define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2 101 #define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20 102 #define PCI_BCNF_BCNTRL_DTO_STAT 0x400 103 104 #define PCI_BCNF_BCNTRL_RESET 0x0040 105 #define PCI_BCNF_BCNTRL_B2B_ENAB 0x0080 106 107 #define PCI_BCNF_IO_MASK 0xf0 108 #define PCI_BCNF_MEM_MASK 0xfff0 109 110 /* 111 * Header type 2 (Cardbus) offsets 112 */ 113 #define PCI_CBUS_SOCK_REG 0x10 /* Cardbus socket regs, 4 bytes */ 114 #define PCI_CBUS_RESERVED1 0x14 /* Reserved, 2 bytes */ 115 #define PCI_CBUS_SEC_STATUS 0x16 /* Secondary status, 2 bytes */ 116 #define PCI_CBUS_PCI_BUS_NO 0x18 /* PCI bus number, 1 byte */ 117 #define PCI_CBUS_CBUS_NO 0x19 /* Cardbus bus number, 1 byte */ 118 #define PCI_CBUS_SUB_BUS_NO 0x1a /* Subordinate bus number, 1 byte */ 119 #define PCI_CBUS_LATENCY_TIMER 0x1b /* Cardbus latency timer, 1 byte */ 120 #define PCI_CBUS_MEM_BASE0 0x1c /* Memory base reg 0, 4 bytes */ 121 #define PCI_CBUS_MEM_LIMIT0 0x20 /* Memory limit reg 0, 4 bytes */ 122 #define PCI_CBUS_MEM_BASE1 0x24 /* Memory base reg 1, 4 bytes */ 123 #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ 124 #define PCI_CBUS_IO_BASE0 0x2c /* IO base reg 0, 4 bytes */ 125 #define PCI_CBUS_IO_LIMIT0 0x30 /* IO limit reg 0, 4 bytes */ 126 #define PCI_CBUS_IO_BASE1 0x34 /* IO base reg 1, 4 bytes */ 127 #define PCI_CBUS_IO_LIMIT1 0x38 /* IO limit reg 1, 4 bytes */ 128 #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */ 129 #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */ 130 #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 131 #define PCI_CBUS_SUBVENID 0x40 /* Subsystem Vendor ID, 2 bytes */ 132 #define PCI_CBUS_SUBSYSID 0x42 /* Subsystem ID, 2 bytes */ 133 #define PCI_CBUS_LEG_MODE_ADDR 0x44 /* PCCard 16bit IF legacy mode addr */ 134 135 #define PCI_CBUS_BASE_NUM 0x1 /* number of base registers */ 136 137 /* 138 * PCI command register bits 139 */ 140 #define PCI_COMM_IO 0x1 /* I/O access enable */ 141 #define PCI_COMM_MAE 0x2 /* memory access enable */ 142 #define PCI_COMM_ME 0x4 /* master enable */ 143 #define PCI_COMM_SPEC_CYC 0x8 144 #define PCI_COMM_MEMWR_INVAL 0x10 145 #define PCI_COMM_PALETTE_SNOOP 0x20 146 #define PCI_COMM_PARITY_DETECT 0x40 147 #define PCI_COMM_WAIT_CYC_ENAB 0x80 148 #define PCI_COMM_SERR_ENABLE 0x100 149 #define PCI_COMM_BACK2BACK_ENAB 0x200 150 #define PCI_COMM_INTX_DISABLE 0x400 /* INTx emulation disable */ 151 152 /* 153 * PCI Interrupt pin value 154 */ 155 #define PCI_INTA 1 156 #define PCI_INTB 2 157 #define PCI_INTC 3 158 #define PCI_INTD 4 159 160 /* 161 * PCI status register bits 162 */ 163 #define PCI_STAT_INTR 0x8 /* Interrupt state */ 164 #define PCI_STAT_CAP 0x10 /* Implements Capabilities */ 165 #define PCI_STAT_66MHZ 0x20 /* 66 MHz capable */ 166 #define PCI_STAT_UDF 0x40 /* UDF supported */ 167 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */ 168 #define PCI_STAT_S_PERROR 0x100 /* Data Parity Reported */ 169 #define PCI_STAT_DEVSELT 0x600 /* Device select timing */ 170 #define PCI_STAT_S_TARG_AB 0x800 /* Signaled Target Abort */ 171 #define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */ 172 #define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */ 173 #define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */ 174 #define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */ 175 176 /* 177 * DEVSEL timing values 178 */ 179 #define PCI_STAT_DEVSELT_FAST 0x0000 180 #define PCI_STAT_DEVSELT_MEDIUM 0x0200 181 #define PCI_STAT_DEVSELT_SLOW 0x0400 182 183 /* 184 * BIST values 185 */ 186 #define PCI_BIST_SUPPORTED 0x80 187 #define PCI_BIST_GO 0x40 188 #define PCI_BIST_RESULT_M 0x0f 189 #define PCI_BIST_RESULT_OK 0x00 190 191 /* 192 * PCI class codes 193 */ 194 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */ 195 #define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */ 196 #define PCI_CLASS_NET 0x2 /* Network Controller class */ 197 #define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */ 198 #define PCI_CLASS_MM 0x4 /* Multimedia Controller class */ 199 #define PCI_CLASS_MEM 0x5 /* Memory Controller class */ 200 #define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */ 201 #define PCI_CLASS_COMM 0x7 /* Communications Controller class */ 202 #define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */ 203 #define PCI_CLASS_INPUT 0x9 /* Input Device class */ 204 #define PCI_CLASS_DOCK 0xa /* Docking Station class */ 205 #define PCI_CLASS_PROCESSOR 0xb /* Processor class */ 206 #define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */ 207 #define PCI_CLASS_WIRELESS 0xd /* Wireless Controller class */ 208 #define PCI_CLASS_INTIO 0xe /* Intelligent IO Controller class */ 209 #define PCI_CLASS_SATELLITE 0xf /* Satellite Communication class */ 210 #define PCI_CLASS_CRYPT 0x10 /* Encrytion/Decryption class */ 211 #define PCI_CLASS_SIGNAL 0x11 /* Signal Processing class */ 212 213 /* 214 * PCI Sub-class codes - base class 0x0 (no new devices should use this code). 215 */ 216 #define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */ 217 #define PCI_NONE_VGA 0x1 /* VGA compatible */ 218 219 /* 220 * PCI Sub-class codes - base class 0x1 (mass storage controllers) 221 */ 222 #define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */ 223 #define PCI_MASS_IDE 0x1 /* IDE Controller */ 224 #define PCI_MASS_FD 0x2 /* floppy disk Controller */ 225 #define PCI_MASS_IPI 0x3 /* IPI bus Controller */ 226 #define PCI_MASS_RAID 0x4 /* RAID Controller */ 227 #define PCI_MASS_ATA 0x5 /* ATA Controller */ 228 #define PCI_MASS_SATA 0x6 /* Serial ATA */ 229 #define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */ 230 231 /* 232 * programming interface for IDE (subclass 1) 233 */ 234 #define PCI_IDE_IF_NATIVE_PRI 0x1 /* primary channel is native */ 235 #define PCI_IDE_IF_PROG_PRI 0x2 /* primary can operate in either mode */ 236 #define PCI_IDE_IF_NATIVE_SEC 0x4 /* secondary channel is native */ 237 #define PCI_IDE_IF_PROG_SEC 0x8 /* sec. can operate in either mode */ 238 #define PCI_IDE_IF_MASK 0xf /* programming interface mask */ 239 240 241 /* 242 * programming interface for ATA (subclass 5) 243 */ 244 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */ 245 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */ 246 247 /* 248 * PCI Sub-class codes - base class 0x2 (Network controllers) 249 */ 250 #define PCI_NET_ENET 0x0 /* Ethernet Controller */ 251 #define PCI_NET_TOKEN 0x1 /* Token Ring Controller */ 252 #define PCI_NET_FDDI 0x2 /* FDDI Controller */ 253 #define PCI_NET_ATM 0x3 /* ATM Controller */ 254 #define PCI_NET_ISDN 0x4 /* ISDN Controller */ 255 #define PCI_NET_WFIP 0x5 /* WorldFip Controller */ 256 #define PCI_NET_PICMG 0x6 /* PICMG 2.14 Multi Computing */ 257 #define PCI_NET_OTHER 0x80 /* Other Network Controller */ 258 259 /* 260 * PCI Sub-class codes - base class 03 (display controllers) 261 */ 262 #define PCI_DISPLAY_VGA 0x0 /* VGA device */ 263 #define PCI_DISPLAY_XGA 0x1 /* XGA device */ 264 #define PCI_DISPLAY_3D 0x2 /* 3D controller */ 265 #define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */ 266 267 /* 268 * programming interface for display for display class (subclass 0) VGA ctrlrs 269 */ 270 #define PCI_DISPLAY_IF_VGA 0x0 /* VGA compatible */ 271 #define PCI_DISPLAY_IF_8514 0x1 /* 8514 compatible */ 272 273 /* 274 * PCI Sub-class codes - base class 0x4 (multi-media devices) 275 */ 276 #define PCI_MM_VIDEO 0x0 /* Video device */ 277 #define PCI_MM_AUDIO 0x1 /* Audio device */ 278 #define PCI_MM_TELEPHONY 0x2 /* Computer Telephony device */ 279 #define PCI_MM_OTHER 0x80 /* Other Multimedia Device */ 280 281 /* 282 * PCI Sub-class codes - base class 0x5 (memory controllers) 283 */ 284 #define PCI_MEM_RAM 0x0 /* RAM device */ 285 #define PCI_MEM_FLASH 0x1 /* FLASH device */ 286 #define PCI_MEM_OTHER 0x80 /* Other Memory Controller */ 287 288 /* 289 * PCI Sub-class codes - base class 0x6 (Bridge devices) 290 */ 291 #define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */ 292 #define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */ 293 #define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */ 294 #define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */ 295 #define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */ 296 #define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */ 297 #define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */ 298 #define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */ 299 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */ 300 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */ 301 #define PCI_BRIDGE_IB 0xA /* InfiniBand/PCI host Bridge */ 302 #define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */ 303 304 /* 305 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge 306 */ 307 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */ 308 #define PCI_BRIDGE_PCI_IF_SUBDECODE 0x1 /* Subtractive Decode */ 309 /* PCI/PCI bridge */ 310 311 /* 312 * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge 313 */ 314 #define PCI_BRIDGE_RACE_IF_TRANSPARENT 0x0 /* Transport mode */ 315 #define PCI_BRIDGE_RACE_IF_ENDPOINT 0x1 /* Endpoint mode */ 316 317 /* 318 * programming interface for Bridges class 0x6 (subclass 09) 319 * Semi-transparent PCI-to-PCI bridge 320 */ 321 #define PCI_BRIDGE_STPCI_IF_PRIMARY 0x40 /* primary PCI side bus */ 322 /* facing system processor */ 323 #define PCI_BRIDGE_STPCI_IF_SECONDARY 0x80 /* secondary PCI side bus */ 324 /* facing system processor */ 325 326 /* 327 * PCI Sub-class codes - base class 0x7 (communication devices) 328 */ 329 #define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */ 330 #define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */ 331 #define PCI_COMM_MSC 0x2 /* Multiport Serial Controller */ 332 #define PCI_COMM_MODEM 0x3 /* Modem Controller */ 333 #define PCI_COMM_GPIB 0x4 /* GPIB Controller */ 334 #define PCI_COMM_SMARTCARD 0x5 /* Smart Card Controller */ 335 #define PCI_COMM_OTHER 0x80 /* Other Communications Controller */ 336 337 /* 338 * Programming interfaces for class 0x7 / subclass 0x0 (Serial) 339 */ 340 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */ 341 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */ 342 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */ 343 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */ 344 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */ 345 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */ 346 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */ 347 348 /* 349 * Programming interfaces for class 0x7 / subclass 0x1 (Parallel) 350 */ 351 #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */ 352 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */ 353 #define PCI_COMM_PARALLEL_IF_ECP 0x2 /* ECP 1.X Parallel port */ 354 #define PCI_COMM_PARALLEL_IF_1284 0x3 /* IEEE 1284 Parallel port */ 355 #define PCI_COMM_PARALLEL_IF_1284_TARG 0xFE /* IEEE 1284 target device */ 356 357 /* 358 * Programming interfaces for class 0x7 / subclass 0x3 (Modem) 359 */ 360 #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */ 361 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */ 362 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */ 363 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */ 364 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */ 365 366 /* 367 * PCI Sub-class codes - base class 0x8 368 */ 369 #define PCI_PERIPH_PIC 0x0 /* Generic PIC */ 370 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */ 371 #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */ 372 #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */ 373 #define PCI_PERIPH_HPC 0x3 /* Generic PCI Hot-Plug Controller */ 374 #define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */ 375 376 /* 377 * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller) 378 */ 379 #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */ 380 #define PCI_PERIPH_PIC_IF_ISA 0x1 /* ISA PIC */ 381 #define PCI_PERIPH_PIC_IF_EISA 0x2 /* EISA PIC */ 382 #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */ 383 #define PCI_PERIPH_PIC_IF_IOX_APIC 0x20 /* I/O(x) APIC intr ctrlr */ 384 385 /* 386 * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller) 387 */ 388 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */ 389 #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */ 390 #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */ 391 392 /* 393 * Programming interfaces for class 0x8 / subclass 0x2 (timer) 394 */ 395 #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */ 396 #define PCI_PERIPH_TIMER_IF_ISA 0x1 /* ISA system timers */ 397 #define PCI_PERIPH_TIMER_IF_EISA 0x2 /* EISA system timers (two) */ 398 399 /* 400 * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock) 401 */ 402 #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */ 403 #define PCI_PERIPH_RTC_IF_ISA 0x1 /* ISA RTC controller */ 404 405 /* 406 * PCI Sub-class codes - base class 0x9 407 */ 408 #define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controller */ 409 #define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */ 410 #define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */ 411 #define PCI_INPUT_SCANNER 0x3 /* Scanner Controller */ 412 #define PCI_INPUT_GAMEPORT 0x4 /* Gameport Controller */ 413 #define PCI_INPUT_OTHER 0x80 /* Other Input Controller */ 414 415 /* 416 * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller) 417 */ 418 #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */ 419 #define PCI_INPUT_GAMEPORT_IF_LEGACY 0x10 /* Legacy controller */ 420 421 /* 422 * PCI Sub-class codes - base class 0xa 423 */ 424 #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */ 425 #define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */ 426 427 /* 428 * PCI Sub-class codes - base class 0xb 429 */ 430 #define PCI_PROCESSOR_386 0x0 /* 386 */ 431 #define PCI_PROCESSOR_486 0x1 /* 486 */ 432 #define PCI_PROCESSOR_PENT 0x2 /* Pentium */ 433 #define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */ 434 #define PCI_PROCESSOR_POWERPC 0x20 /* PowerPC */ 435 #define PCI_PROCESSOR_MIPS 0x30 /* MIPS */ 436 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */ 437 438 /* 439 * PCI Sub-class codes - base class 0xc (Serial Controllers) 440 */ 441 #define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */ 442 #define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */ 443 #define PCI_SERIAL_SSA 0x2 /* SSA */ 444 #define PCI_SERIAL_USB 0x3 /* Universal Serial Bus */ 445 #define PCI_SERIAL_FIBRE 0x4 /* Fibre Channel */ 446 #define PCI_SERIAL_SMBUS 0x5 /* System Management Bus */ 447 #define PCI_SERIAL_IB 0x6 /* InfiniBand */ 448 #define PCI_SERIAL_IPMI 0x7 /* IPMI */ 449 #define PCI_SERIAL_SERCOS 0x8 /* SERCOS Interface Std (IEC 61491) */ 450 #define PCI_SERIAL_CANBUS 0x9 /* CANbus */ 451 452 /* 453 * Programming interfaces for class 0xC / subclass 0x3 (USB controller) 454 */ 455 #define PCI_SERIAL_USB_IF_UHCI 0x00 /* UHCI Compliant */ 456 #define PCI_SERIAL_USB_IF_OHCI 0x10 /* OHCI Compliant */ 457 #define PCI_SERIAL_USB_IF_EHCI 0x20 /* EHCI Compliant */ 458 #define PCI_SERIAL_USB_IF_GENERIC 0x80 /* no specific HCD */ 459 #define PCI_SERIAL_USB_IF_DEVICE 0xFE /* not a HCD */ 460 461 /* 462 * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller) 463 */ 464 #define PCI_SERIAL_IPMI_IF_SMIC 0x0 /* SMIC Interface */ 465 #define PCI_SERIAL_IPMI_IF_KBD 0x1 /* Keyboard Ctrl Style Intfc */ 466 #define PCI_SERIAL_IPMI_IF_BTI 0x2 /* Block Transfer Interface */ 467 468 /* 469 * PCI Sub-class codes - base class 0xd (Wireless controllers) 470 */ 471 #define PCI_WIRELESS_IRDA 0x0 /* iRDA Compatible Controller */ 472 #define PCI_WIRELESS_IR 0x1 /* Consumer IR Controller */ 473 #define PCI_WIRELESS_RF 0x10 /* RF Controller */ 474 #define PCI_WIRELESS_BLUETOOTH 0x11 /* Bluetooth Controller */ 475 #define PCI_WIRELESS_BROADBAND 0x12 /* Broadband Controller */ 476 #define PCI_WIRELESS_80211A 0x20 /* Ethernet 802.11a 5 GHz */ 477 #define PCI_WIRELESS_80211B 0x21 /* Ethernet 802.11b 2.4 GHz */ 478 #define PCI_WIRELESS_OTHER 0x80 /* Other Wireless Controllers */ 479 480 /* 481 * PCI Sub-class codes - base class 0xe (Intelligent I/O controllers) 482 */ 483 #define PCI_INTIO_I20 0x1 /* I20 Arch Spec 1.0 */ 484 485 /* 486 * PCI Sub-class codes - base class 0xf (Satellite Communication controllers) 487 */ 488 #define PCI_SATELLITE_COMM_TV 0x01 /* TV */ 489 #define PCI_SATELLITE_COMM_AUDIO 0x02 /* Audio */ 490 #define PCI_SATELLITE_COMM_VOICE 0x03 /* Voice */ 491 #define PCI_SATELLITE_COMM_DATA 0x04 /* DATA */ 492 493 /* 494 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers) 495 */ 496 #define PCI_CRYPT_NETWORK 0x00 /* Network and Computing */ 497 #define PCI_CRYPT_ENTERTAINMENT 0x10 /* Entertainment en/decrypt */ 498 #define PCI_CRYPT_OTHER 0x80 /* Other en/decryption ctrlrs */ 499 500 /* 501 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers) 502 */ 503 #define PCI_SIGNAL_DPIO 0x00 /* DPIO modules */ 504 #define PCI_SIGNAL_PERF_COUNTERS 0x01 /* Performance counters */ 505 #define PCI_SIGNAL_COMM_SYNC 0x10 /* Comm. synchronization plus */ 506 /* time and freq test ctrlr */ 507 #define PCI_SIGNAL_MANAGEMENT 0x20 /* Management card */ 508 #define PCI_SIGNAL_OTHER 0x80 /* DSP/DAP controller */ 509 510 /* PCI header decode */ 511 #define PCI_HEADER_MULTI 0x80 /* multi-function device */ 512 #define PCI_HEADER_ZERO 0x00 /* type zero PCI header */ 513 #define PCI_HEADER_ONE 0x01 /* type one PCI header */ 514 #define PCI_HEADER_TWO 0x02 /* type two PCI header */ 515 #define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */ 516 #define PCI_HEADER_CARDBUS PCI_HEADER_TWO /* type one PCI header */ 517 518 #define PCI_HEADER_TYPE_M 0x7f /* type mask for header */ 519 520 /* 521 * Base register bit definitions. 522 */ 523 #define PCI_BASE_SPACE_M 0x1 /* memory space indicator */ 524 #define PCI_BASE_SPACE_IO 0x1 /* IO space */ 525 #define PCI_BASE_SPACE_MEM 0x0 /* memory space */ 526 527 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */ 528 #define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */ 529 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */ 530 #define PCI_BASE_TYPE_RES 0x6 /* reserved */ 531 532 #define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */ 533 #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */ 534 #define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */ 535 #define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */ 536 537 #define PCI_BASE_ROM_ADDR_M 0xfffff800 /* ROM address mask */ 538 #define PCI_BASE_ROM_ENABLE 0x00000001 /* ROM decoder enable */ 539 540 /* 541 * Capabilities linked list entry offsets 542 */ 543 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 544 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 545 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 546 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 547 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 548 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 549 550 /* 551 * Capability identifier values 552 */ 553 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 554 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 555 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 556 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 557 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 558 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 559 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 560 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 561 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 562 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 563 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 564 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug supported */ 565 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 566 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 567 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 568 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 569 570 /* 571 * Capability next entry pointer values 572 */ 573 #define PCI_CAP_NEXT_PTR_NULL 0x0 /* no more entries in the list */ 574 575 /* 576 * PCI power management (PM) capability entry offsets 577 */ 578 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 579 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 580 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 581 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 582 583 /* 584 * PM capabilities values - 2 bytes 585 */ 586 #define PCI_PMCAP_VER_1_0 0x1 /* PCI PM spec 1.0 */ 587 #define PCI_PMCAP_VER_1_1 0x2 /* PCI PM spec 1.1 */ 588 #define PCI_PMCAP_VER_MASK 0x7 /* version mask */ 589 #define PCI_PMCAP_PME_CLOCK 0x8 /* needs PCI clock for PME */ 590 #define PCI_PMCAP_DSI 0x20 /* needs device specific init */ 591 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */ 592 #define PCI_PMCAP_AUX_CUR_55mA 0x40 /* 55 mA aux current */ 593 #define PCI_PMCAP_AUX_CUR_100mA 0x80 /* 100 mA aux current */ 594 #define PCI_PMCAP_AUX_CUR_160mA 0xc0 /* 160 mA aux current */ 595 #define PCI_PMCAP_AUX_CUR_220mA 0x100 /* 220 mA aux current */ 596 #define PCI_PMCAP_AUX_CUR_270mA 0x140 /* 270 mA aux current */ 597 #define PCI_PMCAP_AUX_CUR_320mA 0x180 /* 320 mA aux current */ 598 #define PCI_PMCAP_AUX_CUR_375mA 0x1c0 /* 375 mA aux current */ 599 #define PCI_PMCAP_AUX_CUR_MASK 0x1c0 /* 3.3Vaux aux current needs */ 600 #define PCI_PMCAP_D1 0x200 /* D1 state supported */ 601 #define PCI_PMCAP_D2 0x400 /* D2 state supported */ 602 #define PCI_PMCAP_D0_PME 0x800 /* PME from D0 */ 603 #define PCI_PMCAP_D1_PME 0x1000 /* PME from D1 */ 604 #define PCI_PMCAP_D2_PME 0x2000 /* PME from D2 */ 605 #define PCI_PMCAP_D3HOT_PME 0x4000 /* PME from D3hot */ 606 #define PCI_PMCAP_D3COLD_PME 0x8000 /* PME from D3cold */ 607 #define PCI_PMCAP_PME_MASK 0xf800 /* PME support mask */ 608 609 /* 610 * PM control/status values - 2 bytes 611 */ 612 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 613 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 614 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 615 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 616 #define PCI_PMCSR_STATE_MASK 0x3 /* power state mask */ 617 #define PCI_PMCSR_PME_EN 0x100 /* enable PME assertion */ 618 #define PCI_PMCSR_DSEL_D0_PWR_C 0x0 /* D0 power consumed */ 619 #define PCI_PMCSR_DSEL_D1_PWR_C 0x200 /* D1 power consumed */ 620 #define PCI_PMCSR_DSEL_D2_PWR_C 0x400 /* D2 power consumed */ 621 #define PCI_PMCSR_DSEL_D3_PWR_C 0x600 /* D3 power consumed */ 622 #define PCI_PMCSR_DSEL_D0_PWR_D 0x800 /* D0 power dissipated */ 623 #define PCI_PMCSR_DSEL_D1_PWR_D 0xa00 /* D1 power dissipated */ 624 #define PCI_PMCSR_DSEL_D2_PWR_D 0xc00 /* D2 power dissipated */ 625 #define PCI_PMCSR_DSEL_D3_PWR_D 0xe00 /* D3 power dissipated */ 626 #define PCI_PMCSR_DSEL_COM_C 0x1000 /* common power consumption */ 627 #define PCI_PMCSR_DSEL_MASK 0x1e00 /* data select mask */ 628 #define PCI_PMCSR_DSCL_UNKNOWN 0x0 /* data scale unknown */ 629 #define PCI_PMCSR_DSCL_1_BY_10 0x2000 /* data scale 0.1x */ 630 #define PCI_PMCSR_DSCL_1_BY_100 0x4000 /* data scale 0.01x */ 631 #define PCI_PMCSR_DSCL_1_BY_1000 0x6000 /* data scale 0.001x */ 632 #define PCI_PMCSR_DSCL_MASK 0x6000 /* data scale mask */ 633 #define PCI_PMCSR_PME_STAT 0x8000 /* PME status */ 634 635 /* 636 * PM PMCSR PCI to PCI bridge support extension values - 1 byte 637 */ 638 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */ 639 #define PCI_PMCSR_BSE_BPCC_EN 0x80 /* bus power/clock control enabled */ 640 641 /* 642 * PCI-X capability related definitions 643 */ 644 #define PCI_PCIX_COMMAND 0x2 /* Command register offset */ 645 #define PCI_PCIX_STATUS 0x4 /* Status register offset */ 646 #define PCI_PCIX_ECC_STATUS 0x8 /* ECC Status register offset */ 647 #define PCI_PCIX_ECC_FST_AD 0xC /* ECC First address register offset */ 648 #define PCI_PCIX_ECC_SEC_AD 0x10 /* ECC Second address register offset */ 649 #define PCI_PCIX_ECC_ATTR 0x14 /* ECC Attribute register offset */ 650 651 /* 652 * PCI-X bridge capability related definitions 653 */ 654 #define PCI_PCIX_SEC_STATUS 0x2 /* Secondary status register offset */ 655 #define PCI_PCIX_BDG_STATUS 0x4 /* Bridge Status register offset */ 656 #define PCI_PCIX_UP_SPL_CTL 0x8 /* Upstream split ctrl reg offset */ 657 #define PCI_PCIX_DOWN_SPL_CTL 0xC /* Downstream split ctrl reg offset */ 658 #define PCI_PCIX_BDG_ECC_STATUS 0x10 /* ECC Status register offset */ 659 #define PCI_PCIX_BDG_ECC_FST_AD 0x14 /* ECC First address register offset */ 660 #define PCI_PCIX_BDG_ECC_SEC_AD 0x18 /* ECC Second address register offset */ 661 #define PCI_PCIX_BDG_ECC_ATTR 0x1C /* ECC Attribute register offset */ 662 663 /* 664 * PCIX capabilities values 665 */ 666 #define PCI_PCIX_VER_MASK 0x3000 /* Bits 12 and 13 */ 667 #define PCI_PCIX_VER_0 0x0000 /* PCIX cap list item version 0 */ 668 #define PCI_PCIX_VER_1 0x1000 /* PCIX cap list item version 1 */ 669 #define PCI_PCIX_VER_2 0x2000 /* PCIX cap list item version 2 */ 670 671 #define PCI_PCIX_SPL_DSCD 0x40000 /* Split Completion Discarded */ 672 #define PCI_PCIX_UNEX_SPL 0x80000 /* Unexpected Split Completion */ 673 #define PCI_PCIX_RX_SPL_MSG 0x20000000 /* Recieved Spl Comp Error Message */ 674 675 #define PCI_PCIX_ECC_SEL 0x1 /* Secondary ECC register select */ 676 #define PCI_PCIX_ECC_EP 0x2 /* Error Present on other side */ 677 #define PCI_PCIX_ECC_S_CE 0x4 /* Addl Correctable ECC Error */ 678 #define PCI_PCIX_ECC_S_UE 0x8 /* Addl Uncorrectable ECC Error */ 679 #define PCI_PCIX_ECC_PHASE 0x70 /* ECC Error Phase */ 680 #define PCI_PCIX_ECC_CORR 0x80 /* ECC Error Corrected */ 681 #define PCI_PCIX_ECC_SYN 0xff00 /* ECC Error Syndrome */ 682 #define PCI_PCIX_ECC_FST_CMD 0xf0000 /* ECC Error First Command */ 683 #define PCI_PCIX_ECC_SEC_CMD 0xf00000 /* ECC Error Second Command */ 684 #define PCI_PCIX_ECC_UP_ATTR 0xf000000 /* ECC Error Upper Attributes */ 685 686 /* 687 * PCIX ECC Phase Values 688 */ 689 #define PCI_PCIX_ECC_PHASE_NOERR 0x0 690 #define PCI_PCIX_ECC_PHASE_FADDR 0x1 691 #define PCI_PCIX_ECC_PHASE_SADDR 0x2 692 #define PCI_PCIX_ECC_PHASE_ATTR 0x3 693 #define PCI_PCIX_ECC_PHASE_DATA32 0x4 694 #define PCI_PCIX_ECC_PHASE_DATA64 0x5 695 696 /* 697 * PCI-X Command Encoding 698 */ 699 #define PCI_PCIX_CMD_INTR 0x0 700 #define PCI_PCIX_CMD_SPEC 0x1 701 #define PCI_PCIX_CMD_IORD 0x2 702 #define PCI_PCIX_CMD_IOWR 0x3 703 #define PCI_PCIX_CMD_DEVID 0x5 704 #define PCI_PCIX_CMD_MEMRD_DW 0x6 705 #define PCI_PCIX_CMD_MEMWR 0x7 706 #define PCI_PCIX_CMD_MEMRD_BL 0x8 707 #define PCI_PCIX_CMD_MEMWR_BL 0x9 708 #define PCI_PCIX_CMD_CFRD 0xA 709 #define PCI_PCIX_CMD_CFWR 0xB 710 #define PCI_PCIX_CMD_SPL 0xC 711 #define PCI_PCIX_CMD_DADR 0xD 712 #define PCI_PCIX_CMD_MEMRDBL 0xE 713 #define PCI_PCIX_CMD_MEMWRBL 0xF 714 715 #if defined(_BIT_FIELDS_LTOH) 716 typedef struct pcix_attr { 717 uint32_t lbc :8, 718 rid :16, 719 tag :5, 720 ro :1, 721 ns :1, 722 r :1; 723 } pcix_attr_t; 724 #elif defined(_BIT_FIELDS_HTOL) 725 typedef struct pcix_attr { 726 uint32_t r :1, 727 ns :1, 728 ro :1, 729 tag :5, 730 rid :16, 731 lbc :8; 732 } pcix_attr_t; 733 #else 734 #error "bit field not defined" 735 #endif 736 737 #define PCI_PCIX_BSS_SPL_DSCD 0x4 /* Secondary split comp discarded */ 738 #define PCI_PCIX_BSS_UNEX_SPL 0x8 /* Secondary unexpected split comp */ 739 #define PCI_PCIX_BSS_SPL_OR 0x10 /* Secondary split comp overrun */ 740 #define PCI_PCIX_BSS_SPL_DLY 0x20 /* Secondary split comp delayed */ 741 742 /* 743 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit 744 */ 745 #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */ 746 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */ 747 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */ 748 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */ 749 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */ 750 751 /* 752 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit 753 */ 754 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */ 755 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */ 756 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */ 757 758 /* 759 * PCI Message Signalled Interrupts (MSI) capability masks and shifts 760 */ 761 #define PCI_MSI_ENABLE_BIT 0x0001 /* MSI enable mask in MSI ctrl reg */ 762 #define PCI_MSI_MMC_MASK 0x000E /* MMC mask in MSI ctrl reg */ 763 #define PCI_MSI_MMC_SHIFT 0x1 /* Shift for MMC bits */ 764 #define PCI_MSI_MME_MASK 0x0070 /* MME mask in MSI ctrl reg */ 765 #define PCI_MSI_MME_SHIFT 0x4 /* Shift for MME bits */ 766 #define PCI_MSI_64BIT_MASK 0x0080 /* 64bit support mask in MSI ctrl reg */ 767 #define PCI_MSI_PVM_MASK 0x0100 /* PVM support mask in MSI ctrl reg */ 768 769 /* 770 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets 771 */ 772 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */ 773 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */ 774 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */ 775 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */ 776 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */ 777 778 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */ 779 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */ 780 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */ 781 782 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */ 783 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */ 784 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */ 785 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */ 786 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */ 787 788 /* 789 * PCI Message Signalled Interrupts: other interesting constants 790 */ 791 #define PCI_MSI_MAX_INTRS 32 /* maximum MSI interrupts supported */ 792 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */ 793 794 /* 795 * PCI Slot Id Capabilities, 2 bytes 796 */ 797 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */ 798 #define PCI_CAPSLOT_ESR_NSLOTS_MASK 0x1F /* Number of slots mask */ 799 #define PCI_CAPSLOT_ESR_FIC 0x20 /* First In Chassis bit */ 800 #define PCI_CAPSLOT_ESR_FIC_MASK 0x01 /* First In Chassis mask */ 801 #define PCI_CAPSLOT_ESR_FIC_SHIFT 5 /* First In Chassis shift */ 802 #define PCI_CAPSLOT_FIC(esr_reg) ((esr_reg) & PCI_CAPSLOT_ESR_FIC) 803 #define PCI_CAPSLOT_NSLOTS(esr_reg) ((esr_reg) & \ 804 PCI_CAPSLOT_ESR_NSLOTS_MASK) 805 806 /* 807 * other interesting PCI constants 808 */ 809 #define PCI_BASE_NUM 6 /* num of base regs in configuration header */ 810 #define PCI_BAR_SZ_32 4 /* size of 32 bit base addr reg in bytes */ 811 #define PCI_BAR_SZ_64 8 /* size of 64 bit base addr reg in bytes */ 812 #define PCI_BASE_SIZE 4 /* size of base reg in bytes */ 813 #define PCI_CONF_HDR_SIZE 256 /* configuration header size */ 814 #define PCI_MAX_BUS_NUM 256 /* Maximum PCI buses allowed */ 815 #define PCI_MAX_DEVICES 32 /* Max PCI devices allowed */ 816 #define PCI_MAX_FUNCTIONS 8 /* Max PCI functions allowed */ 817 #define PCI_MAX_CHILDREN PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS 818 #define PCI_CLK_33MHZ (33 * 1000 * 1000) /* 33MHz clock speed */ 819 #define PCI_CLK_66MHZ (66 * 1000 * 1000) /* 66MHz clock speed */ 820 #define PCI_CLK_133MHZ (133 * 1000 * 1000) /* 133MHz clock speed */ 821 822 /* 823 * pci bus range definition 824 */ 825 typedef struct pci_bus_range { 826 uint32_t lo; 827 uint32_t hi; 828 } pci_bus_range_t; 829 830 /* 831 * The following typedef is used to represent an entry in the "ranges" 832 * property of a pci hostbridge device node. 833 */ 834 typedef struct pci_ranges { 835 uint32_t child_high; 836 uint32_t child_mid; 837 uint32_t child_low; 838 uint32_t parent_high; 839 uint32_t parent_low; 840 uint32_t size_high; 841 uint32_t size_low; 842 } pci_ranges_t; 843 844 /* 845 * The following typedef is used to represent an entry in the "ranges" 846 * property of a pci-pci bridge device node. 847 */ 848 typedef struct { 849 uint32_t child_high; 850 uint32_t child_mid; 851 uint32_t child_low; 852 uint32_t parent_high; 853 uint32_t parent_mid; 854 uint32_t parent_low; 855 uint32_t size_high; 856 uint32_t size_low; 857 } ppb_ranges_t; 858 859 /* 860 * This structure represents one entry of the 1275 "reg" property and 861 * "assigned-addresses" property for a PCI node. For the "reg" property, it 862 * may be one of an arbitrary length array for devices with multiple address 863 * windows. For the "assigned-addresses" property, it denotes an assigned 864 * physical address on the PCI bus. It may be one entry of the six entries 865 * for devices with multiple base registers. 866 * 867 * The physical address format is: 868 * 869 * Bit#: 33222222 22221111 11111100 00000000 870 * 10987654 32109876 54321098 76543210 871 * 872 * pci_phys_hi cell: np0000tt bbbbbbbb dddddfff rrrrrrrr 873 * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 874 * pci_phys_low cell: llllllll llllllll llllllll llllllll 875 * 876 * n is 0 if the address is relocatable, 1 otherwise 877 * p is 1 if the addressable region is "prefetchable", 0 otherwise 878 * t is 1 if the address range is aliased 879 * tt is the type code, denoting which address space 880 * bbbbbbbb is the 8-bit bus number 881 * ddddd is the 5-bit device number 882 * fff is the 3-bit function number 883 * rrrrrrrr is the 8-bit register number 884 * hh...hhh is the 32-bit unsigned number 885 * ll...lll is the 32-bit unsigned number 886 * 887 * The physical size format is: 888 * 889 * pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 890 * pci_size_low cell: llllllll llllllll llllllll llllllll 891 * 892 * hh...hhh is the 32-bit unsigned number 893 * ll...lll is the 32-bit unsigned number 894 */ 895 struct pci_phys_spec { 896 uint_t pci_phys_hi; /* child's address, hi word */ 897 uint_t pci_phys_mid; /* child's address, middle word */ 898 uint_t pci_phys_low; /* child's address, low word */ 899 uint_t pci_size_hi; /* high word of size field */ 900 uint_t pci_size_low; /* low word of size field */ 901 }; 902 903 typedef struct pci_phys_spec pci_regspec_t; 904 905 /* 906 * PCI masks for pci_phy_hi of PCI 1275 address cell. 907 */ 908 #define PCI_REG_REG_M 0xff /* register mask */ 909 #define PCI_REG_FUNC_M 0x700 /* function mask */ 910 #define PCI_REG_DEV_M 0xf800 /* device mask */ 911 #define PCI_REG_BUS_M 0xff0000 /* bus number mask */ 912 #define PCI_REG_ADDR_M 0x3000000 /* address space mask */ 913 #define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */ 914 #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */ 915 #define PCI_REG_REL_M 0x80000000 /* relocation bit mask */ 916 #define PCI_REG_BDFR_M 0xffffff /* bus, dev, func, reg mask */ 917 918 #define PCI_REG_FUNC_SHIFT 8 /* Offset of function bits */ 919 #define PCI_REG_DEV_SHIFT 11 /* Offset of device bits */ 920 #define PCI_REG_BUS_SHIFT 16 /* Offset of bus bits */ 921 #define PCI_REG_ADDR_SHIFT 24 /* Offset of address bits */ 922 923 #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) 924 #define PCI_REG_FUNC_G(x) (((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT) 925 #define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT) 926 #define PCI_REG_BUS_G(x) (((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT) 927 #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) 928 #define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M) 929 930 /* 931 * PCI bit encodings of pci_phys_hi of PCI 1275 address cell. 932 */ 933 #define PCI_ADDR_MASK PCI_REG_ADDR_M 934 #define PCI_ADDR_CONFIG 0x00000000 /* configuration address */ 935 #define PCI_ADDR_IO 0x01000000 /* I/O address */ 936 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */ 937 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */ 938 #define PCI_ALIAS_B PCI_REG_ALIAS_M /* aliased bit */ 939 #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */ 940 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */ 941 #define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */ 942 943 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */ 944 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */ 945 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */ 946 #define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */ 947 #define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */ 948 949 /* 950 * PCI Expansion ROM Header Format 951 */ 952 #define PCI_ROM_SIGNATURE 0x0 /* ROM Signature 0xaa55 */ 953 #define PCI_ROM_ARCH_UNIQUE_START 0x2 /* Start of processor unique */ 954 #define PCI_ROM_PCI_DATA_STRUCT_PTR 0x18 /* Ptr to PCI Data Structure */ 955 956 /* 957 * PCI Data Structure 958 * 959 * The PCI Data Structure is located within the first 64KB 960 * of the ROM image and must be DWORD aligned. 961 */ 962 #define PCI_PDS_SIGNATURE 0x0 /* Signature, the string 'PCIR' */ 963 #define PCI_PDS_VENDOR_ID 0x4 /* Vendor Identification */ 964 #define PCI_PDS_DEVICE_ID 0x6 /* Device Identification */ 965 #define PCI_PDS_VPD_PTR 0x8 /* Pointer to Vital Product Data */ 966 #define PCI_PDS_PDS_LENGTH 0xa /* PCI Data Structure Length */ 967 #define PCI_PDS_PDS_REVISION 0xc /* PCI Data Structure Revision */ 968 #define PCI_PDS_CLASS_CODE 0xd /* Class Code */ 969 #define PCI_PDS_IMAGE_LENGTH 0x10 /* Image Length in 512 byte units */ 970 #define PCI_PDS_CODE_REVISON 0x12 /* Revision Level of Code/Data */ 971 #define PCI_PDS_CODE_TYPE 0x14 /* Code Type */ 972 #define PCI_PDS_INDICATOR 0x15 /* Indicates if image is last in ROM */ 973 974 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */ 975 #define PCI_PDS_CODE_TYPE_OPEN_FW 0x1 /* Open Firmware */ 976 977 #ifdef __cplusplus 978 } 979 #endif 980 981 #endif /* _SYS_PCI_H */ 982