1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * Copyright 2019, Joyent, Inc. 25 * Copyright 2025 Oxide Computer Company 26 */ 27 28 #ifndef _SYS_PCI_H 29 #define _SYS_PCI_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/stdint.h> 36 #include <sys/types.h> 37 38 /* 39 * PCI Configuration Header offsets 40 */ 41 #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 42 #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 43 #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 44 #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 45 #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 46 #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 47 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 48 #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 49 #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 50 #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ 51 #define PCI_CONF_HEADER 0xE /* header type, 1 byte */ 52 #define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */ 53 54 /* 55 * Header type 0 offsets 56 */ 57 #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ 58 #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ 59 #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ 60 #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ 61 #define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */ 62 #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ 63 #define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */ 64 #define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */ 65 #define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */ 66 #define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */ 67 #define PCI_CONF_CAP_PTR 0x34 /* capabilities pointer, 1 byte */ 68 #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */ 69 #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */ 70 #define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */ 71 #define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */ 72 73 /* 74 * PCI to PCI bridge configuration space header format 75 */ 76 #define PCI_BCNF_PRIBUS 0x18 /* primary bus number */ 77 #define PCI_BCNF_SECBUS 0x19 /* secondary bus number */ 78 #define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */ 79 #define PCI_BCNF_LATENCY_TIMER 0x1b 80 #define PCI_BCNF_IO_BASE_LOW 0x1c 81 #define PCI_BCNF_IO_LIMIT_LOW 0x1d 82 #define PCI_BCNF_SEC_STATUS 0x1e 83 #define PCI_BCNF_MEM_BASE 0x20 84 #define PCI_BCNF_MEM_LIMIT 0x22 85 #define PCI_BCNF_PF_BASE_LOW 0x24 86 #define PCI_BCNF_PF_LIMIT_LOW 0x26 87 #define PCI_BCNF_PF_BASE_HIGH 0x28 88 #define PCI_BCNF_PF_LIMIT_HIGH 0x2c 89 #define PCI_BCNF_IO_BASE_HI 0x30 90 #define PCI_BCNF_IO_LIMIT_HI 0x32 91 #define PCI_BCNF_CAP_PTR 0x34 92 #define PCI_BCNF_ROM 0x38 93 #define PCI_BCNF_ILINE 0x3c 94 #define PCI_BCNF_IPIN 0x3d 95 #define PCI_BCNF_BCNTRL 0x3e 96 97 #define PCI_BCNF_BASE_NUM 0x2 98 99 /* 100 * PCI to PCI bridge control register (0x3e) format 101 */ 102 #define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1 103 #define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2 104 #define PCI_BCNF_BCNTRL_ISA_ENABLE 0x4 105 #define PCI_BCNF_BCNTRL_VGA_ENABLE 0x8 106 #define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20 107 #define PCI_BCNF_BCNTRL_DTO_STAT 0x400 108 109 #define PCI_BCNF_BCNTRL_RESET 0x0040 110 #define PCI_BCNF_BCNTRL_B2B_ENAB 0x0080 111 112 #define PCI_BCNF_IO_MASK 0xf0 113 #define PCI_BCNF_IO_SHIFT 8 114 #define PCI_BCNF_IO_LIMIT_BITS 0xfff 115 #define PCI_BCNF_MEM_MASK 0xfff0 116 #define PCI_BCNF_MEM_SHIFT 16 117 #define PCI_BCNF_MEM_LIMIT_BITS 0xfffff 118 #define PCI_BCNF_ADDR_MASK 0x000f 119 120 #define PCI_BCNF_IO_32BIT 0x01 121 #define PCI_BCNF_PF_MEM_64BIT 0x01 122 123 /* 124 * Header type 2 (Cardbus) offsets 125 */ 126 #define PCI_CBUS_SOCK_REG 0x10 /* Cardbus socket regs, 4 bytes */ 127 #define PCI_CBUS_CAP_PTR 0x14 /* Capability ptr, 1 byte */ 128 #define PCI_CBUS_RESERVED1 0x15 /* Reserved, 1 byte */ 129 #define PCI_CBUS_SEC_STATUS 0x16 /* Secondary status, 2 bytes */ 130 #define PCI_CBUS_PCI_BUS_NO 0x18 /* PCI bus number, 1 byte */ 131 #define PCI_CBUS_CBUS_NO 0x19 /* Cardbus bus number, 1 byte */ 132 #define PCI_CBUS_SUB_BUS_NO 0x1a /* Subordinate bus number, 1 byte */ 133 #define PCI_CBUS_LATENCY_TIMER 0x1b /* Cardbus latency timer, 1 byte */ 134 #define PCI_CBUS_MEM_BASE0 0x1c /* Memory base reg 0, 4 bytes */ 135 #define PCI_CBUS_MEM_LIMIT0 0x20 /* Memory limit reg 0, 4 bytes */ 136 #define PCI_CBUS_MEM_BASE1 0x24 /* Memory base reg 1, 4 bytes */ 137 #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ 138 #define PCI_CBUS_IO_BASE0 0x2c /* IO base reg 0, 4 bytes */ 139 #define PCI_CBUS_IO_LIMIT0 0x30 /* IO limit reg 0, 4 bytes */ 140 #define PCI_CBUS_IO_BASE1 0x34 /* IO base reg 1, 4 bytes */ 141 #define PCI_CBUS_IO_LIMIT1 0x38 /* IO limit reg 1, 4 bytes */ 142 #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */ 143 #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */ 144 #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 145 #define PCI_CBUS_SUBVENID 0x40 /* Subsystem Vendor ID, 2 bytes */ 146 #define PCI_CBUS_SUBSYSID 0x42 /* Subsystem ID, 2 bytes */ 147 #define PCI_CBUS_LEG_MODE_ADDR 0x44 /* PCCard 16bit IF legacy mode addr */ 148 149 #define PCI_CBUS_BASE_NUM 0x1 /* number of base registers */ 150 151 /* 152 * PCI command register bits 153 */ 154 #define PCI_COMM_IO 0x1 /* I/O access enable */ 155 #define PCI_COMM_MAE 0x2 /* memory access enable */ 156 #define PCI_COMM_ME 0x4 /* master enable */ 157 #define PCI_COMM_SPEC_CYC 0x8 158 #define PCI_COMM_MEMWR_INVAL 0x10 159 #define PCI_COMM_PALETTE_SNOOP 0x20 160 #define PCI_COMM_PARITY_DETECT 0x40 161 #define PCI_COMM_WAIT_CYC_ENAB 0x80 162 #define PCI_COMM_SERR_ENABLE 0x100 163 #define PCI_COMM_BACK2BACK_ENAB 0x200 164 #define PCI_COMM_INTX_DISABLE 0x400 /* INTx emulation disable */ 165 166 /* 167 * PCI Interrupt pin value 168 */ 169 #define PCI_INTA 1 170 #define PCI_INTB 2 171 #define PCI_INTC 3 172 #define PCI_INTD 4 173 174 /* 175 * PCI status register bits 176 */ 177 #define PCI_STAT_READY 0x1 /* Immediate Readiness */ 178 #define PCI_STAT_INTR 0x8 /* Interrupt state */ 179 #define PCI_STAT_CAP 0x10 /* Implements Capabilities */ 180 #define PCI_STAT_66MHZ 0x20 /* 66 MHz capable */ 181 #define PCI_STAT_UDF 0x40 /* UDF supported */ 182 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */ 183 #define PCI_STAT_S_PERROR 0x100 /* Data Parity Reported */ 184 #define PCI_STAT_DEVSELT 0x600 /* Device select timing */ 185 #define PCI_STAT_S_TARG_AB 0x800 /* Signaled Target Abort */ 186 #define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */ 187 #define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */ 188 #define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */ 189 #define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */ 190 191 /* 192 * DEVSEL timing values 193 */ 194 #define PCI_STAT_DEVSELT_FAST 0x0000 195 #define PCI_STAT_DEVSELT_MEDIUM 0x0200 196 #define PCI_STAT_DEVSELT_SLOW 0x0400 197 198 /* 199 * BIST values 200 */ 201 #define PCI_BIST_SUPPORTED 0x80 202 #define PCI_BIST_GO 0x40 203 #define PCI_BIST_RESULT_M 0x0f 204 #define PCI_BIST_RESULT_OK 0x00 205 206 /* 207 * PCI class codes 208 */ 209 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */ 210 #define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */ 211 #define PCI_CLASS_NET 0x2 /* Network Controller class */ 212 #define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */ 213 #define PCI_CLASS_MM 0x4 /* Multimedia Controller class */ 214 #define PCI_CLASS_MEM 0x5 /* Memory Controller class */ 215 #define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */ 216 #define PCI_CLASS_COMM 0x7 /* Communications Controller class */ 217 #define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */ 218 #define PCI_CLASS_INPUT 0x9 /* Input Device class */ 219 #define PCI_CLASS_DOCK 0xa /* Docking Station class */ 220 #define PCI_CLASS_PROCESSOR 0xb /* Processor class */ 221 #define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */ 222 #define PCI_CLASS_WIRELESS 0xd /* Wireless Controller class */ 223 #define PCI_CLASS_INTIO 0xe /* Intelligent IO Controller class */ 224 #define PCI_CLASS_SATELLITE 0xf /* Satellite Communication class */ 225 #define PCI_CLASS_CRYPT 0x10 /* Encrytion/Decryption class */ 226 #define PCI_CLASS_SIGNAL 0x11 /* Signal Processing class */ 227 228 /* 229 * PCI Sub-class codes - base class 0x0 (no new devices should use this code). 230 */ 231 #define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */ 232 #define PCI_NONE_VGA 0x1 /* VGA compatible */ 233 234 /* 235 * PCI Sub-class codes - base class 0x1 (mass storage controllers) 236 */ 237 #define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */ 238 #define PCI_MASS_IDE 0x1 /* IDE Controller */ 239 #define PCI_MASS_FD 0x2 /* Floppy disk Controller */ 240 #define PCI_MASS_IPI 0x3 /* IPI bus Controller */ 241 #define PCI_MASS_RAID 0x4 /* RAID Controller */ 242 #define PCI_MASS_ATA 0x5 /* ATA Controller */ 243 #define PCI_MASS_SATA 0x6 /* Serial ATA */ 244 #define PCI_MASS_SAS 0x7 /* Serial Attached SCSI (SAS) Cntrlr */ 245 #define PCI_MASS_NVME 0x8 /* Non-Volatile memory controller */ 246 #define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */ 247 248 /* 249 * programming interface for IDE (subclass 1) 250 */ 251 #define PCI_IDE_IF_NATIVE_PRI 0x1 /* primary channel is native */ 252 #define PCI_IDE_IF_PROG_PRI 0x2 /* primary can operate in either mode */ 253 #define PCI_IDE_IF_NATIVE_SEC 0x4 /* secondary channel is native */ 254 #define PCI_IDE_IF_PROG_SEC 0x8 /* sec. can operate in either mode */ 255 #define PCI_IDE_IF_MASK 0xf /* programming interface mask */ 256 257 258 /* 259 * programming interface for ATA (subclass 5) 260 */ 261 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */ 262 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */ 263 264 /* 265 * programming interface for ATA (subclass 6) for SATA 266 */ 267 #define PCI_SATA_VS_INTERFACE 0x0 /* SATA Ctlr Vendor Specific Intfc */ 268 #define PCI_SATA_AHCI_INTERFACE 0x1 /* SATA Ctlr AHCI 1.0 Interface */ 269 #define PCI_SATA_SSB_INTERFACE 0x2 /* Serial Storage Bus Interface */ 270 271 /* 272 * programming interface for ATA (subclass 7) for SAS 273 */ 274 #define PCI_SAS_CONTROLLER 0x0 /* SAS Controller */ 275 #define PCI_SAS_BUS_INTERFACE 0x1 /* Serial Storage Bus Interface */ 276 277 /* 278 * PCI Sub-class codes - base class 0x2 (Network controllers) 279 */ 280 #define PCI_NET_ENET 0x0 /* Ethernet Controller */ 281 #define PCI_NET_TOKEN 0x1 /* Token Ring Controller */ 282 #define PCI_NET_FDDI 0x2 /* FDDI Controller */ 283 #define PCI_NET_ATM 0x3 /* ATM Controller */ 284 #define PCI_NET_ISDN 0x4 /* ISDN Controller */ 285 #define PCI_NET_WFIP 0x5 /* WorldFip Controller */ 286 #define PCI_NET_PICMG 0x6 /* PICMG 2.14 Multi Computing */ 287 #define PCI_NET_OTHER 0x80 /* Other Network Controller */ 288 289 /* 290 * PCI Sub-class codes - base class 03 (display controllers) 291 */ 292 #define PCI_DISPLAY_VGA 0x0 /* VGA device */ 293 #define PCI_DISPLAY_XGA 0x1 /* XGA device */ 294 #define PCI_DISPLAY_3D 0x2 /* 3D controller */ 295 #define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */ 296 297 /* 298 * programming interface for display for display class (subclass 0) VGA ctrlrs 299 */ 300 #define PCI_DISPLAY_IF_VGA 0x0 /* VGA compatible */ 301 #define PCI_DISPLAY_IF_8514 0x1 /* 8514 compatible */ 302 303 /* 304 * PCI Sub-class codes - base class 0x4 (multi-media devices) 305 */ 306 #define PCI_MM_VIDEO 0x0 /* Video device */ 307 #define PCI_MM_AUDIO 0x1 /* Audio device */ 308 #define PCI_MM_TELEPHONY 0x2 /* Computer Telephony device */ 309 #define PCI_MM_MIXED_MODE 0x3 /* Mixed Mode device */ 310 #define PCI_MM_OTHER 0x80 /* Other Multimedia Device */ 311 312 /* 313 * PCI Sub-class codes - base class 0x5 (memory controllers) 314 */ 315 #define PCI_MEM_RAM 0x0 /* RAM device */ 316 #define PCI_MEM_FLASH 0x1 /* FLASH device */ 317 #define PCI_MEM_OTHER 0x80 /* Other Memory Controller */ 318 319 /* 320 * PCI Sub-class codes - base class 0x6 (Bridge devices) 321 */ 322 #define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */ 323 #define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */ 324 #define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */ 325 #define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */ 326 #define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */ 327 #define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */ 328 #define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */ 329 #define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */ 330 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */ 331 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */ 332 #define PCI_BRIDGE_IB 0xA /* InfiniBand/PCI host Bridge */ 333 #define PCI_BRIDGE_AS 0xB /* AS/PCI host Bridge */ 334 #define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */ 335 336 /* 337 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge 338 */ 339 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */ 340 #define PCI_BRIDGE_PCI_IF_SUBDECODE 0x1 /* Subtractive Decode */ 341 /* PCI/PCI bridge */ 342 343 /* 344 * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge 345 */ 346 #define PCI_BRIDGE_RACE_IF_TRANSPARENT 0x0 /* Transport mode */ 347 #define PCI_BRIDGE_RACE_IF_ENDPOINT 0x1 /* Endpoint mode */ 348 349 /* 350 * programming interface for Bridges class 0x6 (subclass 09) 351 * Semi-transparent PCI-to-PCI bridge 352 */ 353 #define PCI_BRIDGE_STPCI_IF_PRIMARY 0x40 /* primary PCI side bus */ 354 /* facing system processor */ 355 #define PCI_BRIDGE_STPCI_IF_SECONDARY 0x80 /* secondary PCI side bus */ 356 /* facing system processor */ 357 358 /* 359 * programming interface for Bridges class 0x6 (subclass 0B) AS bridge 360 */ 361 #define PCI_BRIDGE_AS_CUSTOM_INTFC 0x0 /* Custom interface */ 362 #define PCI_BRIDGE_AS_PORTAL_INTFC 0x1 /* ASI-SIG Portal Interface */ 363 364 /* 365 * PCI Sub-class codes - base class 0x7 (communication devices) 366 */ 367 #define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */ 368 #define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */ 369 #define PCI_COMM_MSC 0x2 /* Multiport Serial Controller */ 370 #define PCI_COMM_MODEM 0x3 /* Modem Controller */ 371 #define PCI_COMM_GPIB 0x4 /* GPIB Controller */ 372 #define PCI_COMM_SMARTCARD 0x5 /* Smart Card Controller */ 373 #define PCI_COMM_OTHER 0x80 /* Other Communications Controller */ 374 375 /* 376 * Programming interfaces for class 0x7 / subclass 0x0 (Serial) 377 */ 378 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */ 379 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */ 380 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */ 381 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */ 382 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */ 383 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */ 384 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */ 385 386 /* 387 * Programming interfaces for class 0x7 / subclass 0x1 (Parallel) 388 */ 389 #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */ 390 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */ 391 #define PCI_COMM_PARALLEL_IF_ECP 0x2 /* ECP 1.X Parallel port */ 392 #define PCI_COMM_PARALLEL_IF_1284 0x3 /* IEEE 1284 Parallel port */ 393 #define PCI_COMM_PARALLEL_IF_1284_TARG 0xFE /* IEEE 1284 target device */ 394 395 /* 396 * Programming interfaces for class 0x7 / subclass 0x3 (Modem) 397 */ 398 #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */ 399 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */ 400 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */ 401 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */ 402 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */ 403 404 /* 405 * PCI Sub-class codes - base class 0x8 406 */ 407 #define PCI_PERIPH_PIC 0x0 /* Generic PIC */ 408 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */ 409 #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */ 410 #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */ 411 #define PCI_PERIPH_HPC 0x4 /* Generic PCI Hot-Plug Controller */ 412 #define PCI_PERIPH_SD_HC 0x5 /* SD Host Controller */ 413 #define PCI_PERIPH_IOMMU 0x6 /* IOMMU */ 414 #define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */ 415 416 /* 417 * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller) 418 */ 419 #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */ 420 #define PCI_PERIPH_PIC_IF_ISA 0x1 /* ISA PIC */ 421 #define PCI_PERIPH_PIC_IF_EISA 0x2 /* EISA PIC */ 422 #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */ 423 #define PCI_PERIPH_PIC_IF_IOX_APIC 0x20 /* I/O(x) APIC intr ctrlr */ 424 425 /* 426 * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller) 427 */ 428 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */ 429 #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */ 430 #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */ 431 432 /* 433 * Programming interfaces for class 0x8 / subclass 0x2 (timer) 434 */ 435 #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */ 436 #define PCI_PERIPH_TIMER_IF_ISA 0x1 /* ISA system timers */ 437 #define PCI_PERIPH_TIMER_IF_EISA 0x2 /* EISA system timers (two) */ 438 #define PCI_PERIPH_TIMER_IF_HPET 0x3 /* High Perf Event timer */ 439 440 /* 441 * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock) 442 */ 443 #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */ 444 #define PCI_PERIPH_RTC_IF_ISA 0x1 /* ISA RTC controller */ 445 446 /* 447 * PCI Sub-class codes - base class 0x9 448 */ 449 #define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controller */ 450 #define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */ 451 #define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */ 452 #define PCI_INPUT_SCANNER 0x3 /* Scanner Controller */ 453 #define PCI_INPUT_GAMEPORT 0x4 /* Gameport Controller */ 454 #define PCI_INPUT_OTHER 0x80 /* Other Input Controller */ 455 456 /* 457 * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller) 458 */ 459 #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */ 460 #define PCI_INPUT_GAMEPORT_IF_LEGACY 0x10 /* Legacy controller */ 461 462 /* 463 * PCI Sub-class codes - base class 0xA 464 */ 465 #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */ 466 #define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */ 467 468 /* 469 * PCI Sub-class codes - base class 0xB 470 */ 471 #define PCI_PROCESSOR_386 0x0 /* 386 */ 472 #define PCI_PROCESSOR_486 0x1 /* 486 */ 473 #define PCI_PROCESSOR_PENT 0x2 /* Pentium */ 474 #define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */ 475 #define PCI_PROCESSOR_POWERPC 0x20 /* PowerPC */ 476 #define PCI_PROCESSOR_MIPS 0x30 /* MIPS */ 477 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */ 478 #define PCI_PROCESSOR_OTHER 0x80 /* Other processors */ 479 480 /* 481 * PCI Sub-class codes - base class 0xC (Serial Controllers) 482 */ 483 #define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */ 484 #define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */ 485 #define PCI_SERIAL_SSA 0x2 /* SSA */ 486 #define PCI_SERIAL_USB 0x3 /* Universal Serial Bus */ 487 #define PCI_SERIAL_FIBRE 0x4 /* Fibre Channel */ 488 #define PCI_SERIAL_SMBUS 0x5 /* System Management Bus */ 489 #define PCI_SERIAL_IB 0x6 /* InfiniBand */ 490 #define PCI_SERIAL_IPMI 0x7 /* IPMI */ 491 #define PCI_SERIAL_SERCOS 0x8 /* SERCOS Interface Std (IEC 61491) */ 492 #define PCI_SERIAL_CANBUS 0x9 /* CANbus */ 493 #define PCI_SERIAL_OTHER 0x80 /* Other Serial Bus Controllers */ 494 495 /* 496 * Programming interfaces for class 0xC / subclass 0x0 (Firewire) 497 */ 498 #define PCI_SERIAL_FIRE_WIRE 0x00 /* IEEE 1394 (Firewire) */ 499 #define PCI_SERIAL_FIRE_1394_HCI 0x10 /* 1394 OpenHCI Host Cntrlr */ 500 501 /* 502 * Programming interfaces for class 0xC / subclass 0x3 (USB controller) 503 */ 504 #define PCI_SERIAL_USB_IF_UHCI 0x00 /* UHCI Compliant */ 505 #define PCI_SERIAL_USB_IF_OHCI 0x10 /* OHCI Compliant */ 506 #define PCI_SERIAL_USB_IF_EHCI 0x20 /* EHCI Compliant */ 507 #define PCI_SERIAL_USB_IF_GENERIC 0x80 /* no specific HCD */ 508 #define PCI_SERIAL_USB_IF_DEVICE 0xFE /* not a HCD */ 509 510 /* 511 * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller) 512 */ 513 #define PCI_SERIAL_IPMI_IF_SMIC 0x0 /* SMIC Interface */ 514 #define PCI_SERIAL_IPMI_IF_KBD 0x1 /* Keyboard Ctrl Style Intfc */ 515 #define PCI_SERIAL_IPMI_IF_BTI 0x2 /* Block Transfer Interface */ 516 517 /* 518 * PCI Sub-class codes - base class 0xD (Wireless controllers) 519 */ 520 #define PCI_WIRELESS_IRDA 0x0 /* iRDA Compatible Controller */ 521 #define PCI_WIRELESS_IR 0x1 /* Consumer IR Controller */ 522 #define PCI_WIRELESS_RF 0x10 /* RF Controller */ 523 #define PCI_WIRELESS_BLUETOOTH 0x11 /* Bluetooth Controller */ 524 #define PCI_WIRELESS_BROADBAND 0x12 /* Broadband Controller */ 525 #define PCI_WIRELESS_80211A 0x20 /* Ethernet 802.11a 5 GHz */ 526 #define PCI_WIRELESS_80211B 0x21 /* Ethernet 802.11b 2.4 GHz */ 527 #define PCI_WIRELESS_OTHER 0x80 /* Other Wireless Controllers */ 528 529 /* 530 * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller) 531 */ 532 #define PCI_WIRELESS_IR_CONSUMER 0x00 /* Consumer IR Controller */ 533 #define PCI_WIRELESS_IR_UWB_RC 0x10 /* UWB Radio Controller */ 534 535 /* 536 * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers) 537 */ 538 #define PCI_INTIO_MSG_FIFO 0x0 /* Message FIFO at off 40h */ 539 #define PCI_INTIO_I20 0x1 /* I20 Arch Spec 1.0 */ 540 541 /* 542 * PCI Sub-class codes - base class 0xF (Satellite Communication controllers) 543 */ 544 #define PCI_SATELLITE_COMM_TV 0x01 /* TV */ 545 #define PCI_SATELLITE_COMM_AUDIO 0x02 /* Audio */ 546 #define PCI_SATELLITE_COMM_VOICE 0x03 /* Voice */ 547 #define PCI_SATELLITE_COMM_DATA 0x04 /* DATA */ 548 #define PCI_SATELLITE_COMM_OTHER 0x80 /* Other Satelite Comm Cntrlr */ 549 550 /* 551 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers) 552 */ 553 #define PCI_CRYPT_NETWORK 0x00 /* Network and Computing */ 554 #define PCI_CRYPT_ENTERTAINMENT 0x10 /* Entertainment en/decrypt */ 555 #define PCI_CRYPT_OTHER 0x80 /* Other en/decryption ctrlrs */ 556 557 /* 558 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers) 559 */ 560 #define PCI_SIGNAL_DPIO 0x00 /* DPIO modules */ 561 #define PCI_SIGNAL_PERF_COUNTERS 0x01 /* Performance counters */ 562 #define PCI_SIGNAL_COMM_SYNC 0x10 /* Comm. synchronization plus */ 563 /* time and freq test ctrlr */ 564 #define PCI_SIGNAL_MANAGEMENT 0x20 /* Management card */ 565 #define PCI_SIGNAL_OTHER 0x80 /* DSP/DAP controller */ 566 567 /* PCI header decode */ 568 #define PCI_HEADER_MULTI 0x80 /* multi-function device */ 569 #define PCI_HEADER_ZERO 0x00 /* type zero PCI header */ 570 #define PCI_HEADER_ONE 0x01 /* type one PCI header */ 571 #define PCI_HEADER_TWO 0x02 /* type two PCI header */ 572 #define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */ 573 #define PCI_HEADER_CARDBUS PCI_HEADER_TWO /* type one PCI header */ 574 575 #define PCI_HEADER_TYPE_M 0x7f /* type mask for header */ 576 577 /* 578 * Base register bit definitions. 579 */ 580 #define PCI_BASE_SPACE_M 0x1 /* memory space indicator */ 581 #define PCI_BASE_SPACE_IO 0x1 /* IO space */ 582 #define PCI_BASE_SPACE_MEM 0x0 /* memory space */ 583 584 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */ 585 #define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */ 586 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */ 587 #define PCI_BASE_TYPE_RES 0x6 /* reserved */ 588 589 #define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */ 590 #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */ 591 #define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */ 592 #define PCI_BASE_M_ADDR64_M 0xfffffffffffffff0ULL /* 64bit mem addr mask */ 593 #define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */ 594 595 #define PCI_BASE_ROM_ADDR_M 0xfffff800 /* ROM address mask */ 596 #define PCI_BASE_ROM_ENABLE 0x00000001 /* ROM decoder enable */ 597 598 /* 599 * Capabilities linked list entry offsets 600 */ 601 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 602 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 603 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 604 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 605 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 606 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 607 608 /* 609 * Capability identifier values 610 */ 611 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 612 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 613 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 614 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 615 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 616 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 617 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 618 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 619 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 620 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 621 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 622 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug (SHPC) supported */ 623 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */ 624 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 625 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 626 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 627 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 628 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Config supported */ 629 #define PCI_CAP_ID_FLR 0x13 /* Function Level Reset supported */ 630 #define PCI_CAP_ID_EA 0x14 /* Enhanced Allocation */ 631 #define PCI_CAP_ID_FPB 0x15 /* Flattening Portal Bridge */ 632 633 /* 634 * Capability next entry pointer values 635 */ 636 #define PCI_CAP_NEXT_PTR_NULL 0x0 /* no more entries in the list */ 637 638 /* 639 * PCI power management (PM) capability entry offsets 640 */ 641 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 642 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 643 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 644 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 645 646 /* 647 * PM capabilities values - 2 bytes 648 */ 649 #define PCI_PMCAP_VER_1_0 0x1 /* PCI PM spec 1.0 */ 650 #define PCI_PMCAP_VER_1_1 0x2 /* PCI PM spec 1.1 */ 651 #define PCI_PMCAP_VER_MASK 0x7 /* version mask */ 652 #define PCI_PMCAP_PME_CLOCK 0x8 /* needs PCI clock for PME */ 653 #define PCI_PMCAP_DSI 0x20 /* needs device specific init */ 654 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */ 655 #define PCI_PMCAP_AUX_CUR_55mA 0x40 /* 55 mA aux current */ 656 #define PCI_PMCAP_AUX_CUR_100mA 0x80 /* 100 mA aux current */ 657 #define PCI_PMCAP_AUX_CUR_160mA 0xc0 /* 160 mA aux current */ 658 #define PCI_PMCAP_AUX_CUR_220mA 0x100 /* 220 mA aux current */ 659 #define PCI_PMCAP_AUX_CUR_270mA 0x140 /* 270 mA aux current */ 660 #define PCI_PMCAP_AUX_CUR_320mA 0x180 /* 320 mA aux current */ 661 #define PCI_PMCAP_AUX_CUR_375mA 0x1c0 /* 375 mA aux current */ 662 #define PCI_PMCAP_AUX_CUR_MASK 0x1c0 /* 3.3Vaux aux current needs */ 663 #define PCI_PMCAP_D1 0x200 /* D1 state supported */ 664 #define PCI_PMCAP_D2 0x400 /* D2 state supported */ 665 #define PCI_PMCAP_D0_PME 0x800 /* PME from D0 */ 666 #define PCI_PMCAP_D1_PME 0x1000 /* PME from D1 */ 667 #define PCI_PMCAP_D2_PME 0x2000 /* PME from D2 */ 668 #define PCI_PMCAP_D3HOT_PME 0x4000 /* PME from D3hot */ 669 #define PCI_PMCAP_D3COLD_PME 0x8000 /* PME from D3cold */ 670 #define PCI_PMCAP_PME_MASK 0xf800 /* PME support mask */ 671 672 /* 673 * PM control/status values - 2 bytes 674 */ 675 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 676 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 677 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 678 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 679 #define PCI_PMCSR_STATE_MASK 0x3 /* power state mask */ 680 #define PCI_PMCSR_PME_EN 0x100 /* enable PME assertion */ 681 #define PCI_PMCSR_DSEL_D0_PWR_C 0x0 /* D0 power consumed */ 682 #define PCI_PMCSR_DSEL_D1_PWR_C 0x200 /* D1 power consumed */ 683 #define PCI_PMCSR_DSEL_D2_PWR_C 0x400 /* D2 power consumed */ 684 #define PCI_PMCSR_DSEL_D3_PWR_C 0x600 /* D3 power consumed */ 685 #define PCI_PMCSR_DSEL_D0_PWR_D 0x800 /* D0 power dissipated */ 686 #define PCI_PMCSR_DSEL_D1_PWR_D 0xa00 /* D1 power dissipated */ 687 #define PCI_PMCSR_DSEL_D2_PWR_D 0xc00 /* D2 power dissipated */ 688 #define PCI_PMCSR_DSEL_D3_PWR_D 0xe00 /* D3 power dissipated */ 689 #define PCI_PMCSR_DSEL_COM_C 0x1000 /* common power consumption */ 690 #define PCI_PMCSR_DSEL_MASK 0x1e00 /* data select mask */ 691 #define PCI_PMCSR_DSCL_UNKNOWN 0x0 /* data scale unknown */ 692 #define PCI_PMCSR_DSCL_1_BY_10 0x2000 /* data scale 0.1x */ 693 #define PCI_PMCSR_DSCL_1_BY_100 0x4000 /* data scale 0.01x */ 694 #define PCI_PMCSR_DSCL_1_BY_1000 0x6000 /* data scale 0.001x */ 695 #define PCI_PMCSR_DSCL_MASK 0x6000 /* data scale mask */ 696 #define PCI_PMCSR_PME_STAT 0x8000 /* PME status */ 697 698 /* 699 * PM PMCSR PCI to PCI bridge support extension values - 1 byte 700 */ 701 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */ 702 #define PCI_PMCSR_BSE_BPCC_EN 0x80 /* bus power/clock control enabled */ 703 704 /* 705 * PCI-X capability related definitions 706 */ 707 #define PCI_PCIX_COMMAND 0x2 /* Command register offset */ 708 #define PCI_PCIX_STATUS 0x4 /* Status register offset */ 709 #define PCI_PCIX_ECC_STATUS 0x8 /* ECC Status register offset */ 710 #define PCI_PCIX_ECC_FST_AD 0xC /* ECC First address register offset */ 711 #define PCI_PCIX_ECC_SEC_AD 0x10 /* ECC Second address register offset */ 712 #define PCI_PCIX_ECC_ATTR 0x14 /* ECC Attribute register offset */ 713 714 /* 715 * PCI-X bridge capability related definitions 716 */ 717 #define PCI_PCIX_SEC_STATUS 0x2 /* Secondary Status offset */ 718 #define PCI_PCIX_SEC_STATUS_SCD 0x4 /* Split Completion Discarded */ 719 #define PCI_PCIX_SEC_STATUS_USC 0x8 /* Unexpected Split Complete */ 720 #define PCI_PCIX_SEC_STATUS_SCO 0x10 /* Split Completion Overrun */ 721 #define PCI_PCIX_SEC_STATUS_SRD 0x20 /* Split Completion Delayed */ 722 #define PCI_PCIX_SEC_STATUS_ERR_MASK 0x3C 723 724 #define PCI_PCIX_BDG_STATUS 0x4 /* Bridge Status offset */ 725 #define PCI_PCIX_BDG_STATUS_USC 0x80000 726 #define PCI_PCIX_BDG_STATUS_SCO 0x100000 727 #define PCI_PCIX_BDG_STATUS_SRD 0x200000 728 #define PCI_PCIX_BDG_STATUS_ERR_MASK 0x380000 729 730 #define PCI_PCIX_UP_SPL_CTL 0x8 /* Upstream split ctrl reg offset */ 731 #define PCI_PCIX_DOWN_SPL_CTL 0xC /* Downstream split ctrl reg offset */ 732 #define PCI_PCIX_BDG_ECC_STATUS 0x10 /* ECC Status register offset */ 733 #define PCI_PCIX_BDG_ECC_FST_AD 0x14 /* ECC First address register offset */ 734 #define PCI_PCIX_BDG_ECC_SEC_AD 0x18 /* ECC Second address register offset */ 735 #define PCI_PCIX_BDG_ECC_ATTR 0x1C /* ECC Attribute register offset */ 736 737 /* 738 * PCIX capabilities values 739 */ 740 #define PCI_PCIX_VER_MASK 0x3000 /* Bits 12 and 13 */ 741 #define PCI_PCIX_VER_0 0x0000 /* PCIX cap list item version 0 */ 742 #define PCI_PCIX_VER_1 0x1000 /* PCIX cap list item version 1 */ 743 #define PCI_PCIX_VER_2 0x2000 /* PCIX cap list item version 2 */ 744 745 #define PCI_PCIX_SPL_DSCD 0x40000 /* Split Completion Discarded */ 746 #define PCI_PCIX_UNEX_SPL 0x80000 /* Unexpected Split Completion */ 747 #define PCI_PCIX_RX_SPL_MSG 0x20000000 /* Recieved Spl Comp Error Message */ 748 749 #define PCI_PCIX_ECC_SEL 0x1 /* Secondary ECC register select */ 750 #define PCI_PCIX_ECC_EP 0x2 /* Error Present on other side */ 751 #define PCI_PCIX_ECC_S_CE 0x4 /* Addl Correctable ECC Error */ 752 #define PCI_PCIX_ECC_S_UE 0x8 /* Addl Uncorrectable ECC Error */ 753 #define PCI_PCIX_ECC_PHASE 0x70 /* ECC Error Phase */ 754 #define PCI_PCIX_ECC_CORR 0x80 /* ECC Error Corrected */ 755 #define PCI_PCIX_ECC_SYN 0xff00 /* ECC Error Syndrome */ 756 #define PCI_PCIX_ECC_FST_CMD 0xf0000 /* ECC Error First Command */ 757 #define PCI_PCIX_ECC_SEC_CMD 0xf00000 /* ECC Error Second Command */ 758 #define PCI_PCIX_ECC_UP_ATTR 0xf000000 /* ECC Error Upper Attributes */ 759 760 /* 761 * PCIX ECC Phase Values 762 */ 763 #define PCI_PCIX_ECC_PHASE_NOERR 0x0 764 #define PCI_PCIX_ECC_PHASE_FADDR 0x1 765 #define PCI_PCIX_ECC_PHASE_SADDR 0x2 766 #define PCI_PCIX_ECC_PHASE_ATTR 0x3 767 #define PCI_PCIX_ECC_PHASE_DATA32 0x4 768 #define PCI_PCIX_ECC_PHASE_DATA64 0x5 769 770 /* 771 * PCI-X Command Encoding 772 */ 773 #define PCI_PCIX_CMD_INTR 0x0 774 #define PCI_PCIX_CMD_SPEC 0x1 775 #define PCI_PCIX_CMD_IORD 0x2 776 #define PCI_PCIX_CMD_IOWR 0x3 777 #define PCI_PCIX_CMD_DEVID 0x5 778 #define PCI_PCIX_CMD_MEMRD_DW 0x6 779 #define PCI_PCIX_CMD_MEMWR 0x7 780 #define PCI_PCIX_CMD_MEMRD_BL 0x8 781 #define PCI_PCIX_CMD_MEMWR_BL 0x9 782 #define PCI_PCIX_CMD_CFRD 0xA 783 #define PCI_PCIX_CMD_CFWR 0xB 784 #define PCI_PCIX_CMD_SPL 0xC 785 #define PCI_PCIX_CMD_DADR 0xD 786 #define PCI_PCIX_CMD_MEMRDBL 0xE 787 #define PCI_PCIX_CMD_MEMWRBL 0xF 788 789 #if defined(_BIT_FIELDS_LTOH) 790 typedef struct pcix_attr { 791 uint32_t lbc :8, 792 rid :16, 793 tag :5, 794 ro :1, 795 ns :1, 796 r :1; 797 } pcix_attr_t; 798 #elif defined(_BIT_FIELDS_HTOL) 799 typedef struct pcix_attr { 800 uint32_t r :1, 801 ns :1, 802 ro :1, 803 tag :5, 804 rid :16, 805 lbc :8; 806 } pcix_attr_t; 807 #else 808 #error "bit field not defined" 809 #endif 810 811 #define PCI_PCIX_BSS_SPL_DSCD 0x4 /* Secondary split comp discarded */ 812 #define PCI_PCIX_BSS_UNEX_SPL 0x8 /* Secondary unexpected split comp */ 813 #define PCI_PCIX_BSS_SPL_OR 0x10 /* Secondary split comp overrun */ 814 #define PCI_PCIX_BSS_SPL_DLY 0x20 /* Secondary split comp delayed */ 815 816 /* 817 * PCI Hotplug capability entry offsets 818 * 819 * SHPC based PCI hotplug controller registers accessed via the DWORD 820 * select and DATA registers in PCI configuration space relative to the 821 * PCI HP capibility pointer. 822 */ 823 #define PCI_HP_DWORD_SELECT_OFF 0x2 824 #define PCI_HP_DWORD_DATA_OFF 0x4 825 826 #define PCI_HP_BASE_OFFSET_REG 0x00 827 #define PCI_HP_SLOTS_AVAIL_I_REG 0x01 828 #define PCI_HP_SLOTS_AVAIL_II_REG 0x02 829 #define PCI_HP_SLOT_CONFIGURATION_REG 0x03 830 #define PCI_HP_PROF_IF_SBCR_REG 0x04 831 #define PCI_HP_COMMAND_STATUS_REG 0x05 832 #define PCI_HP_IRQ_LOCATOR_REG 0x06 833 #define PCI_HP_SERR_LOCATOR_REG 0x07 834 #define PCI_HP_CTRL_SERR_INT_REG 0x08 835 #define PCI_HP_LOGICAL_SLOT_REGS 0x09 836 #define PCI_HP_VENDOR_SPECIFIC 0x28 837 838 /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */ 839 #define PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT 0 840 #define PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT 8 841 #define PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT 16 842 #define PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT 24 843 #define PCI_HP_AVAIL_SPEED_MASK 0x1F 844 845 /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */ 846 #define PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT 0 847 848 /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */ 849 #define PCI_HP_SBCR_33MHZ_CONV_SPEED 0x0 850 #define PCI_HP_SBCR_66MHZ_CONV_SPEED 0x1 851 #define PCI_HP_SBCR_66MHZ_PCIX_SPEED 0x2 852 #define PCI_HP_SBCR_100MHZ_PCIX_SPEED 0x3 853 #define PCI_HP_SBCR_133MHZ_PCIX_SPEED 0x4 854 #define PCI_HP_SBCR_SPEED_MASK 0x7 855 856 /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */ 857 #define PCI_HP_COMM_STS_ERR_INVALID_SPEED 0x80000 858 #define PCI_HP_COMM_STS_ERR_INVALID_COMMAND 0x40000 859 #define PCI_HP_COMM_STS_ERR_MRL_OPEN 0x20000 860 #define PCI_HP_COMM_STS_ERR_MASK 0xe0000 861 #define PCI_HP_COMM_STS_CTRL_BUSY 0x10000 862 #define PCI_HP_COMM_STS_SET_SPEED 0x40 863 864 /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */ 865 #define PCI_HP_SERR_INT_GLOBAL_IRQ_MASK 0x1 866 #define PCI_HP_SERR_INT_GLOBAL_SERR_MASK 0x2 867 #define PCI_HP_SERR_INT_CMD_COMPLETE_MASK 0x4 868 #define PCI_HP_SERR_INT_ARBITER_SERR_MASK 0x8 869 #define PCI_HP_SERR_INT_CMD_COMPLETE_IRQ 0x10000 870 #define PCI_HP_SERR_INT_ARBITER_IRQ 0x20000 871 #define PCI_HP_SERR_INT_MASK_ALL 0xf 872 873 /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */ 874 #define PCI_HP_SLOT_POWER_ONLY 0x1 875 #define PCI_HP_SLOT_ENABLED 0x2 876 #define PCI_HP_SLOT_DISABLED 0x3 877 #define PCI_HP_SLOT_STATE_MASK 0x3 878 #define PCI_HP_SLOT_MRL_STATE_MASK 0x100 879 #define PCI_HP_SLOT_66MHZ_CONV_CAPABLE 0x200 880 #define PCI_HP_SLOT_CARD_EMPTY_MASK 0xc00 881 #define PCI_HP_SLOT_66MHZ_PCIX_CAPABLE 0x1000 882 #define PCI_HP_SLOT_100MHZ_PCIX_CAPABLE 0x2000 883 #define PCI_HP_SLOT_133MHZ_PCIX_CAPABLE 0x3000 884 #define PCI_HP_SLOT_PCIX_CAPABLE_MASK 0x3000 885 #define PCI_HP_SLOT_PCIX_CAPABLE_SHIFT 12 886 #define PCI_HP_SLOT_PRESENCE_DETECTED 0x10000 887 #define PCI_HP_SLOT_ISO_PWR_DETECTED 0x20000 888 #define PCI_HP_SLOT_ATTN_DETECTED 0x40000 889 #define PCI_HP_SLOT_MRL_DETECTED 0x80000 890 #define PCI_HP_SLOT_POWER_DETECTED 0x100000 891 #define PCI_HP_SLOT_PRESENCE_MASK 0x1000000 892 #define PCI_HP_SLOT_ISO_PWR_MASK 0x2000000 893 #define PCI_HP_SLOT_ATTN_MASK 0x4000000 894 #define PCI_HP_SLOT_MRL_MASK 0x8000000 895 #define PCI_HP_SLOT_POWER_MASK 0x10000000 896 #define PCI_HP_SLOT_MRL_SERR_MASK 0x20000000 897 #define PCI_HP_SLOT_POWER_SERR_MASK 0x40000000 898 #define PCI_HP_SLOT_MASK_ALL 0x5f000000 899 900 /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */ 901 #define PCI_HP_IRQ_CMD_COMPLETE 0x1 902 #define PCI_HP_IRQ_SLOT_N_PENDING 0x2 903 904 /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */ 905 #define PCI_HP_IRQ_SERR_ARBITER_PENDING 0x1 906 #define PCI_HP_IRQ_SERR_SLOT_N_PENDING 0x2 907 908 /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */ 909 #define PCI_HP_SLOT_CONFIG_MRL_SENSOR 0x40000000 910 #define PCI_HP_SLOT_CONFIG_ATTN_BUTTON 0x80000000 911 #define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT 16 912 #define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK 0x3FF 913 914 /* 915 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit 916 */ 917 #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */ 918 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */ 919 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */ 920 #define PCI_MSI_32BIT_EXTDATA 0x0A /* MSI 32-bit msg ext data, 2 bytes */ 921 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */ 922 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */ 923 924 /* 925 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit 926 */ 927 #define PCI_MSI_64BIT_ADDR 0x08 /* MSI 64-bit upper address, 4 bytes */ 928 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */ 929 #define PCI_MSI_64BIT_EXTDATA 0x0E /* MSI 64-bit msg ext data, 2 bytes */ 930 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */ 931 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */ 932 933 /* 934 * PCI Message Signalled Interrupts (MSI) capability masks and shifts 935 */ 936 #define PCI_MSI_ENABLE_BIT 0x0001 /* MSI enable mask in MSI ctrl reg */ 937 #define PCI_MSI_MMC_MASK 0x000E /* MMC mask in MSI ctrl reg */ 938 #define PCI_MSI_MMC_SHIFT 0x1 /* Shift for MMC bits */ 939 #define PCI_MSI_MME_MASK 0x0070 /* MME mask in MSI ctrl reg */ 940 #define PCI_MSI_MME_SHIFT 0x4 /* Shift for MME bits */ 941 #define PCI_MSI_64BIT_MASK 0x0080 /* 64bit support mask in MSI ctrl reg */ 942 #define PCI_MSI_PVM_MASK 0x0100 /* PVM support mask in MSI ctrl reg */ 943 #define PCI_MSI_EMD_MASK 0x0200 /* EMD Capable Mask */ 944 #define PCI_MSI_EMD_ENABLE 0x0400 /* EMD Enable bit */ 945 946 /* 947 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets 948 */ 949 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */ 950 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */ 951 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */ 952 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */ 953 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */ 954 955 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */ 956 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */ 957 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */ 958 959 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */ 960 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */ 961 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */ 962 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */ 963 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */ 964 965 /* 966 * PCI Message Signalled Interrupts: other interesting constants 967 */ 968 #define PCI_MSI_MAX_INTRS 32 /* maximum MSI interrupts supported */ 969 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */ 970 971 /* 972 * PCI Slot Id Capabilities, 2 bytes 973 */ 974 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */ 975 #define PCI_CAPSLOT_ESR_NSLOTS_MASK 0x1F /* Number of slots mask */ 976 #define PCI_CAPSLOT_ESR_FIC 0x20 /* First In Chassis bit */ 977 #define PCI_CAPSLOT_ESR_FIC_MASK 0x01 /* First In Chassis mask */ 978 #define PCI_CAPSLOT_ESR_FIC_SHIFT 5 /* First In Chassis shift */ 979 #define PCI_CAPSLOT_FIC(esr_reg) ((esr_reg) & PCI_CAPSLOT_ESR_FIC) 980 #define PCI_CAPSLOT_NSLOTS(esr_reg) ((esr_reg) & \ 981 PCI_CAPSLOT_ESR_NSLOTS_MASK) 982 983 /* 984 * HyperTransport Capabilities; each HT cap uses the same PCI cap id of 985 * PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT 986 * cap type reg at bits [15:11]. For Slave/Pri Interface and Host/Sec 987 * Interface types, only bits [15:13] are used. 988 */ 989 #define PCI_HTCAP_TYPE_MASK 0xF800 990 #define PCI_HTCAP_TYPE_SLHOST_MASK 0xE000 /* SLPRI and HOSTSEC types */ 991 #define PCI_HTCAP_TYPE_SHIFT 11 992 993 #define PCI_HTCAP_SLPRI_ID 0x00 994 #define PCI_HTCAP_HOSTSEC_ID 0x04 995 #define PCI_HTCAP_SWITCH_ID 0x08 996 #define PCI_HTCAP_INTCONF_ID 0x10 997 #define PCI_HTCAP_REVID_ID 0x11 998 #define PCI_HTCAP_UNITID_CLUMP_ID 0x12 999 #define PCI_HTCAP_ECFG_ID 0x13 1000 #define PCI_HTCAP_ADDRMAP_ID 0x14 1001 #define PCI_HTCAP_MSIMAP_ID 0x15 1002 #define PCI_HTCAP_DIRROUTE_ID 0x16 1003 #define PCI_HTCAP_VCSET_ID 0x17 1004 #define PCI_HTCAP_RETRYMODE_ID 0x18 1005 #define PCI_HTCAP_X86ENC_ID 0x19 1006 #define PCI_HTCAP_GEN3_ID 0x1A 1007 #define PCI_HTCAP_FUNCEXT_ID 0x1B 1008 #define PCI_HTCAP_PM_ID 0x1C 1009 1010 #define PCI_HTCAP_SLPRI_TYPE /* 0x0000 */ \ 1011 (PCI_HTCAP_SLPRI_ID << PCI_HTCAP_TYPE_SHIFT) 1012 1013 #define PCI_HTCAP_HOSTSEC_TYPE /* 0x2000 */ \ 1014 (PCI_HTCAP_HOSTSEC_ID << PCI_HTCAP_TYPE_SHIFT) 1015 1016 #define PCI_HTCAP_SWITCH_TYPE /* 0x4000 */ \ 1017 (PCI_HTCAP_SWITCH_ID << PCI_HTCAP_TYPE_SHIFT) 1018 1019 #define PCI_HTCAP_INTCONF_TYPE /* 0x8000 */ \ 1020 (PCI_HTCAP_INTCONF_ID << PCI_HTCAP_TYPE_SHIFT) 1021 1022 #define PCI_HTCAP_REVID_TYPE /* 0x8800 */ \ 1023 (PCI_HTCAP_REVID_ID << PCI_HTCAP_TYPE_SHIFT) 1024 1025 #define PCI_HTCAP_UNITID_CLUMP_TYPE /* 0x9000 */ \ 1026 (PCI_HTCAP_UNITID_CLUMP_ID << PCI_HTCAP_TYPE_SHIFT) 1027 1028 #define PCI_HTCAP_ECFG_TYPE /* 0x9800 */ \ 1029 (PCI_HTCAP_ECFG_ID << PCI_HTCAP_TYPE_SHIFT) 1030 1031 #define PCI_HTCAP_ADDRMAP_TYPE /* 0xA000 */ \ 1032 (PCI_HTCAP_ADDRMAP_ID << PCI_HTCAP_TYPE_SHIFT) 1033 1034 #define PCI_HTCAP_MSIMAP_TYPE /* 0xA800 */ \ 1035 (PCI_HTCAP_MSIMAP_ID << PCI_HTCAP_TYPE_SHIFT) 1036 1037 #define PCI_HTCAP_DIRROUTE_TYPE /* 0xB000 */ \ 1038 (PCI_HTCAP_DIRROUTE_ID << PCI_HTCAP_TYPE_SHIFT) 1039 1040 #define PCI_HTCAP_VCSET_TYPE /* 0xB800 */ \ 1041 (PCI_HTCAP_VCSET_ID << PCI_HTCAP_TYPE_SHIFT) 1042 1043 #define PCI_HTCAP_RETRYMODE_TYPE /* 0xC000 */ \ 1044 (PCI_HTCAP_RETRYMODE_ID << PCI_HTCAP_TYPE_SHIFT) 1045 1046 #define PCI_HTCAP_X86ENC_TYPE /* 0xC800 */ \ 1047 (PCI_HTCAP_X86ENC_ID << PCI_HTCAP_TYPE_SHIFT) 1048 1049 #define PCI_HTCAP_GEN3_TYPE /* 0xD000 */ \ 1050 (PCI_HTCAP_GEN3_ID << PCI_HTCAP_TYPE_SHIFT) 1051 1052 #define PCI_HTCAP_FUNCEXT_TYPE /* 0xD800 */ \ 1053 (PCI_HTCAP_FUNCEXT_ID << PCI_HTCAP_TYPE_SHIFT) 1054 1055 #define PCI_HTCAP_PM_TYPE /* 0xE000 */ \ 1056 (PCI_HTCAP_PM_ID << PCI_HTCAP_TYPE_SHIFT) 1057 1058 #define PCI_HTCAP_MSIMAP_ENABLE 0x0001 1059 #define PCI_HTCAP_MSIMAP_ENABLE_MASK 0x0001 1060 1061 #define PCI_HTCAP_ADDRMAP_MAPTYPE_MASK 0x600 1062 #define PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT 9 1063 #define PCI_HTCAP_ADDRMAP_NUMMAP_MASK 0xF 1064 #define PCI_HTCAP_ADDRMAP_40BIT_ID 0x0 1065 #define PCI_HTCAP_ADDRMAP_64BIT_ID 0x1 1066 1067 #define PCI_HTCAP_FUNCEXT_LEN_MASK 0xFF 1068 1069 /* 1070 * PCI Bridge Subsystem Capability (PCI_CAP_ID_P2P_SUBSYS) 1071 */ 1072 #define PCI_SUBSYSCAP_SUBVID 0x4 1073 #define PCI_SUBSYSCAP_SUBSYS 0x6 1074 1075 /* 1076 * other interesting PCI constants 1077 */ 1078 #define PCI_BASE_NUM 6 /* num of base regs in configuration header */ 1079 #define PCI_BAR_SZ_32 4 /* size of 32 bit base addr reg in bytes */ 1080 #define PCI_BAR_SZ_64 8 /* size of 64 bit base addr reg in bytes */ 1081 #define PCI_BASE_SIZE 4 /* size of base reg in bytes */ 1082 #define PCI_CONF_HDR_SIZE 256 /* configuration header size */ 1083 #define PCI_MAX_BUS_NUM 256 /* Maximum PCI buses allowed */ 1084 #define PCI_MAX_DEVICES 32 /* Max PCI devices allowed */ 1085 #define PCI_MAX_FUNCTIONS 8 /* Max PCI functions allowed */ 1086 #define PCI_MAX_CHILDREN PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS 1087 #define PCI_CLK_33MHZ (33 * 1000 * 1000) /* 33MHz clock speed */ 1088 #define PCI_CLK_66MHZ (66 * 1000 * 1000) /* 66MHz clock speed */ 1089 #define PCI_CLK_133MHZ (133 * 1000 * 1000) /* 133MHz clock speed */ 1090 1091 /* 1092 * pci bus range definition 1093 */ 1094 typedef struct pci_bus_range { 1095 uint32_t lo; 1096 uint32_t hi; 1097 } pci_bus_range_t; 1098 1099 /* 1100 * The following typedef is used to represent an entry in the "ranges" 1101 * property of a pci hostbridge device node. 1102 */ 1103 typedef struct pci_ranges { 1104 uint32_t child_high; 1105 uint32_t child_mid; 1106 uint32_t child_low; 1107 uint32_t parent_high; 1108 uint32_t parent_low; 1109 uint32_t size_high; 1110 uint32_t size_low; 1111 } pci_ranges_t; 1112 1113 /* 1114 * The following typedef is used to represent an entry in the "ranges" 1115 * property of a pci-pci bridge device node. 1116 */ 1117 typedef struct { 1118 uint32_t child_high; 1119 uint32_t child_mid; 1120 uint32_t child_low; 1121 uint32_t parent_high; 1122 uint32_t parent_mid; 1123 uint32_t parent_low; 1124 uint32_t size_high; 1125 uint32_t size_low; 1126 } ppb_ranges_t; 1127 1128 /* 1129 * This structure represents one entry of the 1275 "reg" property and 1130 * "assigned-addresses" property for a PCI node. For the "reg" property, it 1131 * may be one of an arbitrary length array for devices with multiple address 1132 * windows. For the "assigned-addresses" property, it denotes an assigned 1133 * physical address on the PCI bus. It may be one entry of the six entries 1134 * for devices with multiple base registers. 1135 * 1136 * The physical address format is: 1137 * 1138 * Bit#: 33222222 22221111 11111100 00000000 1139 * 10987654 32109876 54321098 76543210 1140 * 1141 * pci_phys_hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 1142 * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 1143 * pci_phys_low cell: llllllll llllllll llllllll llllllll 1144 * 1145 * n is 0 if the address is relocatable, 1 otherwise 1146 * p is 1 if the addressable region is "prefetchable", 0 otherwise 1147 * t is 1 if the address is aliased (for non-relocatable I/O), below 1148 * 1MB (for mem), or below 64 KB (for relocatable I/O). 1149 * ss is the type code, denoting which address space 1150 * bbbbbbbb is the 8-bit bus number 1151 * ddddd is the 5-bit device number 1152 * fff is the 3-bit function number 1153 * rrrrrrrr is the 8-bit register number 1154 * should be zero for non-relocatable, when ss is 01, or 10 1155 * hh...hhh is the 32-bit unsigned number 1156 * ll...lll is the 32-bit unsigned number 1157 * 1158 * The physical size format is: 1159 * 1160 * pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 1161 * pci_size_low cell: llllllll llllllll llllllll llllllll 1162 * 1163 * hh...hhh is the 32-bit unsigned number 1164 * ll...lll is the 32-bit unsigned number 1165 */ 1166 struct pci_phys_spec { 1167 uint_t pci_phys_hi; /* child's address, hi word */ 1168 uint_t pci_phys_mid; /* child's address, middle word */ 1169 uint_t pci_phys_low; /* child's address, low word */ 1170 uint_t pci_size_hi; /* high word of size field */ 1171 uint_t pci_size_low; /* low word of size field */ 1172 }; 1173 1174 typedef struct pci_phys_spec pci_regspec_t; 1175 1176 /* 1177 * PCI masks for pci_phy_hi of PCI 1275 address cell. 1178 */ 1179 #define PCI_REG_REG_M 0xff /* register mask */ 1180 #define PCI_REG_FUNC_M 0x700 /* function mask */ 1181 #define PCI_REG_DEV_M 0xf800 /* device mask */ 1182 #define PCI_REG_BUS_M 0xff0000 /* bus number mask */ 1183 #define PCI_REG_ADDR_M 0x3000000 /* address space mask */ 1184 #define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */ 1185 #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */ 1186 #define PCI_REG_REL_M 0x80000000 /* relocation bit mask */ 1187 #define PCI_REG_BDFR_M 0xffffff /* bus, dev, func, reg mask */ 1188 #define PCI_REG_EXTREG_M 0xF0000000 /* extended config bits mask */ 1189 1190 #define PCI_REG_FUNC_SHIFT 8 /* Offset of function bits */ 1191 #define PCI_REG_DEV_SHIFT 11 /* Offset of device bits */ 1192 #define PCI_REG_BUS_SHIFT 16 /* Offset of bus bits */ 1193 #define PCI_REG_ADDR_SHIFT 24 /* Offset of address bits */ 1194 #define PCI_REG_EXTREG_SHIFT 28 /* Offset of ext. config bits */ 1195 1196 #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) 1197 #define PCI_REG_FUNC_G(x) (((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT) 1198 #define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT) 1199 #define PCI_REG_BUS_G(x) (((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT) 1200 #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) 1201 #define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M) 1202 1203 #define PCI_REG_MAKE_BDFR(b, d, f, r) ( \ 1204 (uint_t)(b) << PCI_REG_BUS_SHIFT | \ 1205 (uint_t)(d) << PCI_REG_DEV_SHIFT | \ 1206 (uint_t)(f) << PCI_REG_FUNC_SHIFT | (r)) 1207 1208 /* 1209 * PCI bit encodings of pci_phys_hi of PCI 1275 address cell. 1210 */ 1211 #define PCI_ADDR_MASK PCI_REG_ADDR_M 1212 #define PCI_ADDR_CONFIG 0x00000000 /* configuration address */ 1213 #define PCI_ADDR_IO 0x01000000 /* I/O address */ 1214 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */ 1215 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */ 1216 #define PCI_ALIAS_B PCI_REG_ALIAS_M /* aliased bit */ 1217 #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */ 1218 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */ 1219 #define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */ 1220 1221 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */ 1222 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */ 1223 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */ 1224 #define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */ 1225 #define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */ 1226 1227 /* 1228 * PCI Expansion ROM Header Format 1229 */ 1230 #define PCI_ROM_SIGNATURE 0x0 /* ROM Signature 0xaa55 */ 1231 #define PCI_ROM_ARCH_UNIQUE_START 0x2 /* Start of processor unique */ 1232 #define PCI_ROM_PCI_DATA_STRUCT_PTR 0x18 /* Ptr to PCI Data Structure */ 1233 1234 /* 1235 * PCI Data Structure 1236 * 1237 * The PCI Data Structure is located within the first 64KB 1238 * of the ROM image and must be DWORD aligned. 1239 */ 1240 #define PCI_PDS_SIGNATURE 0x0 /* Signature, the string 'PCIR' */ 1241 #define PCI_PDS_VENDOR_ID 0x4 /* Vendor Identification */ 1242 #define PCI_PDS_DEVICE_ID 0x6 /* Device Identification */ 1243 #define PCI_PDS_VPD_PTR 0x8 /* Pointer to Vital Product Data */ 1244 #define PCI_PDS_PDS_LENGTH 0xa /* PCI Data Structure Length */ 1245 #define PCI_PDS_PDS_REVISION 0xc /* PCI Data Structure Revision */ 1246 #define PCI_PDS_CLASS_CODE 0xd /* Class Code */ 1247 #define PCI_PDS_IMAGE_LENGTH 0x10 /* Image Length in 512 byte units */ 1248 #define PCI_PDS_CODE_REVISON 0x12 /* Revision Level of Code/Data */ 1249 #define PCI_PDS_CODE_TYPE 0x14 /* Code Type */ 1250 #define PCI_PDS_INDICATOR 0x15 /* Indicates if image is last in ROM */ 1251 1252 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */ 1253 #define PCI_PDS_CODE_TYPE_OPEN_FW 0x1 /* Open Firmware */ 1254 1255 /* 1256 * we recognize the non transparent bridge child nodes with the 1257 * following property. This is specific to an implementation only. 1258 * This property is specific to AP nodes only. 1259 */ 1260 #define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect" 1261 1262 /* 1263 * If a bridge device provides its own config space access services, 1264 * and supports a hotplug/hotswap bus below at any level, then 1265 * the following property must be defined for the node either by 1266 * the driver or the OBP. 1267 */ 1268 #define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect" 1269 1270 /* 1271 * PCI returns all 1s for an invalid read. 1272 */ 1273 #define PCI_EINVAL8 0xff 1274 #define PCI_EINVAL16 0xffff 1275 #define PCI_EINVAL32 0xffffffff 1276 1277 #ifdef __cplusplus 1278 } 1279 #endif 1280 1281 #endif /* _SYS_PCI_H */ 1282