1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * Copyright 2019, Joyent, Inc. 25 * Copyright 2023 Oxide Computer Company 26 */ 27 28 #ifndef _SYS_PCI_H 29 #define _SYS_PCI_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * PCI Configuration Header offsets 37 */ 38 #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 39 #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 40 #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 41 #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 42 #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 43 #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 44 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 45 #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 46 #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 47 #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ 48 #define PCI_CONF_HEADER 0xE /* header type, 1 byte */ 49 #define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */ 50 51 /* 52 * Header type 0 offsets 53 */ 54 #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ 55 #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ 56 #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ 57 #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ 58 #define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */ 59 #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ 60 #define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */ 61 #define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */ 62 #define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */ 63 #define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */ 64 #define PCI_CONF_CAP_PTR 0x34 /* capabilities pointer, 1 byte */ 65 #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */ 66 #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */ 67 #define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */ 68 #define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */ 69 70 /* 71 * PCI to PCI bridge configuration space header format 72 */ 73 #define PCI_BCNF_PRIBUS 0x18 /* primary bus number */ 74 #define PCI_BCNF_SECBUS 0x19 /* secondary bus number */ 75 #define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */ 76 #define PCI_BCNF_LATENCY_TIMER 0x1b 77 #define PCI_BCNF_IO_BASE_LOW 0x1c 78 #define PCI_BCNF_IO_LIMIT_LOW 0x1d 79 #define PCI_BCNF_SEC_STATUS 0x1e 80 #define PCI_BCNF_MEM_BASE 0x20 81 #define PCI_BCNF_MEM_LIMIT 0x22 82 #define PCI_BCNF_PF_BASE_LOW 0x24 83 #define PCI_BCNF_PF_LIMIT_LOW 0x26 84 #define PCI_BCNF_PF_BASE_HIGH 0x28 85 #define PCI_BCNF_PF_LIMIT_HIGH 0x2c 86 #define PCI_BCNF_IO_BASE_HI 0x30 87 #define PCI_BCNF_IO_LIMIT_HI 0x32 88 #define PCI_BCNF_CAP_PTR 0x34 89 #define PCI_BCNF_ROM 0x38 90 #define PCI_BCNF_ILINE 0x3c 91 #define PCI_BCNF_IPIN 0x3d 92 #define PCI_BCNF_BCNTRL 0x3e 93 94 #define PCI_BCNF_BASE_NUM 0x2 95 96 /* 97 * PCI to PCI bridge control register (0x3e) format 98 */ 99 #define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1 100 #define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2 101 #define PCI_BCNF_BCNTRL_ISA_ENABLE 0x4 102 #define PCI_BCNF_BCNTRL_VGA_ENABLE 0x8 103 #define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20 104 #define PCI_BCNF_BCNTRL_DTO_STAT 0x400 105 106 #define PCI_BCNF_BCNTRL_RESET 0x0040 107 #define PCI_BCNF_BCNTRL_B2B_ENAB 0x0080 108 109 #define PCI_BCNF_IO_MASK 0xf0 110 #define PCI_BCNF_IO_SHIFT 8 111 #define PCI_BCNF_IO_LIMIT_BITS 0xfff 112 #define PCI_BCNF_MEM_MASK 0xfff0 113 #define PCI_BCNF_MEM_SHIFT 16 114 #define PCI_BCNF_MEM_LIMIT_BITS 0xfffff 115 #define PCI_BCNF_ADDR_MASK 0x000f 116 117 #define PCI_BCNF_IO_32BIT 0x01 118 #define PCI_BCNF_PF_MEM_64BIT 0x01 119 120 /* 121 * Header type 2 (Cardbus) offsets 122 */ 123 #define PCI_CBUS_SOCK_REG 0x10 /* Cardbus socket regs, 4 bytes */ 124 #define PCI_CBUS_CAP_PTR 0x14 /* Capability ptr, 1 byte */ 125 #define PCI_CBUS_RESERVED1 0x15 /* Reserved, 1 byte */ 126 #define PCI_CBUS_SEC_STATUS 0x16 /* Secondary status, 2 bytes */ 127 #define PCI_CBUS_PCI_BUS_NO 0x18 /* PCI bus number, 1 byte */ 128 #define PCI_CBUS_CBUS_NO 0x19 /* Cardbus bus number, 1 byte */ 129 #define PCI_CBUS_SUB_BUS_NO 0x1a /* Subordinate bus number, 1 byte */ 130 #define PCI_CBUS_LATENCY_TIMER 0x1b /* Cardbus latency timer, 1 byte */ 131 #define PCI_CBUS_MEM_BASE0 0x1c /* Memory base reg 0, 4 bytes */ 132 #define PCI_CBUS_MEM_LIMIT0 0x20 /* Memory limit reg 0, 4 bytes */ 133 #define PCI_CBUS_MEM_BASE1 0x24 /* Memory base reg 1, 4 bytes */ 134 #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ 135 #define PCI_CBUS_IO_BASE0 0x2c /* IO base reg 0, 4 bytes */ 136 #define PCI_CBUS_IO_LIMIT0 0x30 /* IO limit reg 0, 4 bytes */ 137 #define PCI_CBUS_IO_BASE1 0x34 /* IO base reg 1, 4 bytes */ 138 #define PCI_CBUS_IO_LIMIT1 0x38 /* IO limit reg 1, 4 bytes */ 139 #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */ 140 #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */ 141 #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 142 #define PCI_CBUS_SUBVENID 0x40 /* Subsystem Vendor ID, 2 bytes */ 143 #define PCI_CBUS_SUBSYSID 0x42 /* Subsystem ID, 2 bytes */ 144 #define PCI_CBUS_LEG_MODE_ADDR 0x44 /* PCCard 16bit IF legacy mode addr */ 145 146 #define PCI_CBUS_BASE_NUM 0x1 /* number of base registers */ 147 148 /* 149 * PCI command register bits 150 */ 151 #define PCI_COMM_IO 0x1 /* I/O access enable */ 152 #define PCI_COMM_MAE 0x2 /* memory access enable */ 153 #define PCI_COMM_ME 0x4 /* master enable */ 154 #define PCI_COMM_SPEC_CYC 0x8 155 #define PCI_COMM_MEMWR_INVAL 0x10 156 #define PCI_COMM_PALETTE_SNOOP 0x20 157 #define PCI_COMM_PARITY_DETECT 0x40 158 #define PCI_COMM_WAIT_CYC_ENAB 0x80 159 #define PCI_COMM_SERR_ENABLE 0x100 160 #define PCI_COMM_BACK2BACK_ENAB 0x200 161 #define PCI_COMM_INTX_DISABLE 0x400 /* INTx emulation disable */ 162 163 /* 164 * PCI Interrupt pin value 165 */ 166 #define PCI_INTA 1 167 #define PCI_INTB 2 168 #define PCI_INTC 3 169 #define PCI_INTD 4 170 171 /* 172 * PCI status register bits 173 */ 174 #define PCI_STAT_READY 0x1 /* Immediate Readiness */ 175 #define PCI_STAT_INTR 0x8 /* Interrupt state */ 176 #define PCI_STAT_CAP 0x10 /* Implements Capabilities */ 177 #define PCI_STAT_66MHZ 0x20 /* 66 MHz capable */ 178 #define PCI_STAT_UDF 0x40 /* UDF supported */ 179 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */ 180 #define PCI_STAT_S_PERROR 0x100 /* Data Parity Reported */ 181 #define PCI_STAT_DEVSELT 0x600 /* Device select timing */ 182 #define PCI_STAT_S_TARG_AB 0x800 /* Signaled Target Abort */ 183 #define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */ 184 #define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */ 185 #define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */ 186 #define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */ 187 188 /* 189 * DEVSEL timing values 190 */ 191 #define PCI_STAT_DEVSELT_FAST 0x0000 192 #define PCI_STAT_DEVSELT_MEDIUM 0x0200 193 #define PCI_STAT_DEVSELT_SLOW 0x0400 194 195 /* 196 * BIST values 197 */ 198 #define PCI_BIST_SUPPORTED 0x80 199 #define PCI_BIST_GO 0x40 200 #define PCI_BIST_RESULT_M 0x0f 201 #define PCI_BIST_RESULT_OK 0x00 202 203 /* 204 * PCI class codes 205 */ 206 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */ 207 #define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */ 208 #define PCI_CLASS_NET 0x2 /* Network Controller class */ 209 #define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */ 210 #define PCI_CLASS_MM 0x4 /* Multimedia Controller class */ 211 #define PCI_CLASS_MEM 0x5 /* Memory Controller class */ 212 #define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */ 213 #define PCI_CLASS_COMM 0x7 /* Communications Controller class */ 214 #define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */ 215 #define PCI_CLASS_INPUT 0x9 /* Input Device class */ 216 #define PCI_CLASS_DOCK 0xa /* Docking Station class */ 217 #define PCI_CLASS_PROCESSOR 0xb /* Processor class */ 218 #define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */ 219 #define PCI_CLASS_WIRELESS 0xd /* Wireless Controller class */ 220 #define PCI_CLASS_INTIO 0xe /* Intelligent IO Controller class */ 221 #define PCI_CLASS_SATELLITE 0xf /* Satellite Communication class */ 222 #define PCI_CLASS_CRYPT 0x10 /* Encrytion/Decryption class */ 223 #define PCI_CLASS_SIGNAL 0x11 /* Signal Processing class */ 224 225 /* 226 * PCI Sub-class codes - base class 0x0 (no new devices should use this code). 227 */ 228 #define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */ 229 #define PCI_NONE_VGA 0x1 /* VGA compatible */ 230 231 /* 232 * PCI Sub-class codes - base class 0x1 (mass storage controllers) 233 */ 234 #define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */ 235 #define PCI_MASS_IDE 0x1 /* IDE Controller */ 236 #define PCI_MASS_FD 0x2 /* Floppy disk Controller */ 237 #define PCI_MASS_IPI 0x3 /* IPI bus Controller */ 238 #define PCI_MASS_RAID 0x4 /* RAID Controller */ 239 #define PCI_MASS_ATA 0x5 /* ATA Controller */ 240 #define PCI_MASS_SATA 0x6 /* Serial ATA */ 241 #define PCI_MASS_SAS 0x7 /* Serial Attached SCSI (SAS) Cntrlr */ 242 #define PCI_MASS_NVME 0x8 /* Non-Volatile memory controller */ 243 #define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */ 244 245 /* 246 * programming interface for IDE (subclass 1) 247 */ 248 #define PCI_IDE_IF_NATIVE_PRI 0x1 /* primary channel is native */ 249 #define PCI_IDE_IF_PROG_PRI 0x2 /* primary can operate in either mode */ 250 #define PCI_IDE_IF_NATIVE_SEC 0x4 /* secondary channel is native */ 251 #define PCI_IDE_IF_PROG_SEC 0x8 /* sec. can operate in either mode */ 252 #define PCI_IDE_IF_MASK 0xf /* programming interface mask */ 253 254 255 /* 256 * programming interface for ATA (subclass 5) 257 */ 258 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */ 259 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */ 260 261 /* 262 * programming interface for ATA (subclass 6) for SATA 263 */ 264 #define PCI_SATA_VS_INTERFACE 0x0 /* SATA Ctlr Vendor Specific Intfc */ 265 #define PCI_SATA_AHCI_INTERFACE 0x1 /* SATA Ctlr AHCI 1.0 Interface */ 266 #define PCI_SATA_SSB_INTERFACE 0x2 /* Serial Storage Bus Interface */ 267 268 /* 269 * programming interface for ATA (subclass 7) for SAS 270 */ 271 #define PCI_SAS_CONTROLLER 0x0 /* SAS Controller */ 272 #define PCI_SAS_BUS_INTERFACE 0x1 /* Serial Storage Bus Interface */ 273 274 /* 275 * PCI Sub-class codes - base class 0x2 (Network controllers) 276 */ 277 #define PCI_NET_ENET 0x0 /* Ethernet Controller */ 278 #define PCI_NET_TOKEN 0x1 /* Token Ring Controller */ 279 #define PCI_NET_FDDI 0x2 /* FDDI Controller */ 280 #define PCI_NET_ATM 0x3 /* ATM Controller */ 281 #define PCI_NET_ISDN 0x4 /* ISDN Controller */ 282 #define PCI_NET_WFIP 0x5 /* WorldFip Controller */ 283 #define PCI_NET_PICMG 0x6 /* PICMG 2.14 Multi Computing */ 284 #define PCI_NET_OTHER 0x80 /* Other Network Controller */ 285 286 /* 287 * PCI Sub-class codes - base class 03 (display controllers) 288 */ 289 #define PCI_DISPLAY_VGA 0x0 /* VGA device */ 290 #define PCI_DISPLAY_XGA 0x1 /* XGA device */ 291 #define PCI_DISPLAY_3D 0x2 /* 3D controller */ 292 #define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */ 293 294 /* 295 * programming interface for display for display class (subclass 0) VGA ctrlrs 296 */ 297 #define PCI_DISPLAY_IF_VGA 0x0 /* VGA compatible */ 298 #define PCI_DISPLAY_IF_8514 0x1 /* 8514 compatible */ 299 300 /* 301 * PCI Sub-class codes - base class 0x4 (multi-media devices) 302 */ 303 #define PCI_MM_VIDEO 0x0 /* Video device */ 304 #define PCI_MM_AUDIO 0x1 /* Audio device */ 305 #define PCI_MM_TELEPHONY 0x2 /* Computer Telephony device */ 306 #define PCI_MM_MIXED_MODE 0x3 /* Mixed Mode device */ 307 #define PCI_MM_OTHER 0x80 /* Other Multimedia Device */ 308 309 /* 310 * PCI Sub-class codes - base class 0x5 (memory controllers) 311 */ 312 #define PCI_MEM_RAM 0x0 /* RAM device */ 313 #define PCI_MEM_FLASH 0x1 /* FLASH device */ 314 #define PCI_MEM_OTHER 0x80 /* Other Memory Controller */ 315 316 /* 317 * PCI Sub-class codes - base class 0x6 (Bridge devices) 318 */ 319 #define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */ 320 #define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */ 321 #define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */ 322 #define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */ 323 #define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */ 324 #define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */ 325 #define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */ 326 #define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */ 327 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */ 328 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */ 329 #define PCI_BRIDGE_IB 0xA /* InfiniBand/PCI host Bridge */ 330 #define PCI_BRIDGE_AS 0xB /* AS/PCI host Bridge */ 331 #define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */ 332 333 /* 334 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge 335 */ 336 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */ 337 #define PCI_BRIDGE_PCI_IF_SUBDECODE 0x1 /* Subtractive Decode */ 338 /* PCI/PCI bridge */ 339 340 /* 341 * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge 342 */ 343 #define PCI_BRIDGE_RACE_IF_TRANSPARENT 0x0 /* Transport mode */ 344 #define PCI_BRIDGE_RACE_IF_ENDPOINT 0x1 /* Endpoint mode */ 345 346 /* 347 * programming interface for Bridges class 0x6 (subclass 09) 348 * Semi-transparent PCI-to-PCI bridge 349 */ 350 #define PCI_BRIDGE_STPCI_IF_PRIMARY 0x40 /* primary PCI side bus */ 351 /* facing system processor */ 352 #define PCI_BRIDGE_STPCI_IF_SECONDARY 0x80 /* secondary PCI side bus */ 353 /* facing system processor */ 354 355 /* 356 * programming interface for Bridges class 0x6 (subclass 0B) AS bridge 357 */ 358 #define PCI_BRIDGE_AS_CUSTOM_INTFC 0x0 /* Custom interface */ 359 #define PCI_BRIDGE_AS_PORTAL_INTFC 0x1 /* ASI-SIG Portal Interface */ 360 361 /* 362 * PCI Sub-class codes - base class 0x7 (communication devices) 363 */ 364 #define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */ 365 #define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */ 366 #define PCI_COMM_MSC 0x2 /* Multiport Serial Controller */ 367 #define PCI_COMM_MODEM 0x3 /* Modem Controller */ 368 #define PCI_COMM_GPIB 0x4 /* GPIB Controller */ 369 #define PCI_COMM_SMARTCARD 0x5 /* Smart Card Controller */ 370 #define PCI_COMM_OTHER 0x80 /* Other Communications Controller */ 371 372 /* 373 * Programming interfaces for class 0x7 / subclass 0x0 (Serial) 374 */ 375 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */ 376 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */ 377 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */ 378 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */ 379 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */ 380 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */ 381 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */ 382 383 /* 384 * Programming interfaces for class 0x7 / subclass 0x1 (Parallel) 385 */ 386 #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */ 387 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */ 388 #define PCI_COMM_PARALLEL_IF_ECP 0x2 /* ECP 1.X Parallel port */ 389 #define PCI_COMM_PARALLEL_IF_1284 0x3 /* IEEE 1284 Parallel port */ 390 #define PCI_COMM_PARALLEL_IF_1284_TARG 0xFE /* IEEE 1284 target device */ 391 392 /* 393 * Programming interfaces for class 0x7 / subclass 0x3 (Modem) 394 */ 395 #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */ 396 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */ 397 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */ 398 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */ 399 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */ 400 401 /* 402 * PCI Sub-class codes - base class 0x8 403 */ 404 #define PCI_PERIPH_PIC 0x0 /* Generic PIC */ 405 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */ 406 #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */ 407 #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */ 408 #define PCI_PERIPH_HPC 0x4 /* Generic PCI Hot-Plug Controller */ 409 #define PCI_PERIPH_SD_HC 0x5 /* SD Host Controller */ 410 #define PCI_PERIPH_IOMMU 0x6 /* IOMMU */ 411 #define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */ 412 413 /* 414 * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller) 415 */ 416 #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */ 417 #define PCI_PERIPH_PIC_IF_ISA 0x1 /* ISA PIC */ 418 #define PCI_PERIPH_PIC_IF_EISA 0x2 /* EISA PIC */ 419 #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */ 420 #define PCI_PERIPH_PIC_IF_IOX_APIC 0x20 /* I/O(x) APIC intr ctrlr */ 421 422 /* 423 * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller) 424 */ 425 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */ 426 #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */ 427 #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */ 428 429 /* 430 * Programming interfaces for class 0x8 / subclass 0x2 (timer) 431 */ 432 #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */ 433 #define PCI_PERIPH_TIMER_IF_ISA 0x1 /* ISA system timers */ 434 #define PCI_PERIPH_TIMER_IF_EISA 0x2 /* EISA system timers (two) */ 435 #define PCI_PERIPH_TIMER_IF_HPET 0x3 /* High Perf Event timer */ 436 437 /* 438 * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock) 439 */ 440 #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */ 441 #define PCI_PERIPH_RTC_IF_ISA 0x1 /* ISA RTC controller */ 442 443 /* 444 * PCI Sub-class codes - base class 0x9 445 */ 446 #define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controller */ 447 #define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */ 448 #define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */ 449 #define PCI_INPUT_SCANNER 0x3 /* Scanner Controller */ 450 #define PCI_INPUT_GAMEPORT 0x4 /* Gameport Controller */ 451 #define PCI_INPUT_OTHER 0x80 /* Other Input Controller */ 452 453 /* 454 * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller) 455 */ 456 #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */ 457 #define PCI_INPUT_GAMEPORT_IF_LEGACY 0x10 /* Legacy controller */ 458 459 /* 460 * PCI Sub-class codes - base class 0xA 461 */ 462 #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */ 463 #define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */ 464 465 /* 466 * PCI Sub-class codes - base class 0xB 467 */ 468 #define PCI_PROCESSOR_386 0x0 /* 386 */ 469 #define PCI_PROCESSOR_486 0x1 /* 486 */ 470 #define PCI_PROCESSOR_PENT 0x2 /* Pentium */ 471 #define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */ 472 #define PCI_PROCESSOR_POWERPC 0x20 /* PowerPC */ 473 #define PCI_PROCESSOR_MIPS 0x30 /* MIPS */ 474 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */ 475 #define PCI_PROCESSOR_OTHER 0x80 /* Other processors */ 476 477 /* 478 * PCI Sub-class codes - base class 0xC (Serial Controllers) 479 */ 480 #define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */ 481 #define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */ 482 #define PCI_SERIAL_SSA 0x2 /* SSA */ 483 #define PCI_SERIAL_USB 0x3 /* Universal Serial Bus */ 484 #define PCI_SERIAL_FIBRE 0x4 /* Fibre Channel */ 485 #define PCI_SERIAL_SMBUS 0x5 /* System Management Bus */ 486 #define PCI_SERIAL_IB 0x6 /* InfiniBand */ 487 #define PCI_SERIAL_IPMI 0x7 /* IPMI */ 488 #define PCI_SERIAL_SERCOS 0x8 /* SERCOS Interface Std (IEC 61491) */ 489 #define PCI_SERIAL_CANBUS 0x9 /* CANbus */ 490 #define PCI_SERIAL_OTHER 0x80 /* Other Serial Bus Controllers */ 491 492 /* 493 * Programming interfaces for class 0xC / subclass 0x0 (Firewire) 494 */ 495 #define PCI_SERIAL_FIRE_WIRE 0x00 /* IEEE 1394 (Firewire) */ 496 #define PCI_SERIAL_FIRE_1394_HCI 0x10 /* 1394 OpenHCI Host Cntrlr */ 497 498 /* 499 * Programming interfaces for class 0xC / subclass 0x3 (USB controller) 500 */ 501 #define PCI_SERIAL_USB_IF_UHCI 0x00 /* UHCI Compliant */ 502 #define PCI_SERIAL_USB_IF_OHCI 0x10 /* OHCI Compliant */ 503 #define PCI_SERIAL_USB_IF_EHCI 0x20 /* EHCI Compliant */ 504 #define PCI_SERIAL_USB_IF_GENERIC 0x80 /* no specific HCD */ 505 #define PCI_SERIAL_USB_IF_DEVICE 0xFE /* not a HCD */ 506 507 /* 508 * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller) 509 */ 510 #define PCI_SERIAL_IPMI_IF_SMIC 0x0 /* SMIC Interface */ 511 #define PCI_SERIAL_IPMI_IF_KBD 0x1 /* Keyboard Ctrl Style Intfc */ 512 #define PCI_SERIAL_IPMI_IF_BTI 0x2 /* Block Transfer Interface */ 513 514 /* 515 * PCI Sub-class codes - base class 0xD (Wireless controllers) 516 */ 517 #define PCI_WIRELESS_IRDA 0x0 /* iRDA Compatible Controller */ 518 #define PCI_WIRELESS_IR 0x1 /* Consumer IR Controller */ 519 #define PCI_WIRELESS_RF 0x10 /* RF Controller */ 520 #define PCI_WIRELESS_BLUETOOTH 0x11 /* Bluetooth Controller */ 521 #define PCI_WIRELESS_BROADBAND 0x12 /* Broadband Controller */ 522 #define PCI_WIRELESS_80211A 0x20 /* Ethernet 802.11a 5 GHz */ 523 #define PCI_WIRELESS_80211B 0x21 /* Ethernet 802.11b 2.4 GHz */ 524 #define PCI_WIRELESS_OTHER 0x80 /* Other Wireless Controllers */ 525 526 /* 527 * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller) 528 */ 529 #define PCI_WIRELESS_IR_CONSUMER 0x00 /* Consumer IR Controller */ 530 #define PCI_WIRELESS_IR_UWB_RC 0x10 /* UWB Radio Controller */ 531 532 /* 533 * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers) 534 */ 535 #define PCI_INTIO_MSG_FIFO 0x0 /* Message FIFO at off 40h */ 536 #define PCI_INTIO_I20 0x1 /* I20 Arch Spec 1.0 */ 537 538 /* 539 * PCI Sub-class codes - base class 0xF (Satellite Communication controllers) 540 */ 541 #define PCI_SATELLITE_COMM_TV 0x01 /* TV */ 542 #define PCI_SATELLITE_COMM_AUDIO 0x02 /* Audio */ 543 #define PCI_SATELLITE_COMM_VOICE 0x03 /* Voice */ 544 #define PCI_SATELLITE_COMM_DATA 0x04 /* DATA */ 545 #define PCI_SATELLITE_COMM_OTHER 0x80 /* Other Satelite Comm Cntrlr */ 546 547 /* 548 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers) 549 */ 550 #define PCI_CRYPT_NETWORK 0x00 /* Network and Computing */ 551 #define PCI_CRYPT_ENTERTAINMENT 0x10 /* Entertainment en/decrypt */ 552 #define PCI_CRYPT_OTHER 0x80 /* Other en/decryption ctrlrs */ 553 554 /* 555 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers) 556 */ 557 #define PCI_SIGNAL_DPIO 0x00 /* DPIO modules */ 558 #define PCI_SIGNAL_PERF_COUNTERS 0x01 /* Performance counters */ 559 #define PCI_SIGNAL_COMM_SYNC 0x10 /* Comm. synchronization plus */ 560 /* time and freq test ctrlr */ 561 #define PCI_SIGNAL_MANAGEMENT 0x20 /* Management card */ 562 #define PCI_SIGNAL_OTHER 0x80 /* DSP/DAP controller */ 563 564 /* PCI header decode */ 565 #define PCI_HEADER_MULTI 0x80 /* multi-function device */ 566 #define PCI_HEADER_ZERO 0x00 /* type zero PCI header */ 567 #define PCI_HEADER_ONE 0x01 /* type one PCI header */ 568 #define PCI_HEADER_TWO 0x02 /* type two PCI header */ 569 #define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */ 570 #define PCI_HEADER_CARDBUS PCI_HEADER_TWO /* type one PCI header */ 571 572 #define PCI_HEADER_TYPE_M 0x7f /* type mask for header */ 573 574 /* 575 * Base register bit definitions. 576 */ 577 #define PCI_BASE_SPACE_M 0x1 /* memory space indicator */ 578 #define PCI_BASE_SPACE_IO 0x1 /* IO space */ 579 #define PCI_BASE_SPACE_MEM 0x0 /* memory space */ 580 581 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */ 582 #define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */ 583 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */ 584 #define PCI_BASE_TYPE_RES 0x6 /* reserved */ 585 586 #define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */ 587 #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */ 588 #define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */ 589 #define PCI_BASE_M_ADDR64_M 0xfffffffffffffff0ULL /* 64bit mem addr mask */ 590 #define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */ 591 592 #define PCI_BASE_ROM_ADDR_M 0xfffff800 /* ROM address mask */ 593 #define PCI_BASE_ROM_ENABLE 0x00000001 /* ROM decoder enable */ 594 595 /* 596 * Capabilities linked list entry offsets 597 */ 598 #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 599 #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 600 #define PCI_CAP_ID_REGS_OFF 0x2 /* cap id register offset */ 601 #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 602 #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 603 #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 604 605 /* 606 * Capability identifier values 607 */ 608 #define PCI_CAP_ID_PM 0x1 /* power management entry */ 609 #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 610 #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 611 #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 612 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 613 #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 614 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 615 #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 616 #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 617 #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 618 #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 619 #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug (SHPC) supported */ 620 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */ 621 #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 622 #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 623 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 624 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 625 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Config supported */ 626 #define PCI_CAP_ID_FLR 0x13 /* Function Level Reset supported */ 627 #define PCI_CAP_ID_EA 0x14 /* Enhanced Allocation */ 628 #define PCI_CAP_ID_FPB 0x15 /* Flattening Portal Bridge */ 629 630 /* 631 * Capability next entry pointer values 632 */ 633 #define PCI_CAP_NEXT_PTR_NULL 0x0 /* no more entries in the list */ 634 635 /* 636 * PCI power management (PM) capability entry offsets 637 */ 638 #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 639 #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 640 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 641 #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 642 643 /* 644 * PM capabilities values - 2 bytes 645 */ 646 #define PCI_PMCAP_VER_1_0 0x1 /* PCI PM spec 1.0 */ 647 #define PCI_PMCAP_VER_1_1 0x2 /* PCI PM spec 1.1 */ 648 #define PCI_PMCAP_VER_MASK 0x7 /* version mask */ 649 #define PCI_PMCAP_PME_CLOCK 0x8 /* needs PCI clock for PME */ 650 #define PCI_PMCAP_DSI 0x20 /* needs device specific init */ 651 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */ 652 #define PCI_PMCAP_AUX_CUR_55mA 0x40 /* 55 mA aux current */ 653 #define PCI_PMCAP_AUX_CUR_100mA 0x80 /* 100 mA aux current */ 654 #define PCI_PMCAP_AUX_CUR_160mA 0xc0 /* 160 mA aux current */ 655 #define PCI_PMCAP_AUX_CUR_220mA 0x100 /* 220 mA aux current */ 656 #define PCI_PMCAP_AUX_CUR_270mA 0x140 /* 270 mA aux current */ 657 #define PCI_PMCAP_AUX_CUR_320mA 0x180 /* 320 mA aux current */ 658 #define PCI_PMCAP_AUX_CUR_375mA 0x1c0 /* 375 mA aux current */ 659 #define PCI_PMCAP_AUX_CUR_MASK 0x1c0 /* 3.3Vaux aux current needs */ 660 #define PCI_PMCAP_D1 0x200 /* D1 state supported */ 661 #define PCI_PMCAP_D2 0x400 /* D2 state supported */ 662 #define PCI_PMCAP_D0_PME 0x800 /* PME from D0 */ 663 #define PCI_PMCAP_D1_PME 0x1000 /* PME from D1 */ 664 #define PCI_PMCAP_D2_PME 0x2000 /* PME from D2 */ 665 #define PCI_PMCAP_D3HOT_PME 0x4000 /* PME from D3hot */ 666 #define PCI_PMCAP_D3COLD_PME 0x8000 /* PME from D3cold */ 667 #define PCI_PMCAP_PME_MASK 0xf800 /* PME support mask */ 668 669 /* 670 * PM control/status values - 2 bytes 671 */ 672 #define PCI_PMCSR_D0 0x0 /* power state D0 */ 673 #define PCI_PMCSR_D1 0x1 /* power state D1 */ 674 #define PCI_PMCSR_D2 0x2 /* power state D2 */ 675 #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 676 #define PCI_PMCSR_STATE_MASK 0x3 /* power state mask */ 677 #define PCI_PMCSR_PME_EN 0x100 /* enable PME assertion */ 678 #define PCI_PMCSR_DSEL_D0_PWR_C 0x0 /* D0 power consumed */ 679 #define PCI_PMCSR_DSEL_D1_PWR_C 0x200 /* D1 power consumed */ 680 #define PCI_PMCSR_DSEL_D2_PWR_C 0x400 /* D2 power consumed */ 681 #define PCI_PMCSR_DSEL_D3_PWR_C 0x600 /* D3 power consumed */ 682 #define PCI_PMCSR_DSEL_D0_PWR_D 0x800 /* D0 power dissipated */ 683 #define PCI_PMCSR_DSEL_D1_PWR_D 0xa00 /* D1 power dissipated */ 684 #define PCI_PMCSR_DSEL_D2_PWR_D 0xc00 /* D2 power dissipated */ 685 #define PCI_PMCSR_DSEL_D3_PWR_D 0xe00 /* D3 power dissipated */ 686 #define PCI_PMCSR_DSEL_COM_C 0x1000 /* common power consumption */ 687 #define PCI_PMCSR_DSEL_MASK 0x1e00 /* data select mask */ 688 #define PCI_PMCSR_DSCL_UNKNOWN 0x0 /* data scale unknown */ 689 #define PCI_PMCSR_DSCL_1_BY_10 0x2000 /* data scale 0.1x */ 690 #define PCI_PMCSR_DSCL_1_BY_100 0x4000 /* data scale 0.01x */ 691 #define PCI_PMCSR_DSCL_1_BY_1000 0x6000 /* data scale 0.001x */ 692 #define PCI_PMCSR_DSCL_MASK 0x6000 /* data scale mask */ 693 #define PCI_PMCSR_PME_STAT 0x8000 /* PME status */ 694 695 /* 696 * PM PMCSR PCI to PCI bridge support extension values - 1 byte 697 */ 698 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */ 699 #define PCI_PMCSR_BSE_BPCC_EN 0x80 /* bus power/clock control enabled */ 700 701 /* 702 * PCI-X capability related definitions 703 */ 704 #define PCI_PCIX_COMMAND 0x2 /* Command register offset */ 705 #define PCI_PCIX_STATUS 0x4 /* Status register offset */ 706 #define PCI_PCIX_ECC_STATUS 0x8 /* ECC Status register offset */ 707 #define PCI_PCIX_ECC_FST_AD 0xC /* ECC First address register offset */ 708 #define PCI_PCIX_ECC_SEC_AD 0x10 /* ECC Second address register offset */ 709 #define PCI_PCIX_ECC_ATTR 0x14 /* ECC Attribute register offset */ 710 711 /* 712 * PCI-X bridge capability related definitions 713 */ 714 #define PCI_PCIX_SEC_STATUS 0x2 /* Secondary Status offset */ 715 #define PCI_PCIX_SEC_STATUS_SCD 0x4 /* Split Completion Discarded */ 716 #define PCI_PCIX_SEC_STATUS_USC 0x8 /* Unexpected Split Complete */ 717 #define PCI_PCIX_SEC_STATUS_SCO 0x10 /* Split Completion Overrun */ 718 #define PCI_PCIX_SEC_STATUS_SRD 0x20 /* Split Completion Delayed */ 719 #define PCI_PCIX_SEC_STATUS_ERR_MASK 0x3C 720 721 #define PCI_PCIX_BDG_STATUS 0x4 /* Bridge Status offset */ 722 #define PCI_PCIX_BDG_STATUS_USC 0x80000 723 #define PCI_PCIX_BDG_STATUS_SCO 0x100000 724 #define PCI_PCIX_BDG_STATUS_SRD 0x200000 725 #define PCI_PCIX_BDG_STATUS_ERR_MASK 0x380000 726 727 #define PCI_PCIX_UP_SPL_CTL 0x8 /* Upstream split ctrl reg offset */ 728 #define PCI_PCIX_DOWN_SPL_CTL 0xC /* Downstream split ctrl reg offset */ 729 #define PCI_PCIX_BDG_ECC_STATUS 0x10 /* ECC Status register offset */ 730 #define PCI_PCIX_BDG_ECC_FST_AD 0x14 /* ECC First address register offset */ 731 #define PCI_PCIX_BDG_ECC_SEC_AD 0x18 /* ECC Second address register offset */ 732 #define PCI_PCIX_BDG_ECC_ATTR 0x1C /* ECC Attribute register offset */ 733 734 /* 735 * PCIX capabilities values 736 */ 737 #define PCI_PCIX_VER_MASK 0x3000 /* Bits 12 and 13 */ 738 #define PCI_PCIX_VER_0 0x0000 /* PCIX cap list item version 0 */ 739 #define PCI_PCIX_VER_1 0x1000 /* PCIX cap list item version 1 */ 740 #define PCI_PCIX_VER_2 0x2000 /* PCIX cap list item version 2 */ 741 742 #define PCI_PCIX_SPL_DSCD 0x40000 /* Split Completion Discarded */ 743 #define PCI_PCIX_UNEX_SPL 0x80000 /* Unexpected Split Completion */ 744 #define PCI_PCIX_RX_SPL_MSG 0x20000000 /* Recieved Spl Comp Error Message */ 745 746 #define PCI_PCIX_ECC_SEL 0x1 /* Secondary ECC register select */ 747 #define PCI_PCIX_ECC_EP 0x2 /* Error Present on other side */ 748 #define PCI_PCIX_ECC_S_CE 0x4 /* Addl Correctable ECC Error */ 749 #define PCI_PCIX_ECC_S_UE 0x8 /* Addl Uncorrectable ECC Error */ 750 #define PCI_PCIX_ECC_PHASE 0x70 /* ECC Error Phase */ 751 #define PCI_PCIX_ECC_CORR 0x80 /* ECC Error Corrected */ 752 #define PCI_PCIX_ECC_SYN 0xff00 /* ECC Error Syndrome */ 753 #define PCI_PCIX_ECC_FST_CMD 0xf0000 /* ECC Error First Command */ 754 #define PCI_PCIX_ECC_SEC_CMD 0xf00000 /* ECC Error Second Command */ 755 #define PCI_PCIX_ECC_UP_ATTR 0xf000000 /* ECC Error Upper Attributes */ 756 757 /* 758 * PCIX ECC Phase Values 759 */ 760 #define PCI_PCIX_ECC_PHASE_NOERR 0x0 761 #define PCI_PCIX_ECC_PHASE_FADDR 0x1 762 #define PCI_PCIX_ECC_PHASE_SADDR 0x2 763 #define PCI_PCIX_ECC_PHASE_ATTR 0x3 764 #define PCI_PCIX_ECC_PHASE_DATA32 0x4 765 #define PCI_PCIX_ECC_PHASE_DATA64 0x5 766 767 /* 768 * PCI-X Command Encoding 769 */ 770 #define PCI_PCIX_CMD_INTR 0x0 771 #define PCI_PCIX_CMD_SPEC 0x1 772 #define PCI_PCIX_CMD_IORD 0x2 773 #define PCI_PCIX_CMD_IOWR 0x3 774 #define PCI_PCIX_CMD_DEVID 0x5 775 #define PCI_PCIX_CMD_MEMRD_DW 0x6 776 #define PCI_PCIX_CMD_MEMWR 0x7 777 #define PCI_PCIX_CMD_MEMRD_BL 0x8 778 #define PCI_PCIX_CMD_MEMWR_BL 0x9 779 #define PCI_PCIX_CMD_CFRD 0xA 780 #define PCI_PCIX_CMD_CFWR 0xB 781 #define PCI_PCIX_CMD_SPL 0xC 782 #define PCI_PCIX_CMD_DADR 0xD 783 #define PCI_PCIX_CMD_MEMRDBL 0xE 784 #define PCI_PCIX_CMD_MEMWRBL 0xF 785 786 #if defined(_BIT_FIELDS_LTOH) 787 typedef struct pcix_attr { 788 uint32_t lbc :8, 789 rid :16, 790 tag :5, 791 ro :1, 792 ns :1, 793 r :1; 794 } pcix_attr_t; 795 #elif defined(_BIT_FIELDS_HTOL) 796 typedef struct pcix_attr { 797 uint32_t r :1, 798 ns :1, 799 ro :1, 800 tag :5, 801 rid :16, 802 lbc :8; 803 } pcix_attr_t; 804 #else 805 #error "bit field not defined" 806 #endif 807 808 #define PCI_PCIX_BSS_SPL_DSCD 0x4 /* Secondary split comp discarded */ 809 #define PCI_PCIX_BSS_UNEX_SPL 0x8 /* Secondary unexpected split comp */ 810 #define PCI_PCIX_BSS_SPL_OR 0x10 /* Secondary split comp overrun */ 811 #define PCI_PCIX_BSS_SPL_DLY 0x20 /* Secondary split comp delayed */ 812 813 /* 814 * PCI Hotplug capability entry offsets 815 * 816 * SHPC based PCI hotplug controller registers accessed via the DWORD 817 * select and DATA registers in PCI configuration space relative to the 818 * PCI HP capibility pointer. 819 */ 820 #define PCI_HP_DWORD_SELECT_OFF 0x2 821 #define PCI_HP_DWORD_DATA_OFF 0x4 822 823 #define PCI_HP_BASE_OFFSET_REG 0x00 824 #define PCI_HP_SLOTS_AVAIL_I_REG 0x01 825 #define PCI_HP_SLOTS_AVAIL_II_REG 0x02 826 #define PCI_HP_SLOT_CONFIGURATION_REG 0x03 827 #define PCI_HP_PROF_IF_SBCR_REG 0x04 828 #define PCI_HP_COMMAND_STATUS_REG 0x05 829 #define PCI_HP_IRQ_LOCATOR_REG 0x06 830 #define PCI_HP_SERR_LOCATOR_REG 0x07 831 #define PCI_HP_CTRL_SERR_INT_REG 0x08 832 #define PCI_HP_LOGICAL_SLOT_REGS 0x09 833 #define PCI_HP_VENDOR_SPECIFIC 0x28 834 835 /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */ 836 #define PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT 0 837 #define PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT 8 838 #define PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT 16 839 #define PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT 24 840 #define PCI_HP_AVAIL_SPEED_MASK 0x1F 841 842 /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */ 843 #define PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT 0 844 845 /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */ 846 #define PCI_HP_SBCR_33MHZ_CONV_SPEED 0x0 847 #define PCI_HP_SBCR_66MHZ_CONV_SPEED 0x1 848 #define PCI_HP_SBCR_66MHZ_PCIX_SPEED 0x2 849 #define PCI_HP_SBCR_100MHZ_PCIX_SPEED 0x3 850 #define PCI_HP_SBCR_133MHZ_PCIX_SPEED 0x4 851 #define PCI_HP_SBCR_SPEED_MASK 0x7 852 853 /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */ 854 #define PCI_HP_COMM_STS_ERR_INVALID_SPEED 0x80000 855 #define PCI_HP_COMM_STS_ERR_INVALID_COMMAND 0x40000 856 #define PCI_HP_COMM_STS_ERR_MRL_OPEN 0x20000 857 #define PCI_HP_COMM_STS_ERR_MASK 0xe0000 858 #define PCI_HP_COMM_STS_CTRL_BUSY 0x10000 859 #define PCI_HP_COMM_STS_SET_SPEED 0x40 860 861 /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */ 862 #define PCI_HP_SERR_INT_GLOBAL_IRQ_MASK 0x1 863 #define PCI_HP_SERR_INT_GLOBAL_SERR_MASK 0x2 864 #define PCI_HP_SERR_INT_CMD_COMPLETE_MASK 0x4 865 #define PCI_HP_SERR_INT_ARBITER_SERR_MASK 0x8 866 #define PCI_HP_SERR_INT_CMD_COMPLETE_IRQ 0x10000 867 #define PCI_HP_SERR_INT_ARBITER_IRQ 0x20000 868 #define PCI_HP_SERR_INT_MASK_ALL 0xf 869 870 /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */ 871 #define PCI_HP_SLOT_POWER_ONLY 0x1 872 #define PCI_HP_SLOT_ENABLED 0x2 873 #define PCI_HP_SLOT_DISABLED 0x3 874 #define PCI_HP_SLOT_STATE_MASK 0x3 875 #define PCI_HP_SLOT_MRL_STATE_MASK 0x100 876 #define PCI_HP_SLOT_66MHZ_CONV_CAPABLE 0x200 877 #define PCI_HP_SLOT_CARD_EMPTY_MASK 0xc00 878 #define PCI_HP_SLOT_66MHZ_PCIX_CAPABLE 0x1000 879 #define PCI_HP_SLOT_100MHZ_PCIX_CAPABLE 0x2000 880 #define PCI_HP_SLOT_133MHZ_PCIX_CAPABLE 0x3000 881 #define PCI_HP_SLOT_PCIX_CAPABLE_MASK 0x3000 882 #define PCI_HP_SLOT_PCIX_CAPABLE_SHIFT 12 883 #define PCI_HP_SLOT_PRESENCE_DETECTED 0x10000 884 #define PCI_HP_SLOT_ISO_PWR_DETECTED 0x20000 885 #define PCI_HP_SLOT_ATTN_DETECTED 0x40000 886 #define PCI_HP_SLOT_MRL_DETECTED 0x80000 887 #define PCI_HP_SLOT_POWER_DETECTED 0x100000 888 #define PCI_HP_SLOT_PRESENCE_MASK 0x1000000 889 #define PCI_HP_SLOT_ISO_PWR_MASK 0x2000000 890 #define PCI_HP_SLOT_ATTN_MASK 0x4000000 891 #define PCI_HP_SLOT_MRL_MASK 0x8000000 892 #define PCI_HP_SLOT_POWER_MASK 0x10000000 893 #define PCI_HP_SLOT_MRL_SERR_MASK 0x20000000 894 #define PCI_HP_SLOT_POWER_SERR_MASK 0x40000000 895 #define PCI_HP_SLOT_MASK_ALL 0x5f000000 896 897 /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */ 898 #define PCI_HP_IRQ_CMD_COMPLETE 0x1 899 #define PCI_HP_IRQ_SLOT_N_PENDING 0x2 900 901 /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */ 902 #define PCI_HP_IRQ_SERR_ARBITER_PENDING 0x1 903 #define PCI_HP_IRQ_SERR_SLOT_N_PENDING 0x2 904 905 /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */ 906 #define PCI_HP_SLOT_CONFIG_MRL_SENSOR 0x40000000 907 #define PCI_HP_SLOT_CONFIG_ATTN_BUTTON 0x80000000 908 #define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT 16 909 #define PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK 0x3FF 910 911 /* 912 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit 913 */ 914 #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */ 915 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */ 916 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */ 917 #define PCI_MSI_32BIT_EXTDATA 0x0A /* MSI 32-bit msg ext data, 2 bytes */ 918 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */ 919 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */ 920 921 /* 922 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit 923 */ 924 #define PCI_MSI_64BIT_ADDR 0x08 /* MSI 64-bit upper address, 4 bytes */ 925 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */ 926 #define PCI_MSI_64BIT_EXTDATA 0x0E /* MSI 64-bit msg ext data, 2 bytes */ 927 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */ 928 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */ 929 930 /* 931 * PCI Message Signalled Interrupts (MSI) capability masks and shifts 932 */ 933 #define PCI_MSI_ENABLE_BIT 0x0001 /* MSI enable mask in MSI ctrl reg */ 934 #define PCI_MSI_MMC_MASK 0x000E /* MMC mask in MSI ctrl reg */ 935 #define PCI_MSI_MMC_SHIFT 0x1 /* Shift for MMC bits */ 936 #define PCI_MSI_MME_MASK 0x0070 /* MME mask in MSI ctrl reg */ 937 #define PCI_MSI_MME_SHIFT 0x4 /* Shift for MME bits */ 938 #define PCI_MSI_64BIT_MASK 0x0080 /* 64bit support mask in MSI ctrl reg */ 939 #define PCI_MSI_PVM_MASK 0x0100 /* PVM support mask in MSI ctrl reg */ 940 #define PCI_MSI_EMD_MASK 0x0200 /* EMD Capable Mask */ 941 #define PCI_MSI_EMD_ENABLE 0x0400 /* EMD Enable bit */ 942 943 /* 944 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets 945 */ 946 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */ 947 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */ 948 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */ 949 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */ 950 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */ 951 952 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */ 953 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */ 954 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */ 955 956 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */ 957 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */ 958 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */ 959 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */ 960 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */ 961 962 /* 963 * PCI Message Signalled Interrupts: other interesting constants 964 */ 965 #define PCI_MSI_MAX_INTRS 32 /* maximum MSI interrupts supported */ 966 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */ 967 968 /* 969 * PCI Slot Id Capabilities, 2 bytes 970 */ 971 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */ 972 #define PCI_CAPSLOT_ESR_NSLOTS_MASK 0x1F /* Number of slots mask */ 973 #define PCI_CAPSLOT_ESR_FIC 0x20 /* First In Chassis bit */ 974 #define PCI_CAPSLOT_ESR_FIC_MASK 0x01 /* First In Chassis mask */ 975 #define PCI_CAPSLOT_ESR_FIC_SHIFT 5 /* First In Chassis shift */ 976 #define PCI_CAPSLOT_FIC(esr_reg) ((esr_reg) & PCI_CAPSLOT_ESR_FIC) 977 #define PCI_CAPSLOT_NSLOTS(esr_reg) ((esr_reg) & \ 978 PCI_CAPSLOT_ESR_NSLOTS_MASK) 979 980 /* 981 * HyperTransport Capabilities; each HT cap uses the same PCI cap id of 982 * PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT 983 * cap type reg at bits [15:11]. For Slave/Pri Interface and Host/Sec 984 * Interface types, only bits [15:13] are used. 985 */ 986 #define PCI_HTCAP_TYPE_MASK 0xF800 987 #define PCI_HTCAP_TYPE_SLHOST_MASK 0xE000 /* SLPRI and HOSTSEC types */ 988 #define PCI_HTCAP_TYPE_SHIFT 11 989 990 #define PCI_HTCAP_SLPRI_ID 0x00 991 #define PCI_HTCAP_HOSTSEC_ID 0x04 992 #define PCI_HTCAP_SWITCH_ID 0x08 993 #define PCI_HTCAP_INTCONF_ID 0x10 994 #define PCI_HTCAP_REVID_ID 0x11 995 #define PCI_HTCAP_UNITID_CLUMP_ID 0x12 996 #define PCI_HTCAP_ECFG_ID 0x13 997 #define PCI_HTCAP_ADDRMAP_ID 0x14 998 #define PCI_HTCAP_MSIMAP_ID 0x15 999 #define PCI_HTCAP_DIRROUTE_ID 0x16 1000 #define PCI_HTCAP_VCSET_ID 0x17 1001 #define PCI_HTCAP_RETRYMODE_ID 0x18 1002 #define PCI_HTCAP_X86ENC_ID 0x19 1003 #define PCI_HTCAP_GEN3_ID 0x1A 1004 #define PCI_HTCAP_FUNCEXT_ID 0x1B 1005 #define PCI_HTCAP_PM_ID 0x1C 1006 1007 #define PCI_HTCAP_SLPRI_TYPE /* 0x0000 */ \ 1008 (PCI_HTCAP_SLPRI_ID << PCI_HTCAP_TYPE_SHIFT) 1009 1010 #define PCI_HTCAP_HOSTSEC_TYPE /* 0x2000 */ \ 1011 (PCI_HTCAP_HOSTSEC_ID << PCI_HTCAP_TYPE_SHIFT) 1012 1013 #define PCI_HTCAP_SWITCH_TYPE /* 0x4000 */ \ 1014 (PCI_HTCAP_SWITCH_ID << PCI_HTCAP_TYPE_SHIFT) 1015 1016 #define PCI_HTCAP_INTCONF_TYPE /* 0x8000 */ \ 1017 (PCI_HTCAP_INTCONF_ID << PCI_HTCAP_TYPE_SHIFT) 1018 1019 #define PCI_HTCAP_REVID_TYPE /* 0x8800 */ \ 1020 (PCI_HTCAP_REVID_ID << PCI_HTCAP_TYPE_SHIFT) 1021 1022 #define PCI_HTCAP_UNITID_CLUMP_TYPE /* 0x9000 */ \ 1023 (PCI_HTCAP_UNITID_CLUMP_ID << PCI_HTCAP_TYPE_SHIFT) 1024 1025 #define PCI_HTCAP_ECFG_TYPE /* 0x9800 */ \ 1026 (PCI_HTCAP_ECFG_ID << PCI_HTCAP_TYPE_SHIFT) 1027 1028 #define PCI_HTCAP_ADDRMAP_TYPE /* 0xA000 */ \ 1029 (PCI_HTCAP_ADDRMAP_ID << PCI_HTCAP_TYPE_SHIFT) 1030 1031 #define PCI_HTCAP_MSIMAP_TYPE /* 0xA800 */ \ 1032 (PCI_HTCAP_MSIMAP_ID << PCI_HTCAP_TYPE_SHIFT) 1033 1034 #define PCI_HTCAP_DIRROUTE_TYPE /* 0xB000 */ \ 1035 (PCI_HTCAP_DIRROUTE_ID << PCI_HTCAP_TYPE_SHIFT) 1036 1037 #define PCI_HTCAP_VCSET_TYPE /* 0xB800 */ \ 1038 (PCI_HTCAP_VCSET_ID << PCI_HTCAP_TYPE_SHIFT) 1039 1040 #define PCI_HTCAP_RETRYMODE_TYPE /* 0xC000 */ \ 1041 (PCI_HTCAP_RETRYMODE_ID << PCI_HTCAP_TYPE_SHIFT) 1042 1043 #define PCI_HTCAP_X86ENC_TYPE /* 0xC800 */ \ 1044 (PCI_HTCAP_X86ENC_ID << PCI_HTCAP_TYPE_SHIFT) 1045 1046 #define PCI_HTCAP_GEN3_TYPE /* 0xD000 */ \ 1047 (PCI_HTCAP_GEN3_ID << PCI_HTCAP_TYPE_SHIFT) 1048 1049 #define PCI_HTCAP_FUNCEXT_TYPE /* 0xD800 */ \ 1050 (PCI_HTCAP_FUNCEXT_ID << PCI_HTCAP_TYPE_SHIFT) 1051 1052 #define PCI_HTCAP_PM_TYPE /* 0xE000 */ \ 1053 (PCI_HTCAP_PM_ID << PCI_HTCAP_TYPE_SHIFT) 1054 1055 #define PCI_HTCAP_MSIMAP_ENABLE 0x0001 1056 #define PCI_HTCAP_MSIMAP_ENABLE_MASK 0x0001 1057 1058 #define PCI_HTCAP_ADDRMAP_MAPTYPE_MASK 0x600 1059 #define PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT 9 1060 #define PCI_HTCAP_ADDRMAP_NUMMAP_MASK 0xF 1061 #define PCI_HTCAP_ADDRMAP_40BIT_ID 0x0 1062 #define PCI_HTCAP_ADDRMAP_64BIT_ID 0x1 1063 1064 #define PCI_HTCAP_FUNCEXT_LEN_MASK 0xFF 1065 1066 /* 1067 * PCI Bridge Subsystem Capability (PCI_CAP_ID_P2P_SUBSYS) 1068 */ 1069 #define PCI_SUBSYSCAP_SUBVID 0x4 1070 #define PCI_SUBSYSCAP_SUBSYS 0x6 1071 1072 /* 1073 * other interesting PCI constants 1074 */ 1075 #define PCI_BASE_NUM 6 /* num of base regs in configuration header */ 1076 #define PCI_BAR_SZ_32 4 /* size of 32 bit base addr reg in bytes */ 1077 #define PCI_BAR_SZ_64 8 /* size of 64 bit base addr reg in bytes */ 1078 #define PCI_BASE_SIZE 4 /* size of base reg in bytes */ 1079 #define PCI_CONF_HDR_SIZE 256 /* configuration header size */ 1080 #define PCI_MAX_BUS_NUM 256 /* Maximum PCI buses allowed */ 1081 #define PCI_MAX_DEVICES 32 /* Max PCI devices allowed */ 1082 #define PCI_MAX_FUNCTIONS 8 /* Max PCI functions allowed */ 1083 #define PCI_MAX_CHILDREN PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS 1084 #define PCI_CLK_33MHZ (33 * 1000 * 1000) /* 33MHz clock speed */ 1085 #define PCI_CLK_66MHZ (66 * 1000 * 1000) /* 66MHz clock speed */ 1086 #define PCI_CLK_133MHZ (133 * 1000 * 1000) /* 133MHz clock speed */ 1087 1088 /* 1089 * pci bus range definition 1090 */ 1091 typedef struct pci_bus_range { 1092 uint32_t lo; 1093 uint32_t hi; 1094 } pci_bus_range_t; 1095 1096 /* 1097 * The following typedef is used to represent an entry in the "ranges" 1098 * property of a pci hostbridge device node. 1099 */ 1100 typedef struct pci_ranges { 1101 uint32_t child_high; 1102 uint32_t child_mid; 1103 uint32_t child_low; 1104 uint32_t parent_high; 1105 uint32_t parent_low; 1106 uint32_t size_high; 1107 uint32_t size_low; 1108 } pci_ranges_t; 1109 1110 /* 1111 * The following typedef is used to represent an entry in the "ranges" 1112 * property of a pci-pci bridge device node. 1113 */ 1114 typedef struct { 1115 uint32_t child_high; 1116 uint32_t child_mid; 1117 uint32_t child_low; 1118 uint32_t parent_high; 1119 uint32_t parent_mid; 1120 uint32_t parent_low; 1121 uint32_t size_high; 1122 uint32_t size_low; 1123 } ppb_ranges_t; 1124 1125 /* 1126 * This structure represents one entry of the 1275 "reg" property and 1127 * "assigned-addresses" property for a PCI node. For the "reg" property, it 1128 * may be one of an arbitrary length array for devices with multiple address 1129 * windows. For the "assigned-addresses" property, it denotes an assigned 1130 * physical address on the PCI bus. It may be one entry of the six entries 1131 * for devices with multiple base registers. 1132 * 1133 * The physical address format is: 1134 * 1135 * Bit#: 33222222 22221111 11111100 00000000 1136 * 10987654 32109876 54321098 76543210 1137 * 1138 * pci_phys_hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 1139 * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 1140 * pci_phys_low cell: llllllll llllllll llllllll llllllll 1141 * 1142 * n is 0 if the address is relocatable, 1 otherwise 1143 * p is 1 if the addressable region is "prefetchable", 0 otherwise 1144 * t is 1 if the address is aliased (for non-relocatable I/O), below 1145 * 1MB (for mem), or below 64 KB (for relocatable I/O). 1146 * ss is the type code, denoting which address space 1147 * bbbbbbbb is the 8-bit bus number 1148 * ddddd is the 5-bit device number 1149 * fff is the 3-bit function number 1150 * rrrrrrrr is the 8-bit register number 1151 * should be zero for non-relocatable, when ss is 01, or 10 1152 * hh...hhh is the 32-bit unsigned number 1153 * ll...lll is the 32-bit unsigned number 1154 * 1155 * The physical size format is: 1156 * 1157 * pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 1158 * pci_size_low cell: llllllll llllllll llllllll llllllll 1159 * 1160 * hh...hhh is the 32-bit unsigned number 1161 * ll...lll is the 32-bit unsigned number 1162 */ 1163 struct pci_phys_spec { 1164 uint_t pci_phys_hi; /* child's address, hi word */ 1165 uint_t pci_phys_mid; /* child's address, middle word */ 1166 uint_t pci_phys_low; /* child's address, low word */ 1167 uint_t pci_size_hi; /* high word of size field */ 1168 uint_t pci_size_low; /* low word of size field */ 1169 }; 1170 1171 typedef struct pci_phys_spec pci_regspec_t; 1172 1173 /* 1174 * PCI masks for pci_phy_hi of PCI 1275 address cell. 1175 */ 1176 #define PCI_REG_REG_M 0xff /* register mask */ 1177 #define PCI_REG_FUNC_M 0x700 /* function mask */ 1178 #define PCI_REG_DEV_M 0xf800 /* device mask */ 1179 #define PCI_REG_BUS_M 0xff0000 /* bus number mask */ 1180 #define PCI_REG_ADDR_M 0x3000000 /* address space mask */ 1181 #define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */ 1182 #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */ 1183 #define PCI_REG_REL_M 0x80000000 /* relocation bit mask */ 1184 #define PCI_REG_BDFR_M 0xffffff /* bus, dev, func, reg mask */ 1185 #define PCI_REG_EXTREG_M 0xF0000000 /* extended config bits mask */ 1186 1187 #define PCI_REG_FUNC_SHIFT 8 /* Offset of function bits */ 1188 #define PCI_REG_DEV_SHIFT 11 /* Offset of device bits */ 1189 #define PCI_REG_BUS_SHIFT 16 /* Offset of bus bits */ 1190 #define PCI_REG_ADDR_SHIFT 24 /* Offset of address bits */ 1191 #define PCI_REG_EXTREG_SHIFT 28 /* Offset of ext. config bits */ 1192 1193 #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) 1194 #define PCI_REG_FUNC_G(x) (((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT) 1195 #define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT) 1196 #define PCI_REG_BUS_G(x) (((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT) 1197 #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) 1198 #define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M) 1199 1200 #define PCI_REG_MAKE_BDFR(b, d, f, r) ( \ 1201 (uint_t)(b) << PCI_REG_BUS_SHIFT | \ 1202 (uint_t)(d) << PCI_REG_DEV_SHIFT | \ 1203 (uint_t)(f) << PCI_REG_FUNC_SHIFT | (r)) 1204 1205 /* 1206 * PCI bit encodings of pci_phys_hi of PCI 1275 address cell. 1207 */ 1208 #define PCI_ADDR_MASK PCI_REG_ADDR_M 1209 #define PCI_ADDR_CONFIG 0x00000000 /* configuration address */ 1210 #define PCI_ADDR_IO 0x01000000 /* I/O address */ 1211 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */ 1212 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */ 1213 #define PCI_ALIAS_B PCI_REG_ALIAS_M /* aliased bit */ 1214 #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */ 1215 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */ 1216 #define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */ 1217 1218 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */ 1219 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */ 1220 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */ 1221 #define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */ 1222 #define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */ 1223 1224 /* 1225 * PCI Expansion ROM Header Format 1226 */ 1227 #define PCI_ROM_SIGNATURE 0x0 /* ROM Signature 0xaa55 */ 1228 #define PCI_ROM_ARCH_UNIQUE_START 0x2 /* Start of processor unique */ 1229 #define PCI_ROM_PCI_DATA_STRUCT_PTR 0x18 /* Ptr to PCI Data Structure */ 1230 1231 /* 1232 * PCI Data Structure 1233 * 1234 * The PCI Data Structure is located within the first 64KB 1235 * of the ROM image and must be DWORD aligned. 1236 */ 1237 #define PCI_PDS_SIGNATURE 0x0 /* Signature, the string 'PCIR' */ 1238 #define PCI_PDS_VENDOR_ID 0x4 /* Vendor Identification */ 1239 #define PCI_PDS_DEVICE_ID 0x6 /* Device Identification */ 1240 #define PCI_PDS_VPD_PTR 0x8 /* Pointer to Vital Product Data */ 1241 #define PCI_PDS_PDS_LENGTH 0xa /* PCI Data Structure Length */ 1242 #define PCI_PDS_PDS_REVISION 0xc /* PCI Data Structure Revision */ 1243 #define PCI_PDS_CLASS_CODE 0xd /* Class Code */ 1244 #define PCI_PDS_IMAGE_LENGTH 0x10 /* Image Length in 512 byte units */ 1245 #define PCI_PDS_CODE_REVISON 0x12 /* Revision Level of Code/Data */ 1246 #define PCI_PDS_CODE_TYPE 0x14 /* Code Type */ 1247 #define PCI_PDS_INDICATOR 0x15 /* Indicates if image is last in ROM */ 1248 1249 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */ 1250 #define PCI_PDS_CODE_TYPE_OPEN_FW 0x1 /* Open Firmware */ 1251 1252 /* 1253 * we recognize the non transparent bridge child nodes with the 1254 * following property. This is specific to an implementation only. 1255 * This property is specific to AP nodes only. 1256 */ 1257 #define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect" 1258 1259 /* 1260 * If a bridge device provides its own config space access services, 1261 * and supports a hotplug/hotswap bus below at any level, then 1262 * the following property must be defined for the node either by 1263 * the driver or the OBP. 1264 */ 1265 #define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect" 1266 1267 /* 1268 * PCI returns all 1s for an invalid read. 1269 */ 1270 #define PCI_EINVAL8 0xff 1271 #define PCI_EINVAL16 0xffff 1272 #define PCI_EINVAL32 0xffffffff 1273 1274 #ifdef __cplusplus 1275 } 1276 #endif 1277 1278 #endif /* _SYS_PCI_H */ 1279