1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXDMA_HW_H 27 #define _SYS_NXGE_NXGE_TXDMA_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 #include <nxge_hw.h> 35 36 #if !defined(_BIG_ENDIAN) 37 #define SWAP(X) (X) 38 #else 39 #define SWAP(X) \ 40 (((X >> 32) & 0x00000000ffffffff) | \ 41 ((X << 32) & 0xffffffff00000000)) 42 #endif 43 44 /* 45 * Partitioning Suport: same as those defined for the RX 46 */ 47 48 /* 49 * TDC: Partitioning Support 50 * (Each of the following registers is for each TDC) 51 */ 52 #define TX_LOG_REG_SIZE 512 53 #define TX_LOG_DMA_OFFSET(channel) (channel * TX_LOG_REG_SIZE) 54 55 #define TX_LOG_PAGE_VLD_REG (FZC_DMC + 0x40000) 56 #define TX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x40008) 57 #define TX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x40010) 58 #define TX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x40018) 59 #define TX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x40020) 60 #define TX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x40028) 61 #define TX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x40030) 62 #define TX_LOG_PAGE_HDL_REG (FZC_DMC + 0x40038) 63 64 /* Transmit Addressing Mode: Set to 1 to select 32-bit addressing mode */ 65 #define TX_ADDR_MD_REG (FZC_DMC + 0x45000) 66 67 #define TX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 68 #define TX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 69 #define TX_ADDR_MD_MASK 0x0000000000000001ULL 70 71 typedef union _tx_addr_md_t { 72 uint64_t value; 73 struct { 74 #if defined(_BIG_ENDIAN) 75 uint32_t hdw; 76 #endif 77 struct { 78 #if defined(_BIT_FIELDS_HTOL) 79 uint32_t res1_1:31; 80 uint32_t mode32:1; 81 #elif defined(_BIT_FIELDS_LTOH) 82 uint32_t mode32:1; 83 uint32_t res1_1:31; 84 #endif 85 } ldw; 86 #if !defined(_BIG_ENDIAN) 87 uint32_t hdw; 88 #endif 89 } bits; 90 } tx_addr_md_t, *p_tx_addr_md_t; 91 92 /* Transmit Packet Descriptor Structure */ 93 #define TX_PKT_DESC_SAD_SHIFT 0 /* bits 43:0 */ 94 #define TX_PKT_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL 95 #define TX_PKT_DESC_TR_LEN_SHIFT 44 /* bits 56:44 */ 96 #define TX_PKT_DESC_TR_LEN_MASK 0x01FFF00000000000ULL 97 #define TX_PKT_DESC_NUM_PTR_SHIFT 58 /* bits 61:58 */ 98 #define TX_PKT_DESC_NUM_PTR_MASK 0x3C00000000000000ULL 99 #define TX_PKT_DESC_MARK_SHIFT 62 /* bit 62 */ 100 #define TX_PKT_DESC_MARK 0x4000000000000000ULL 101 #define TX_PKT_DESC_MARK_MASK 0x4000000000000000ULL 102 #define TX_PKT_DESC_SOP_SHIFT 63 /* bit 63 */ 103 #define TX_PKT_DESC_SOP 0x8000000000000000ULL 104 #define TX_PKT_DESC_SOP_MASK 0x8000000000000000ULL 105 106 typedef union _tx_desc_t { 107 uint64_t value; 108 struct { 109 #if defined(_BIG_ENDIAN) 110 struct { 111 #if defined(_BIT_FIELDS_HTOL) 112 uint32_t sop:1; 113 uint32_t mark:1; 114 uint32_t num_ptr:4; 115 uint32_t res1:1; 116 uint32_t tr_len:13; 117 uint32_t sad:12; 118 119 #elif defined(_BIT_FIELDS_LTOH) 120 uint32_t sad:12; 121 uint32_t tr_len:13; 122 uint32_t res1:1; 123 uint32_t num_ptr:4; 124 uint32_t mark:1; 125 uint32_t sop:1; 126 127 #endif 128 } hdw; 129 #endif 130 struct { 131 #if defined(_BIT_FIELDS_HTOL) 132 uint32_t sad:32; 133 #elif defined(_BIT_FIELDS_LTOH) 134 uint32_t sad:32; 135 #endif 136 } ldw; 137 #if !defined(_BIG_ENDIAN) 138 struct { 139 140 #if defined(_BIT_FIELDS_HTOL) 141 uint32_t sop:1; 142 uint32_t mark:1; 143 uint32_t num_ptr:4; 144 uint32_t res1:1; 145 uint32_t tr_len:13; 146 uint32_t sad:12; 147 #elif defined(_BIT_FIELDS_LTOH) 148 uint32_t sad:12; 149 uint32_t tr_len:13; 150 uint32_t res1:1; 151 uint32_t num_ptr:4; 152 uint32_t mark:1; 153 uint32_t sop:1; 154 #endif 155 } hdw; 156 #endif 157 } bits; 158 } tx_desc_t, *p_tx_desc_t; 159 160 161 /* Transmit Ring Configuration (24 Channels) */ 162 #define TX_RNG_CFIG_REG (DMC + 0x40000) 163 #if OLD 164 #define TX_RING_HDH_REG (DMC + 0x40008) 165 #endif 166 #define TX_RING_HDL_REG (DMC + 0x40010) 167 #define TX_RING_KICK_REG (DMC + 0x40018) 168 #define TX_ENT_MSK_REG (DMC + 0x40020) 169 #define TX_CS_REG (DMC + 0x40028) 170 #define TXDMA_MBH_REG (DMC + 0x40030) 171 #define TXDMA_MBL_REG (DMC + 0x40038) 172 #define TX_DMA_PRE_ST_REG (DMC + 0x40040) 173 #define TX_RNG_ERR_LOGH_REG (DMC + 0x40048) 174 #define TX_RNG_ERR_LOGL_REG (DMC + 0x40050) 175 #define TDMC_INTR_DBG_REG (DMC + 0x40060) 176 #define TX_CS_DBG_REG (DMC + 0x40068) 177 178 /* Transmit Ring Configuration */ 179 #define TX_RNG_CFIG_STADDR_SHIFT 6 /* bits 18:6 */ 180 #define TX_RNG_CFIG_STADDR_MASK 0x000000000007FFC0ULL 181 #define TX_RNG_CFIG_ADDR_MASK 0x00000FFFFFFFFFC0ULL 182 #define TX_RNG_CFIG_STADDR_BASE_SHIFT 19 /* bits 43:19 */ 183 #define TX_RNG_CFIG_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 184 #define TX_RNG_CFIG_LEN_SHIFT 48 /* bits 60:48 */ 185 #define TX_RNG_CFIG_LEN_MASK 0xFFF8000000000000ULL 186 187 #define TX_RNG_HEAD_TAIL_SHIFT 3 188 #define TX_RNG_HEAD_TAIL_WRAP_SHIFT 19 189 190 typedef union _tx_rng_cfig_t { 191 uint64_t value; 192 struct { 193 #if defined(_BIG_ENDIAN) 194 struct { 195 #if defined(_BIT_FIELDS_HTOL) 196 uint32_t res2:3; 197 uint32_t len:13; 198 uint32_t res1:4; 199 uint32_t staddr_base:12; 200 #elif defined(_BIT_FIELDS_LTOH) 201 uint32_t staddr_base:12; 202 uint32_t res1:4; 203 uint32_t len:13; 204 uint32_t res2:3; 205 #endif 206 } hdw; 207 #endif 208 struct { 209 #if defined(_BIT_FIELDS_HTOL) 210 uint32_t staddr_base:13; 211 uint32_t staddr:13; 212 uint32_t res2:6; 213 #elif defined(_BIT_FIELDS_LTOH) 214 uint32_t res2:6; 215 uint32_t staddr:13; 216 uint32_t staddr_base:13; 217 #endif 218 } ldw; 219 #ifndef _BIG_ENDIAN 220 struct { 221 #if defined(_BIT_FIELDS_HTOL) 222 uint32_t res2:3; 223 uint32_t len:13; 224 uint32_t res1:4; 225 uint32_t staddr_base:12; 226 #elif defined(_BIT_FIELDS_LTOH) 227 uint32_t staddr_base:12; 228 uint32_t res1:4; 229 uint32_t len:13; 230 uint32_t res2:3; 231 #endif 232 } hdw; 233 #endif 234 } bits; 235 } tx_rng_cfig_t, *p_tx_rng_cfig_t; 236 237 /* Transmit Ring Head Low */ 238 #define TX_RING_HDL_SHIFT 3 /* bit 31:3 */ 239 #define TX_RING_HDL_MASK 0x00000000FFFFFFF8ULL 240 241 typedef union _tx_ring_hdl_t { 242 uint64_t value; 243 struct { 244 #if defined(_BIG_ENDIAN) 245 uint32_t hdw; 246 #endif 247 struct { 248 #if defined(_BIT_FIELDS_HTOL) 249 uint32_t res0:12; 250 uint32_t wrap:1; 251 uint32_t head:16; 252 uint32_t res2:3; 253 #elif defined(_BIT_FIELDS_LTOH) 254 uint32_t res2:3; 255 uint32_t head:16; 256 uint32_t wrap:1; 257 uint32_t res0:12; 258 #endif 259 } ldw; 260 #ifndef _BIG_ENDIAN 261 uint32_t hdw; 262 #endif 263 } bits; 264 } tx_ring_hdl_t, *p_tx_ring_hdl_t; 265 266 /* Transmit Ring Kick */ 267 #define TX_RING_KICK_TAIL_SHIFT 3 /* bit 43:3 */ 268 #define TX_RING_KICK_TAIL_MASK 0x000000FFFFFFFFFF8ULL 269 270 typedef union _tx_ring_kick_t { 271 uint64_t value; 272 struct { 273 #ifdef _BIG_ENDIAN 274 uint32_t hdw; 275 #endif 276 struct { 277 #if defined(_BIT_FIELDS_HTOL) 278 uint32_t res0:12; 279 uint32_t wrap:1; 280 uint32_t tail:16; 281 uint32_t res2:3; 282 #elif defined(_BIT_FIELDS_LTOH) 283 uint32_t res2:3; 284 uint32_t tail:16; 285 uint32_t wrap:1; 286 uint32_t res0:12; 287 #endif 288 } ldw; 289 #ifndef _BIG_ENDIAN 290 uint32_t hdw; 291 #endif 292 } bits; 293 } tx_ring_kick_t, *p_tx_ring_kick_t; 294 295 /* Transmit Event Mask (DMC + 0x40020) */ 296 #define TX_ENT_MSK_PKT_PRT_ERR_SHIFT 0 /* bit 0: 0 to flag */ 297 #define TX_ENT_MSK_PKT_PRT_ERR_MASK 0x0000000000000001ULL 298 #define TX_ENT_MSK_CONF_PART_ERR_SHIFT 1 /* bit 1: 0 to flag */ 299 #define TX_ENT_MSK_CONF_PART_ERR_MASK 0x0000000000000002ULL 300 #define TX_ENT_MSK_NACK_PKT_RD_SHIFT 2 /* bit 2: 0 to flag */ 301 #define TX_ENT_MSK_NACK_PKT_RD_MASK 0x0000000000000004ULL 302 #define TX_ENT_MSK_NACK_PREF_SHIFT 3 /* bit 3: 0 to flag */ 303 #define TX_ENT_MSK_NACK_PREF_MASK 0x0000000000000008ULL 304 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_SHIFT 4 /* bit 4: 0 to flag */ 305 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK 0x0000000000000010ULL 306 #define TX_ENT_MSK_TX_RING_OFLOW_SHIFT 5 /* bit 5: 0 to flag */ 307 #define TX_ENT_MSK_TX_RING_OFLOW_MASK 0x0000000000000020ULL 308 #define TX_ENT_MSK_PKT_SIZE_ERR_SHIFT 6 /* bit 6: 0 to flag */ 309 #define TX_ENT_MSK_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 310 #define TX_ENT_MSK_MBOX_ERR_SHIFT 7 /* bit 7: 0 to flag */ 311 #define TX_ENT_MSK_MBOX_ERR_MASK 0x0000000000000080ULL 312 #define TX_ENT_MSK_MK_SHIFT 15 /* bit 15: 0 to flag */ 313 #define TX_ENT_MSK_MK_MASK 0x0000000000008000ULL 314 #define TX_ENT_MSK_MK_ALL (TX_ENT_MSK_PKT_PRT_ERR_MASK | \ 315 TX_ENT_MSK_CONF_PART_ERR_MASK | \ 316 TX_ENT_MSK_NACK_PKT_RD_MASK | \ 317 TX_ENT_MSK_NACK_PREF_MASK | \ 318 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | \ 319 TX_ENT_MSK_TX_RING_OFLOW_MASK | \ 320 TX_ENT_MSK_PKT_SIZE_ERR_MASK | \ 321 TX_ENT_MSK_MBOX_ERR_MASK | \ 322 TX_ENT_MSK_MK_MASK) 323 324 325 typedef union _tx_dma_ent_msk_t { 326 uint64_t value; 327 struct { 328 #ifdef _BIG_ENDIAN 329 uint32_t hdw; 330 #endif 331 struct { 332 #if defined(_BIT_FIELDS_HTOL) 333 uint32_t res1_1:16; 334 uint32_t mk:1; 335 uint32_t res2:7; 336 uint32_t mbox_err:1; 337 uint32_t pkt_size_err:1; 338 uint32_t tx_ring_oflow:1; 339 uint32_t pref_buf_ecc_err:1; 340 uint32_t nack_pref:1; 341 uint32_t nack_pkt_rd:1; 342 uint32_t conf_part_err:1; 343 uint32_t pkt_prt_err:1; 344 #elif defined(_BIT_FIELDS_LTOH) 345 uint32_t pkt_prt_err:1; 346 uint32_t conf_part_err:1; 347 uint32_t nack_pkt_rd:1; 348 uint32_t nack_pref:1; 349 uint32_t pref_buf_ecc_err:1; 350 uint32_t tx_ring_oflow:1; 351 uint32_t pkt_size_err:1; 352 uint32_t mbox_err:1; 353 uint32_t res2:7; 354 uint32_t mk:1; 355 uint32_t res1_1:16; 356 #endif 357 } ldw; 358 #ifndef _BIG_ENDIAN 359 uint32_t hdw; 360 #endif 361 } bits; 362 } tx_dma_ent_msk_t, *p_tx_dma_ent_msk_t; 363 364 365 /* Transmit Control and Status (DMC + 0x40028) */ 366 #define TX_CS_PKT_PRT_ERR_SHIFT 0 /* RO, bit 0 */ 367 #define TX_CS_PKT_PRT_ERR_MASK 0x0000000000000001ULL 368 #define TX_CS_CONF_PART_ERR_SHIF 1 /* RO, bit 1 */ 369 #define TX_CS_CONF_PART_ERR_MASK 0x0000000000000002ULL 370 #define TX_CS_NACK_PKT_RD_SHIFT 2 /* RO, bit 2 */ 371 #define TX_CS_NACK_PKT_RD_MASK 0x0000000000000004ULL 372 #define TX_CS_PREF_SHIFT 3 /* RO, bit 3 */ 373 #define TX_CS_PREF_MASK 0x0000000000000008ULL 374 #define TX_CS_PREF_BUF_PAR_ERR_SHIFT 4 /* RO, bit 4 */ 375 #define TX_CS_PREF_BUF_PAR_ERR_MASK 0x0000000000000010ULL 376 #define TX_CS_RING_OFLOW_SHIFT 5 /* RO, bit 5 */ 377 #define TX_CS_RING_OFLOW_MASK 0x0000000000000020ULL 378 #define TX_CS_PKT_SIZE_ERR_SHIFT 6 /* RW, bit 6 */ 379 #define TX_CS_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 380 #define TX_CS_MMK_SHIFT 14 /* RC, bit 14 */ 381 #define TX_CS_MMK_MASK 0x0000000000004000ULL 382 #define TX_CS_MK_SHIFT 15 /* RCW1C, bit 15 */ 383 #define TX_CS_MK_MASK 0x0000000000008000ULL 384 #define TX_CS_SNG_SHIFT 27 /* RO, bit 27 */ 385 #define TX_CS_SNG_MASK 0x0000000008000000ULL 386 #define TX_CS_STOP_N_GO_SHIFT 28 /* RW, bit 28 */ 387 #define TX_CS_STOP_N_GO_MASK 0x0000000010000000ULL 388 #define TX_CS_MB_SHIFT 29 /* RO, bit 29 */ 389 #define TX_CS_MB_MASK 0x0000000020000000ULL 390 #define TX_CS_RST_STATE_SHIFT 30 /* Rw, bit 30 */ 391 #define TX_CS_RST_STATE_MASK 0x0000000040000000ULL 392 #define TX_CS_RST_SHIFT 31 /* Rw, bit 31 */ 393 #define TX_CS_RST_MASK 0x0000000080000000ULL 394 #define TX_CS_LASTMASK_SHIFT 32 /* RW, bit 43:32 */ 395 #define TX_CS_LASTMARK_MASK 0x00000FFF00000000ULL 396 #define TX_CS_PKT_CNT_SHIFT 48 /* RW, bit 59:48 */ 397 #define TX_CS_PKT_CNT_MASK 0x0FFF000000000000ULL 398 399 /* Trasnmit Control and Status */ 400 typedef union _tx_cs_t { 401 uint64_t value; 402 struct { 403 #ifdef _BIG_ENDIAN 404 struct { 405 #if defined(_BIT_FIELDS_HTOL) 406 uint32_t res1:4; 407 uint32_t pkt_cnt:12; 408 uint32_t res2:4; 409 uint32_t lastmark:12; 410 #elif defined(_BIT_FIELDS_LTOH) 411 uint32_t lastmark:12; 412 uint32_t res2:4; 413 uint32_t pkt_cnt:12; 414 uint32_t res1:4; 415 #endif 416 } hdw; 417 418 #endif 419 struct { 420 #if defined(_BIT_FIELDS_HTOL) 421 uint32_t rst:1; 422 uint32_t rst_state:1; 423 uint32_t mb:1; 424 uint32_t stop_n_go:1; 425 uint32_t sng_state:1; 426 uint32_t res1:11; 427 uint32_t mk:1; 428 uint32_t mmk:1; 429 uint32_t res2:6; 430 uint32_t mbox_err:1; 431 uint32_t pkt_size_err:1; 432 uint32_t tx_ring_oflow:1; 433 uint32_t pref_buf_par_err:1; 434 uint32_t nack_pref:1; 435 uint32_t nack_pkt_rd:1; 436 uint32_t conf_part_err:1; 437 uint32_t pkt_prt_err:1; 438 #elif defined(_BIT_FIELDS_LTOH) 439 uint32_t pkt_prt_err:1; 440 uint32_t conf_part_err:1; 441 uint32_t nack_pkt_rd:1; 442 uint32_t nack_pref:1; 443 uint32_t pref_buf_par_err:1; 444 uint32_t tx_ring_oflow:1; 445 uint32_t pkt_size_err:1; 446 uint32_t mbox_err:1; 447 uint32_t res2:6; 448 uint32_t mmk:1; 449 uint32_t mk:1; 450 uint32_t res1:11; 451 uint32_t sng_state:1; 452 uint32_t stop_n_go:1; 453 uint32_t mb:1; 454 uint32_t rst_state:1; 455 uint32_t rst:1; 456 #endif 457 } ldw; 458 #ifndef _BIG_ENDIAN 459 struct { 460 #if defined(_BIT_FIELDS_HTOL) 461 uint32_t res1:4; 462 uint32_t pkt_cnt:12; 463 uint32_t res2:4; 464 uint32_t lastmark:12; 465 #elif defined(_BIT_FIELDS_LTOH) 466 uint32_t lastmark:12; 467 uint32_t res2:4; 468 uint32_t pkt_cnt:12; 469 uint32_t res1:4; 470 #endif 471 } hdw; 472 473 #endif 474 } bits; 475 } tx_cs_t, *p_tx_cs_t; 476 477 /* Trasnmit Mailbox High (DMC + 0x40030) */ 478 #define TXDMA_MBH_SHIFT 0 /* bit 11:0 */ 479 #define TXDMA_MBH_ADDR_SHIFT 32 /* bit 43:32 */ 480 #define TXDMA_MBH_MASK 0x0000000000000FFFULL 481 482 typedef union _txdma_mbh_t { 483 uint64_t value; 484 struct { 485 #ifdef _BIG_ENDIAN 486 uint32_t hdw; 487 #endif 488 struct { 489 #if defined(_BIT_FIELDS_HTOL) 490 uint32_t res1_1:20; 491 uint32_t mbaddr:12; 492 493 #elif defined(_BIT_FIELDS_LTOH) 494 uint32_t mbaddr:12; 495 uint32_t res1_1:20; 496 #endif 497 } ldw; 498 #ifndef _BIG_ENDIAN 499 uint32_t hdw; 500 #endif 501 } bits; 502 } txdma_mbh_t, *p_txdma_mbh_t; 503 504 505 /* Trasnmit Mailbox Low (DMC + 0x40038) */ 506 #define TXDMA_MBL_SHIFT 6 /* bit 31:6 */ 507 #define TXDMA_MBL_MASK 0x00000000FFFFFFC0ULL 508 509 typedef union _txdma_mbl_t { 510 uint64_t value; 511 struct { 512 #ifdef _BIG_ENDIAN 513 uint32_t hdw; 514 #endif 515 struct { 516 #if defined(_BIT_FIELDS_HTOL) 517 uint32_t mbaddr:26; 518 uint32_t res2:6; 519 520 #elif defined(_BIT_FIELDS_LTOH) 521 uint32_t res2:6; 522 uint32_t mbaddr:26; 523 #endif 524 } ldw; 525 #ifndef _BIG_ENDIAN 526 uint32_t hdw; 527 #endif 528 } bits; 529 } txdma_mbl_t, *p_txdma_mbl_t; 530 531 /* Trasnmit Prefetch State High (DMC + 0x40040) */ 532 #define TX_DMA_PREF_ST_SHIFT 0 /* bit 5:0 */ 533 #define TX_DMA_PREF_ST_MASK 0x000000000000003FULL 534 535 typedef union _tx_dma_pre_st_t { 536 uint64_t value; 537 struct { 538 #ifdef _BIG_ENDIAN 539 uint32_t hdw; 540 #endif 541 struct { 542 #if defined(_BIT_FIELDS_HTOL) 543 uint32_t res1_1:13; 544 uint32_t shadow_hd:19; 545 #elif defined(_BIT_FIELDS_LTOH) 546 uint32_t shadow_hd:19; 547 uint32_t res1_1:13; 548 #endif 549 } ldw; 550 #ifndef _BIG_ENDIAN 551 uint32_t hdw; 552 #endif 553 } bits; 554 } tx_dma_pre_st_t, *p_tx_dma_pre_st_t; 555 556 /* Trasnmit Ring Error Log High (DMC + 0x40048) */ 557 #define TX_RNG_ERR_LOGH_ERR_ADDR_SHIFT 0 /* RO bit 11:0 */ 558 #define TX_RNG_ERR_LOGH_ERR_ADDR_MASK 0x0000000000000FFFULL 559 #define TX_RNG_ERR_LOGH_ADDR_SHIFT 32 560 #define TX_RNG_ERR_LOGH_ERRCODE_SHIFT 26 /* RO bit 29:26 */ 561 #define TX_RNG_ERR_LOGH_ERRCODE_MASK 0x000000003C000000ULL 562 #define TX_RNG_ERR_LOGH_MERR_SHIFT 30 /* RO bit 30 */ 563 #define TX_RNG_ERR_LOGH_MERR_MASK 0x0000000040000000ULL 564 #define TX_RNG_ERR_LOGH_ERR_SHIFT 31 /* RO bit 31 */ 565 #define TX_RNG_ERR_LOGH_ERR_MASK 0x0000000080000000ULL 566 567 /* Transmit Ring Error codes */ 568 #define TXDMA_RING_PKT_PRT_ERR 0 569 #define TXDMA_RING_CONF_PART_ERR 0x01 570 #define TXDMA_RING_NACK_PKT_ERR 0x02 571 #define TXDMA_RING_NACK_PREF_ERR 0x03 572 #define TXDMA_RING_PREF_BUF_PAR_ERR 0x04 573 #define TXDMA_RING_TX_RING_OFLOW_ERR 0x05 574 #define TXDMA_RING_PKT_SIZE_ERR 0x06 575 576 typedef union _tx_rng_err_logh_t { 577 uint64_t value; 578 struct { 579 #ifdef _BIG_ENDIAN 580 uint32_t hdw; 581 #endif 582 struct { 583 #if defined(_BIT_FIELDS_HTOL) 584 uint32_t err:1; 585 uint32_t merr:1; 586 uint32_t errcode:4; 587 uint32_t res2:14; 588 uint32_t err_addr:12; 589 #elif defined(_BIT_FIELDS_LTOH) 590 uint32_t err_addr:12; 591 uint32_t res2:14; 592 uint32_t errcode:4; 593 uint32_t merr:1; 594 uint32_t err:1; 595 596 #endif 597 } ldw; 598 #ifndef _BIG_ENDIAN 599 uint32_t hdw; 600 #endif 601 } bits; 602 } tx_rng_err_logh_t, *p_tx_rng_err_logh_t; 603 604 605 /* Trasnmit Ring Error Log Log (DMC + 0x40050) */ 606 #define TX_RNG_ERR_LOGL_ERR_ADDR_SHIFT 0 /* RO bit 31:0 */ 607 #define TX_RNG_ERR_LOGL_ERR_ADDR_MASK 0x00000000FFFFFFFFULL 608 609 typedef union _tx_rng_err_logl_t { 610 uint64_t value; 611 struct { 612 #ifdef _BIG_ENDIAN 613 uint32_t hdw; 614 #endif 615 struct { 616 #if defined(_BIT_FIELDS_HTOL) 617 uint32_t err_addr:32; 618 #elif defined(_BIT_FIELDS_LTOH) 619 uint32_t err_addr:32; 620 621 #endif 622 } ldw; 623 #ifndef _BIG_ENDIAN 624 uint32_t hdw; 625 #endif 626 } bits; 627 } tx_rng_err_logl_t, *p_tx_rng_err_logl_t; 628 629 /* 630 * TDMC_INTR_RBG_REG (DMC + 0x40060) 631 */ 632 typedef union _tdmc_intr_dbg_t { 633 uint64_t value; 634 struct { 635 #ifdef _BIG_ENDIAN 636 uint32_t hdw; 637 #endif 638 struct { 639 #if defined(_BIT_FIELDS_HTOL) 640 uint32_t res:16; 641 uint32_t mk:1; 642 uint32_t rsvd:7; 643 uint32_t mbox_err:1; 644 uint32_t pkt_size_err:1; 645 uint32_t tx_ring_oflow:1; 646 uint32_t pref_buf_par_err:1; 647 uint32_t nack_pref:1; 648 uint32_t nack_pkt_rd:1; 649 uint32_t conf_part_err:1; 650 uint32_t pkt_part_err:1; 651 #elif defined(_BIT_FIELDS_LTOH) 652 uint32_t pkt_part_err:1; 653 uint32_t conf_part_err:1; 654 uint32_t nack_pkt_rd:1; 655 uint32_t nack_pref:1; 656 uint32_t pref_buf_par_err:1; 657 uint32_t tx_ring_oflow:1; 658 uint32_t pkt_size_err:1; 659 uint32_t mbox_err:1; 660 uint32_t rsvd:7; 661 uint32_t mk:1; 662 uint32_t res:16; 663 #endif 664 } ldw; 665 #ifndef _BIG_ENDIAN 666 uint32_t hdw; 667 #endif 668 } bits; 669 } tdmc_intr_dbg_t, *p_tdmc_intr_dbg_t; 670 671 672 /* 673 * TX_CS_DBG (DMC + 0x40068) 674 */ 675 typedef union _tx_cs_dbg_t { 676 uint64_t value; 677 struct { 678 #ifdef _BIG_ENDIAN 679 struct { 680 #if defined(_BIT_FIELDS_HTOL) 681 uint32_t res1:4; 682 uint32_t pkt_cnt:12; 683 uint32_t res2:16; 684 #elif defined(_BIT_FIELDS_LTOH) 685 uint32_t res2:16; 686 uint32_t pkt_cnt:12; 687 uint32_t res1:4; 688 #endif 689 } hdw; 690 691 #endif 692 struct { 693 #if defined(_BIT_FIELDS_HTOL) 694 uint32_t rsvd:32; 695 #elif defined(_BIT_FIELDS_LTOH) 696 uint32_t rsvd:32; 697 698 #endif 699 } ldw; 700 701 #ifndef _BIG_ENDIAN 702 struct { 703 #if defined(_BIT_FIELDS_HTOL) 704 uint32_t res1:4; 705 uint32_t pkt_cnt:12; 706 uint32_t res2:16; 707 #elif defined(_BIT_FIELDS_LTOH) 708 uint32_t res2:16; 709 uint32_t pkt_cnt:12; 710 uint32_t res1:4; 711 #endif 712 } hdw; 713 714 #endif 715 } bits; 716 } tx_cs_dbg_t, *p_tx_cs_dbg_t; 717 718 #define TXDMA_MAILBOX_BYTE_LENGTH 64 719 #define TXDMA_MAILBOX_UNUSED 24 720 721 typedef struct _txdma_mailbox_t { 722 tx_cs_t tx_cs; /* 8 bytes */ 723 tx_dma_pre_st_t tx_dma_pre_st; /* 8 bytes */ 724 tx_ring_hdl_t tx_ring_hdl; /* 8 bytes */ 725 tx_ring_kick_t tx_ring_kick; /* 8 bytes */ 726 uint32_t tx_rng_err_logh; /* 4 bytes */ 727 uint32_t tx_rng_err_logl; /* 4 bytes */ 728 uint32_t resv[TXDMA_MAILBOX_UNUSED]; 729 } txdma_mailbox_t, *p_txdma_mailbox_t; 730 731 #if OLD 732 /* Transmit Ring Scheduler (per port) */ 733 #define TX_DMA_MAP_OFFSET(port) (port * 8 + TX_DMA_MAP_REG) 734 #define TX_DMA_MAP_PORT_OFFSET(port) (port * 8) 735 #define TX_DMA_MAP_REG (FZC_DMC + 0x50000) 736 #define TX_DMA_MAP0_REG (FZC_DMC + 0x50000) 737 #define TX_DMA_MAP1_REG (FZC_DMC + 0x50008) 738 #define TX_DMA_MAP2_REG (FZC_DMC + 0x50010) 739 #define TX_DMA_MAP3_REG (FZC_DMC + 0x50018) 740 741 #define TX_DMA_MAP_SHIFT 0 /* RO bit 31:0 */ 742 #define TX_DMA_MAPMASK 0x00000000FFFFFFFFULL 743 744 typedef union _tx_dma_map_t { 745 uint64_t value; 746 struct { 747 #ifdef _BIG_ENDIAN 748 uint32_t hdw; 749 #endif 750 struct { 751 #if defined(_BIT_FIELDS_HTOL) 752 uint32_t bind:32; 753 #elif defined(_BIT_FIELDS_LTOH) 754 uint32_t bind:32; 755 756 #endif 757 } ldw; 758 #ifndef _BIG_ENDIAN 759 uint32_t hdw; 760 #endif 761 } bits; 762 } tx_dma_map_t, *p_tx_dma_map_t; 763 #endif 764 765 #if OLD 766 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 767 #define DRR_WT_REG (FZC_DMC + 0x51000) 768 #define DRR_WT_SHIFT 0 /* RO bit 19:0 */ 769 #define DRR_WT_MASK 0x00000000000FFFFFULL 770 771 #define TXDMA_DRR_RNG_USE_OFFSET(channel) (channel * 16) 772 773 typedef union _drr_wt_t { 774 uint64_t value; 775 struct { 776 #ifdef _BIG_ENDIAN 777 uint32_t hdw; 778 #endif 779 struct { 780 #if defined(_BIT_FIELDS_HTOL) 781 uint32_t res1_1:12; 782 uint32_t wt:20; 783 #elif defined(_BIT_FIELDS_LTOH) 784 uint32_t wt:20; 785 uint32_t res1_1:12; 786 #endif 787 } ldw; 788 #ifndef _BIG_ENDIAN 789 uint32_t hdw; 790 #endif 791 } bits; 792 } drr_wt_t, *p_drr_wt_t; 793 #endif 794 795 #if OLD 796 797 /* Performance Monitoring (32 Channels) */ 798 #define TXRNG_USE_REG (FZC_DMC + 0x51008) 799 #define TXRNG_USE_CNT_SHIFT 0 /* RO bit 26:0 */ 800 #define TXRNG_USE_CNT_MASK 0x0000000007FFFFFFULL 801 #define TXRNG_USE_OFLOW_SHIFT 0 /* RO bit 27 */ 802 #define TXRNG_USE_OFLOW_MASK 0x0000000008000000ULL 803 804 typedef union _txrng_use_t { 805 uint64_t value; 806 struct { 807 #ifdef _BIG_ENDIAN 808 uint32_t hdw; 809 #endif 810 struct { 811 #if defined(_BIT_FIELDS_HTOL) 812 uint32_t res1_1:4; 813 uint32_t oflow:1; 814 uint32_t cnt:27; 815 #elif defined(_BIT_FIELDS_LTOH) 816 uint32_t cnt:27; 817 uint32_t oflow:1; 818 uint32_t res1_1:4; 819 820 #endif 821 } ldw; 822 #ifndef _BIG_ENDIAN 823 uint32_t hdw; 824 #endif 825 } bits; 826 } txrng_use_t, *p_txrng_use_t; 827 828 #endif 829 830 /* 831 * Internal Transmit Packet Format (16 bytes) 832 */ 833 #define TX_PKT_HEADER_SIZE 16 834 #define TX_MAX_GATHER_POINTERS 15 835 #define TX_GATHER_POINTERS_THRESHOLD 8 836 /* 837 * There is bugs in the hardware 838 * and max sfter len is changed from 4096 to 4076. 839 * 840 * Jumbo from 9500 to 9216 841 */ 842 #define TX_MAX_TRANSFER_LENGTH 4076 843 #define TX_JUMBO_MTU 9216 844 845 #define TX_PKT_HEADER_PAD_SHIFT 0 /* bit 2:0 */ 846 #define TX_PKT_HEADER_PAD_MASK 0x0000000000000007ULL 847 #define TX_PKT_HEADER_TOT_XFER_LEN_SHIFT 16 /* bit 16:29 */ 848 #define TX_PKT_HEADER_TOT_XFER_LEN_MASK 0x000000000000FFF8ULL 849 #define TX_PKT_HEADER_L4STUFF_SHIFT 32 /* bit 37:32 */ 850 #define TX_PKT_HEADER_L4STUFF_MASK 0x0000003F00000000ULL 851 #define TX_PKT_HEADER_L4START_SHIFT 40 /* bit 45:40 */ 852 #define TX_PKT_HEADER_L4START_MASK 0x00003F0000000000ULL 853 #define TX_PKT_HEADER_L3START_SHIFT 48 /* bit 45:40 */ 854 #define TX_PKT_HEADER_IHL_SHIFT 52 /* bit 52 */ 855 #define TX_PKT_HEADER_VLAN__SHIFT 56 /* bit 56 */ 856 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT 57 /* bit 57 */ 857 #define TX_PKT_HEADER_LLC_SHIFT 57 /* bit 57 */ 858 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SET 0x0200000000000000ULL 859 #define TX_PKT_HEADER_TCP_UDP_CRC32C_MASK 0x0200000000000000ULL 860 #define TX_PKT_HEADER_L4_PROTO_OP_SHIFT 2 /* bit 59:58 */ 861 #define TX_PKT_HEADER_L4_PROTO_OP_MASK 0x0C00000000000000ULL 862 #define TX_PKT_HEADER_V4_HDR_CS_SHIFT 60 /* bit 60 */ 863 #define TX_PKT_HEADER_V4_HDR_CS_SET 0x1000000000000000ULL 864 #define TX_PKT_HEADER_V4_HDR_CS_MASK 0x1000000000000000ULL 865 #define TX_PKT_HEADER_IP_VER_SHIFT 61 /* bit 61 */ 866 #define TX_PKT_HEADER_IP_VER_MASK 0x2000000000000000ULL 867 #define TX_PKT_HEADER_PKT_TYPE_SHIFT 62 /* bit 62 */ 868 #define TX_PKT_HEADER_PKT_TYPE_MASK 0x4000000000000000ULL 869 870 /* L4 Prototol Operations */ 871 #define TX_PKT_L4_PROTO_OP_NOP 0x00 872 #define TX_PKT_L4_PROTO_OP_FULL_L4_CSUM 0x01 873 #define TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM 0x02 874 #define TX_PKT_L4_PROTO_OP_SCTP_CRC32 0x04 875 876 /* Transmit Packet Types */ 877 #define TX_PKT_PKT_TYPE_NOP 0x00 878 #define TX_PKT_PKT_TYPE_TCP 0x01 879 #define TX_PKT_PKT_TYPE_UDP 0x02 880 #define TX_PKT_PKT_TYPE_SCTP 0x03 881 882 #define TX_CKSUM_EN_PKT_TYPE_TCP (1ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 883 #define TX_CKSUM_EN_PKT_TYPE_UDP (2ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 884 #define TX_CKSUM_EN_PKT_TYPE_NOOP (0ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 885 886 typedef union _tx_pkt_header_t { 887 uint64_t value; 888 struct { 889 struct { 890 #if defined(_BIT_FIELDS_HTOL) 891 uint32_t pad:3; 892 uint32_t resv2:13; 893 uint32_t tot_xfer_len:14; 894 uint32_t resv1:2; 895 #elif defined(_BIT_FIELDS_LTOH) 896 uint32_t pad:3; 897 uint32_t resv2:13; 898 uint32_t tot_xfer_len:14; 899 uint32_t resv1:2; 900 #endif 901 } ldw; 902 struct { 903 #if defined(_BIT_FIELDS_HTOL) 904 uint32_t l4stuff:6; 905 uint32_t resv3:2; 906 uint32_t l4start:6; 907 uint32_t resv2:2; 908 uint32_t l3start:4; 909 uint32_t ihl:4; 910 uint32_t vlan:1; 911 uint32_t llc:1; 912 uint32_t res1:3; 913 uint32_t ip_ver:1; 914 uint32_t cksum_en_pkt_type:2; 915 #elif defined(_BIT_FIELDS_LTOH) 916 uint32_t l4stuff:6; 917 uint32_t resv3:2; 918 uint32_t l4start:6; 919 uint32_t resv2:2; 920 uint32_t l3start:4; 921 uint32_t ihl:4; 922 uint32_t vlan:1; 923 uint32_t llc:1; 924 uint32_t res1:3; 925 uint32_t ip_ver:1; 926 uint32_t cksum_en_pkt_type:2; 927 #endif 928 } hdw; 929 } bits; 930 } tx_pkt_header_t, *p_tx_pkt_header_t; 931 932 typedef struct _tx_pkt_hdr_all_t { 933 tx_pkt_header_t pkthdr; 934 uint64_t reserved; 935 } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t; 936 937 /* Debug only registers */ 938 #define TDMC_INJ_PAR_ERR_REG (FZC_DMC + 0x45040) 939 #define TDMC_INJ_PAR_ERR_MASK 0x0000000000FFFFFFULL 940 #define TDMC_INJ_PAR_ERR_MASK_N2 0x000000000000FFFFULL 941 942 typedef union _tdmc_inj_par_err_t { 943 uint64_t value; 944 struct { 945 #ifdef _BIG_ENDIAN 946 uint32_t hdw; 947 #endif 948 struct { 949 #if defined(_BIT_FIELDS_HTOL) 950 uint32_t rsvc:8; 951 uint32_t inject_parity_error:24; 952 #elif defined(_BIT_FIELDS_LTOH) 953 uint32_t inject_parity_error:24; 954 uint32_t rsvc:8; 955 #endif 956 } ldw; 957 #ifndef _BIG_ENDIAN 958 uint32_t hdw; 959 #endif 960 } bits; 961 } tdmc_inj_par_err_t, *p_tdmc_inj_par_err_t; 962 963 typedef union _tdmc_inj_par_err_n2_t { 964 uint64_t value; 965 struct { 966 #ifdef _BIG_ENDIAN 967 uint32_t hdw; 968 #endif 969 struct { 970 #if defined(_BIT_FIELDS_HTOL) 971 uint32_t rsvc:16; 972 uint32_t inject_parity_error:16; 973 #elif defined(_BIT_FIELDS_LTOH) 974 uint32_t inject_parity_error:16; 975 uint32_t rsvc:16; 976 #endif 977 } ldw; 978 #ifndef _BIG_ENDIAN 979 uint32_t hdw; 980 #endif 981 } bits; 982 } tdmc_inj_par_err_n2_t, *p_tdmc_inj_par_err_n2_t; 983 984 #define TDMC_DBG_SEL_REG (FZC_DMC + 0x45080) 985 #define TDMC_DBG_SEL_MASK 0x000000000000003FULL 986 987 typedef union _tdmc_dbg_sel_t { 988 uint64_t value; 989 struct { 990 #ifdef _BIG_ENDIAN 991 uint32_t hdw; 992 #endif 993 struct { 994 #if defined(_BIT_FIELDS_HTOL) 995 uint32_t rsvc:26; 996 uint32_t dbg_sel:6; 997 #elif defined(_BIT_FIELDS_LTOH) 998 uint32_t dbg_sel:6; 999 uint32_t rsvc:26; 1000 #endif 1001 } ldw; 1002 #ifndef _BIG_ENDIAN 1003 uint32_t hdw; 1004 #endif 1005 } bits; 1006 } tdmc_dbg_sel_t, *p_tdmc_dbg_sel_t; 1007 1008 #define TDMC_TRAINING_REG (FZC_DMC + 0x45088) 1009 #define TDMC_TRAINING_MASK 0x00000000FFFFFFFFULL 1010 1011 typedef union _tdmc_training_t { 1012 uint64_t value; 1013 struct { 1014 #ifdef _BIG_ENDIAN 1015 uint32_t hdw; 1016 #endif 1017 struct { 1018 #if defined(_BIT_FIELDS_HTOL) 1019 uint32_t vec:32; 1020 #elif defined(_BIT_FIELDS_LTOH) 1021 uint32_t vec:6; 1022 #endif 1023 } ldw; 1024 #ifndef _BIG_ENDIAN 1025 uint32_t hdw; 1026 #endif 1027 } bits; 1028 } tdmc_training_t, *p_tdmc_training_t; 1029 1030 #ifdef __cplusplus 1031 } 1032 #endif 1033 1034 #endif /* _SYS_NXGE_NXGE_TXDMA_HW_H */ 1035