1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXDMA_HW_H 27 #define _SYS_NXGE_NXGE_TXDMA_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 #include <nxge_hw.h> 37 38 #if !defined(_BIG_ENDIAN) 39 #define SWAP(X) (X) 40 #else 41 #define SWAP(X) \ 42 (((X >> 32) & 0x00000000ffffffff) | \ 43 ((X << 32) & 0xffffffff00000000)) 44 #endif 45 46 /* 47 * Partitioning Suport: same as those defined for the RX 48 */ 49 50 /* 51 * TDC: Partitioning Support 52 * (Each of the following registers is for each TDC) 53 */ 54 #define TX_LOG_REG_SIZE 512 55 #define TX_LOG_DMA_OFFSET(channel) (channel * TX_LOG_REG_SIZE) 56 57 #define TX_LOG_PAGE_VLD_REG (FZC_DMC + 0x40000) 58 #define TX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x40008) 59 #define TX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x40010) 60 #define TX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x40018) 61 #define TX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x40020) 62 #define TX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x40028) 63 #define TX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x40030) 64 #define TX_LOG_PAGE_HDL_REG (FZC_DMC + 0x40038) 65 66 /* Transmit Addressing Mode: Set to 1 to select 32-bit addressing mode */ 67 #define TX_ADDR_MD_REG (FZC_DMC + 0x45000) 68 69 #define TX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 70 #define TX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 71 #define TX_ADDR_MD_MASK 0x0000000000000001ULL 72 73 typedef union _tx_addr_md_t { 74 uint64_t value; 75 struct { 76 #if defined(_BIG_ENDIAN) 77 uint32_t hdw; 78 #endif 79 struct { 80 #if defined(_BIT_FIELDS_HTOL) 81 uint32_t res1_1:31; 82 uint32_t mode32:1; 83 #elif defined(_BIT_FIELDS_LTOH) 84 uint32_t mode32:1; 85 uint32_t res1_1:31; 86 #endif 87 } ldw; 88 #if !defined(_BIG_ENDIAN) 89 uint32_t hdw; 90 #endif 91 } bits; 92 } tx_addr_md_t, *p_tx_addr_md_t; 93 94 /* Transmit Packet Descriptor Structure */ 95 #define TX_PKT_DESC_SAD_SHIFT 0 /* bits 43:0 */ 96 #define TX_PKT_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL 97 #define TX_PKT_DESC_TR_LEN_SHIFT 44 /* bits 56:44 */ 98 #define TX_PKT_DESC_TR_LEN_MASK 0x01FFF00000000000ULL 99 #define TX_PKT_DESC_NUM_PTR_SHIFT 58 /* bits 61:58 */ 100 #define TX_PKT_DESC_NUM_PTR_MASK 0x3C00000000000000ULL 101 #define TX_PKT_DESC_MARK_SHIFT 62 /* bit 62 */ 102 #define TX_PKT_DESC_MARK 0x4000000000000000ULL 103 #define TX_PKT_DESC_MARK_MASK 0x4000000000000000ULL 104 #define TX_PKT_DESC_SOP_SHIFT 63 /* bit 63 */ 105 #define TX_PKT_DESC_SOP 0x8000000000000000ULL 106 #define TX_PKT_DESC_SOP_MASK 0x8000000000000000ULL 107 108 typedef union _tx_desc_t { 109 uint64_t value; 110 struct { 111 #if defined(_BIG_ENDIAN) 112 struct { 113 #if defined(_BIT_FIELDS_HTOL) 114 uint32_t sop:1; 115 uint32_t mark:1; 116 uint32_t num_ptr:4; 117 uint32_t res1:1; 118 uint32_t tr_len:13; 119 uint32_t sad:12; 120 121 #elif defined(_BIT_FIELDS_LTOH) 122 uint32_t sad:12; 123 uint32_t tr_len:13; 124 uint32_t res1:1; 125 uint32_t num_ptr:4; 126 uint32_t mark:1; 127 uint32_t sop:1; 128 129 #endif 130 } hdw; 131 #endif 132 struct { 133 #if defined(_BIT_FIELDS_HTOL) 134 uint32_t sad:32; 135 #elif defined(_BIT_FIELDS_LTOH) 136 uint32_t sad:32; 137 #endif 138 } ldw; 139 #if !defined(_BIG_ENDIAN) 140 struct { 141 142 #if defined(_BIT_FIELDS_HTOL) 143 uint32_t sop:1; 144 uint32_t mark:1; 145 uint32_t num_ptr:4; 146 uint32_t res1:1; 147 uint32_t tr_len:13; 148 uint32_t sad:12; 149 #elif defined(_BIT_FIELDS_LTOH) 150 uint32_t sad:12; 151 uint32_t tr_len:13; 152 uint32_t res1:1; 153 uint32_t num_ptr:4; 154 uint32_t mark:1; 155 uint32_t sop:1; 156 #endif 157 } hdw; 158 #endif 159 } bits; 160 } tx_desc_t, *p_tx_desc_t; 161 162 163 /* Transmit Ring Configuration (24 Channels) */ 164 #define TX_RNG_CFIG_REG (DMC + 0x40000) 165 #if OLD 166 #define TX_RING_HDH_REG (DMC + 0x40008) 167 #endif 168 #define TX_RING_HDL_REG (DMC + 0x40010) 169 #define TX_RING_KICK_REG (DMC + 0x40018) 170 #define TX_ENT_MSK_REG (DMC + 0x40020) 171 #define TX_CS_REG (DMC + 0x40028) 172 #define TXDMA_MBH_REG (DMC + 0x40030) 173 #define TXDMA_MBL_REG (DMC + 0x40038) 174 #define TX_DMA_PRE_ST_REG (DMC + 0x40040) 175 #define TX_RNG_ERR_LOGH_REG (DMC + 0x40048) 176 #define TX_RNG_ERR_LOGL_REG (DMC + 0x40050) 177 #define TDMC_INTR_DBG_REG (DMC + 0x40060) 178 #define TX_CS_DBG_REG (DMC + 0x40068) 179 180 /* Transmit Ring Configuration */ 181 #define TX_RNG_CFIG_STADDR_SHIFT 6 /* bits 18:6 */ 182 #define TX_RNG_CFIG_STADDR_MASK 0x000000000007FFC0ULL 183 #define TX_RNG_CFIG_ADDR_MASK 0x00000FFFFFFFFFC0ULL 184 #define TX_RNG_CFIG_STADDR_BASE_SHIFT 19 /* bits 43:19 */ 185 #define TX_RNG_CFIG_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 186 #define TX_RNG_CFIG_LEN_SHIFT 48 /* bits 60:48 */ 187 #define TX_RNG_CFIG_LEN_MASK 0xFFF8000000000000ULL 188 189 #define TX_RNG_HEAD_TAIL_SHIFT 3 190 #define TX_RNG_HEAD_TAIL_WRAP_SHIFT 19 191 192 typedef union _tx_rng_cfig_t { 193 uint64_t value; 194 struct { 195 #if defined(_BIG_ENDIAN) 196 struct { 197 #if defined(_BIT_FIELDS_HTOL) 198 uint32_t res2:3; 199 uint32_t len:13; 200 uint32_t res1:4; 201 uint32_t staddr_base:12; 202 #elif defined(_BIT_FIELDS_LTOH) 203 uint32_t staddr_base:12; 204 uint32_t res1:4; 205 uint32_t len:13; 206 uint32_t res2:3; 207 #endif 208 } hdw; 209 #endif 210 struct { 211 #if defined(_BIT_FIELDS_HTOL) 212 uint32_t staddr_base:13; 213 uint32_t staddr:13; 214 uint32_t res2:6; 215 #elif defined(_BIT_FIELDS_LTOH) 216 uint32_t res2:6; 217 uint32_t staddr:13; 218 uint32_t staddr_base:13; 219 #endif 220 } ldw; 221 #ifndef _BIG_ENDIAN 222 struct { 223 #if defined(_BIT_FIELDS_HTOL) 224 uint32_t res2:3; 225 uint32_t len:13; 226 uint32_t res1:4; 227 uint32_t staddr_base:12; 228 #elif defined(_BIT_FIELDS_LTOH) 229 uint32_t staddr_base:12; 230 uint32_t res1:4; 231 uint32_t len:13; 232 uint32_t res2:3; 233 #endif 234 } hdw; 235 #endif 236 } bits; 237 } tx_rng_cfig_t, *p_tx_rng_cfig_t; 238 239 /* Transmit Ring Head Low */ 240 #define TX_RING_HDL_SHIFT 3 /* bit 31:3 */ 241 #define TX_RING_HDL_MASK 0x00000000FFFFFFF8ULL 242 243 typedef union _tx_ring_hdl_t { 244 uint64_t value; 245 struct { 246 #if defined(_BIG_ENDIAN) 247 uint32_t hdw; 248 #endif 249 struct { 250 #if defined(_BIT_FIELDS_HTOL) 251 uint32_t res0:12; 252 uint32_t wrap:1; 253 uint32_t head:16; 254 uint32_t res2:3; 255 #elif defined(_BIT_FIELDS_LTOH) 256 uint32_t res2:3; 257 uint32_t head:16; 258 uint32_t wrap:1; 259 uint32_t res0:12; 260 #endif 261 } ldw; 262 #ifndef _BIG_ENDIAN 263 uint32_t hdw; 264 #endif 265 } bits; 266 } tx_ring_hdl_t, *p_tx_ring_hdl_t; 267 268 /* Transmit Ring Kick */ 269 #define TX_RING_KICK_TAIL_SHIFT 3 /* bit 43:3 */ 270 #define TX_RING_KICK_TAIL_MASK 0x000000FFFFFFFFFF8ULL 271 272 typedef union _tx_ring_kick_t { 273 uint64_t value; 274 struct { 275 #ifdef _BIG_ENDIAN 276 uint32_t hdw; 277 #endif 278 struct { 279 #if defined(_BIT_FIELDS_HTOL) 280 uint32_t res0:12; 281 uint32_t wrap:1; 282 uint32_t tail:16; 283 uint32_t res2:3; 284 #elif defined(_BIT_FIELDS_LTOH) 285 uint32_t res2:3; 286 uint32_t tail:16; 287 uint32_t wrap:1; 288 uint32_t res0:12; 289 #endif 290 } ldw; 291 #ifndef _BIG_ENDIAN 292 uint32_t hdw; 293 #endif 294 } bits; 295 } tx_ring_kick_t, *p_tx_ring_kick_t; 296 297 /* Transmit Event Mask (DMC + 0x40020) */ 298 #define TX_ENT_MSK_PKT_PRT_ERR_SHIFT 0 /* bit 0: 0 to flag */ 299 #define TX_ENT_MSK_PKT_PRT_ERR_MASK 0x0000000000000001ULL 300 #define TX_ENT_MSK_CONF_PART_ERR_SHIFT 1 /* bit 1: 0 to flag */ 301 #define TX_ENT_MSK_CONF_PART_ERR_MASK 0x0000000000000002ULL 302 #define TX_ENT_MSK_NACK_PKT_RD_SHIFT 2 /* bit 2: 0 to flag */ 303 #define TX_ENT_MSK_NACK_PKT_RD_MASK 0x0000000000000004ULL 304 #define TX_ENT_MSK_NACK_PREF_SHIFT 3 /* bit 3: 0 to flag */ 305 #define TX_ENT_MSK_NACK_PREF_MASK 0x0000000000000008ULL 306 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_SHIFT 4 /* bit 4: 0 to flag */ 307 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK 0x0000000000000010ULL 308 #define TX_ENT_MSK_TX_RING_OFLOW_SHIFT 5 /* bit 5: 0 to flag */ 309 #define TX_ENT_MSK_TX_RING_OFLOW_MASK 0x0000000000000020ULL 310 #define TX_ENT_MSK_PKT_SIZE_ERR_SHIFT 6 /* bit 6: 0 to flag */ 311 #define TX_ENT_MSK_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 312 #define TX_ENT_MSK_MBOX_ERR_SHIFT 7 /* bit 7: 0 to flag */ 313 #define TX_ENT_MSK_MBOX_ERR_MASK 0x0000000000000080ULL 314 #define TX_ENT_MSK_MK_SHIFT 15 /* bit 15: 0 to flag */ 315 #define TX_ENT_MSK_MK_MASK 0x0000000000008000ULL 316 #define TX_ENT_MSK_MK_ALL (TX_ENT_MSK_PKT_PRT_ERR_MASK | \ 317 TX_ENT_MSK_CONF_PART_ERR_MASK | \ 318 TX_ENT_MSK_NACK_PKT_RD_MASK | \ 319 TX_ENT_MSK_NACK_PREF_MASK | \ 320 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | \ 321 TX_ENT_MSK_TX_RING_OFLOW_MASK | \ 322 TX_ENT_MSK_PKT_SIZE_ERR_MASK | \ 323 TX_ENT_MSK_MBOX_ERR_MASK | \ 324 TX_ENT_MSK_MK_MASK) 325 326 327 typedef union _tx_dma_ent_msk_t { 328 uint64_t value; 329 struct { 330 #ifdef _BIG_ENDIAN 331 uint32_t hdw; 332 #endif 333 struct { 334 #if defined(_BIT_FIELDS_HTOL) 335 uint32_t res1_1:16; 336 uint32_t mk:1; 337 uint32_t res2:7; 338 uint32_t mbox_err:1; 339 uint32_t pkt_size_err:1; 340 uint32_t tx_ring_oflow:1; 341 uint32_t pref_buf_ecc_err:1; 342 uint32_t nack_pref:1; 343 uint32_t nack_pkt_rd:1; 344 uint32_t conf_part_err:1; 345 uint32_t pkt_prt_err:1; 346 #elif defined(_BIT_FIELDS_LTOH) 347 uint32_t pkt_prt_err:1; 348 uint32_t conf_part_err:1; 349 uint32_t nack_pkt_rd:1; 350 uint32_t nack_pref:1; 351 uint32_t pref_buf_ecc_err:1; 352 uint32_t tx_ring_oflow:1; 353 uint32_t pkt_size_err:1; 354 uint32_t mbox_err:1; 355 uint32_t res2:7; 356 uint32_t mk:1; 357 uint32_t res1_1:16; 358 #endif 359 } ldw; 360 #ifndef _BIG_ENDIAN 361 uint32_t hdw; 362 #endif 363 } bits; 364 } tx_dma_ent_msk_t, *p_tx_dma_ent_msk_t; 365 366 367 /* Transmit Control and Status (DMC + 0x40028) */ 368 #define TX_CS_PKT_PRT_ERR_SHIFT 0 /* RO, bit 0 */ 369 #define TX_CS_PKT_PRT_ERR_MASK 0x0000000000000001ULL 370 #define TX_CS_CONF_PART_ERR_SHIF 1 /* RO, bit 1 */ 371 #define TX_CS_CONF_PART_ERR_MASK 0x0000000000000002ULL 372 #define TX_CS_NACK_PKT_RD_SHIFT 2 /* RO, bit 2 */ 373 #define TX_CS_NACK_PKT_RD_MASK 0x0000000000000004ULL 374 #define TX_CS_PREF_SHIFT 3 /* RO, bit 3 */ 375 #define TX_CS_PREF_MASK 0x0000000000000008ULL 376 #define TX_CS_PREF_BUF_PAR_ERR_SHIFT 4 /* RO, bit 4 */ 377 #define TX_CS_PREF_BUF_PAR_ERR_MASK 0x0000000000000010ULL 378 #define TX_CS_RING_OFLOW_SHIFT 5 /* RO, bit 5 */ 379 #define TX_CS_RING_OFLOW_MASK 0x0000000000000020ULL 380 #define TX_CS_PKT_SIZE_ERR_SHIFT 6 /* RW, bit 6 */ 381 #define TX_CS_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 382 #define TX_CS_MMK_SHIFT 14 /* RC, bit 14 */ 383 #define TX_CS_MMK_MASK 0x0000000000004000ULL 384 #define TX_CS_MK_SHIFT 15 /* RCW1C, bit 15 */ 385 #define TX_CS_MK_MASK 0x0000000000008000ULL 386 #define TX_CS_SNG_SHIFT 27 /* RO, bit 27 */ 387 #define TX_CS_SNG_MASK 0x0000000008000000ULL 388 #define TX_CS_STOP_N_GO_SHIFT 28 /* RW, bit 28 */ 389 #define TX_CS_STOP_N_GO_MASK 0x0000000010000000ULL 390 #define TX_CS_MB_SHIFT 29 /* RO, bit 29 */ 391 #define TX_CS_MB_MASK 0x0000000020000000ULL 392 #define TX_CS_RST_STATE_SHIFT 30 /* Rw, bit 30 */ 393 #define TX_CS_RST_STATE_MASK 0x0000000040000000ULL 394 #define TX_CS_RST_SHIFT 31 /* Rw, bit 31 */ 395 #define TX_CS_RST_MASK 0x0000000080000000ULL 396 #define TX_CS_LASTMASK_SHIFT 32 /* RW, bit 43:32 */ 397 #define TX_CS_LASTMARK_MASK 0x00000FFF00000000ULL 398 #define TX_CS_PKT_CNT_SHIFT 48 /* RW, bit 59:48 */ 399 #define TX_CS_PKT_CNT_MASK 0x0FFF000000000000ULL 400 401 /* Trasnmit Control and Status */ 402 typedef union _tx_cs_t { 403 uint64_t value; 404 struct { 405 #ifdef _BIG_ENDIAN 406 struct { 407 #if defined(_BIT_FIELDS_HTOL) 408 uint32_t res1:4; 409 uint32_t pkt_cnt:12; 410 uint32_t res2:4; 411 uint32_t lastmark:12; 412 #elif defined(_BIT_FIELDS_LTOH) 413 uint32_t lastmark:12; 414 uint32_t res2:4; 415 uint32_t pkt_cnt:12; 416 uint32_t res1:4; 417 #endif 418 } hdw; 419 420 #endif 421 struct { 422 #if defined(_BIT_FIELDS_HTOL) 423 uint32_t rst:1; 424 uint32_t rst_state:1; 425 uint32_t mb:1; 426 uint32_t stop_n_go:1; 427 uint32_t sng_state:1; 428 uint32_t res1:11; 429 uint32_t mk:1; 430 uint32_t mmk:1; 431 uint32_t res2:6; 432 uint32_t mbox_err:1; 433 uint32_t pkt_size_err:1; 434 uint32_t tx_ring_oflow:1; 435 uint32_t pref_buf_par_err:1; 436 uint32_t nack_pref:1; 437 uint32_t nack_pkt_rd:1; 438 uint32_t conf_part_err:1; 439 uint32_t pkt_prt_err:1; 440 #elif defined(_BIT_FIELDS_LTOH) 441 uint32_t pkt_prt_err:1; 442 uint32_t conf_part_err:1; 443 uint32_t nack_pkt_rd:1; 444 uint32_t nack_pref:1; 445 uint32_t pref_buf_par_err:1; 446 uint32_t tx_ring_oflow:1; 447 uint32_t pkt_size_err:1; 448 uint32_t mbox_err:1; 449 uint32_t res2:6; 450 uint32_t mmk:1; 451 uint32_t mk:1; 452 uint32_t res1:11; 453 uint32_t sng_state:1; 454 uint32_t stop_n_go:1; 455 uint32_t mb:1; 456 uint32_t rst_state:1; 457 uint32_t rst:1; 458 #endif 459 } ldw; 460 #ifndef _BIG_ENDIAN 461 struct { 462 #if defined(_BIT_FIELDS_HTOL) 463 uint32_t res1:4; 464 uint32_t pkt_cnt:12; 465 uint32_t res2:4; 466 uint32_t lastmark:12; 467 #elif defined(_BIT_FIELDS_LTOH) 468 uint32_t lastmark:12; 469 uint32_t res2:4; 470 uint32_t pkt_cnt:12; 471 uint32_t res1:4; 472 #endif 473 } hdw; 474 475 #endif 476 } bits; 477 } tx_cs_t, *p_tx_cs_t; 478 479 /* Trasnmit Mailbox High (DMC + 0x40030) */ 480 #define TXDMA_MBH_SHIFT 0 /* bit 11:0 */ 481 #define TXDMA_MBH_ADDR_SHIFT 32 /* bit 43:32 */ 482 #define TXDMA_MBH_MASK 0x0000000000000FFFULL 483 484 typedef union _txdma_mbh_t { 485 uint64_t value; 486 struct { 487 #ifdef _BIG_ENDIAN 488 uint32_t hdw; 489 #endif 490 struct { 491 #if defined(_BIT_FIELDS_HTOL) 492 uint32_t res1_1:20; 493 uint32_t mbaddr:12; 494 495 #elif defined(_BIT_FIELDS_LTOH) 496 uint32_t mbaddr:12; 497 uint32_t res1_1:20; 498 #endif 499 } ldw; 500 #ifndef _BIG_ENDIAN 501 uint32_t hdw; 502 #endif 503 } bits; 504 } txdma_mbh_t, *p_txdma_mbh_t; 505 506 507 /* Trasnmit Mailbox Low (DMC + 0x40038) */ 508 #define TXDMA_MBL_SHIFT 6 /* bit 31:6 */ 509 #define TXDMA_MBL_MASK 0x00000000FFFFFFC0ULL 510 511 typedef union _txdma_mbl_t { 512 uint64_t value; 513 struct { 514 #ifdef _BIG_ENDIAN 515 uint32_t hdw; 516 #endif 517 struct { 518 #if defined(_BIT_FIELDS_HTOL) 519 uint32_t mbaddr:26; 520 uint32_t res2:6; 521 522 #elif defined(_BIT_FIELDS_LTOH) 523 uint32_t res2:6; 524 uint32_t mbaddr:26; 525 #endif 526 } ldw; 527 #ifndef _BIG_ENDIAN 528 uint32_t hdw; 529 #endif 530 } bits; 531 } txdma_mbl_t, *p_txdma_mbl_t; 532 533 /* Trasnmit Prefetch State High (DMC + 0x40040) */ 534 #define TX_DMA_PREF_ST_SHIFT 0 /* bit 5:0 */ 535 #define TX_DMA_PREF_ST_MASK 0x000000000000003FULL 536 537 typedef union _tx_dma_pre_st_t { 538 uint64_t value; 539 struct { 540 #ifdef _BIG_ENDIAN 541 uint32_t hdw; 542 #endif 543 struct { 544 #if defined(_BIT_FIELDS_HTOL) 545 uint32_t res1_1:13; 546 uint32_t shadow_hd:19; 547 #elif defined(_BIT_FIELDS_LTOH) 548 uint32_t shadow_hd:19; 549 uint32_t res1_1:13; 550 #endif 551 } ldw; 552 #ifndef _BIG_ENDIAN 553 uint32_t hdw; 554 #endif 555 } bits; 556 } tx_dma_pre_st_t, *p_tx_dma_pre_st_t; 557 558 /* Trasnmit Ring Error Log High (DMC + 0x40048) */ 559 #define TX_RNG_ERR_LOGH_ERR_ADDR_SHIFT 0 /* RO bit 11:0 */ 560 #define TX_RNG_ERR_LOGH_ERR_ADDR_MASK 0x0000000000000FFFULL 561 #define TX_RNG_ERR_LOGH_ADDR_SHIFT 32 562 #define TX_RNG_ERR_LOGH_ERRCODE_SHIFT 26 /* RO bit 29:26 */ 563 #define TX_RNG_ERR_LOGH_ERRCODE_MASK 0x000000003C000000ULL 564 #define TX_RNG_ERR_LOGH_MERR_SHIFT 30 /* RO bit 30 */ 565 #define TX_RNG_ERR_LOGH_MERR_MASK 0x0000000040000000ULL 566 #define TX_RNG_ERR_LOGH_ERR_SHIFT 31 /* RO bit 31 */ 567 #define TX_RNG_ERR_LOGH_ERR_MASK 0x0000000080000000ULL 568 569 /* Transmit Ring Error codes */ 570 #define TXDMA_RING_PKT_PRT_ERR 0 571 #define TXDMA_RING_CONF_PART_ERR 0x01 572 #define TXDMA_RING_NACK_PKT_ERR 0x02 573 #define TXDMA_RING_NACK_PREF_ERR 0x03 574 #define TXDMA_RING_PREF_BUF_PAR_ERR 0x04 575 #define TXDMA_RING_TX_RING_OFLOW_ERR 0x05 576 #define TXDMA_RING_PKT_SIZE_ERR 0x06 577 578 typedef union _tx_rng_err_logh_t { 579 uint64_t value; 580 struct { 581 #ifdef _BIG_ENDIAN 582 uint32_t hdw; 583 #endif 584 struct { 585 #if defined(_BIT_FIELDS_HTOL) 586 uint32_t err:1; 587 uint32_t merr:1; 588 uint32_t errcode:4; 589 uint32_t res2:14; 590 uint32_t err_addr:12; 591 #elif defined(_BIT_FIELDS_LTOH) 592 uint32_t err_addr:12; 593 uint32_t res2:14; 594 uint32_t errcode:4; 595 uint32_t merr:1; 596 uint32_t err:1; 597 598 #endif 599 } ldw; 600 #ifndef _BIG_ENDIAN 601 uint32_t hdw; 602 #endif 603 } bits; 604 } tx_rng_err_logh_t, *p_tx_rng_err_logh_t; 605 606 607 /* Trasnmit Ring Error Log Log (DMC + 0x40050) */ 608 #define TX_RNG_ERR_LOGL_ERR_ADDR_SHIFT 0 /* RO bit 31:0 */ 609 #define TX_RNG_ERR_LOGL_ERR_ADDR_MASK 0x00000000FFFFFFFFULL 610 611 typedef union _tx_rng_err_logl_t { 612 uint64_t value; 613 struct { 614 #ifdef _BIG_ENDIAN 615 uint32_t hdw; 616 #endif 617 struct { 618 #if defined(_BIT_FIELDS_HTOL) 619 uint32_t err_addr:32; 620 #elif defined(_BIT_FIELDS_LTOH) 621 uint32_t err_addr:32; 622 623 #endif 624 } ldw; 625 #ifndef _BIG_ENDIAN 626 uint32_t hdw; 627 #endif 628 } bits; 629 } tx_rng_err_logl_t, *p_tx_rng_err_logl_t; 630 631 /* 632 * TDMC_INTR_RBG_REG (DMC + 0x40060) 633 */ 634 typedef union _tdmc_intr_dbg_t { 635 uint64_t value; 636 struct { 637 #ifdef _BIG_ENDIAN 638 uint32_t hdw; 639 #endif 640 struct { 641 #if defined(_BIT_FIELDS_HTOL) 642 uint32_t res:16; 643 uint32_t mk:1; 644 uint32_t rsvd:7; 645 uint32_t mbox_err:1; 646 uint32_t pkt_size_err:1; 647 uint32_t tx_ring_oflow:1; 648 uint32_t pref_buf_par_err:1; 649 uint32_t nack_pref:1; 650 uint32_t nack_pkt_rd:1; 651 uint32_t conf_part_err:1; 652 uint32_t pkt_part_err:1; 653 #elif defined(_BIT_FIELDS_LTOH) 654 uint32_t pkt_part_err:1; 655 uint32_t conf_part_err:1; 656 uint32_t nack_pkt_rd:1; 657 uint32_t nack_pref:1; 658 uint32_t pref_buf_par_err:1; 659 uint32_t tx_ring_oflow:1; 660 uint32_t pkt_size_err:1; 661 uint32_t mbox_err:1; 662 uint32_t rsvd:7; 663 uint32_t mk:1; 664 uint32_t res:16; 665 #endif 666 } ldw; 667 #ifndef _BIG_ENDIAN 668 uint32_t hdw; 669 #endif 670 } bits; 671 } tdmc_intr_dbg_t, *p_tdmc_intr_dbg_t; 672 673 674 /* 675 * TX_CS_DBG (DMC + 0x40068) 676 */ 677 typedef union _tx_cs_dbg_t { 678 uint64_t value; 679 struct { 680 #ifdef _BIG_ENDIAN 681 struct { 682 #if defined(_BIT_FIELDS_HTOL) 683 uint32_t res1:4; 684 uint32_t pkt_cnt:12; 685 uint32_t res2:16; 686 #elif defined(_BIT_FIELDS_LTOH) 687 uint32_t res2:16; 688 uint32_t pkt_cnt:12; 689 uint32_t res1:4; 690 #endif 691 } hdw; 692 693 #endif 694 struct { 695 #if defined(_BIT_FIELDS_HTOL) 696 uint32_t rsvd:32; 697 #elif defined(_BIT_FIELDS_LTOH) 698 uint32_t rsvd:32; 699 700 #endif 701 } ldw; 702 703 #ifndef _BIG_ENDIAN 704 struct { 705 #if defined(_BIT_FIELDS_HTOL) 706 uint32_t res1:4; 707 uint32_t pkt_cnt:12; 708 uint32_t res2:16; 709 #elif defined(_BIT_FIELDS_LTOH) 710 uint32_t res2:16; 711 uint32_t pkt_cnt:12; 712 uint32_t res1:4; 713 #endif 714 } hdw; 715 716 #endif 717 } bits; 718 } tx_cs_dbg_t, *p_tx_cs_dbg_t; 719 720 #define TXDMA_MAILBOX_BYTE_LENGTH 64 721 #define TXDMA_MAILBOX_UNUSED 24 722 723 typedef struct _txdma_mailbox_t { 724 tx_cs_t tx_cs; /* 8 bytes */ 725 tx_dma_pre_st_t tx_dma_pre_st; /* 8 bytes */ 726 tx_ring_hdl_t tx_ring_hdl; /* 8 bytes */ 727 tx_ring_kick_t tx_ring_kick; /* 8 bytes */ 728 uint32_t tx_rng_err_logh; /* 4 bytes */ 729 uint32_t tx_rng_err_logl; /* 4 bytes */ 730 uint32_t resv[TXDMA_MAILBOX_UNUSED]; 731 } txdma_mailbox_t, *p_txdma_mailbox_t; 732 733 #if OLD 734 /* Transmit Ring Scheduler (per port) */ 735 #define TX_DMA_MAP_OFFSET(port) (port * 8 + TX_DMA_MAP_REG) 736 #define TX_DMA_MAP_PORT_OFFSET(port) (port * 8) 737 #define TX_DMA_MAP_REG (FZC_DMC + 0x50000) 738 #define TX_DMA_MAP0_REG (FZC_DMC + 0x50000) 739 #define TX_DMA_MAP1_REG (FZC_DMC + 0x50008) 740 #define TX_DMA_MAP2_REG (FZC_DMC + 0x50010) 741 #define TX_DMA_MAP3_REG (FZC_DMC + 0x50018) 742 743 #define TX_DMA_MAP_SHIFT 0 /* RO bit 31:0 */ 744 #define TX_DMA_MAPMASK 0x00000000FFFFFFFFULL 745 746 typedef union _tx_dma_map_t { 747 uint64_t value; 748 struct { 749 #ifdef _BIG_ENDIAN 750 uint32_t hdw; 751 #endif 752 struct { 753 #if defined(_BIT_FIELDS_HTOL) 754 uint32_t bind:32; 755 #elif defined(_BIT_FIELDS_LTOH) 756 uint32_t bind:32; 757 758 #endif 759 } ldw; 760 #ifndef _BIG_ENDIAN 761 uint32_t hdw; 762 #endif 763 } bits; 764 } tx_dma_map_t, *p_tx_dma_map_t; 765 #endif 766 767 #if OLD 768 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 769 #define DRR_WT_REG (FZC_DMC + 0x51000) 770 #define DRR_WT_SHIFT 0 /* RO bit 19:0 */ 771 #define DRR_WT_MASK 0x00000000000FFFFFULL 772 773 #define TXDMA_DRR_RNG_USE_OFFSET(channel) (channel * 16) 774 775 typedef union _drr_wt_t { 776 uint64_t value; 777 struct { 778 #ifdef _BIG_ENDIAN 779 uint32_t hdw; 780 #endif 781 struct { 782 #if defined(_BIT_FIELDS_HTOL) 783 uint32_t res1_1:12; 784 uint32_t wt:20; 785 #elif defined(_BIT_FIELDS_LTOH) 786 uint32_t wt:20; 787 uint32_t res1_1:12; 788 #endif 789 } ldw; 790 #ifndef _BIG_ENDIAN 791 uint32_t hdw; 792 #endif 793 } bits; 794 } drr_wt_t, *p_drr_wt_t; 795 #endif 796 797 #if OLD 798 799 /* Performance Monitoring (32 Channels) */ 800 #define TXRNG_USE_REG (FZC_DMC + 0x51008) 801 #define TXRNG_USE_CNT_SHIFT 0 /* RO bit 26:0 */ 802 #define TXRNG_USE_CNT_MASK 0x0000000007FFFFFFULL 803 #define TXRNG_USE_OFLOW_SHIFT 0 /* RO bit 27 */ 804 #define TXRNG_USE_OFLOW_MASK 0x0000000008000000ULL 805 806 typedef union _txrng_use_t { 807 uint64_t value; 808 struct { 809 #ifdef _BIG_ENDIAN 810 uint32_t hdw; 811 #endif 812 struct { 813 #if defined(_BIT_FIELDS_HTOL) 814 uint32_t res1_1:4; 815 uint32_t oflow:1; 816 uint32_t cnt:27; 817 #elif defined(_BIT_FIELDS_LTOH) 818 uint32_t cnt:27; 819 uint32_t oflow:1; 820 uint32_t res1_1:4; 821 822 #endif 823 } ldw; 824 #ifndef _BIG_ENDIAN 825 uint32_t hdw; 826 #endif 827 } bits; 828 } txrng_use_t, *p_txrng_use_t; 829 830 #endif 831 832 /* 833 * Internal Transmit Packet Format (16 bytes) 834 */ 835 #define TX_PKT_HEADER_SIZE 16 836 #define TX_MAX_GATHER_POINTERS 15 837 #define TX_GATHER_POINTERS_THRESHOLD 8 838 /* 839 * There is bugs in the hardware 840 * and max sfter len is changed from 4096 to 4076. 841 * 842 * Jumbo from 9500 to 9216 843 */ 844 #define TX_MAX_TRANSFER_LENGTH 4076 845 #define TX_JUMBO_MTU 9216 846 847 #define TX_PKT_HEADER_PAD_SHIFT 0 /* bit 2:0 */ 848 #define TX_PKT_HEADER_PAD_MASK 0x0000000000000007ULL 849 #define TX_PKT_HEADER_TOT_XFER_LEN_SHIFT 16 /* bit 16:29 */ 850 #define TX_PKT_HEADER_TOT_XFER_LEN_MASK 0x000000000000FFF8ULL 851 #define TX_PKT_HEADER_L4STUFF_SHIFT 32 /* bit 37:32 */ 852 #define TX_PKT_HEADER_L4STUFF_MASK 0x0000003F00000000ULL 853 #define TX_PKT_HEADER_L4START_SHIFT 40 /* bit 45:40 */ 854 #define TX_PKT_HEADER_L4START_MASK 0x00003F0000000000ULL 855 #define TX_PKT_HEADER_L3START_SHIFT 48 /* bit 45:40 */ 856 #define TX_PKT_HEADER_IHL_SHIFT 52 /* bit 52 */ 857 #define TX_PKT_HEADER_VLAN__SHIFT 56 /* bit 56 */ 858 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT 57 /* bit 57 */ 859 #define TX_PKT_HEADER_LLC_SHIFT 57 /* bit 57 */ 860 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SET 0x0200000000000000ULL 861 #define TX_PKT_HEADER_TCP_UDP_CRC32C_MASK 0x0200000000000000ULL 862 #define TX_PKT_HEADER_L4_PROTO_OP_SHIFT 2 /* bit 59:58 */ 863 #define TX_PKT_HEADER_L4_PROTO_OP_MASK 0x0C00000000000000ULL 864 #define TX_PKT_HEADER_V4_HDR_CS_SHIFT 60 /* bit 60 */ 865 #define TX_PKT_HEADER_V4_HDR_CS_SET 0x1000000000000000ULL 866 #define TX_PKT_HEADER_V4_HDR_CS_MASK 0x1000000000000000ULL 867 #define TX_PKT_HEADER_IP_VER_SHIFT 61 /* bit 61 */ 868 #define TX_PKT_HEADER_IP_VER_MASK 0x2000000000000000ULL 869 #define TX_PKT_HEADER_PKT_TYPE_SHIFT 62 /* bit 62 */ 870 #define TX_PKT_HEADER_PKT_TYPE_MASK 0x4000000000000000ULL 871 872 /* L4 Prototol Operations */ 873 #define TX_PKT_L4_PROTO_OP_NOP 0x00 874 #define TX_PKT_L4_PROTO_OP_FULL_L4_CSUM 0x01 875 #define TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM 0x02 876 #define TX_PKT_L4_PROTO_OP_SCTP_CRC32 0x04 877 878 /* Transmit Packet Types */ 879 #define TX_PKT_PKT_TYPE_NOP 0x00 880 #define TX_PKT_PKT_TYPE_TCP 0x01 881 #define TX_PKT_PKT_TYPE_UDP 0x02 882 #define TX_PKT_PKT_TYPE_SCTP 0x03 883 884 typedef union _tx_pkt_header_t { 885 uint64_t value; 886 struct { 887 struct { 888 #if defined(_BIT_FIELDS_HTOL) 889 uint32_t pad:3; 890 uint32_t resv2:13; 891 uint32_t tot_xfer_len:14; 892 uint32_t resv1:2; 893 #elif defined(_BIT_FIELDS_LTOH) 894 uint32_t pad:3; 895 uint32_t resv2:13; 896 uint32_t tot_xfer_len:14; 897 uint32_t resv1:2; 898 #endif 899 } ldw; 900 struct { 901 #if defined(_BIT_FIELDS_HTOL) 902 uint32_t l4stuff:6; 903 uint32_t resv3:2; 904 uint32_t l4start:6; 905 uint32_t resv2:2; 906 uint32_t l3start:4; 907 uint32_t ihl:4; 908 uint32_t vlan:1; 909 uint32_t llc:1; 910 uint32_t res1:3; 911 uint32_t ip_ver:1; 912 uint32_t cksum_en_pkt_type:2; 913 #elif defined(_BIT_FIELDS_LTOH) 914 uint32_t l4stuff:6; 915 uint32_t resv3:2; 916 uint32_t l4start:6; 917 uint32_t resv2:2; 918 uint32_t l3start:4; 919 uint32_t ihl:4; 920 uint32_t vlan:1; 921 uint32_t llc:1; 922 uint32_t res1:3; 923 uint32_t ip_ver:1; 924 uint32_t cksum_en_pkt_type:2; 925 #endif 926 } hdw; 927 } bits; 928 } tx_pkt_header_t, *p_tx_pkt_header_t; 929 930 typedef struct _tx_pkt_hdr_all_t { 931 tx_pkt_header_t pkthdr; 932 uint64_t reserved; 933 } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t; 934 935 /* Debug only registers */ 936 #define TDMC_INJ_PAR_ERR_REG (FZC_DMC + 0x45040) 937 #define TDMC_INJ_PAR_ERR_MASK 0x0000000000FFFFFFULL 938 #define TDMC_INJ_PAR_ERR_MASK_N2 0x000000000000FFFFULL 939 940 typedef union _tdmc_inj_par_err_t { 941 uint64_t value; 942 struct { 943 #ifdef _BIG_ENDIAN 944 uint32_t hdw; 945 #endif 946 struct { 947 #if defined(_BIT_FIELDS_HTOL) 948 uint32_t rsvc:8; 949 uint32_t inject_parity_error:24; 950 #elif defined(_BIT_FIELDS_LTOH) 951 uint32_t inject_parity_error:24; 952 uint32_t rsvc:8; 953 #endif 954 } ldw; 955 #ifndef _BIG_ENDIAN 956 uint32_t hdw; 957 #endif 958 } bits; 959 } tdmc_inj_par_err_t, *p_tdmc_inj_par_err_t; 960 961 typedef union _tdmc_inj_par_err_n2_t { 962 uint64_t value; 963 struct { 964 #ifdef _BIG_ENDIAN 965 uint32_t hdw; 966 #endif 967 struct { 968 #if defined(_BIT_FIELDS_HTOL) 969 uint32_t rsvc:16; 970 uint32_t inject_parity_error:16; 971 #elif defined(_BIT_FIELDS_LTOH) 972 uint32_t inject_parity_error:16; 973 uint32_t rsvc:16; 974 #endif 975 } ldw; 976 #ifndef _BIG_ENDIAN 977 uint32_t hdw; 978 #endif 979 } bits; 980 } tdmc_inj_par_err_n2_t, *p_tdmc_inj_par_err_n2_t; 981 982 #define TDMC_DBG_SEL_REG (FZC_DMC + 0x45080) 983 #define TDMC_DBG_SEL_MASK 0x000000000000003FULL 984 985 typedef union _tdmc_dbg_sel_t { 986 uint64_t value; 987 struct { 988 #ifdef _BIG_ENDIAN 989 uint32_t hdw; 990 #endif 991 struct { 992 #if defined(_BIT_FIELDS_HTOL) 993 uint32_t rsvc:26; 994 uint32_t dbg_sel:6; 995 #elif defined(_BIT_FIELDS_LTOH) 996 uint32_t dbg_sel:6; 997 uint32_t rsvc:26; 998 #endif 999 } ldw; 1000 #ifndef _BIG_ENDIAN 1001 uint32_t hdw; 1002 #endif 1003 } bits; 1004 } tdmc_dbg_sel_t, *p_tdmc_dbg_sel_t; 1005 1006 #define TDMC_TRAINING_REG (FZC_DMC + 0x45088) 1007 #define TDMC_TRAINING_MASK 0x00000000FFFFFFFFULL 1008 1009 typedef union _tdmc_training_t { 1010 uint64_t value; 1011 struct { 1012 #ifdef _BIG_ENDIAN 1013 uint32_t hdw; 1014 #endif 1015 struct { 1016 #if defined(_BIT_FIELDS_HTOL) 1017 uint32_t vec:32; 1018 #elif defined(_BIT_FIELDS_LTOH) 1019 uint32_t vec:6; 1020 #endif 1021 } ldw; 1022 #ifndef _BIG_ENDIAN 1023 uint32_t hdw; 1024 #endif 1025 } bits; 1026 } tdmc_training_t, *p_tdmc_training_t; 1027 1028 #ifdef __cplusplus 1029 } 1030 #endif 1031 1032 #endif /* _SYS_NXGE_NXGE_TXDMA_HW_H */ 1033