1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXDMA_HW_H 27 #define _SYS_NXGE_NXGE_TXDMA_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 #include <nxge_hw.h> 37 38 #if !defined(_BIG_ENDIAN) 39 #define SWAP(X) (X) 40 #else 41 #define SWAP(X) \ 42 (((X >> 32) & 0x00000000ffffffff) | \ 43 ((X << 32) & 0xffffffff00000000)) 44 #endif 45 46 /* 47 * Partitioning Suport: same as those defined for the RX 48 */ 49 /* 50 * TDC: Partitioning Support 51 * (Each of the following registers is for each TDC) 52 */ 53 #define TX_LOG_REG_SIZE 512 54 #define TX_LOG_DMA_OFFSET(channel) (channel * TX_LOG_REG_SIZE) 55 56 #define TX_LOG_PAGE_VLD_REG (FZC_DMC + 0x40000) 57 #define TX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x40008) 58 #define TX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x40010) 59 #define TX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x40018) 60 #define TX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x40020) 61 #define TX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x40028) 62 #define TX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x40030) 63 #define TX_LOG_PAGE_HDL_REG (FZC_DMC + 0x40038) 64 65 /* Transmit Addressing Mode: Set to 1 to select 32-bit addressing mode */ 66 #define TX_ADDR_MD_REG (FZC_DMC + 0x45000) 67 68 #define TX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 69 #define TX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 70 #define TX_ADDR_MD_MASK 0x0000000000000001ULL 71 72 typedef union _tx_addr_md_t { 73 uint64_t value; 74 struct { 75 #if defined(_BIG_ENDIAN) 76 uint32_t hdw; 77 #endif 78 struct { 79 #if defined(_BIT_FIELDS_HTOL) 80 uint32_t res1_1:31; 81 uint32_t mode32:1; 82 #elif defined(_BIT_FIELDS_LTOH) 83 uint32_t mode32:1; 84 uint32_t res1_1:31; 85 #endif 86 } ldw; 87 #if !defined(_BIG_ENDIAN) 88 uint32_t hdw; 89 #endif 90 } bits; 91 } tx_addr_md_t, *p_tx_addr_md_t; 92 93 /* Transmit Packet Descriptor Structure */ 94 #define TX_PKT_DESC_SAD_SHIFT 0 /* bits 43:0 */ 95 #define TX_PKT_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL 96 #define TX_PKT_DESC_TR_LEN_SHIFT 44 /* bits 56:44 */ 97 #define TX_PKT_DESC_TR_LEN_MASK 0x01FFF00000000000ULL 98 #define TX_PKT_DESC_NUM_PTR_SHIFT 58 /* bits 61:58 */ 99 #define TX_PKT_DESC_NUM_PTR_MASK 0x3C00000000000000ULL 100 #define TX_PKT_DESC_MARK_SHIFT 62 /* bit 62 */ 101 #define TX_PKT_DESC_MARK 0x4000000000000000ULL 102 #define TX_PKT_DESC_MARK_MASK 0x4000000000000000ULL 103 #define TX_PKT_DESC_SOP_SHIFT 63 /* bit 63 */ 104 #define TX_PKT_DESC_SOP 0x8000000000000000ULL 105 #define TX_PKT_DESC_SOP_MASK 0x8000000000000000ULL 106 107 typedef union _tx_desc_t { 108 uint64_t value; 109 struct { 110 #if defined(_BIG_ENDIAN) 111 struct { 112 #if defined(_BIT_FIELDS_HTOL) 113 uint32_t sop:1; 114 uint32_t mark:1; 115 uint32_t num_ptr:4; 116 uint32_t res1:1; 117 uint32_t tr_len:13; 118 uint32_t sad:12; 119 120 #elif defined(_BIT_FIELDS_LTOH) 121 uint32_t sad:12; 122 uint32_t tr_len:13; 123 uint32_t res1:1; 124 uint32_t num_ptr:4; 125 uint32_t mark:1; 126 uint32_t sop:1; 127 128 #endif 129 } hdw; 130 #endif 131 struct { 132 #if defined(_BIT_FIELDS_HTOL) 133 uint32_t sad:32; 134 #elif defined(_BIT_FIELDS_LTOH) 135 uint32_t sad:32; 136 #endif 137 } ldw; 138 #if !defined(_BIG_ENDIAN) 139 struct { 140 141 #if defined(_BIT_FIELDS_HTOL) 142 uint32_t sop:1; 143 uint32_t mark:1; 144 uint32_t num_ptr:4; 145 uint32_t res1:1; 146 uint32_t tr_len:13; 147 uint32_t sad:12; 148 #elif defined(_BIT_FIELDS_LTOH) 149 uint32_t sad:12; 150 uint32_t tr_len:13; 151 uint32_t res1:1; 152 uint32_t num_ptr:4; 153 uint32_t mark:1; 154 uint32_t sop:1; 155 #endif 156 } hdw; 157 #endif 158 } bits; 159 } tx_desc_t, *p_tx_desc_t; 160 161 162 /* Transmit Ring Configuration (24 Channels) */ 163 #define TX_RNG_CFIG_REG (DMC + 0x40000) 164 #if OLD 165 #define TX_RING_HDH_REG (DMC + 0x40008) 166 #endif 167 #define TX_RING_HDL_REG (DMC + 0x40010) 168 #define TX_RING_KICK_REG (DMC + 0x40018) 169 #define TX_ENT_MSK_REG (DMC + 0x40020) 170 #define TX_CS_REG (DMC + 0x40028) 171 #define TXDMA_MBH_REG (DMC + 0x40030) 172 #define TXDMA_MBL_REG (DMC + 0x40038) 173 #define TX_DMA_PRE_ST_REG (DMC + 0x40040) 174 #define TX_RNG_ERR_LOGH_REG (DMC + 0x40048) 175 #define TX_RNG_ERR_LOGL_REG (DMC + 0x40050) 176 #define TDMC_INTR_DBG_REG (DMC + 0x40060) 177 #define TX_CS_DBG_REG (DMC + 0x40068) 178 179 /* Transmit Ring Configuration */ 180 #define TX_RNG_CFIG_STADDR_SHIFT 6 /* bits 18:6 */ 181 #define TX_RNG_CFIG_STADDR_MASK 0x000000000007FFC0ULL 182 #define TX_RNG_CFIG_ADDR_MASK 0x00000FFFFFFFFFC0ULL 183 #define TX_RNG_CFIG_STADDR_BASE_SHIFT 19 /* bits 43:19 */ 184 #define TX_RNG_CFIG_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 185 #define TX_RNG_CFIG_LEN_SHIFT 48 /* bits 60:48 */ 186 #define TX_RNG_CFIG_LEN_MASK 0xFFF8000000000000ULL 187 188 #define TX_RNG_HEAD_TAIL_SHIFT 3 189 #define TX_RNG_HEAD_TAIL_WRAP_SHIFT 19 190 191 typedef union _tx_rng_cfig_t { 192 uint64_t value; 193 struct { 194 #if defined(_BIG_ENDIAN) 195 struct { 196 #if defined(_BIT_FIELDS_HTOL) 197 uint32_t res2:3; 198 uint32_t len:13; 199 uint32_t res1:4; 200 uint32_t staddr_base:12; 201 #elif defined(_BIT_FIELDS_LTOH) 202 uint32_t staddr_base:12; 203 uint32_t res1:4; 204 uint32_t len:13; 205 uint32_t res2:3; 206 #endif 207 } hdw; 208 #endif 209 struct { 210 #if defined(_BIT_FIELDS_HTOL) 211 uint32_t staddr_base:13; 212 uint32_t staddr:13; 213 uint32_t res2:6; 214 #elif defined(_BIT_FIELDS_LTOH) 215 uint32_t res2:6; 216 uint32_t staddr:13; 217 uint32_t staddr_base:13; 218 #endif 219 } ldw; 220 #ifndef _BIG_ENDIAN 221 struct { 222 #if defined(_BIT_FIELDS_HTOL) 223 uint32_t res2:3; 224 uint32_t len:13; 225 uint32_t res1:4; 226 uint32_t staddr_base:12; 227 #elif defined(_BIT_FIELDS_LTOH) 228 uint32_t staddr_base:12; 229 uint32_t res1:4; 230 uint32_t len:13; 231 uint32_t res2:3; 232 #endif 233 } hdw; 234 #endif 235 } bits; 236 } tx_rng_cfig_t, *p_tx_rng_cfig_t; 237 238 /* Transmit Ring Head Low */ 239 #define TX_RING_HDL_SHIFT 3 /* bit 31:3 */ 240 #define TX_RING_HDL_MASK 0x00000000FFFFFFF8ULL 241 242 typedef union _tx_ring_hdl_t { 243 uint64_t value; 244 struct { 245 #if defined(_BIG_ENDIAN) 246 uint32_t hdw; 247 #endif 248 struct { 249 #if defined(_BIT_FIELDS_HTOL) 250 uint32_t res0:12; 251 uint32_t wrap:1; 252 uint32_t head:16; 253 uint32_t res2:3; 254 #elif defined(_BIT_FIELDS_LTOH) 255 uint32_t res2:3; 256 uint32_t head:16; 257 uint32_t wrap:1; 258 uint32_t res0:12; 259 #endif 260 } ldw; 261 #ifndef _BIG_ENDIAN 262 uint32_t hdw; 263 #endif 264 } bits; 265 } tx_ring_hdl_t, *p_tx_ring_hdl_t; 266 267 /* Transmit Ring Kick */ 268 #define TX_RING_KICK_TAIL_SHIFT 3 /* bit 43:3 */ 269 #define TX_RING_KICK_TAIL_MASK 0x000000FFFFFFFFFF8ULL 270 271 typedef union _tx_ring_kick_t { 272 uint64_t value; 273 struct { 274 #ifdef _BIG_ENDIAN 275 uint32_t hdw; 276 #endif 277 struct { 278 #if defined(_BIT_FIELDS_HTOL) 279 uint32_t res0:12; 280 uint32_t wrap:1; 281 uint32_t tail:16; 282 uint32_t res2:3; 283 #elif defined(_BIT_FIELDS_LTOH) 284 uint32_t res2:3; 285 uint32_t tail:16; 286 uint32_t wrap:1; 287 uint32_t res0:12; 288 #endif 289 } ldw; 290 #ifndef _BIG_ENDIAN 291 uint32_t hdw; 292 #endif 293 } bits; 294 } tx_ring_kick_t, *p_tx_ring_kick_t; 295 296 /* Transmit Event Mask (DMC + 0x40020) */ 297 #define TX_ENT_MSK_PKT_PRT_ERR_SHIFT 0 /* bit 0: 0 to flag */ 298 #define TX_ENT_MSK_PKT_PRT_ERR_MASK 0x0000000000000001ULL 299 #define TX_ENT_MSK_CONF_PART_ERR_SHIFT 1 /* bit 1: 0 to flag */ 300 #define TX_ENT_MSK_CONF_PART_ERR_MASK 0x0000000000000002ULL 301 #define TX_ENT_MSK_NACK_PKT_RD_SHIFT 2 /* bit 2: 0 to flag */ 302 #define TX_ENT_MSK_NACK_PKT_RD_MASK 0x0000000000000004ULL 303 #define TX_ENT_MSK_NACK_PREF_SHIFT 3 /* bit 3: 0 to flag */ 304 #define TX_ENT_MSK_NACK_PREF_MASK 0x0000000000000008ULL 305 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_SHIFT 4 /* bit 4: 0 to flag */ 306 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK 0x0000000000000010ULL 307 #define TX_ENT_MSK_TX_RING_OFLOW_SHIFT 5 /* bit 5: 0 to flag */ 308 #define TX_ENT_MSK_TX_RING_OFLOW_MASK 0x0000000000000020ULL 309 #define TX_ENT_MSK_PKT_SIZE_ERR_SHIFT 6 /* bit 6: 0 to flag */ 310 #define TX_ENT_MSK_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 311 #define TX_ENT_MSK_MBOX_ERR_SHIFT 7 /* bit 7: 0 to flag */ 312 #define TX_ENT_MSK_MBOX_ERR_MASK 0x0000000000000080ULL 313 #define TX_ENT_MSK_MK_SHIFT 15 /* bit 15: 0 to flag */ 314 #define TX_ENT_MSK_MK_MASK 0x0000000000008000ULL 315 #define TX_ENT_MSK_MK_ALL (TX_ENT_MSK_PKT_PRT_ERR_MASK | \ 316 TX_ENT_MSK_CONF_PART_ERR_MASK | \ 317 TX_ENT_MSK_NACK_PKT_RD_MASK | \ 318 TX_ENT_MSK_NACK_PREF_MASK | \ 319 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | \ 320 TX_ENT_MSK_TX_RING_OFLOW_MASK | \ 321 TX_ENT_MSK_PKT_SIZE_ERR_MASK | \ 322 TX_ENT_MSK_MBOX_ERR_MASK | \ 323 TX_ENT_MSK_MK_MASK) 324 325 326 typedef union _tx_dma_ent_msk_t { 327 uint64_t value; 328 struct { 329 #ifdef _BIG_ENDIAN 330 uint32_t hdw; 331 #endif 332 struct { 333 #if defined(_BIT_FIELDS_HTOL) 334 uint32_t res1_1:16; 335 uint32_t mk:1; 336 uint32_t res2:7; 337 uint32_t mbox_err:1; 338 uint32_t pkt_size_err:1; 339 uint32_t tx_ring_oflow:1; 340 uint32_t pref_buf_ecc_err:1; 341 uint32_t nack_pref:1; 342 uint32_t nack_pkt_rd:1; 343 uint32_t conf_part_err:1; 344 uint32_t pkt_prt_err:1; 345 #elif defined(_BIT_FIELDS_LTOH) 346 uint32_t pkt_prt_err:1; 347 uint32_t conf_part_err:1; 348 uint32_t nack_pkt_rd:1; 349 uint32_t nack_pref:1; 350 uint32_t pref_buf_ecc_err:1; 351 uint32_t tx_ring_oflow:1; 352 uint32_t pkt_size_err:1; 353 uint32_t mbox_err:1; 354 uint32_t res2:7; 355 uint32_t mk:1; 356 uint32_t res1_1:16; 357 #endif 358 } ldw; 359 #ifndef _BIG_ENDIAN 360 uint32_t hdw; 361 #endif 362 } bits; 363 } tx_dma_ent_msk_t, *p_tx_dma_ent_msk_t; 364 365 366 /* Transmit Control and Status (DMC + 0x40028) */ 367 #define TX_CS_PKT_PRT_ERR_SHIFT 0 /* RO, bit 0 */ 368 #define TX_CS_PKT_PRT_ERR_MASK 0x0000000000000001ULL 369 #define TX_CS_CONF_PART_ERR_SHIF 1 /* RO, bit 1 */ 370 #define TX_CS_CONF_PART_ERR_MASK 0x0000000000000002ULL 371 #define TX_CS_NACK_PKT_RD_SHIFT 2 /* RO, bit 2 */ 372 #define TX_CS_NACK_PKT_RD_MASK 0x0000000000000004ULL 373 #define TX_CS_PREF_SHIFT 3 /* RO, bit 3 */ 374 #define TX_CS_PREF_MASK 0x0000000000000008ULL 375 #define TX_CS_PREF_BUF_PAR_ERR_SHIFT 4 /* RO, bit 4 */ 376 #define TX_CS_PREF_BUF_PAR_ERR_MASK 0x0000000000000010ULL 377 #define TX_CS_RING_OFLOW_SHIFT 5 /* RO, bit 5 */ 378 #define TX_CS_RING_OFLOW_MASK 0x0000000000000020ULL 379 #define TX_CS_PKT_SIZE_ERR_SHIFT 6 /* RW, bit 6 */ 380 #define TX_CS_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 381 #define TX_CS_MMK_SHIFT 14 /* RC, bit 14 */ 382 #define TX_CS_MMK_MASK 0x0000000000004000ULL 383 #define TX_CS_MK_SHIFT 15 /* RCW1C, bit 15 */ 384 #define TX_CS_MK_MASK 0x0000000000008000ULL 385 #define TX_CS_SNG_SHIFT 27 /* RO, bit 27 */ 386 #define TX_CS_SNG_MASK 0x0000000008000000ULL 387 #define TX_CS_STOP_N_GO_SHIFT 28 /* RW, bit 28 */ 388 #define TX_CS_STOP_N_GO_MASK 0x0000000010000000ULL 389 #define TX_CS_MB_SHIFT 29 /* RO, bit 29 */ 390 #define TX_CS_MB_MASK 0x0000000020000000ULL 391 #define TX_CS_RST_STATE_SHIFT 30 /* Rw, bit 30 */ 392 #define TX_CS_RST_STATE_MASK 0x0000000040000000ULL 393 #define TX_CS_RST_SHIFT 31 /* Rw, bit 31 */ 394 #define TX_CS_RST_MASK 0x0000000080000000ULL 395 #define TX_CS_LASTMASK_SHIFT 32 /* RW, bit 43:32 */ 396 #define TX_CS_LASTMARK_MASK 0x00000FFF00000000ULL 397 #define TX_CS_PKT_CNT_SHIFT 48 /* RW, bit 59:48 */ 398 #define TX_CS_PKT_CNT_MASK 0x0FFF000000000000ULL 399 400 /* Trasnmit Control and Status */ 401 typedef union _tx_cs_t { 402 uint64_t value; 403 struct { 404 #ifdef _BIG_ENDIAN 405 struct { 406 #if defined(_BIT_FIELDS_HTOL) 407 uint32_t res1:4; 408 uint32_t pkt_cnt:12; 409 uint32_t res2:4; 410 uint32_t lastmark:12; 411 #elif defined(_BIT_FIELDS_LTOH) 412 uint32_t lastmark:12; 413 uint32_t res2:4; 414 uint32_t pkt_cnt:12; 415 uint32_t res1:4; 416 #endif 417 } hdw; 418 419 #endif 420 struct { 421 #if defined(_BIT_FIELDS_HTOL) 422 uint32_t rst:1; 423 uint32_t rst_state:1; 424 uint32_t mb:1; 425 uint32_t stop_n_go:1; 426 uint32_t sng_state:1; 427 uint32_t res1:11; 428 uint32_t mk:1; 429 uint32_t mmk:1; 430 uint32_t res2:6; 431 uint32_t mbox_err:1; 432 uint32_t pkt_size_err:1; 433 uint32_t tx_ring_oflow:1; 434 uint32_t pref_buf_par_err:1; 435 uint32_t nack_pref:1; 436 uint32_t nack_pkt_rd:1; 437 uint32_t conf_part_err:1; 438 uint32_t pkt_prt_err:1; 439 #elif defined(_BIT_FIELDS_LTOH) 440 uint32_t pkt_prt_err:1; 441 uint32_t conf_part_err:1; 442 uint32_t nack_pkt_rd:1; 443 uint32_t nack_pref:1; 444 uint32_t pref_buf_par_err:1; 445 uint32_t tx_ring_oflow:1; 446 uint32_t pkt_size_err:1; 447 uint32_t mbox_err:1; 448 uint32_t res2:6; 449 uint32_t mmk:1; 450 uint32_t mk:1; 451 uint32_t res1:11; 452 uint32_t sng_state:1; 453 uint32_t stop_n_go:1; 454 uint32_t mb:1; 455 uint32_t rst_state:1; 456 uint32_t rst:1; 457 #endif 458 } ldw; 459 #ifndef _BIG_ENDIAN 460 struct { 461 #if defined(_BIT_FIELDS_HTOL) 462 uint32_t res1:4; 463 uint32_t pkt_cnt:12; 464 uint32_t res2:4; 465 uint32_t lastmark:12; 466 #elif defined(_BIT_FIELDS_LTOH) 467 uint32_t lastmark:12; 468 uint32_t res2:4; 469 uint32_t pkt_cnt:12; 470 uint32_t res1:4; 471 #endif 472 } hdw; 473 474 #endif 475 } bits; 476 } tx_cs_t, *p_tx_cs_t; 477 478 /* Trasnmit Mailbox High (DMC + 0x40030) */ 479 #define TXDMA_MBH_SHIFT 0 /* bit 11:0 */ 480 #define TXDMA_MBH_ADDR_SHIFT 32 /* bit 43:32 */ 481 #define TXDMA_MBH_MASK 0x0000000000000FFFULL 482 483 typedef union _txdma_mbh_t { 484 uint64_t value; 485 struct { 486 #ifdef _BIG_ENDIAN 487 uint32_t hdw; 488 #endif 489 struct { 490 #if defined(_BIT_FIELDS_HTOL) 491 uint32_t res1_1:20; 492 uint32_t mbaddr:12; 493 494 #elif defined(_BIT_FIELDS_LTOH) 495 uint32_t mbaddr:12; 496 uint32_t res1_1:20; 497 #endif 498 } ldw; 499 #ifndef _BIG_ENDIAN 500 uint32_t hdw; 501 #endif 502 } bits; 503 } txdma_mbh_t, *p_txdma_mbh_t; 504 505 506 /* Trasnmit Mailbox Low (DMC + 0x40038) */ 507 #define TXDMA_MBL_SHIFT 6 /* bit 31:6 */ 508 #define TXDMA_MBL_MASK 0x00000000FFFFFFC0ULL 509 510 typedef union _txdma_mbl_t { 511 uint64_t value; 512 struct { 513 #ifdef _BIG_ENDIAN 514 uint32_t hdw; 515 #endif 516 struct { 517 #if defined(_BIT_FIELDS_HTOL) 518 uint32_t mbaddr:26; 519 uint32_t res2:6; 520 521 #elif defined(_BIT_FIELDS_LTOH) 522 uint32_t res2:6; 523 uint32_t mbaddr:26; 524 #endif 525 } ldw; 526 #ifndef _BIG_ENDIAN 527 uint32_t hdw; 528 #endif 529 } bits; 530 } txdma_mbl_t, *p_txdma_mbl_t; 531 532 /* Trasnmit Prefetch State High (DMC + 0x40040) */ 533 #define TX_DMA_PREF_ST_SHIFT 0 /* bit 5:0 */ 534 #define TX_DMA_PREF_ST_MASK 0x000000000000003FULL 535 536 typedef union _tx_dma_pre_st_t { 537 uint64_t value; 538 struct { 539 #ifdef _BIG_ENDIAN 540 uint32_t hdw; 541 #endif 542 struct { 543 #if defined(_BIT_FIELDS_HTOL) 544 uint32_t res1_1:13; 545 uint32_t shadow_hd:19; 546 #elif defined(_BIT_FIELDS_LTOH) 547 uint32_t shadow_hd:19; 548 uint32_t res1_1:13; 549 #endif 550 } ldw; 551 #ifndef _BIG_ENDIAN 552 uint32_t hdw; 553 #endif 554 } bits; 555 } tx_dma_pre_st_t, *p_tx_dma_pre_st_t; 556 557 /* Trasnmit Ring Error Log High (DMC + 0x40048) */ 558 #define TX_RNG_ERR_LOGH_ERR_ADDR_SHIFT 0 /* RO bit 11:0 */ 559 #define TX_RNG_ERR_LOGH_ERR_ADDR_MASK 0x0000000000000FFFULL 560 #define TX_RNG_ERR_LOGH_ADDR_SHIFT 32 561 #define TX_RNG_ERR_LOGH_ERRCODE_SHIFT 26 /* RO bit 29:26 */ 562 #define TX_RNG_ERR_LOGH_ERRCODE_MASK 0x000000003C000000ULL 563 #define TX_RNG_ERR_LOGH_MERR_SHIFT 30 /* RO bit 30 */ 564 #define TX_RNG_ERR_LOGH_MERR_MASK 0x0000000040000000ULL 565 #define TX_RNG_ERR_LOGH_ERR_SHIFT 31 /* RO bit 31 */ 566 #define TX_RNG_ERR_LOGH_ERR_MASK 0x0000000080000000ULL 567 568 /* Transmit Ring Error codes */ 569 #define TXDMA_RING_PKT_PRT_ERR 0 570 #define TXDMA_RING_CONF_PART_ERR 0x01 571 #define TXDMA_RING_NACK_PKT_ERR 0x02 572 #define TXDMA_RING_NACK_PREF_ERR 0x03 573 #define TXDMA_RING_PREF_BUF_PAR_ERR 0x04 574 #define TXDMA_RING_TX_RING_OFLOW_ERR 0x05 575 #define TXDMA_RING_PKT_SIZE_ERR 0x06 576 577 typedef union _tx_rng_err_logh_t { 578 uint64_t value; 579 struct { 580 #ifdef _BIG_ENDIAN 581 uint32_t hdw; 582 #endif 583 struct { 584 #if defined(_BIT_FIELDS_HTOL) 585 uint32_t err:1; 586 uint32_t merr:1; 587 uint32_t errcode:4; 588 uint32_t res2:14; 589 uint32_t err_addr:12; 590 #elif defined(_BIT_FIELDS_LTOH) 591 uint32_t err_addr:12; 592 uint32_t res2:14; 593 uint32_t errcode:4; 594 uint32_t merr:1; 595 uint32_t err:1; 596 597 #endif 598 } ldw; 599 #ifndef _BIG_ENDIAN 600 uint32_t hdw; 601 #endif 602 } bits; 603 } tx_rng_err_logh_t, *p_tx_rng_err_logh_t; 604 605 606 /* Trasnmit Ring Error Log Log (DMC + 0x40050) */ 607 #define TX_RNG_ERR_LOGL_ERR_ADDR_SHIFT 0 /* RO bit 31:0 */ 608 #define TX_RNG_ERR_LOGL_ERR_ADDR_MASK 0x00000000FFFFFFFFULL 609 610 typedef union _tx_rng_err_logl_t { 611 uint64_t value; 612 struct { 613 #ifdef _BIG_ENDIAN 614 uint32_t hdw; 615 #endif 616 struct { 617 #if defined(_BIT_FIELDS_HTOL) 618 uint32_t err_addr:32; 619 #elif defined(_BIT_FIELDS_LTOH) 620 uint32_t err_addr:32; 621 622 #endif 623 } ldw; 624 #ifndef _BIG_ENDIAN 625 uint32_t hdw; 626 #endif 627 } bits; 628 } tx_rng_err_logl_t, *p_tx_rng_err_logl_t; 629 630 /* 631 * TDMC_INTR_RBG_REG (DMC + 0x40060) 632 */ 633 typedef union _tdmc_intr_dbg_t { 634 uint64_t value; 635 struct { 636 #ifdef _BIG_ENDIAN 637 uint32_t hdw; 638 #endif 639 struct { 640 #if defined(_BIT_FIELDS_HTOL) 641 uint32_t res:16; 642 uint32_t mk:1; 643 uint32_t rsvd:7; 644 uint32_t mbox_err:1; 645 uint32_t pkt_size_err:1; 646 uint32_t tx_ring_oflow:1; 647 uint32_t pref_buf_par_err:1; 648 uint32_t nack_pref:1; 649 uint32_t nack_pkt_rd:1; 650 uint32_t conf_part_err:1; 651 uint32_t pkt_part_err:1; 652 #elif defined(_BIT_FIELDS_LTOH) 653 uint32_t pkt_part_err:1; 654 uint32_t conf_part_err:1; 655 uint32_t nack_pkt_rd:1; 656 uint32_t nack_pref:1; 657 uint32_t pref_buf_par_err:1; 658 uint32_t tx_ring_oflow:1; 659 uint32_t pkt_size_err:1; 660 uint32_t mbox_err:1; 661 uint32_t rsvd:7; 662 uint32_t mk:1; 663 uint32_t res:16; 664 #endif 665 } ldw; 666 #ifndef _BIG_ENDIAN 667 uint32_t hdw; 668 #endif 669 } bits; 670 } tdmc_intr_dbg_t, *p_tdmc_intr_dbg_t; 671 672 673 /* 674 * TX_CS_DBG (DMC + 0x40068) 675 */ 676 typedef union _tx_cs_dbg_t { 677 uint64_t value; 678 struct { 679 #ifdef _BIG_ENDIAN 680 struct { 681 #if defined(_BIT_FIELDS_HTOL) 682 uint32_t res1:4; 683 uint32_t pkt_cnt:12; 684 uint32_t res2:16; 685 #elif defined(_BIT_FIELDS_LTOH) 686 uint32_t res2:16; 687 uint32_t pkt_cnt:12; 688 uint32_t res1:4; 689 #endif 690 } hdw; 691 692 #endif 693 struct { 694 #if defined(_BIT_FIELDS_HTOL) 695 uint32_t rsvd:32; 696 #elif defined(_BIT_FIELDS_LTOH) 697 uint32_t rsvd:32; 698 699 #endif 700 } ldw; 701 702 #ifndef _BIG_ENDIAN 703 struct { 704 #if defined(_BIT_FIELDS_HTOL) 705 uint32_t res1:4; 706 uint32_t pkt_cnt:12; 707 uint32_t res2:16; 708 #elif defined(_BIT_FIELDS_LTOH) 709 uint32_t res2:16; 710 uint32_t pkt_cnt:12; 711 uint32_t res1:4; 712 #endif 713 } hdw; 714 715 #endif 716 } bits; 717 } tx_cs_dbg_t, *p_tx_cs_dbg_t; 718 719 #define TXDMA_MAILBOX_BYTE_LENGTH 64 720 #define TXDMA_MAILBOX_UNUSED 24 721 722 typedef struct _txdma_mailbox_t { 723 tx_cs_t tx_cs; /* 8 bytes */ 724 tx_dma_pre_st_t tx_dma_pre_st; /* 8 bytes */ 725 tx_ring_hdl_t tx_ring_hdl; /* 8 bytes */ 726 tx_ring_kick_t tx_ring_kick; /* 8 bytes */ 727 uint32_t tx_rng_err_logh; /* 4 bytes */ 728 uint32_t tx_rng_err_logl; /* 4 bytes */ 729 uint32_t resv[TXDMA_MAILBOX_UNUSED]; 730 } txdma_mailbox_t, *p_txdma_mailbox_t; 731 732 #if OLD 733 /* Transmit Ring Scheduler (per port) */ 734 #define TX_DMA_MAP_OFFSET(port) (port * 8 + TX_DMA_MAP_REG) 735 #define TX_DMA_MAP_PORT_OFFSET(port) (port * 8) 736 #define TX_DMA_MAP_REG (FZC_DMC + 0x50000) 737 #define TX_DMA_MAP0_REG (FZC_DMC + 0x50000) 738 #define TX_DMA_MAP1_REG (FZC_DMC + 0x50008) 739 #define TX_DMA_MAP2_REG (FZC_DMC + 0x50010) 740 #define TX_DMA_MAP3_REG (FZC_DMC + 0x50018) 741 742 #define TX_DMA_MAP_SHIFT 0 /* RO bit 31:0 */ 743 #define TX_DMA_MAPMASK 0x00000000FFFFFFFFULL 744 745 typedef union _tx_dma_map_t { 746 uint64_t value; 747 struct { 748 #ifdef _BIG_ENDIAN 749 uint32_t hdw; 750 #endif 751 struct { 752 #if defined(_BIT_FIELDS_HTOL) 753 uint32_t bind:32; 754 #elif defined(_BIT_FIELDS_LTOH) 755 uint32_t bind:32; 756 757 #endif 758 } ldw; 759 #ifndef _BIG_ENDIAN 760 uint32_t hdw; 761 #endif 762 } bits; 763 } tx_dma_map_t, *p_tx_dma_map_t; 764 #endif 765 766 #if OLD 767 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 768 #define DRR_WT_REG (FZC_DMC + 0x51000) 769 #define DRR_WT_SHIFT 0 /* RO bit 19:0 */ 770 #define DRR_WT_MASK 0x00000000000FFFFFULL 771 772 #define TXDMA_DRR_RNG_USE_OFFSET(channel) (channel * 16) 773 774 typedef union _drr_wt_t { 775 uint64_t value; 776 struct { 777 #ifdef _BIG_ENDIAN 778 uint32_t hdw; 779 #endif 780 struct { 781 #if defined(_BIT_FIELDS_HTOL) 782 uint32_t res1_1:12; 783 uint32_t wt:20; 784 #elif defined(_BIT_FIELDS_LTOH) 785 uint32_t wt:20; 786 uint32_t res1_1:12; 787 #endif 788 } ldw; 789 #ifndef _BIG_ENDIAN 790 uint32_t hdw; 791 #endif 792 } bits; 793 } drr_wt_t, *p_drr_wt_t; 794 #endif 795 796 #if OLD 797 798 /* Performance Monitoring (32 Channels) */ 799 #define TXRNG_USE_REG (FZC_DMC + 0x51008) 800 #define TXRNG_USE_CNT_SHIFT 0 /* RO bit 26:0 */ 801 #define TXRNG_USE_CNT_MASK 0x0000000007FFFFFFULL 802 #define TXRNG_USE_OFLOW_SHIFT 0 /* RO bit 27 */ 803 #define TXRNG_USE_OFLOW_MASK 0x0000000008000000ULL 804 805 typedef union _txrng_use_t { 806 uint64_t value; 807 struct { 808 #ifdef _BIG_ENDIAN 809 uint32_t hdw; 810 #endif 811 struct { 812 #if defined(_BIT_FIELDS_HTOL) 813 uint32_t res1_1:4; 814 uint32_t oflow:1; 815 uint32_t cnt:27; 816 #elif defined(_BIT_FIELDS_LTOH) 817 uint32_t cnt:27; 818 uint32_t oflow:1; 819 uint32_t res1_1:4; 820 821 #endif 822 } ldw; 823 #ifndef _BIG_ENDIAN 824 uint32_t hdw; 825 #endif 826 } bits; 827 } txrng_use_t, *p_txrng_use_t; 828 829 #endif 830 831 /* 832 * Internal Transmit Packet Format (16 bytes) 833 */ 834 #define TX_PKT_HEADER_SIZE 16 835 #define TX_MAX_GATHER_POINTERS 15 836 #define TX_GATHER_POINTERS_THRESHOLD 8 837 /* 838 * There is bugs in the hardware 839 * and max sfter len is changed from 4096 to 4076. 840 * 841 * Jumbo from 9500 to 9216 842 */ 843 #define TX_MAX_TRANSFER_LENGTH 4076 844 #define TX_JUMBO_MTU 9216 845 846 #define TX_PKT_HEADER_PAD_SHIFT 0 /* bit 2:0 */ 847 #define TX_PKT_HEADER_PAD_MASK 0x0000000000000007ULL 848 #define TX_PKT_HEADER_TOT_XFER_LEN_SHIFT 16 /* bit 16:29 */ 849 #define TX_PKT_HEADER_TOT_XFER_LEN_MASK 0x000000000000FFF8ULL 850 #define TX_PKT_HEADER_L4STUFF_SHIFT 32 /* bit 37:32 */ 851 #define TX_PKT_HEADER_L4STUFF_MASK 0x0000003F00000000ULL 852 #define TX_PKT_HEADER_L4START_SHIFT 40 /* bit 45:40 */ 853 #define TX_PKT_HEADER_L4START_MASK 0x00003F0000000000ULL 854 #define TX_PKT_HEADER_L3START_SHIFT 48 /* bit 45:40 */ 855 #define TX_PKT_HEADER_IHL_SHIFT 52 /* bit 52 */ 856 #define TX_PKT_HEADER_VLAN__SHIFT 56 /* bit 56 */ 857 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT 57 /* bit 57 */ 858 #define TX_PKT_HEADER_LLC_SHIFT 57 /* bit 57 */ 859 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SET 0x0200000000000000ULL 860 #define TX_PKT_HEADER_TCP_UDP_CRC32C_MASK 0x0200000000000000ULL 861 #define TX_PKT_HEADER_L4_PROTO_OP_SHIFT 2 /* bit 59:58 */ 862 #define TX_PKT_HEADER_L4_PROTO_OP_MASK 0x0C00000000000000ULL 863 #define TX_PKT_HEADER_V4_HDR_CS_SHIFT 60 /* bit 60 */ 864 #define TX_PKT_HEADER_V4_HDR_CS_SET 0x1000000000000000ULL 865 #define TX_PKT_HEADER_V4_HDR_CS_MASK 0x1000000000000000ULL 866 #define TX_PKT_HEADER_IP_VER_SHIFT 61 /* bit 61 */ 867 #define TX_PKT_HEADER_IP_VER_MASK 0x2000000000000000ULL 868 #define TX_PKT_HEADER_PKT_TYPE_SHIFT 62 /* bit 62 */ 869 #define TX_PKT_HEADER_PKT_TYPE_MASK 0x4000000000000000ULL 870 871 /* L4 Prototol Operations */ 872 #define TX_PKT_L4_PROTO_OP_NOP 0x00 873 #define TX_PKT_L4_PROTO_OP_FULL_L4_CSUM 0x01 874 #define TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM 0x02 875 #define TX_PKT_L4_PROTO_OP_SCTP_CRC32 0x04 876 877 /* Transmit Packet Types */ 878 #define TX_PKT_PKT_TYPE_NOP 0x00 879 #define TX_PKT_PKT_TYPE_TCP 0x01 880 #define TX_PKT_PKT_TYPE_UDP 0x02 881 #define TX_PKT_PKT_TYPE_SCTP 0x03 882 883 typedef union _tx_pkt_header_t { 884 uint64_t value; 885 struct { 886 struct { 887 #if defined(_BIT_FIELDS_HTOL) 888 uint32_t pad:3; 889 uint32_t resv2:13; 890 uint32_t tot_xfer_len:14; 891 uint32_t resv1:2; 892 #elif defined(_BIT_FIELDS_LTOH) 893 uint32_t pad:3; 894 uint32_t resv2:13; 895 uint32_t tot_xfer_len:14; 896 uint32_t resv1:2; 897 #endif 898 } ldw; 899 struct { 900 #if defined(_BIT_FIELDS_HTOL) 901 uint32_t l4stuff:6; 902 uint32_t resv3:2; 903 uint32_t l4start:6; 904 uint32_t resv2:2; 905 uint32_t l3start:4; 906 uint32_t ihl:4; 907 uint32_t vlan:1; 908 uint32_t llc:1; 909 uint32_t res1:3; 910 uint32_t ip_ver:1; 911 uint32_t cksum_en_pkt_type:2; 912 #elif defined(_BIT_FIELDS_LTOH) 913 uint32_t l4stuff:6; 914 uint32_t resv3:2; 915 uint32_t l4start:6; 916 uint32_t resv2:2; 917 uint32_t l3start:4; 918 uint32_t ihl:4; 919 uint32_t vlan:1; 920 uint32_t llc:1; 921 uint32_t res1:3; 922 uint32_t ip_ver:1; 923 uint32_t cksum_en_pkt_type:2; 924 #endif 925 } hdw; 926 } bits; 927 } tx_pkt_header_t, *p_tx_pkt_header_t; 928 929 typedef struct _tx_pkt_hdr_all_t { 930 tx_pkt_header_t pkthdr; 931 uint64_t reserved; 932 } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t; 933 934 /* Debug only registers */ 935 #define TDMC_INJ_PAR_ERR_REG (FZC_DMC + 0x45040) 936 #define TDMC_INJ_PAR_ERR_MASK 0x0000000000FFFFFFULL 937 #define TDMC_INJ_PAR_ERR_MASK_N2 0x000000000000FFFFULL 938 939 typedef union _tdmc_inj_par_err_t { 940 uint64_t value; 941 struct { 942 #ifdef _BIG_ENDIAN 943 uint32_t hdw; 944 #endif 945 struct { 946 #if defined(_BIT_FIELDS_HTOL) 947 uint32_t rsvc:8; 948 uint32_t inject_parity_error:24; 949 #elif defined(_BIT_FIELDS_LTOH) 950 uint32_t inject_parity_error:24; 951 uint32_t rsvc:8; 952 #endif 953 } ldw; 954 #ifndef _BIG_ENDIAN 955 uint32_t hdw; 956 #endif 957 } bits; 958 } tdmc_inj_par_err_t, *p_tdmc_inj_par_err_t; 959 960 typedef union _tdmc_inj_par_err_n2_t { 961 uint64_t value; 962 struct { 963 #ifdef _BIG_ENDIAN 964 uint32_t hdw; 965 #endif 966 struct { 967 #if defined(_BIT_FIELDS_HTOL) 968 uint32_t rsvc:16; 969 uint32_t inject_parity_error:16; 970 #elif defined(_BIT_FIELDS_LTOH) 971 uint32_t inject_parity_error:16; 972 uint32_t rsvc:16; 973 #endif 974 } ldw; 975 #ifndef _BIG_ENDIAN 976 uint32_t hdw; 977 #endif 978 } bits; 979 } tdmc_inj_par_err_n2_t, *p_tdmc_inj_par_err_n2_t; 980 981 #define TDMC_DBG_SEL_REG (FZC_DMC + 0x45080) 982 #define TDMC_DBG_SEL_MASK 0x000000000000003FULL 983 984 typedef union _tdmc_dbg_sel_t { 985 uint64_t value; 986 struct { 987 #ifdef _BIG_ENDIAN 988 uint32_t hdw; 989 #endif 990 struct { 991 #if defined(_BIT_FIELDS_HTOL) 992 uint32_t rsvc:26; 993 uint32_t dbg_sel:6; 994 #elif defined(_BIT_FIELDS_LTOH) 995 uint32_t dbg_sel:6; 996 uint32_t rsvc:26; 997 #endif 998 } ldw; 999 #ifndef _BIG_ENDIAN 1000 uint32_t hdw; 1001 #endif 1002 } bits; 1003 } tdmc_dbg_sel_t, *p_tdmc_dbg_sel_t; 1004 1005 #define TDMC_TRAINING_REG (FZC_DMC + 0x45088) 1006 #define TDMC_TRAINING_MASK 0x00000000FFFFFFFFULL 1007 1008 typedef union _tdmc_training_t { 1009 uint64_t value; 1010 struct { 1011 #ifdef _BIG_ENDIAN 1012 uint32_t hdw; 1013 #endif 1014 struct { 1015 #if defined(_BIT_FIELDS_HTOL) 1016 uint32_t vec:32; 1017 #elif defined(_BIT_FIELDS_LTOH) 1018 uint32_t vec:6; 1019 #endif 1020 } ldw; 1021 #ifndef _BIG_ENDIAN 1022 uint32_t hdw; 1023 #endif 1024 } bits; 1025 } tdmc_training_t, *p_tdmc_training_t; 1026 1027 #ifdef __cplusplus 1028 } 1029 #endif 1030 1031 #endif /* _SYS_NXGE_NXGE_TXDMA_HW_H */ 1032