1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXC_HW_H 27 #define _SYS_NXGE_NXGE_TXC_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 35 /* Transmit Ring Scheduler Registers */ 36 #define TXC_PORT_DMA_ENABLE_REG (FZC_TXC + 0x20028) 37 #define TXC_PORT_DMA_LIST 0 /* RW bit 23:0 */ 38 #define TXC_DMA_DMA_LIST_MASK 0x0000000000FFFFFFULL 39 #define TXC_DMA_DMA_LIST_MASK_N2 0x000000000000FFFFULL 40 41 typedef union _txc_port_enable_t { 42 uint64_t value; 43 struct { 44 #ifdef _BIG_ENDIAN 45 uint32_t hdw; 46 #endif 47 struct { 48 #if defined(_BIT_FIELDS_HTOL) 49 uint32_t res:8; 50 uint32_t port_dma_list:24; 51 #elif defined(_BIT_FIELDS_LTOH) 52 uint32_t port_dma_list:24; 53 uint32_t res:8; 54 #endif 55 } ldw; 56 #ifndef _BIG_ENDIAN 57 uint32_t hdw; 58 #endif 59 } bits; 60 } txc_port_enable_t, *p_txc_port_enable_t; 61 62 typedef union _txc_port_enable_n2_t { 63 uint64_t value; 64 struct { 65 #ifdef _BIG_ENDIAN 66 uint32_t hdw; 67 #endif 68 struct { 69 #if defined(_BIT_FIELDS_HTOL) 70 uint32_t res:16; 71 uint32_t port_dma_list:16; 72 #elif defined(_BIT_FIELDS_LTOH) 73 uint32_t port_dma_list:16; 74 uint32_t res:16; 75 #endif 76 } ldw; 77 #ifndef _BIG_ENDIAN 78 uint32_t hdw; 79 #endif 80 } bits; 81 } txc_port_enable_n2_t, *p_txc_port_enable_n2_t; 82 83 /* Transmit Controller - Registers */ 84 #define TXC_FZC_OFFSET 0x1000 85 #define TXC_FZC_PORT_OFFSET(port) (port * TXC_FZC_OFFSET) 86 #define TXC_FZC_CHANNEL_OFFSET(channel) (channel * TXC_FZC_OFFSET) 87 #define TXC_FZC_REG_CN_OFFSET(x, cn) (x + TXC_FZC_CHANNEL_OFFSET(cn)) 88 89 #define TXC_FZC_CONTROL_OFFSET 0x100 90 #define TXC_FZC_CNTL_PORT_OFFSET(port) (port * TXC_FZC_CONTROL_OFFSET) 91 #define TXC_FZC_REG_PT_OFFSET(x, pt) (x + TXC_FZC_CNTL_PORT_OFFSET(pt)) 92 93 #define TXC_DMA_MAX_BURST_REG (FZC_TXC + 0x00000) 94 #define TXC_DMA_MAX_BURST_SHIFT 0 /* RW bit 19:0 */ 95 #define TXC_DMA_MAX_BURST_MASK 0x00000000000FFFFFULL 96 97 #define TXC_MAX_BURST_OFFSET(channel) (TXC_DMA_MAX_BURST_REG + \ 98 (channel * TXC_FZC_OFFSET)) 99 100 typedef union _txc_dma_max_burst_t { 101 uint64_t value; 102 struct { 103 #ifdef _BIG_ENDIAN 104 uint32_t hdw; 105 #endif 106 struct { 107 #if defined(_BIT_FIELDS_HTOL) 108 uint32_t res:12; 109 uint32_t dma_max_burst:20; 110 #elif defined(_BIT_FIELDS_LTOH) 111 uint32_t dma_max_burst:20; 112 uint32_t res:12; 113 114 #endif 115 } ldw; 116 #ifndef _BIG_ENDIAN 117 uint32_t hdw; 118 #endif 119 } bits; 120 } txc_dma_max_burst_t, *p_txc_dma_max_burst_t; 121 122 /* DRR Performance Monitoring Register */ 123 #define TXC_DMA_MAX_LENGTH_REG (FZC_TXC + 0x00008) 124 #define TXC_DMA_MAX_LENGTH_SHIFT /* RW bit 27:0 */ 125 #define TXC_DMA_MAX_LENGTH_MASK 0x000000000FFFFFFFULL 126 127 #define TXC_DMA_MAX_LEN_OFFSET(channel) (TXC_DMA_MAX_LENGTH_REG + \ 128 (channel * TXC_FZC_OFFSET)) 129 130 typedef union _txc_dma_max_length_t { 131 uint64_t value; 132 struct { 133 #ifdef _BIG_ENDIAN 134 uint32_t hdw; 135 #endif 136 struct { 137 #if defined(_BIT_FIELDS_HTOL) 138 uint32_t res:4; 139 uint32_t dma_length:28; 140 #elif defined(_BIT_FIELDS_LTOH) 141 uint32_t dma_length:28; 142 uint32_t res:4; 143 144 #endif 145 } ldw; 146 #ifndef _BIG_ENDIAN 147 uint32_t hdw; 148 #endif 149 } bits; 150 } txc_dma_max_length_t, *p_txc_dma_max_length_t; 151 152 153 #define TXC_CONTROL_REG (FZC_TXC + 0x20000) 154 #define TXC_DMA_LENGTH_SHIFT 0 /* RW bit 27:0 */ 155 #define TXC_DMA_LENGTH_MASK 0x000000000FFFFFFFULL 156 157 typedef union _txc_control_t { 158 uint64_t value; 159 struct { 160 #ifdef _BIG_ENDIAN 161 uint32_t hdw; 162 #endif 163 struct { 164 #if defined(_BIT_FIELDS_HTOL) 165 uint32_t res:27; 166 uint32_t txc_enabled:1; 167 uint32_t port3_enabled:1; 168 uint32_t port2_enabled:1; 169 uint32_t port1_enabled:1; 170 uint32_t port0_enabled:1; 171 #elif defined(_BIT_FIELDS_LTOH) 172 uint32_t port0_enabled:1; 173 uint32_t port1_enabled:1; 174 uint32_t port2_enabled:1; 175 uint32_t port3_enabled:1; 176 uint32_t txc_enabled:1; 177 uint32_t res:27; 178 179 #endif 180 } ldw; 181 #ifndef _BIG_ENDIAN 182 uint32_t hdw; 183 #endif 184 } bits; 185 } txc_control_t, *p_txc_control_t; 186 187 typedef union _txc_control_n2_t { 188 uint64_t value; 189 struct { 190 #ifdef _BIG_ENDIAN 191 uint32_t hdw; 192 #endif 193 struct { 194 #if defined(_BIT_FIELDS_HTOL) 195 uint32_t res:27; 196 uint32_t txc_enabled:1; 197 uint32_t res1:2; 198 uint32_t port1_enabled:1; 199 uint32_t port0_enabled:1; 200 #elif defined(_BIT_FIELDS_LTOH) 201 uint32_t port0_enabled:1; 202 uint32_t port1_enabled:1; 203 uint32_t res1:2; 204 uint32_t txc_enabled:1; 205 uint32_t res:27; 206 207 #endif 208 } ldw; 209 #ifndef _BIG_ENDIAN 210 uint32_t hdw; 211 #endif 212 } bits; 213 } txc_control_n2_t, *p_txc_control_n2_t; 214 215 216 #define TXC_TRAINING_REG (FZC_TXC + 0x20008) 217 #define TXC_TRAINING_VECTOR 0 /* RW bit 32:0 */ 218 #define TXC_TRAINING_VECTOR_MASK 0x00000000FFFFFFFFULL 219 220 typedef union _txc_training_t { 221 uint64_t value; 222 struct { 223 #ifdef _BIG_ENDIAN 224 uint32_t hdw; 225 #endif 226 struct { 227 #if defined(_BIT_FIELDS_HTOL) 228 uint32_t txc_training_vector:32; 229 #elif defined(_BIT_FIELDS_LTOH) 230 uint32_t txc_training_vector:32; 231 232 #endif 233 } ldw; 234 #ifndef _BIG_ENDIAN 235 uint32_t hdw; 236 #endif 237 } bits; 238 } txc_training_t, *p_txc_training_t; 239 240 241 #define TXC_DEBUG_SELECT_REG (FZC_TXC + 0x20010) 242 #define TXC_DEBUG_SELECT_SHIFT 0 /* WO bit 5:0 */ 243 #define TXC_DEBUG_SELECT_MASK 0x000000000000003FULL 244 245 typedef union _txc_debug_select_t { 246 uint64_t value; 247 struct { 248 #ifdef _BIG_ENDIAN 249 uint32_t hdw; 250 #endif 251 struct { 252 #if defined(_BIT_FIELDS_HTOL) 253 uint32_t res:26; 254 uint32_t debug_select:6; 255 #elif defined(_BIT_FIELDS_LTOH) 256 uint32_t debug_select:6; 257 uint32_t res:26; 258 259 #endif 260 } ldw; 261 #ifndef _BIG_ENDIAN 262 uint32_t hdw; 263 #endif 264 } bits; 265 } txc_debug_select_t, *p_txc_debug_select_t; 266 267 268 #define TXC_MAX_REORDER_REG (FZC_TXC + 0x20018) 269 #define TXC_MAX_REORDER_MASK_2 (0xf) 270 #define TXC_MAX_REORDER_MASK_4 (0x7) 271 #define TXC_MAX_REORDER_SHIFT_BITS 8 272 #define TXC_MAX_REORDER_SHIFT(port) (port * (TXC_MAX_REORDER_SHIFT_BITS)) 273 274 typedef union _txc_max_reorder_t { 275 uint64_t value; 276 struct { 277 #ifdef _BIG_ENDIAN 278 uint32_t hdw; 279 #endif 280 struct { 281 #if defined(_BIT_FIELDS_HTOL) 282 uint32_t resv3:4; 283 uint32_t port3:4; 284 uint32_t resv2:4; 285 uint32_t port2:4; 286 uint32_t resv1:4; 287 uint32_t port1:4; 288 uint32_t resv0:4; 289 uint32_t port0:4; 290 #elif defined(_BIT_FIELDS_LTOH) 291 uint32_t port0:4; 292 uint32_t resv0:4; 293 uint32_t port1:4; 294 uint32_t resv1:4; 295 uint32_t port2:4; 296 uint32_t resv2:4; 297 uint32_t port3:4; 298 uint32_t resv3:4; 299 #endif 300 } ldw; 301 #ifndef _BIG_ENDIAN 302 uint32_t hdw; 303 #endif 304 } bits; 305 } txc_max_reorder_t, *p_txc_max_reorder_t; 306 307 308 #define TXC_PORT_CTL_REG (FZC_TXC + 0x20020) /* RO */ 309 #define TXC_PORT_CTL_OFFSET(port) (TXC_PORT_CTL_REG + \ 310 (port * TXC_FZC_CONTROL_OFFSET)) 311 #define TXC_PORT_CNTL_CLEAR 0x1 312 313 typedef union _txc_port_ctl_t { 314 uint64_t value; 315 struct { 316 #ifdef _BIG_ENDIAN 317 uint32_t hdw; 318 #endif 319 struct { 320 #if defined(_BIT_FIELDS_HTOL) 321 uint32_t rsvd:31; 322 uint32_t clr_all_stat:1; 323 #elif defined(_BIT_FIELDS_LTOH) 324 uint32_t clr_all_stat:1; 325 uint32_t rsvd:31; 326 #endif 327 } ldw; 328 #ifndef _BIG_ENDIAN 329 uint32_t hdw; 330 #endif 331 } bits; 332 } txc_port_ctl_t, *p_txc_port_ctl_t; 333 334 #define TXC_PKT_STUFFED_REG (FZC_TXC + 0x20030) 335 #define TXC_PKT_STUFF_PKTASY_SHIFT 16 /* RW bit 16:0 */ 336 #define TXC_PKT_STUFF_PKTASY_MASK 0x000000000000FFFFULL 337 #define TXC_PKT_STUFF_REORDER_SHIFT 0 /* RW bit 31:16 */ 338 #define TXC_PKT_STUFF_REORDER_MASK 0x00000000FFFF0000ULL 339 340 typedef union _txc_pkt_stuffed_t { 341 uint64_t value; 342 struct { 343 #ifdef _BIG_ENDIAN 344 uint32_t hdw; 345 #endif 346 struct { 347 #if defined(_BIT_FIELDS_HTOL) 348 uint32_t pkt_pro_reorder:16; 349 uint32_t pkt_proc_pktasy:16; 350 #elif defined(_BIT_FIELDS_LTOH) 351 uint32_t pkt_proc_pktasy:16; 352 uint32_t pkt_pro_reorder:16; 353 #endif 354 } ldw; 355 #ifndef _BIG_ENDIAN 356 uint32_t hdw; 357 #endif 358 } bits; 359 } txc_pkt_stuffed_t, *p_txc_pkt_stuffed_t; 360 361 362 #define TXC_PKT_XMIT_REG (FZC_TXC + 0x20038) 363 #define TXC_PKTS_XMIT_SHIFT 0 /* RW bit 15:0 */ 364 #define TXC_PKTS_XMIT_MASK 0x000000000000FFFFULL 365 #define TXC_BYTES_XMIT_SHIFT 16 /* RW bit 31:16 */ 366 #define TXC_BYTES_XMIT_MASK 0x00000000FFFF0000ULL 367 368 typedef union _txc_pkt_xmit_t { 369 uint64_t value; 370 struct { 371 #ifdef _BIG_ENDIAN 372 uint32_t hdw; 373 #endif 374 struct { 375 #if defined(_BIT_FIELDS_HTOL) 376 uint32_t bytes_transmitted:16; 377 uint32_t pkts_transmitted:16; 378 #elif defined(_BIT_FIELDS_LTOH) 379 uint32_t pkts_transmitted:16; 380 uint32_t bytes_transmitted:16; 381 #endif 382 } ldw; 383 #ifndef _BIG_ENDIAN 384 uint32_t hdw; 385 #endif 386 } bits; 387 } txc_pkt_xmit, *p_txc_pkt_xmit; 388 389 390 /* count 4 step 0x00100 */ 391 #define TXC_ROECC_CTL_REG (FZC_TXC + 0x20040) 392 #define TXC_ROECC_CTL_OFFSET(port) (TXC_ROECC_CTL_REG + \ 393 (TXC_FZC_CNTL_PORT_OFFSET(port))) 394 395 typedef union _txc_roecc_ctl_t { 396 uint64_t value; 397 struct { 398 #ifdef _BIG_ENDIAN 399 uint32_t hdw; 400 #endif 401 struct { 402 #if defined(_BIT_FIELDS_HTOL) 403 uint32_t disable_ue_error:1; 404 uint32_t rsvd:13; 405 uint32_t double_bit_err:1; 406 uint32_t single_bit_err:1; 407 uint32_t rsvd_2:5; 408 uint32_t all_pkts:1; 409 uint32_t alternate_pkts:1; 410 uint32_t one_pkt:1; 411 uint32_t rsvd_3:5; 412 uint32_t last_line_pkt:1; 413 uint32_t second_line_pkt:1; 414 uint32_t firstd_line_pkt:1; 415 #elif defined(_BIT_FIELDS_LTOH) 416 uint32_t firstd_line_pkt:1; 417 uint32_t second_line_pkt:1; 418 uint32_t last_line_pkt:1; 419 uint32_t rsvd_3:5; 420 uint32_t one_pkt:1; 421 uint32_t alternate_pkts:1; 422 uint32_t all_pkts:1; 423 uint32_t rsvd_2:5; 424 uint32_t single_bit_err:1; 425 uint32_t double_bit_err:1; 426 uint32_t rsvd:13; 427 uint32_t disable_ue_error:1; 428 #endif 429 } ldw; 430 #ifndef _BIG_ENDIAN 431 uint32_t hdw; 432 #endif 433 } bits; 434 } txc_roecc_ctl_t, *p_txc_roecc_ctl_t; 435 436 437 #define TXC_ROECC_ST_REG (FZC_TXC + 0x20048) 438 439 #define TXC_ROECC_ST_OFFSET(port) (TXC_ROECC_ST_REG + \ 440 (TXC_FZC_CNTL_PORT_OFFSET(port))) 441 442 typedef union _txc_roecc_st_t { 443 uint64_t value; 444 struct { 445 #ifdef _BIG_ENDIAN 446 uint32_t hdw; 447 #endif 448 struct { 449 #if defined(_BIT_FIELDS_HTOL) 450 uint32_t clr_st:1; 451 uint32_t res:13; 452 uint32_t correct_error:1; 453 uint32_t uncorrect_error:1; 454 uint32_t rsvd:6; 455 uint32_t ecc_address:10; 456 #elif defined(_BIT_FIELDS_LTOH) 457 uint32_t ecc_address:10; 458 uint32_t rsvd:6; 459 uint32_t uncorrect_error:1; 460 uint32_t correct_error:1; 461 uint32_t res:13; 462 uint32_t clr_st:1; 463 #endif 464 } ldw; 465 #ifndef _BIG_ENDIAN 466 uint32_t hdw; 467 #endif 468 } bits; 469 } txc_roecc_st_t, *p_txc_roecc_st_t; 470 471 472 #define TXC_RO_DATA0_REG (FZC_TXC + 0x20050) 473 #define TXC_RO_DATA0_OFFSET(port) (TXC_RO_DATA0_REG + \ 474 (TXC_FZC_CNTL_PORT_OFFSET(port))) 475 476 typedef union _txc_ro_data0_t { 477 uint64_t value; 478 struct { 479 #ifdef _BIG_ENDIAN 480 uint32_t hdw; 481 #endif 482 struct { 483 #if defined(_BIT_FIELDS_HTOL) 484 uint32_t ro_ecc_data0:32; /* ro_ecc_data[31:0] */ 485 #elif defined(_BIT_FIELDS_LTOH) 486 uint32_t ro_ecc_data0:32; /* ro_ecc_data[31:0] */ 487 #endif 488 } ldw; 489 #ifndef _BIG_ENDIAN 490 uint32_t hdw; 491 #endif 492 } bits; 493 } txc_ro_data0_t, *p_txc_ro_data0_t; 494 495 #define TXC_RO_DATA1_REG (FZC_TXC + 0x20058) 496 #define TXC_RO_DATA1_OFFSET(port) (TXC_RO_DATA1_REG + \ 497 (TXC_FZC_CNTL_PORT_OFFSET(port))) 498 499 typedef union _txc_ro_data1_t { 500 uint64_t value; 501 struct { 502 #ifdef _BIG_ENDIAN 503 uint32_t hdw; 504 #endif 505 struct { 506 #if defined(_BIT_FIELDS_HTOL) 507 uint32_t ro_ecc_data1:32; /* ro_ecc_data[63:32] */ 508 #elif defined(_BIT_FIELDS_LTOH) 509 uint32_t ro_ecc_data1:32; /* ro_ecc_data[31:32] */ 510 #endif 511 } ldw; 512 #ifndef _BIG_ENDIAN 513 uint32_t hdw; 514 #endif 515 } bits; 516 } txc_ro_data1_t, *p_txc_ro_data1_t; 517 518 519 #define TXC_RO_DATA2_REG (FZC_TXC + 0x20060) 520 521 #define TXC_RO_DATA2_OFFSET(port) (TXC_RO_DATA2_REG + \ 522 (TXC_FZC_CNTL_PORT_OFFSET(port))) 523 524 typedef union _txc_ro_data2_t { 525 uint64_t value; 526 struct { 527 #ifdef _BIG_ENDIAN 528 uint32_t hdw; 529 #endif 530 struct { 531 #if defined(_BIT_FIELDS_HTOL) 532 uint32_t ro_ecc_data2:32; /* ro_ecc_data[95:64] */ 533 #elif defined(_BIT_FIELDS_LTOH) 534 uint32_t ro_ecc_data2:32; /* ro_ecc_data[95:64] */ 535 #endif 536 } ldw; 537 #ifndef _BIG_ENDIAN 538 uint32_t hdw; 539 #endif 540 } bits; 541 } txc_ro_data2_t, *p_txc_ro_data2_t; 542 543 #define TXC_RO_DATA3_REG (FZC_TXC + 0x20068) 544 #define TXC_RO_DATA3_OFFSET(port) (TXC_RO_DATA3_REG + \ 545 (TXC_FZC_CNTL_PORT_OFFSET(port))) 546 547 typedef union _txc_ro_data3_t { 548 uint64_t value; 549 struct { 550 #ifdef _BIG_ENDIAN 551 uint32_t hdw; 552 #endif 553 struct { 554 #if defined(_BIT_FIELDS_HTOL) 555 uint32_t ro_ecc_data3:32; /* ro_ecc_data[127:96] */ 556 #elif defined(_BIT_FIELDS_LTOH) 557 uint32_t ro_ecc_data3:32; /* ro_ecc_data[127:96] */ 558 #endif 559 } ldw; 560 #ifndef _BIG_ENDIAN 561 uint32_t hdw; 562 #endif 563 } bits; 564 } txc_ro_data3_t, *p_txc_ro_data3_t; 565 566 #define TXC_RO_DATA4_REG (FZC_TXC + 0x20070) 567 #define TXC_RO_DATA4_OFFSET(port) (TXC_RO_DATA4_REG + \ 568 (TXC_FZC_CNTL_PORT_OFFSET(port))) 569 570 typedef union _txc_ro_data4_t { 571 uint64_t value; 572 struct { 573 #ifdef _BIG_ENDIAN 574 uint32_t hdw; 575 #endif 576 struct { 577 #if defined(_BIT_FIELDS_HTOL) 578 uint32_t ro_ecc_data4:32; /* ro_ecc_data[151:128] */ 579 #elif defined(_BIT_FIELDS_LTOH) 580 uint32_t ro_ecc_data4:32; /* ro_ecc_data[151:128] */ 581 #endif 582 } ldw; 583 #ifndef _BIG_ENDIAN 584 uint32_t hdw; 585 #endif 586 } bits; 587 } txc_ro_data4_t, *p_txc_ro_data4_t; 588 589 /* count 4 step 0x00100 */ 590 #define TXC_SFECC_CTL_REG (FZC_TXC + 0x20078) 591 #define TXC_SFECC_CTL_OFFSET(port) (TXC_SFECC_CTL_REG + \ 592 (TXC_FZC_CNTL_PORT_OFFSET(port))) 593 594 typedef union _txc_sfecc_ctl_t { 595 uint64_t value; 596 struct { 597 #ifdef _BIG_ENDIAN 598 uint32_t hdw; 599 #endif 600 struct { 601 #if defined(_BIT_FIELDS_HTOL) 602 uint32_t disable_ue_error:1; 603 uint32_t rsvd:13; 604 uint32_t double_bit_err:1; 605 uint32_t single_bit_err:1; 606 uint32_t rsvd_2:5; 607 uint32_t all_pkts:1; 608 uint32_t alternate_pkts:1; 609 uint32_t one_pkt:1; 610 uint32_t rsvd_3:5; 611 uint32_t last_line_pkt:1; 612 uint32_t second_line_pkt:1; 613 uint32_t firstd_line_pkt:1; 614 #elif defined(_BIT_FIELDS_LTOH) 615 uint32_t firstd_line_pkt:1; 616 uint32_t second_line_pkt:1; 617 uint32_t last_line_pkt:1; 618 uint32_t rsvd_3:5; 619 uint32_t one_pkt:1; 620 uint32_t alternate_pkts:1; 621 uint32_t all_pkts:1; 622 uint32_t rsvd_2:5; 623 uint32_t single_bit_err:1; 624 uint32_t double_bit_err:1; 625 uint32_t rsvd:13; 626 uint32_t disable_ue_error:1; 627 #endif 628 } ldw; 629 #ifndef _BIG_ENDIAN 630 uint32_t hdw; 631 #endif 632 } bits; 633 } txc_sfecc_ctl_t, *p_txc_sfecc_ctl_t; 634 635 #define TXC_SFECC_ST_REG (FZC_TXC + 0x20080) 636 #define TXC_SFECC_ST_OFFSET(port) (TXC_SFECC_ST_REG + \ 637 (TXC_FZC_CNTL_PORT_OFFSET(port))) 638 639 typedef union _txc_sfecc_st_t { 640 uint64_t value; 641 struct { 642 #ifdef _BIG_ENDIAN 643 uint32_t hdw; 644 #endif 645 struct { 646 #if defined(_BIT_FIELDS_HTOL) 647 uint32_t clr_st:1; 648 uint32_t res:13; 649 uint32_t correct_error:1; 650 uint32_t uncorrect_error:1; 651 uint32_t rsvd:6; 652 uint32_t ecc_address:10; 653 #elif defined(_BIT_FIELDS_LTOH) 654 uint32_t ecc_address:10; 655 uint32_t rsvd:6; 656 uint32_t uncorrect_error:1; 657 uint32_t correct_error:1; 658 uint32_t res:13; 659 uint32_t clr_st:1; 660 #endif 661 } ldw; 662 #ifndef _BIG_ENDIAN 663 uint32_t hdw; 664 #endif 665 } bits; 666 } txc_sfecc_st_t, *p_txc_sfecc_st_t; 667 668 #define TXC_SF_DATA0_REG (FZC_TXC + 0x20088) 669 #define TXC_SF_DATA0_OFFSET(port) (TXC_SF_DATA0_REG + \ 670 (TXC_FZC_CNTL_PORT_OFFSET(port))) 671 672 typedef union _txc_sf_data0_t { 673 uint64_t value; 674 struct { 675 #ifdef _BIG_ENDIAN 676 uint32_t hdw; 677 #endif 678 struct { 679 #if defined(_BIT_FIELDS_HTOL) 680 uint32_t sf_ecc_data0:32; /* sf_ecc_data[31:0] */ 681 #elif defined(_BIT_FIELDS_LTOH) 682 uint32_t sf_ecc_data0:32; /* sf_ecc_data[31:0] */ 683 #endif 684 } ldw; 685 #ifndef _BIG_ENDIAN 686 uint32_t hdw; 687 #endif 688 } bits; 689 } txc_sf_data0_t, *p_txc_sf_data0_t; 690 691 #define TXC_SF_DATA1_REG (FZC_TXC + 0x20090) 692 #define TXC_SF_DATA1_OFFSET(port) (TXC_SF_DATA1_REG + \ 693 (TXC_FZC_CNTL_PORT_OFFSET(port))) 694 695 typedef union _txc_sf_data1_t { 696 uint64_t value; 697 struct { 698 #ifdef _BIG_ENDIAN 699 uint32_t hdw; 700 #endif 701 struct { 702 #if defined(_BIT_FIELDS_HTOL) 703 uint32_t sf_ecc_data1:32; /* sf_ecc_data[63:32] */ 704 #elif defined(_BIT_FIELDS_LTOH) 705 uint32_t sf_ecc_data1:32; /* sf_ecc_data[31:32] */ 706 #endif 707 } ldw; 708 #ifndef _BIG_ENDIAN 709 uint32_t hdw; 710 #endif 711 } bits; 712 } txc_sf_data1_t, *p_txc_sf_data1_t; 713 714 715 #define TXC_SF_DATA2_REG (FZC_TXC + 0x20098) 716 #define TXC_SF_DATA2_OFFSET(port) (TXC_SF_DATA2_REG + \ 717 (TXC_FZC_CNTL_PORT_OFFSET(port))) 718 719 typedef union _txc_sf_data2_t { 720 uint64_t value; 721 struct { 722 #ifdef _BIG_ENDIAN 723 uint32_t hdw; 724 #endif 725 struct { 726 #if defined(_BIT_FIELDS_HTOL) 727 uint32_t sf_ecc_data2:32; /* sf_ecc_data[95:64] */ 728 #elif defined(_BIT_FIELDS_LTOH) 729 uint32_t sf_ecc_data2:32; /* sf_ecc_data[95:64] */ 730 #endif 731 } ldw; 732 #ifndef _BIG_ENDIAN 733 uint32_t hdw; 734 #endif 735 } bits; 736 } txc_sf_data2_t, *p_txc_sf_data2_t; 737 738 #define TXC_SF_DATA3_REG (FZC_TXC + 0x200A0) 739 #define TXC_SF_DATA3_OFFSET(port) (TXC_SF_DATA3_REG + \ 740 (TXC_FZC_CNTL_PORT_OFFSET(port))) 741 742 typedef union _txc_sf_data3_t { 743 uint64_t value; 744 struct { 745 #ifdef _BIG_ENDIAN 746 uint32_t hdw; 747 #endif 748 struct { 749 #if defined(_BIT_FIELDS_HTOL) 750 uint32_t sf_ecc_data3:32; /* sf_ecc_data[127:96] */ 751 #elif defined(_BIT_FIELDS_LTOH) 752 uint32_t sf_ecc_data3:32; /* sf_ecc_data[127:96] */ 753 #endif 754 } ldw; 755 #ifndef _BIG_ENDIAN 756 uint32_t hdw; 757 #endif 758 } bits; 759 } txc_sf_data3_t, *p_txc_sf_data3_t; 760 761 #define TXC_SF_DATA4_REG (FZC_TXC + 0x200A8) 762 #define TXC_SF_DATA4_OFFSET(port) (TXC_SF_DATA4_REG + \ 763 (TXC_FZC_CNTL_PORT_OFFSET(port))) 764 765 typedef union _txc_sf_data4_t { 766 uint64_t value; 767 struct { 768 #ifdef _BIG_ENDIAN 769 uint32_t hdw; 770 #endif 771 struct { 772 #if defined(_BIT_FIELDS_HTOL) 773 uint32_t sf_ecc_data4:32; /* sf_ecc_data[151:128] */ 774 #elif defined(_BIT_FIELDS_LTOH) 775 uint32_t sf_ecc_data4:32; /* sf_ecc_data[151:128] */ 776 #endif 777 } ldw; 778 #ifndef _BIG_ENDIAN 779 uint32_t hdw; 780 #endif 781 } bits; 782 } txc_sf_data4_t, *p_txc_sf_data4_t; 783 784 #define TXC_RO_TIDS_REG (FZC_TXC + 0x200B0) 785 #define TXC_RO_TIDS_OFFSET(port) (TXC_RO_TIDS_REG + \ 786 (TXC_FZC_CNTL_PORT_OFFSET(port))) 787 #define TXC_RO_TIDS_MASK 0x00000000FFFFFFFFULL 788 789 typedef union _txc_ro_tids_t { 790 uint64_t value; 791 struct { 792 #ifdef _BIG_ENDIAN 793 uint32_t hdw; 794 #endif 795 struct { 796 #if defined(_BIT_FIELDS_HTOL) 797 uint32_t tids_in_use:32; 798 #elif defined(_BIT_FIELDS_LTOH) 799 uint32_t tids_in_use:32; 800 #endif 801 } ldw; 802 #ifndef _BIG_ENDIAN 803 uint32_t hdw; 804 #endif 805 } bits; 806 } txc_ro_tids_t, *p_txc_ro_tids_t; 807 808 #define TXC_RO_STATE0_REG (FZC_TXC + 0x200B8) 809 #define TXC_RO_STATE0_OFFSET(port) (TXC_STATE0_REG + \ 810 (TXC_FZC_CNTL_PORT_OFFSET(port))) 811 #define TXC_RO_STATE0_MASK 0x00000000FFFFFFFFULL 812 813 typedef union _txc_ro_state0_t { 814 uint64_t value; 815 struct { 816 #ifdef _BIG_ENDIAN 817 uint32_t hdw; 818 #endif 819 struct { 820 #if defined(_BIT_FIELDS_HTOL) 821 uint32_t duplicate_tid:32; 822 #elif defined(_BIT_FIELDS_LTOH) 823 uint32_t duplicate_tid:32; 824 #endif 825 } ldw; 826 #ifndef _BIG_ENDIAN 827 uint32_t hdw; 828 #endif 829 } bits; 830 } txc_ro_state0_t, *p_txc_ro_state0_t; 831 832 #define TXC_RO_STATE1_REG (FZC_TXC + 0x200C0) 833 #define TXC_RO_STATE1_OFFSET(port) (TXC_STATE1_REG + \ 834 (TXC_FZC_CNTL_PORT_OFFSET(port))) 835 #define TXC_RO_STATE1_MASK 0x00000000FFFFFFFFULL 836 837 typedef union _txc_ro_state1_t { 838 uint64_t value; 839 struct { 840 #ifdef _BIG_ENDIAN 841 uint32_t hdw; 842 #endif 843 struct { 844 #if defined(_BIT_FIELDS_HTOL) 845 uint32_t unused_tid:32; 846 #elif defined(_BIT_FIELDS_LTOH) 847 uint32_t unused_tid:32; 848 #endif 849 } ldw; 850 #ifndef _BIG_ENDIAN 851 uint32_t hdw; 852 #endif 853 } bits; 854 } txc_ro_state1_t, *p_txc_ro_state1_t; 855 856 #define TXC_RO_STATE2_REG (FZC_TXC + 0x200C8) 857 #define TXC_RO_STATE2_OFFSET(port) (TXC_STATE2_REG + \ 858 (TXC_FZC_CNTL_PORT_OFFSET(port))) 859 #define TXC_RO_STATE2_MASK 0x00000000FFFFFFFFULL 860 861 typedef union _txc_ro_state2_t { 862 uint64_t value; 863 struct { 864 #ifdef _BIG_ENDIAN 865 uint32_t hdw; 866 #endif 867 struct { 868 #if defined(_BIT_FIELDS_HTOL) 869 uint32_t transaction_timeout:32; 870 #elif defined(_BIT_FIELDS_LTOH) 871 uint32_t transaction_timeout:32; 872 #endif 873 } ldw; 874 #ifndef _BIG_ENDIAN 875 uint32_t hdw; 876 #endif 877 } bits; 878 } txc_ro_state2_t, *p_txc_ro_state2_t; 879 880 #define TXC_RO_STATE3_REG (FZC_TXC + 0x200D0) 881 #define TXC_RO_STATE3_OFFSET(port) (TXC_RO_STATE3_REG + \ 882 (TXC_FZC_CNTL_PORT_OFFSET(port))) 883 884 typedef union _txc_ro_state3_t { 885 uint64_t value; 886 struct { 887 #ifdef _BIG_ENDIAN 888 uint32_t hdw; 889 #endif 890 struct { 891 #if defined(_BIT_FIELDS_HTOL) 892 uint32_t enable_spacefilled_watermark:1; 893 uint32_t ro_spacefilled_watermask:10; 894 uint32_t ro_fifo_spaceavailable:10; 895 uint32_t rsv:2; 896 uint32_t enable_ro_watermark:1; 897 uint32_t highest_reorder_used:4; 898 uint32_t num_reorder_used:4; 899 #elif defined(_BIT_FIELDS_LTOH) 900 uint32_t num_reorder_used:4; 901 uint32_t highest_reorder_used:4; 902 uint32_t enable_ro_watermark:1; 903 uint32_t rsv:2; 904 uint32_t ro_fifo_spaceavailable:10; 905 uint32_t ro_spacefilled_watermask:10; 906 uint32_t enable_spacefilled_watermark:1; 907 #endif 908 } ldw; 909 #ifndef _BIG_ENDIAN 910 uint32_t hdw; 911 #endif 912 } bits; 913 } txc_ro_state3_t, *p_txc_ro_state3_t; 914 915 #define TXC_RO_CTL_REG (FZC_TXC + 0x200D8) 916 #define TXC_RO_CTL_OFFSET(port) (TXC_RO_CTL_REG + \ 917 (TXC_FZC_CNTL_PORT_OFFSET(port))) 918 919 typedef union _txc_ro_ctl_t { 920 uint64_t value; 921 struct { 922 #ifdef _BIG_ENDIAN 923 uint32_t hdw; 924 #endif 925 struct { 926 #if defined(_BIT_FIELDS_HTOL) 927 uint32_t clr_fail_state:1; 928 uint32_t rsvd3:3; 929 uint32_t ro_addr1:4; 930 uint32_t rsvd2:1; 931 uint32_t address_failed:1; 932 uint32_t dma_failed:1; 933 uint32_t length_failed:1; 934 uint32_t rsv:1; 935 uint32_t capture_address_fail:1; 936 uint32_t capture_dma_fail:1; 937 uint32_t capture_length_fail:1; 938 uint32_t rsvd:8; 939 uint32_t ro_state_rd_done:1; 940 uint32_t ro_state_wr_done:1; 941 uint32_t ro_state_rd:1; 942 uint32_t ro_state_wr:1; 943 uint32_t ro_state_addr:4; 944 #elif defined(_BIT_FIELDS_LTOH) 945 uint32_t ro_state_addr:4; 946 uint32_t ro_state_wr:1; 947 uint32_t ro_state_rd:1; 948 uint32_t ro_state_wr_done:1; 949 uint32_t ro_state_rd_done:1; 950 uint32_t rsvd:8; 951 uint32_t capture_length_fail:1; 952 uint32_t capture_dma_fail:1; 953 uint32_t capture_address_fail:1; 954 uint32_t rsv:1; 955 uint32_t length_failed:1; 956 uint32_t dma_failed:1; 957 uint32_t address_failed:1; 958 uint32_t rsvd2:1; 959 uint32_t ro_addr1:4; 960 uint32_t rsvd3:3; 961 uint32_t clr_fail_state:1; 962 #endif 963 } ldw; 964 #ifndef _BIG_ENDIAN 965 uint32_t hdw; 966 #endif 967 } bits; 968 } txc_ro_ctl_t, *p_txc_ro_ctl_t; 969 970 971 #define TXC_RO_ST_DATA0_REG (FZC_TXC + 0x200E0) 972 #define TXC_RO_ST_DATA0_OFFSET(port) (TXC_RO_ST_DATA0_REG + \ 973 (TXC_FZC_CNTL_PORT_OFFSET(port))) 974 #define TXC_RO_ST_DATA0_MASK 0x00000000FFFFFFFFULL 975 976 typedef union _txc_ro_st_data0_t { 977 uint64_t value; 978 struct { 979 #ifdef _BIG_ENDIAN 980 uint32_t hdw; 981 #endif 982 struct { 983 #if defined(_BIT_FIELDS_HTOL) 984 uint32_t ro_st_dat0:32; 985 #elif defined(_BIT_FIELDS_LTOH) 986 uint32_t ro_st_dat0:32; 987 #endif 988 } ldw; 989 #ifndef _BIG_ENDIAN 990 uint32_t hdw; 991 #endif 992 } bits; 993 } txc_ro_st_data0_t, *p_txc_ro_st_data0_t; 994 995 996 #define TXC_RO_ST_DATA1_REG (FZC_TXC + 0x200E8) 997 #define TXC_RO_ST_DATA1_OFFSET(port) (TXC_RO_ST_DATA1_REG + \ 998 (TXC_FZC_CNTL_PORT_OFFSET(port))) 999 #define TXC_RO_ST_DATA1_MASK 0x00000000FFFFFFFFULL 1000 1001 typedef union _txc_ro_st_data1_t { 1002 uint64_t value; 1003 struct { 1004 #ifdef _BIG_ENDIAN 1005 uint32_t hdw; 1006 #endif 1007 struct { 1008 #if defined(_BIT_FIELDS_HTOL) 1009 uint32_t ro_st_dat1:32; 1010 #elif defined(_BIT_FIELDS_LTOH) 1011 uint32_t ro_st_dat1:32; 1012 #endif 1013 } ldw; 1014 #ifndef _BIG_ENDIAN 1015 uint32_t hdw; 1016 #endif 1017 } bits; 1018 } txc_ro_st_data1_t, *p_txc_ro_st_data1_t; 1019 1020 1021 #define TXC_RO_ST_DATA2_REG (FZC_TXC + 0x200F0) 1022 #define TXC_RO_ST_DATA2_OFFSET(port) (TXC_RO_ST_DATA2_REG + \ 1023 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1024 #define TXC_RO_ST_DATA2_MASK 0x00000000FFFFFFFFULL 1025 1026 typedef union _txc_ro_st_data2_t { 1027 uint64_t value; 1028 struct { 1029 #ifdef _BIG_ENDIAN 1030 uint32_t hdw; 1031 #endif 1032 struct { 1033 #if defined(_BIT_FIELDS_HTOL) 1034 uint32_t ro_st_dat2:32; 1035 #elif defined(_BIT_FIELDS_LTOH) 1036 uint32_t ro_st_dat2:32; 1037 #endif 1038 } ldw; 1039 #ifndef _BIG_ENDIAN 1040 uint32_t hdw; 1041 #endif 1042 } bits; 1043 } txc_ro_st_data2_t, *p_txc_ro_st_data2_t; 1044 1045 #define TXC_RO_ST_DATA3_REG (FZC_TXC + 0x200F8) 1046 #define TXC_RO_ST_DATA3_OFFSET(port) (TXC_RO_ST_DATA3_REG + \ 1047 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1048 #define TXC_RO_ST_DATA3_MASK 0x00000000FFFFFFFFULL 1049 1050 typedef union _txc_ro_st_data3_t { 1051 uint64_t value; 1052 struct { 1053 #ifdef _BIG_ENDIAN 1054 uint32_t hdw; 1055 #endif 1056 struct { 1057 #if defined(_BIT_FIELDS_HTOL) 1058 uint32_t ro_st_dat3:32; 1059 #elif defined(_BIT_FIELDS_LTOH) 1060 uint32_t ro_st_dat3:32; 1061 #endif 1062 } ldw; 1063 #ifndef _BIG_ENDIAN 1064 uint32_t hdw; 1065 #endif 1066 } bits; 1067 } txc_ro_st_data3_t, *p_txc_ro_st_data3_t; 1068 1069 #define TXC_PORT_PACKET_REQ_REG (FZC_TXC + 0x20100) 1070 #define TXC_PORT_PACKET_REQ_OFFSET(port) (TXC_PORT_PACKET_REQ_REG + \ 1071 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1072 #define TXC_PORT_PACKET_REQ_MASK 0x00000000FFFFFFFFULL 1073 1074 typedef union _txc_port_packet_req_t { 1075 uint64_t value; 1076 struct { 1077 #ifdef _BIG_ENDIAN 1078 uint32_t hdw; 1079 #endif 1080 struct { 1081 #if defined(_BIT_FIELDS_HTOL) 1082 uint32_t gather_req:4; 1083 uint32_t packet_eq:12; 1084 uint32_t pkterr_abort:16; 1085 #elif defined(_BIT_FIELDS_LTOH) 1086 uint32_t pkterr_abort:16; 1087 uint32_t packet_eq:12; 1088 uint32_t gather_req:4; 1089 #endif 1090 } ldw; 1091 #ifndef _BIG_ENDIAN 1092 uint32_t hdw; 1093 #endif 1094 } bits; 1095 } txc_port_packet_req_t, *p_txc_port_packet_req_t; 1096 1097 /* Reorder error bits in interrupt registers */ 1098 #define TXC_INT_STAT_SF_CORR_ERR 0x01 1099 #define TXC_INT_STAT_SF_UNCORR_ERR 0x02 1100 #define TXC_INT_STAT_RO_CORR_ERR 0x04 1101 #define TXC_INT_STAT_RO_UNCORR_ERR 0x08 1102 #define TXC_INT_STAT_REORDER_ERR 0x10 1103 #define TXC_INT_STAT_PKTASSYDEAD 0x20 1104 1105 #define TXC_INT_STAT_DBG_REG (FZC_TXC + 0x20420) 1106 #define TXC_INT_STAT_DBG_MASK 0x00000000FFFFFFFFULL 1107 1108 typedef union _txc_int_stat_dbg_t { 1109 uint64_t value; 1110 struct { 1111 #ifdef _BIG_ENDIAN 1112 uint32_t hdw; 1113 #endif 1114 struct { 1115 #if defined(_BIT_FIELDS_HTOL) 1116 uint32_t rsvd3:2; 1117 uint32_t port3_int_status:6; 1118 uint32_t rsvd2:2; 1119 uint32_t port2_int_status:6; 1120 uint32_t rsvd1:2; 1121 uint32_t port1_int_status:6; 1122 uint32_t rsvd:2; 1123 uint32_t port0_int_status:6; 1124 #elif defined(_BIT_FIELDS_LTOH) 1125 uint32_t port0_int_status:6; 1126 uint32_t rsvd:2; 1127 uint32_t port1_int_status:6; 1128 uint32_t rsvd1:2; 1129 uint32_t port2_int_status:6; 1130 uint32_t rsvd2:2; 1131 uint32_t port3_int_status:6; 1132 uint32_t rsvd3:2; 1133 #endif 1134 } ldw; 1135 #ifndef _BIG_ENDIAN 1136 uint32_t hdw; 1137 #endif 1138 } bits; 1139 } txc_int_stat_dbg_t, *p_txc_int_stat_dbg_t; 1140 1141 1142 #define TXC_INT_STAT_REG (FZC_TXC + 0x20428) 1143 #define TXC_INT_STAT_MASK 0x00000000FFFFFFFFULL 1144 1145 typedef union _txc_int_stat_t { 1146 uint64_t value; 1147 struct { 1148 #ifdef _BIG_ENDIAN 1149 uint32_t hdw; 1150 #endif 1151 struct { 1152 #if defined(_BIT_FIELDS_HTOL) 1153 uint32_t rsvd3:2; 1154 uint32_t port3_int_status:6; 1155 uint32_t rsvd2:2; 1156 uint32_t port2_int_status:6; 1157 uint32_t rsvd1:2; 1158 uint32_t port1_int_status:6; 1159 uint32_t rsvd:2; 1160 uint32_t port0_int_status:6; 1161 #elif defined(_BIT_FIELDS_LTOH) 1162 uint32_t port0_int_status:6; 1163 uint32_t rsvd:2; 1164 uint32_t port1_int_status:6; 1165 uint32_t rsvd1:2; 1166 uint32_t port2_int_status:6; 1167 uint32_t rsvd2:2; 1168 uint32_t port3_int_status:6; 1169 uint32_t rsvd3:2; 1170 #endif 1171 } ldw; 1172 #ifndef _BIG_ENDIAN 1173 uint32_t hdw; 1174 #endif 1175 } bits; 1176 } txc_int_stat_t, *p_txc_int_stat_t; 1177 1178 #define TXC_INT_MASK_REG (FZC_TXC + 0x20430) 1179 #define TXC_INT_MASK_MASK 0x00000000FFFFFFFFULL 1180 #define TXC_INT_MASK_IVAL 0x3f 1181 1182 typedef union _txc_int_mask_t { 1183 uint64_t value; 1184 struct { 1185 #ifdef _BIG_ENDIAN 1186 uint32_t hdw; 1187 #endif 1188 struct { 1189 #if defined(_BIT_FIELDS_HTOL) 1190 uint32_t rsvd3:2; 1191 uint32_t port3_int_mask:6; 1192 uint32_t rsvd2:2; 1193 uint32_t port2_int_mask:6; 1194 uint32_t rsvd1:2; 1195 uint32_t port1_int_mask:6; 1196 uint32_t rsvd:2; 1197 uint32_t port0_int_mask:6; 1198 #elif defined(_BIT_FIELDS_LTOH) 1199 uint32_t port0_int_mask:6; 1200 uint32_t rsvd:2; 1201 uint32_t port1_int_mask:6; 1202 uint32_t rsvd1:2; 1203 uint32_t port2_int_mask:6; 1204 uint32_t rsvd2:2; 1205 uint32_t port3_int_mask:6; 1206 uint32_t rsvd3:2; 1207 #endif 1208 } ldw; 1209 #ifndef _BIG_ENDIAN 1210 uint32_t hdw; 1211 #endif 1212 } bits; 1213 } txc_int_mask_t, *p_txc_int_mask_t; 1214 1215 /* 2 ports */ 1216 typedef union _txc_int_mask_n2_t { 1217 uint64_t value; 1218 struct { 1219 #ifdef _BIG_ENDIAN 1220 uint32_t hdw; 1221 #endif 1222 struct { 1223 #if defined(_BIT_FIELDS_HTOL) 1224 uint32_t rsvd1:18; 1225 uint32_t port1_int_mask:6; 1226 uint32_t rsvd:2; 1227 uint32_t port0_int_mask:6; 1228 #elif defined(_BIT_FIELDS_LTOH) 1229 uint32_t port0_int_mask:6; 1230 uint32_t rsvd:2; 1231 uint32_t port1_int_mask:6; 1232 uint32_t rsvd1:18; 1233 #endif 1234 } ldw; 1235 #ifndef _BIG_ENDIAN 1236 uint32_t hdw; 1237 #endif 1238 } bits; 1239 } txc_int_mask_n2_t, *p_txc_int_mask_n2_t; 1240 1241 typedef struct _txc_ro_states { 1242 txc_roecc_st_t roecc; 1243 txc_ro_data0_t d0; 1244 txc_ro_data1_t d1; 1245 txc_ro_data2_t d2; 1246 txc_ro_data3_t d3; 1247 txc_ro_data4_t d4; 1248 txc_ro_tids_t tids; 1249 txc_ro_state0_t st0; 1250 txc_ro_state1_t st1; 1251 txc_ro_state2_t st2; 1252 txc_ro_state3_t st3; 1253 txc_ro_ctl_t ctl; 1254 } txc_ro_states_t, *p_txc_ro_states_t; 1255 1256 typedef struct _txc_sf_states { 1257 txc_sfecc_st_t sfecc; 1258 txc_sf_data0_t d0; 1259 txc_sf_data1_t d1; 1260 txc_sf_data2_t d2; 1261 txc_sf_data3_t d3; 1262 txc_sf_data4_t d4; 1263 } txc_sf_states_t, *p_txc_sf_states_t; 1264 1265 #ifdef __cplusplus 1266 } 1267 #endif 1268 1269 #endif /* _SYS_NXGE_NXGE_TXC_HW_H */ 1270