1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXC_HW_H 27 #define _SYS_NXGE_NXGE_TXC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* Transmit Ring Scheduler Registers */ 38 #define TXC_PORT_DMA_ENABLE_REG (FZC_TXC + 0x20028) 39 #define TXC_PORT_DMA_LIST 0 /* RW bit 23:0 */ 40 #define TXC_DMA_DMA_LIST_MASK 0x0000000000FFFFFFULL 41 #define TXC_DMA_DMA_LIST_MASK_N2 0x000000000000FFFFULL 42 43 typedef union _txc_port_enable_t { 44 uint64_t value; 45 struct { 46 #ifdef _BIG_ENDIAN 47 uint32_t hdw; 48 #endif 49 struct { 50 #if defined(_BIT_FIELDS_HTOL) 51 uint32_t res:8; 52 uint32_t port_dma_list:24; 53 #elif defined(_BIT_FIELDS_LTOH) 54 uint32_t port_dma_list:24; 55 uint32_t res:8; 56 #endif 57 } ldw; 58 #ifndef _BIG_ENDIAN 59 uint32_t hdw; 60 #endif 61 } bits; 62 } txc_port_enable_t, *p_txc_port_enable_t; 63 64 typedef union _txc_port_enable_n2_t { 65 uint64_t value; 66 struct { 67 #ifdef _BIG_ENDIAN 68 uint32_t hdw; 69 #endif 70 struct { 71 #if defined(_BIT_FIELDS_HTOL) 72 uint32_t res:16; 73 uint32_t port_dma_list:16; 74 #elif defined(_BIT_FIELDS_LTOH) 75 uint32_t port_dma_list:16; 76 uint32_t res:16; 77 #endif 78 } ldw; 79 #ifndef _BIG_ENDIAN 80 uint32_t hdw; 81 #endif 82 } bits; 83 } txc_port_enable_n2_t, *p_txc_port_enable_n2_t; 84 85 /* Transmit Controller - Registers */ 86 #define TXC_FZC_OFFSET 0x1000 87 #define TXC_FZC_PORT_OFFSET(port) (port * TXC_FZC_OFFSET) 88 #define TXC_FZC_CHANNEL_OFFSET(channel) (channel * TXC_FZC_OFFSET) 89 #define TXC_FZC_REG_CN_OFFSET(x, cn) (x + TXC_FZC_CHANNEL_OFFSET(cn)) 90 91 #define TXC_FZC_CONTROL_OFFSET 0x100 92 #define TXC_FZC_CNTL_PORT_OFFSET(port) (port * TXC_FZC_CONTROL_OFFSET) 93 #define TXC_FZC_REG_PT_OFFSET(x, pt) (x + TXC_FZC_CNTL_PORT_OFFSET(pt)) 94 95 #define TXC_DMA_MAX_BURST_REG (FZC_TXC + 0x00000) 96 #define TXC_DMA_MAX_BURST_SHIFT 0 /* RW bit 19:0 */ 97 #define TXC_DMA_MAX_BURST_MASK 0x00000000000FFFFFULL 98 99 #define TXC_MAX_BURST_OFFSET(channel) (TXC_DMA_MAX_BURST_REG + \ 100 (channel * TXC_FZC_OFFSET)) 101 102 typedef union _txc_dma_max_burst_t { 103 uint64_t value; 104 struct { 105 #ifdef _BIG_ENDIAN 106 uint32_t hdw; 107 #endif 108 struct { 109 #if defined(_BIT_FIELDS_HTOL) 110 uint32_t res:12; 111 uint32_t dma_max_burst:20; 112 #elif defined(_BIT_FIELDS_LTOH) 113 uint32_t dma_max_burst:20; 114 uint32_t res:12; 115 116 #endif 117 } ldw; 118 #ifndef _BIG_ENDIAN 119 uint32_t hdw; 120 #endif 121 } bits; 122 } txc_dma_max_burst_t, *p_txc_dma_max_burst_t; 123 124 /* DRR Performance Monitoring Register */ 125 #define TXC_DMA_MAX_LENGTH_REG (FZC_TXC + 0x00008) 126 #define TXC_DMA_MAX_LENGTH_SHIFT /* RW bit 27:0 */ 127 #define TXC_DMA_MAX_LENGTH_MASK 0x000000000FFFFFFFULL 128 129 #define TXC_DMA_MAX_LEN_OFFSET(channel) (TXC_DMA_MAX_LENGTH_REG + \ 130 (channel * TXC_FZC_OFFSET)) 131 132 typedef union _txc_dma_max_length_t { 133 uint64_t value; 134 struct { 135 #ifdef _BIG_ENDIAN 136 uint32_t hdw; 137 #endif 138 struct { 139 #if defined(_BIT_FIELDS_HTOL) 140 uint32_t res:4; 141 uint32_t dma_length:28; 142 #elif defined(_BIT_FIELDS_LTOH) 143 uint32_t dma_length:28; 144 uint32_t res:4; 145 146 #endif 147 } ldw; 148 #ifndef _BIG_ENDIAN 149 uint32_t hdw; 150 #endif 151 } bits; 152 } txc_dma_max_length_t, *p_txc_dma_max_length_t; 153 154 155 #define TXC_CONTROL_REG (FZC_TXC + 0x20000) 156 #define TXC_DMA_LENGTH_SHIFT 0 /* RW bit 27:0 */ 157 #define TXC_DMA_LENGTH_MASK 0x000000000FFFFFFFULL 158 159 typedef union _txc_control_t { 160 uint64_t value; 161 struct { 162 #ifdef _BIG_ENDIAN 163 uint32_t hdw; 164 #endif 165 struct { 166 #if defined(_BIT_FIELDS_HTOL) 167 uint32_t res:27; 168 uint32_t txc_enabled:1; 169 uint32_t port3_enabled:1; 170 uint32_t port2_enabled:1; 171 uint32_t port1_enabled:1; 172 uint32_t port0_enabled:1; 173 #elif defined(_BIT_FIELDS_LTOH) 174 uint32_t port0_enabled:1; 175 uint32_t port1_enabled:1; 176 uint32_t port2_enabled:1; 177 uint32_t port3_enabled:1; 178 uint32_t txc_enabled:1; 179 uint32_t res:27; 180 181 #endif 182 } ldw; 183 #ifndef _BIG_ENDIAN 184 uint32_t hdw; 185 #endif 186 } bits; 187 } txc_control_t, *p_txc_control_t; 188 189 typedef union _txc_control_n2_t { 190 uint64_t value; 191 struct { 192 #ifdef _BIG_ENDIAN 193 uint32_t hdw; 194 #endif 195 struct { 196 #if defined(_BIT_FIELDS_HTOL) 197 uint32_t res:27; 198 uint32_t txc_enabled:1; 199 uint32_t res1:2; 200 uint32_t port1_enabled:1; 201 uint32_t port0_enabled:1; 202 #elif defined(_BIT_FIELDS_LTOH) 203 uint32_t port0_enabled:1; 204 uint32_t port1_enabled:1; 205 uint32_t res1:2; 206 uint32_t txc_enabled:1; 207 uint32_t res:27; 208 209 #endif 210 } ldw; 211 #ifndef _BIG_ENDIAN 212 uint32_t hdw; 213 #endif 214 } bits; 215 } txc_control_n2_t, *p_txc_control_n2_t; 216 217 218 #define TXC_TRAINING_REG (FZC_TXC + 0x20008) 219 #define TXC_TRAINING_VECTOR 0 /* RW bit 32:0 */ 220 #define TXC_TRAINING_VECTOR_MASK 0x00000000FFFFFFFFULL 221 222 typedef union _txc_training_t { 223 uint64_t value; 224 struct { 225 #ifdef _BIG_ENDIAN 226 uint32_t hdw; 227 #endif 228 struct { 229 #if defined(_BIT_FIELDS_HTOL) 230 uint32_t txc_training_vector:32; 231 #elif defined(_BIT_FIELDS_LTOH) 232 uint32_t txc_training_vector:32; 233 234 #endif 235 } ldw; 236 #ifndef _BIG_ENDIAN 237 uint32_t hdw; 238 #endif 239 } bits; 240 } txc_training_t, *p_txc_training_t; 241 242 243 #define TXC_DEBUG_SELECT_REG (FZC_TXC + 0x20010) 244 #define TXC_DEBUG_SELECT_SHIFT 0 /* WO bit 5:0 */ 245 #define TXC_DEBUG_SELECT_MASK 0x000000000000003FULL 246 247 typedef union _txc_debug_select_t { 248 uint64_t value; 249 struct { 250 #ifdef _BIG_ENDIAN 251 uint32_t hdw; 252 #endif 253 struct { 254 #if defined(_BIT_FIELDS_HTOL) 255 uint32_t res:26; 256 uint32_t debug_select:6; 257 #elif defined(_BIT_FIELDS_LTOH) 258 uint32_t debug_select:6; 259 uint32_t res:26; 260 261 #endif 262 } ldw; 263 #ifndef _BIG_ENDIAN 264 uint32_t hdw; 265 #endif 266 } bits; 267 } txc_debug_select_t, *p_txc_debug_select_t; 268 269 270 #define TXC_MAX_REORDER_REG (FZC_TXC + 0x20018) 271 #define TXC_MAX_REORDER_MASK_2 (0xf) 272 #define TXC_MAX_REORDER_MASK_4 (0x7) 273 #define TXC_MAX_REORDER_SHIFT_BITS 8 274 #define TXC_MAX_REORDER_SHIFT(port) (port * (TXC_MAX_REORDER_SHIFT_BITS)) 275 276 typedef union _txc_max_reorder_t { 277 uint64_t value; 278 struct { 279 #ifdef _BIG_ENDIAN 280 uint32_t hdw; 281 #endif 282 struct { 283 #if defined(_BIT_FIELDS_HTOL) 284 uint32_t resv3:4; 285 uint32_t port3:4; 286 uint32_t resv2:4; 287 uint32_t port2:4; 288 uint32_t resv1:4; 289 uint32_t port1:4; 290 uint32_t resv0:4; 291 uint32_t port0:4; 292 #elif defined(_BIT_FIELDS_LTOH) 293 uint32_t port0:4; 294 uint32_t resv0:4; 295 uint32_t port1:4; 296 uint32_t resv1:4; 297 uint32_t port2:4; 298 uint32_t resv2:4; 299 uint32_t port3:4; 300 uint32_t resv3:4; 301 #endif 302 } ldw; 303 #ifndef _BIG_ENDIAN 304 uint32_t hdw; 305 #endif 306 } bits; 307 } txc_max_reorder_t, *p_txc_max_reorder_t; 308 309 310 #define TXC_PORT_CTL_REG (FZC_TXC + 0x20020) /* RO */ 311 #define TXC_PORT_CTL_OFFSET(port) (TXC_PORT_CTL_REG + \ 312 (port * TXC_FZC_CONTROL_OFFSET)) 313 #define TXC_PORT_CNTL_CLEAR 0x1 314 315 typedef union _txc_port_ctl_t { 316 uint64_t value; 317 struct { 318 #ifdef _BIG_ENDIAN 319 uint32_t hdw; 320 #endif 321 struct { 322 #if defined(_BIT_FIELDS_HTOL) 323 uint32_t rsvd:31; 324 uint32_t clr_all_stat:1; 325 #elif defined(_BIT_FIELDS_LTOH) 326 uint32_t clr_all_stat:1; 327 uint32_t rsvd:31; 328 #endif 329 } ldw; 330 #ifndef _BIG_ENDIAN 331 uint32_t hdw; 332 #endif 333 } bits; 334 } txc_port_ctl_t, *p_txc_port_ctl_t; 335 336 #define TXC_PKT_STUFFED_REG (FZC_TXC + 0x20030) 337 #define TXC_PKT_STUFF_PKTASY_SHIFT 16 /* RW bit 16:0 */ 338 #define TXC_PKT_STUFF_PKTASY_MASK 0x000000000000FFFFULL 339 #define TXC_PKT_STUFF_REORDER_SHIFT 0 /* RW bit 31:16 */ 340 #define TXC_PKT_STUFF_REORDER_MASK 0x00000000FFFF0000ULL 341 342 typedef union _txc_pkt_stuffed_t { 343 uint64_t value; 344 struct { 345 #ifdef _BIG_ENDIAN 346 uint32_t hdw; 347 #endif 348 struct { 349 #if defined(_BIT_FIELDS_HTOL) 350 uint32_t pkt_pro_reorder:16; 351 uint32_t pkt_proc_pktasy:16; 352 #elif defined(_BIT_FIELDS_LTOH) 353 uint32_t pkt_proc_pktasy:16; 354 uint32_t pkt_pro_reorder:16; 355 #endif 356 } ldw; 357 #ifndef _BIG_ENDIAN 358 uint32_t hdw; 359 #endif 360 } bits; 361 } txc_pkt_stuffed_t, *p_txc_pkt_stuffed_t; 362 363 364 #define TXC_PKT_XMIT_REG (FZC_TXC + 0x20038) 365 #define TXC_PKTS_XMIT_SHIFT 0 /* RW bit 15:0 */ 366 #define TXC_PKTS_XMIT_MASK 0x000000000000FFFFULL 367 #define TXC_BYTES_XMIT_SHIFT 16 /* RW bit 31:16 */ 368 #define TXC_BYTES_XMIT_MASK 0x00000000FFFF0000ULL 369 370 typedef union _txc_pkt_xmit_t { 371 uint64_t value; 372 struct { 373 #ifdef _BIG_ENDIAN 374 uint32_t hdw; 375 #endif 376 struct { 377 #if defined(_BIT_FIELDS_HTOL) 378 uint32_t bytes_transmitted:16; 379 uint32_t pkts_transmitted:16; 380 #elif defined(_BIT_FIELDS_LTOH) 381 uint32_t pkts_transmitted:16; 382 uint32_t bytes_transmitted:16; 383 #endif 384 } ldw; 385 #ifndef _BIG_ENDIAN 386 uint32_t hdw; 387 #endif 388 } bits; 389 } txc_pkt_xmit, *p_txc_pkt_xmit; 390 391 392 /* count 4 step 0x00100 */ 393 #define TXC_ROECC_CTL_REG (FZC_TXC + 0x20040) 394 #define TXC_ROECC_CTL_OFFSET(port) (TXC_ROECC_CTL_REG + \ 395 (TXC_FZC_CNTL_PORT_OFFSET(port))) 396 397 typedef union _txc_roecc_ctl_t { 398 uint64_t value; 399 struct { 400 #ifdef _BIG_ENDIAN 401 uint32_t hdw; 402 #endif 403 struct { 404 #if defined(_BIT_FIELDS_HTOL) 405 uint32_t disable_ue_error:1; 406 uint32_t rsvd:13; 407 uint32_t double_bit_err:1; 408 uint32_t single_bit_err:1; 409 uint32_t rsvd_2:5; 410 uint32_t all_pkts:1; 411 uint32_t alternate_pkts:1; 412 uint32_t one_pkt:1; 413 uint32_t rsvd_3:5; 414 uint32_t last_line_pkt:1; 415 uint32_t second_line_pkt:1; 416 uint32_t firstd_line_pkt:1; 417 #elif defined(_BIT_FIELDS_LTOH) 418 uint32_t firstd_line_pkt:1; 419 uint32_t second_line_pkt:1; 420 uint32_t last_line_pkt:1; 421 uint32_t rsvd_3:5; 422 uint32_t one_pkt:1; 423 uint32_t alternate_pkts:1; 424 uint32_t all_pkts:1; 425 uint32_t rsvd_2:5; 426 uint32_t single_bit_err:1; 427 uint32_t double_bit_err:1; 428 uint32_t rsvd:13; 429 uint32_t disable_ue_error:1; 430 #endif 431 } ldw; 432 #ifndef _BIG_ENDIAN 433 uint32_t hdw; 434 #endif 435 } bits; 436 } txc_roecc_ctl_t, *p_txc_roecc_ctl_t; 437 438 439 #define TXC_ROECC_ST_REG (FZC_TXC + 0x20048) 440 441 #define TXC_ROECC_ST_OFFSET(port) (TXC_ROECC_ST_REG + \ 442 (TXC_FZC_CNTL_PORT_OFFSET(port))) 443 444 typedef union _txc_roecc_st_t { 445 uint64_t value; 446 struct { 447 #ifdef _BIG_ENDIAN 448 uint32_t hdw; 449 #endif 450 struct { 451 #if defined(_BIT_FIELDS_HTOL) 452 uint32_t clr_st:1; 453 uint32_t res:13; 454 uint32_t correct_error:1; 455 uint32_t uncorrect_error:1; 456 uint32_t rsvd:6; 457 uint32_t ecc_address:10; 458 #elif defined(_BIT_FIELDS_LTOH) 459 uint32_t ecc_address:10; 460 uint32_t rsvd:6; 461 uint32_t uncorrect_error:1; 462 uint32_t correct_error:1; 463 uint32_t res:13; 464 uint32_t clr_st:1; 465 #endif 466 } ldw; 467 #ifndef _BIG_ENDIAN 468 uint32_t hdw; 469 #endif 470 } bits; 471 } txc_roecc_st_t, *p_txc_roecc_st_t; 472 473 474 #define TXC_RO_DATA0_REG (FZC_TXC + 0x20050) 475 #define TXC_RO_DATA0_OFFSET(port) (TXC_RO_DATA0_REG + \ 476 (TXC_FZC_CNTL_PORT_OFFSET(port))) 477 478 typedef union _txc_ro_data0_t { 479 uint64_t value; 480 struct { 481 #ifdef _BIG_ENDIAN 482 uint32_t hdw; 483 #endif 484 struct { 485 #if defined(_BIT_FIELDS_HTOL) 486 uint32_t ro_ecc_data0:32; /* ro_ecc_data[31:0] */ 487 #elif defined(_BIT_FIELDS_LTOH) 488 uint32_t ro_ecc_data0:32; /* ro_ecc_data[31:0] */ 489 #endif 490 } ldw; 491 #ifndef _BIG_ENDIAN 492 uint32_t hdw; 493 #endif 494 } bits; 495 } txc_ro_data0_t, *p_txc_ro_data0_t; 496 497 #define TXC_RO_DATA1_REG (FZC_TXC + 0x20058) 498 #define TXC_RO_DATA1_OFFSET(port) (TXC_RO_DATA1_REG + \ 499 (TXC_FZC_CNTL_PORT_OFFSET(port))) 500 501 typedef union _txc_ro_data1_t { 502 uint64_t value; 503 struct { 504 #ifdef _BIG_ENDIAN 505 uint32_t hdw; 506 #endif 507 struct { 508 #if defined(_BIT_FIELDS_HTOL) 509 uint32_t ro_ecc_data1:32; /* ro_ecc_data[63:32] */ 510 #elif defined(_BIT_FIELDS_LTOH) 511 uint32_t ro_ecc_data1:32; /* ro_ecc_data[31:32] */ 512 #endif 513 } ldw; 514 #ifndef _BIG_ENDIAN 515 uint32_t hdw; 516 #endif 517 } bits; 518 } txc_ro_data1_t, *p_txc_ro_data1_t; 519 520 521 #define TXC_RO_DATA2_REG (FZC_TXC + 0x20060) 522 523 #define TXC_RO_DATA2_OFFSET(port) (TXC_RO_DATA2_REG + \ 524 (TXC_FZC_CNTL_PORT_OFFSET(port))) 525 526 typedef union _txc_ro_data2_t { 527 uint64_t value; 528 struct { 529 #ifdef _BIG_ENDIAN 530 uint32_t hdw; 531 #endif 532 struct { 533 #if defined(_BIT_FIELDS_HTOL) 534 uint32_t ro_ecc_data2:32; /* ro_ecc_data[95:64] */ 535 #elif defined(_BIT_FIELDS_LTOH) 536 uint32_t ro_ecc_data2:32; /* ro_ecc_data[95:64] */ 537 #endif 538 } ldw; 539 #ifndef _BIG_ENDIAN 540 uint32_t hdw; 541 #endif 542 } bits; 543 } txc_ro_data2_t, *p_txc_ro_data2_t; 544 545 #define TXC_RO_DATA3_REG (FZC_TXC + 0x20068) 546 #define TXC_RO_DATA3_OFFSET(port) (TXC_RO_DATA3_REG + \ 547 (TXC_FZC_CNTL_PORT_OFFSET(port))) 548 549 typedef union _txc_ro_data3_t { 550 uint64_t value; 551 struct { 552 #ifdef _BIG_ENDIAN 553 uint32_t hdw; 554 #endif 555 struct { 556 #if defined(_BIT_FIELDS_HTOL) 557 uint32_t ro_ecc_data3:32; /* ro_ecc_data[127:96] */ 558 #elif defined(_BIT_FIELDS_LTOH) 559 uint32_t ro_ecc_data3:32; /* ro_ecc_data[127:96] */ 560 #endif 561 } ldw; 562 #ifndef _BIG_ENDIAN 563 uint32_t hdw; 564 #endif 565 } bits; 566 } txc_ro_data3_t, *p_txc_ro_data3_t; 567 568 #define TXC_RO_DATA4_REG (FZC_TXC + 0x20070) 569 #define TXC_RO_DATA4_OFFSET(port) (TXC_RO_DATA4_REG + \ 570 (TXC_FZC_CNTL_PORT_OFFSET(port))) 571 572 typedef union _txc_ro_data4_t { 573 uint64_t value; 574 struct { 575 #ifdef _BIG_ENDIAN 576 uint32_t hdw; 577 #endif 578 struct { 579 #if defined(_BIT_FIELDS_HTOL) 580 uint32_t ro_ecc_data4:32; /* ro_ecc_data[151:128] */ 581 #elif defined(_BIT_FIELDS_LTOH) 582 uint32_t ro_ecc_data4:32; /* ro_ecc_data[151:128] */ 583 #endif 584 } ldw; 585 #ifndef _BIG_ENDIAN 586 uint32_t hdw; 587 #endif 588 } bits; 589 } txc_ro_data4_t, *p_txc_ro_data4_t; 590 591 /* count 4 step 0x00100 */ 592 #define TXC_SFECC_CTL_REG (FZC_TXC + 0x20078) 593 #define TXC_SFECC_CTL_OFFSET(port) (TXC_SFECC_CTL_REG + \ 594 (TXC_FZC_CNTL_PORT_OFFSET(port))) 595 596 typedef union _txc_sfecc_ctl_t { 597 uint64_t value; 598 struct { 599 #ifdef _BIG_ENDIAN 600 uint32_t hdw; 601 #endif 602 struct { 603 #if defined(_BIT_FIELDS_HTOL) 604 uint32_t disable_ue_error:1; 605 uint32_t rsvd:13; 606 uint32_t double_bit_err:1; 607 uint32_t single_bit_err:1; 608 uint32_t rsvd_2:5; 609 uint32_t all_pkts:1; 610 uint32_t alternate_pkts:1; 611 uint32_t one_pkt:1; 612 uint32_t rsvd_3:5; 613 uint32_t last_line_pkt:1; 614 uint32_t second_line_pkt:1; 615 uint32_t firstd_line_pkt:1; 616 #elif defined(_BIT_FIELDS_LTOH) 617 uint32_t firstd_line_pkt:1; 618 uint32_t second_line_pkt:1; 619 uint32_t last_line_pkt:1; 620 uint32_t rsvd_3:5; 621 uint32_t one_pkt:1; 622 uint32_t alternate_pkts:1; 623 uint32_t all_pkts:1; 624 uint32_t rsvd_2:5; 625 uint32_t single_bit_err:1; 626 uint32_t double_bit_err:1; 627 uint32_t rsvd:13; 628 uint32_t disable_ue_error:1; 629 #endif 630 } ldw; 631 #ifndef _BIG_ENDIAN 632 uint32_t hdw; 633 #endif 634 } bits; 635 } txc_sfecc_ctl_t, *p_txc_sfecc_ctl_t; 636 637 #define TXC_SFECC_ST_REG (FZC_TXC + 0x20080) 638 #define TXC_SFECC_ST_OFFSET(port) (TXC_SFECC_ST_REG + \ 639 (TXC_FZC_CNTL_PORT_OFFSET(port))) 640 641 typedef union _txc_sfecc_st_t { 642 uint64_t value; 643 struct { 644 #ifdef _BIG_ENDIAN 645 uint32_t hdw; 646 #endif 647 struct { 648 #if defined(_BIT_FIELDS_HTOL) 649 uint32_t clr_st:1; 650 uint32_t res:13; 651 uint32_t correct_error:1; 652 uint32_t uncorrect_error:1; 653 uint32_t rsvd:6; 654 uint32_t ecc_address:10; 655 #elif defined(_BIT_FIELDS_LTOH) 656 uint32_t ecc_address:10; 657 uint32_t rsvd:6; 658 uint32_t uncorrect_error:1; 659 uint32_t correct_error:1; 660 uint32_t res:13; 661 uint32_t clr_st:1; 662 #endif 663 } ldw; 664 #ifndef _BIG_ENDIAN 665 uint32_t hdw; 666 #endif 667 } bits; 668 } txc_sfecc_st_t, *p_txc_sfecc_st_t; 669 670 #define TXC_SF_DATA0_REG (FZC_TXC + 0x20088) 671 #define TXC_SF_DATA0_OFFSET(port) (TXC_SF_DATA0_REG + \ 672 (TXC_FZC_CNTL_PORT_OFFSET(port))) 673 674 typedef union _txc_sf_data0_t { 675 uint64_t value; 676 struct { 677 #ifdef _BIG_ENDIAN 678 uint32_t hdw; 679 #endif 680 struct { 681 #if defined(_BIT_FIELDS_HTOL) 682 uint32_t sf_ecc_data0:32; /* sf_ecc_data[31:0] */ 683 #elif defined(_BIT_FIELDS_LTOH) 684 uint32_t sf_ecc_data0:32; /* sf_ecc_data[31:0] */ 685 #endif 686 } ldw; 687 #ifndef _BIG_ENDIAN 688 uint32_t hdw; 689 #endif 690 } bits; 691 } txc_sf_data0_t, *p_txc_sf_data0_t; 692 693 #define TXC_SF_DATA1_REG (FZC_TXC + 0x20090) 694 #define TXC_SF_DATA1_OFFSET(port) (TXC_SF_DATA1_REG + \ 695 (TXC_FZC_CNTL_PORT_OFFSET(port))) 696 697 typedef union _txc_sf_data1_t { 698 uint64_t value; 699 struct { 700 #ifdef _BIG_ENDIAN 701 uint32_t hdw; 702 #endif 703 struct { 704 #if defined(_BIT_FIELDS_HTOL) 705 uint32_t sf_ecc_data1:32; /* sf_ecc_data[63:32] */ 706 #elif defined(_BIT_FIELDS_LTOH) 707 uint32_t sf_ecc_data1:32; /* sf_ecc_data[31:32] */ 708 #endif 709 } ldw; 710 #ifndef _BIG_ENDIAN 711 uint32_t hdw; 712 #endif 713 } bits; 714 } txc_sf_data1_t, *p_txc_sf_data1_t; 715 716 717 #define TXC_SF_DATA2_REG (FZC_TXC + 0x20098) 718 #define TXC_SF_DATA2_OFFSET(port) (TXC_SF_DATA2_REG + \ 719 (TXC_FZC_CNTL_PORT_OFFSET(port))) 720 721 typedef union _txc_sf_data2_t { 722 uint64_t value; 723 struct { 724 #ifdef _BIG_ENDIAN 725 uint32_t hdw; 726 #endif 727 struct { 728 #if defined(_BIT_FIELDS_HTOL) 729 uint32_t sf_ecc_data2:32; /* sf_ecc_data[95:64] */ 730 #elif defined(_BIT_FIELDS_LTOH) 731 uint32_t sf_ecc_data2:32; /* sf_ecc_data[95:64] */ 732 #endif 733 } ldw; 734 #ifndef _BIG_ENDIAN 735 uint32_t hdw; 736 #endif 737 } bits; 738 } txc_sf_data2_t, *p_txc_sf_data2_t; 739 740 #define TXC_SF_DATA3_REG (FZC_TXC + 0x200A0) 741 #define TXC_SF_DATA3_OFFSET(port) (TXC_SF_DATA3_REG + \ 742 (TXC_FZC_CNTL_PORT_OFFSET(port))) 743 744 typedef union _txc_sf_data3_t { 745 uint64_t value; 746 struct { 747 #ifdef _BIG_ENDIAN 748 uint32_t hdw; 749 #endif 750 struct { 751 #if defined(_BIT_FIELDS_HTOL) 752 uint32_t sf_ecc_data3:32; /* sf_ecc_data[127:96] */ 753 #elif defined(_BIT_FIELDS_LTOH) 754 uint32_t sf_ecc_data3:32; /* sf_ecc_data[127:96] */ 755 #endif 756 } ldw; 757 #ifndef _BIG_ENDIAN 758 uint32_t hdw; 759 #endif 760 } bits; 761 } txc_sf_data3_t, *p_txc_sf_data3_t; 762 763 #define TXC_SF_DATA4_REG (FZC_TXC + 0x200A8) 764 #define TXC_SF_DATA4_OFFSET(port) (TXC_SF_DATA4_REG + \ 765 (TXC_FZC_CNTL_PORT_OFFSET(port))) 766 767 typedef union _txc_sf_data4_t { 768 uint64_t value; 769 struct { 770 #ifdef _BIG_ENDIAN 771 uint32_t hdw; 772 #endif 773 struct { 774 #if defined(_BIT_FIELDS_HTOL) 775 uint32_t sf_ecc_data4:32; /* sf_ecc_data[151:128] */ 776 #elif defined(_BIT_FIELDS_LTOH) 777 uint32_t sf_ecc_data4:32; /* sf_ecc_data[151:128] */ 778 #endif 779 } ldw; 780 #ifndef _BIG_ENDIAN 781 uint32_t hdw; 782 #endif 783 } bits; 784 } txc_sf_data4_t, *p_txc_sf_data4_t; 785 786 #define TXC_RO_TIDS_REG (FZC_TXC + 0x200B0) 787 #define TXC_RO_TIDS_OFFSET(port) (TXC_RO_TIDS_REG + \ 788 (TXC_FZC_CNTL_PORT_OFFSET(port))) 789 #define TXC_RO_TIDS_MASK 0x00000000FFFFFFFFULL 790 791 typedef union _txc_ro_tids_t { 792 uint64_t value; 793 struct { 794 #ifdef _BIG_ENDIAN 795 uint32_t hdw; 796 #endif 797 struct { 798 #if defined(_BIT_FIELDS_HTOL) 799 uint32_t tids_in_use:32; 800 #elif defined(_BIT_FIELDS_LTOH) 801 uint32_t tids_in_use:32; 802 #endif 803 } ldw; 804 #ifndef _BIG_ENDIAN 805 uint32_t hdw; 806 #endif 807 } bits; 808 } txc_ro_tids_t, *p_txc_ro_tids_t; 809 810 #define TXC_RO_STATE0_REG (FZC_TXC + 0x200B8) 811 #define TXC_RO_STATE0_OFFSET(port) (TXC_STATE0_REG + \ 812 (TXC_FZC_CNTL_PORT_OFFSET(port))) 813 #define TXC_RO_STATE0_MASK 0x00000000FFFFFFFFULL 814 815 typedef union _txc_ro_state0_t { 816 uint64_t value; 817 struct { 818 #ifdef _BIG_ENDIAN 819 uint32_t hdw; 820 #endif 821 struct { 822 #if defined(_BIT_FIELDS_HTOL) 823 uint32_t duplicate_tid:32; 824 #elif defined(_BIT_FIELDS_LTOH) 825 uint32_t duplicate_tid:32; 826 #endif 827 } ldw; 828 #ifndef _BIG_ENDIAN 829 uint32_t hdw; 830 #endif 831 } bits; 832 } txc_ro_state0_t, *p_txc_ro_state0_t; 833 834 #define TXC_RO_STATE1_REG (FZC_TXC + 0x200C0) 835 #define TXC_RO_STATE1_OFFSET(port) (TXC_STATE1_REG + \ 836 (TXC_FZC_CNTL_PORT_OFFSET(port))) 837 #define TXC_RO_STATE1_MASK 0x00000000FFFFFFFFULL 838 839 typedef union _txc_ro_state1_t { 840 uint64_t value; 841 struct { 842 #ifdef _BIG_ENDIAN 843 uint32_t hdw; 844 #endif 845 struct { 846 #if defined(_BIT_FIELDS_HTOL) 847 uint32_t unused_tid:32; 848 #elif defined(_BIT_FIELDS_LTOH) 849 uint32_t unused_tid:32; 850 #endif 851 } ldw; 852 #ifndef _BIG_ENDIAN 853 uint32_t hdw; 854 #endif 855 } bits; 856 } txc_ro_state1_t, *p_txc_ro_state1_t; 857 858 #define TXC_RO_STATE2_REG (FZC_TXC + 0x200C8) 859 #define TXC_RO_STATE2_OFFSET(port) (TXC_STATE2_REG + \ 860 (TXC_FZC_CNTL_PORT_OFFSET(port))) 861 #define TXC_RO_STATE2_MASK 0x00000000FFFFFFFFULL 862 863 typedef union _txc_ro_state2_t { 864 uint64_t value; 865 struct { 866 #ifdef _BIG_ENDIAN 867 uint32_t hdw; 868 #endif 869 struct { 870 #if defined(_BIT_FIELDS_HTOL) 871 uint32_t transaction_timeout:32; 872 #elif defined(_BIT_FIELDS_LTOH) 873 uint32_t transaction_timeout:32; 874 #endif 875 } ldw; 876 #ifndef _BIG_ENDIAN 877 uint32_t hdw; 878 #endif 879 } bits; 880 } txc_ro_state2_t, *p_txc_ro_state2_t; 881 882 #define TXC_RO_STATE3_REG (FZC_TXC + 0x200D0) 883 #define TXC_RO_STATE3_OFFSET(port) (TXC_RO_STATE3_REG + \ 884 (TXC_FZC_CNTL_PORT_OFFSET(port))) 885 886 typedef union _txc_ro_state3_t { 887 uint64_t value; 888 struct { 889 #ifdef _BIG_ENDIAN 890 uint32_t hdw; 891 #endif 892 struct { 893 #if defined(_BIT_FIELDS_HTOL) 894 uint32_t enable_spacefilled_watermark:1; 895 uint32_t ro_spacefilled_watermask:10; 896 uint32_t ro_fifo_spaceavailable:10; 897 uint32_t rsv:2; 898 uint32_t enable_ro_watermark:1; 899 uint32_t highest_reorder_used:4; 900 uint32_t num_reorder_used:4; 901 #elif defined(_BIT_FIELDS_LTOH) 902 uint32_t num_reorder_used:4; 903 uint32_t highest_reorder_used:4; 904 uint32_t enable_ro_watermark:1; 905 uint32_t rsv:2; 906 uint32_t ro_fifo_spaceavailable:10; 907 uint32_t ro_spacefilled_watermask:10; 908 uint32_t enable_spacefilled_watermark:1; 909 #endif 910 } ldw; 911 #ifndef _BIG_ENDIAN 912 uint32_t hdw; 913 #endif 914 } bits; 915 } txc_ro_state3_t, *p_txc_ro_state3_t; 916 917 #define TXC_RO_CTL_REG (FZC_TXC + 0x200D8) 918 #define TXC_RO_CTL_OFFSET(port) (TXC_RO_CTL_REG + \ 919 (TXC_FZC_CNTL_PORT_OFFSET(port))) 920 921 typedef union _txc_ro_ctl_t { 922 uint64_t value; 923 struct { 924 #ifdef _BIG_ENDIAN 925 uint32_t hdw; 926 #endif 927 struct { 928 #if defined(_BIT_FIELDS_HTOL) 929 uint32_t clr_fail_state:1; 930 uint32_t rsvd3:3; 931 uint32_t ro_addr1:4; 932 uint32_t rsvd2:1; 933 uint32_t address_failed:1; 934 uint32_t dma_failed:1; 935 uint32_t length_failed:1; 936 uint32_t rsv:1; 937 uint32_t capture_address_fail:1; 938 uint32_t capture_dma_fail:1; 939 uint32_t capture_length_fail:1; 940 uint32_t rsvd:8; 941 uint32_t ro_state_rd_done:1; 942 uint32_t ro_state_wr_done:1; 943 uint32_t ro_state_rd:1; 944 uint32_t ro_state_wr:1; 945 uint32_t ro_state_addr:4; 946 #elif defined(_BIT_FIELDS_LTOH) 947 uint32_t ro_state_addr:4; 948 uint32_t ro_state_wr:1; 949 uint32_t ro_state_rd:1; 950 uint32_t ro_state_wr_done:1; 951 uint32_t ro_state_rd_done:1; 952 uint32_t rsvd:8; 953 uint32_t capture_length_fail:1; 954 uint32_t capture_dma_fail:1; 955 uint32_t capture_address_fail:1; 956 uint32_t rsv:1; 957 uint32_t length_failed:1; 958 uint32_t dma_failed:1; 959 uint32_t address_failed:1; 960 uint32_t rsvd2:1; 961 uint32_t ro_addr1:4; 962 uint32_t rsvd3:3; 963 uint32_t clr_fail_state:1; 964 #endif 965 } ldw; 966 #ifndef _BIG_ENDIAN 967 uint32_t hdw; 968 #endif 969 } bits; 970 } txc_ro_ctl_t, *p_txc_ro_ctl_t; 971 972 973 #define TXC_RO_ST_DATA0_REG (FZC_TXC + 0x200E0) 974 #define TXC_RO_ST_DATA0_OFFSET(port) (TXC_RO_ST_DATA0_REG + \ 975 (TXC_FZC_CNTL_PORT_OFFSET(port))) 976 #define TXC_RO_ST_DATA0_MASK 0x00000000FFFFFFFFULL 977 978 typedef union _txc_ro_st_data0_t { 979 uint64_t value; 980 struct { 981 #ifdef _BIG_ENDIAN 982 uint32_t hdw; 983 #endif 984 struct { 985 #if defined(_BIT_FIELDS_HTOL) 986 uint32_t ro_st_dat0:32; 987 #elif defined(_BIT_FIELDS_LTOH) 988 uint32_t ro_st_dat0:32; 989 #endif 990 } ldw; 991 #ifndef _BIG_ENDIAN 992 uint32_t hdw; 993 #endif 994 } bits; 995 } txc_ro_st_data0_t, *p_txc_ro_st_data0_t; 996 997 998 #define TXC_RO_ST_DATA1_REG (FZC_TXC + 0x200E8) 999 #define TXC_RO_ST_DATA1_OFFSET(port) (TXC_RO_ST_DATA1_REG + \ 1000 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1001 #define TXC_RO_ST_DATA1_MASK 0x00000000FFFFFFFFULL 1002 1003 typedef union _txc_ro_st_data1_t { 1004 uint64_t value; 1005 struct { 1006 #ifdef _BIG_ENDIAN 1007 uint32_t hdw; 1008 #endif 1009 struct { 1010 #if defined(_BIT_FIELDS_HTOL) 1011 uint32_t ro_st_dat1:32; 1012 #elif defined(_BIT_FIELDS_LTOH) 1013 uint32_t ro_st_dat1:32; 1014 #endif 1015 } ldw; 1016 #ifndef _BIG_ENDIAN 1017 uint32_t hdw; 1018 #endif 1019 } bits; 1020 } txc_ro_st_data1_t, *p_txc_ro_st_data1_t; 1021 1022 1023 #define TXC_RO_ST_DATA2_REG (FZC_TXC + 0x200F0) 1024 #define TXC_RO_ST_DATA2_OFFSET(port) (TXC_RO_ST_DATA2_REG + \ 1025 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1026 #define TXC_RO_ST_DATA2_MASK 0x00000000FFFFFFFFULL 1027 1028 typedef union _txc_ro_st_data2_t { 1029 uint64_t value; 1030 struct { 1031 #ifdef _BIG_ENDIAN 1032 uint32_t hdw; 1033 #endif 1034 struct { 1035 #if defined(_BIT_FIELDS_HTOL) 1036 uint32_t ro_st_dat2:32; 1037 #elif defined(_BIT_FIELDS_LTOH) 1038 uint32_t ro_st_dat2:32; 1039 #endif 1040 } ldw; 1041 #ifndef _BIG_ENDIAN 1042 uint32_t hdw; 1043 #endif 1044 } bits; 1045 } txc_ro_st_data2_t, *p_txc_ro_st_data2_t; 1046 1047 #define TXC_RO_ST_DATA3_REG (FZC_TXC + 0x200F8) 1048 #define TXC_RO_ST_DATA3_OFFSET(port) (TXC_RO_ST_DATA3_REG + \ 1049 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1050 #define TXC_RO_ST_DATA3_MASK 0x00000000FFFFFFFFULL 1051 1052 typedef union _txc_ro_st_data3_t { 1053 uint64_t value; 1054 struct { 1055 #ifdef _BIG_ENDIAN 1056 uint32_t hdw; 1057 #endif 1058 struct { 1059 #if defined(_BIT_FIELDS_HTOL) 1060 uint32_t ro_st_dat3:32; 1061 #elif defined(_BIT_FIELDS_LTOH) 1062 uint32_t ro_st_dat3:32; 1063 #endif 1064 } ldw; 1065 #ifndef _BIG_ENDIAN 1066 uint32_t hdw; 1067 #endif 1068 } bits; 1069 } txc_ro_st_data3_t, *p_txc_ro_st_data3_t; 1070 1071 #define TXC_PORT_PACKET_REQ_REG (FZC_TXC + 0x20100) 1072 #define TXC_PORT_PACKET_REQ_OFFSET(port) (TXC_PORT_PACKET_REQ_REG + \ 1073 (TXC_FZC_CNTL_PORT_OFFSET(port))) 1074 #define TXC_PORT_PACKET_REQ_MASK 0x00000000FFFFFFFFULL 1075 1076 typedef union _txc_port_packet_req_t { 1077 uint64_t value; 1078 struct { 1079 #ifdef _BIG_ENDIAN 1080 uint32_t hdw; 1081 #endif 1082 struct { 1083 #if defined(_BIT_FIELDS_HTOL) 1084 uint32_t gather_req:4; 1085 uint32_t packet_eq:12; 1086 uint32_t pkterr_abort:16; 1087 #elif defined(_BIT_FIELDS_LTOH) 1088 uint32_t pkterr_abort:16; 1089 uint32_t packet_eq:12; 1090 uint32_t gather_req:4; 1091 #endif 1092 } ldw; 1093 #ifndef _BIG_ENDIAN 1094 uint32_t hdw; 1095 #endif 1096 } bits; 1097 } txc_port_packet_req_t, *p_txc_port_packet_req_t; 1098 1099 /* Reorder error bits in interrupt registers */ 1100 #define TXC_INT_STAT_SF_CORR_ERR 0x01 1101 #define TXC_INT_STAT_SF_UNCORR_ERR 0x02 1102 #define TXC_INT_STAT_RO_CORR_ERR 0x04 1103 #define TXC_INT_STAT_RO_UNCORR_ERR 0x08 1104 #define TXC_INT_STAT_REORDER_ERR 0x10 1105 #define TXC_INT_STAT_PKTASSYDEAD 0x20 1106 1107 #define TXC_INT_STAT_DBG_REG (FZC_TXC + 0x20420) 1108 #define TXC_INT_STAT_DBG_MASK 0x00000000FFFFFFFFULL 1109 1110 typedef union _txc_int_stat_dbg_t { 1111 uint64_t value; 1112 struct { 1113 #ifdef _BIG_ENDIAN 1114 uint32_t hdw; 1115 #endif 1116 struct { 1117 #if defined(_BIT_FIELDS_HTOL) 1118 uint32_t rsvd3:2; 1119 uint32_t port3_int_status:6; 1120 uint32_t rsvd2:2; 1121 uint32_t port2_int_status:6; 1122 uint32_t rsvd1:2; 1123 uint32_t port1_int_status:6; 1124 uint32_t rsvd:2; 1125 uint32_t port0_int_status:6; 1126 #elif defined(_BIT_FIELDS_LTOH) 1127 uint32_t port0_int_status:6; 1128 uint32_t rsvd:2; 1129 uint32_t port1_int_status:6; 1130 uint32_t rsvd1:2; 1131 uint32_t port2_int_status:6; 1132 uint32_t rsvd2:2; 1133 uint32_t port3_int_status:6; 1134 uint32_t rsvd3:2; 1135 #endif 1136 } ldw; 1137 #ifndef _BIG_ENDIAN 1138 uint32_t hdw; 1139 #endif 1140 } bits; 1141 } txc_int_stat_dbg_t, *p_txc_int_stat_dbg_t; 1142 1143 1144 #define TXC_INT_STAT_REG (FZC_TXC + 0x20428) 1145 #define TXC_INT_STAT_MASK 0x00000000FFFFFFFFULL 1146 1147 typedef union _txc_int_stat_t { 1148 uint64_t value; 1149 struct { 1150 #ifdef _BIG_ENDIAN 1151 uint32_t hdw; 1152 #endif 1153 struct { 1154 #if defined(_BIT_FIELDS_HTOL) 1155 uint32_t rsvd3:2; 1156 uint32_t port3_int_status:6; 1157 uint32_t rsvd2:2; 1158 uint32_t port2_int_status:6; 1159 uint32_t rsvd1:2; 1160 uint32_t port1_int_status:6; 1161 uint32_t rsvd:2; 1162 uint32_t port0_int_status:6; 1163 #elif defined(_BIT_FIELDS_LTOH) 1164 uint32_t port0_int_status:6; 1165 uint32_t rsvd:2; 1166 uint32_t port1_int_status:6; 1167 uint32_t rsvd1:2; 1168 uint32_t port2_int_status:6; 1169 uint32_t rsvd2:2; 1170 uint32_t port3_int_status:6; 1171 uint32_t rsvd3:2; 1172 #endif 1173 } ldw; 1174 #ifndef _BIG_ENDIAN 1175 uint32_t hdw; 1176 #endif 1177 } bits; 1178 } txc_int_stat_t, *p_txc_int_stat_t; 1179 1180 #define TXC_INT_MASK_REG (FZC_TXC + 0x20430) 1181 #define TXC_INT_MASK_MASK 0x00000000FFFFFFFFULL 1182 1183 typedef union _txc_int_mask_t { 1184 uint64_t value; 1185 struct { 1186 #ifdef _BIG_ENDIAN 1187 uint32_t hdw; 1188 #endif 1189 struct { 1190 #if defined(_BIT_FIELDS_HTOL) 1191 uint32_t rsvd3:2; 1192 uint32_t port3_int_mask:6; 1193 uint32_t rsvd2:2; 1194 uint32_t port2_int_mask:6; 1195 uint32_t rsvd1:2; 1196 uint32_t port1_int_mask:6; 1197 uint32_t rsvd:2; 1198 uint32_t port0_int_mask:6; 1199 #elif defined(_BIT_FIELDS_LTOH) 1200 uint32_t port0_int_mask:6; 1201 uint32_t rsvd:2; 1202 uint32_t port1_int_mask:6; 1203 uint32_t rsvd1:2; 1204 uint32_t port2_int_mask:6; 1205 uint32_t rsvd2:2; 1206 uint32_t port3_int_mask:6; 1207 uint32_t rsvd3:2; 1208 #endif 1209 } ldw; 1210 #ifndef _BIG_ENDIAN 1211 uint32_t hdw; 1212 #endif 1213 } bits; 1214 } txc_int_mask_t, *p_txc_int_mask_t; 1215 1216 /* 2 ports */ 1217 typedef union _txc_int_mask_n2_t { 1218 uint64_t value; 1219 struct { 1220 #ifdef _BIG_ENDIAN 1221 uint32_t hdw; 1222 #endif 1223 struct { 1224 #if defined(_BIT_FIELDS_HTOL) 1225 uint32_t rsvd1:18; 1226 uint32_t port1_int_mask:6; 1227 uint32_t rsvd:2; 1228 uint32_t port0_int_mask:6; 1229 #elif defined(_BIT_FIELDS_LTOH) 1230 uint32_t port0_int_mask:6; 1231 uint32_t rsvd:2; 1232 uint32_t port1_int_mask:6; 1233 uint32_t rsvd1:18; 1234 #endif 1235 } ldw; 1236 #ifndef _BIG_ENDIAN 1237 uint32_t hdw; 1238 #endif 1239 } bits; 1240 } txc_int_mask_n2_t, *p_txc_int_mask_n2_t; 1241 1242 typedef struct _txc_ro_states { 1243 txc_roecc_st_t roecc; 1244 txc_ro_data0_t d0; 1245 txc_ro_data1_t d1; 1246 txc_ro_data2_t d2; 1247 txc_ro_data3_t d3; 1248 txc_ro_data4_t d4; 1249 txc_ro_tids_t tids; 1250 txc_ro_state0_t st0; 1251 txc_ro_state1_t st1; 1252 txc_ro_state2_t st2; 1253 txc_ro_state3_t st3; 1254 txc_ro_ctl_t ctl; 1255 } txc_ro_states_t, *p_txc_ro_states_t; 1256 1257 typedef struct _txc_sf_states { 1258 txc_sfecc_st_t sfecc; 1259 txc_sf_data0_t d0; 1260 txc_sf_data1_t d1; 1261 txc_sf_data2_t d2; 1262 txc_sf_data3_t d3; 1263 txc_sf_data4_t d4; 1264 } txc_sf_states_t, *p_txc_sf_states_t; 1265 1266 #ifdef __cplusplus 1267 } 1268 #endif 1269 1270 #endif /* _SYS_NXGE_NXGE_TXC_HW_H */ 1271