1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_RXDMA_HW_H 27 #define _SYS_NXGE_NXGE_RXDMA_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 #include <nxge_hw.h> 35 36 /* 37 * NIU: Receive DMA Channels 38 */ 39 /* Receive DMA Clock Divider */ 40 #define RX_DMA_CK_DIV_REG (FZC_DMC + 0x00000) 41 #define RX_DMA_CK_DIV_SHIFT 0 /* bits 15:0 */ 42 #define RX_DMA_CK_DIV_MASK 0x000000000000FFFFULL 43 44 typedef union _rx_dma_ck_div_t { 45 uint64_t value; 46 struct { 47 #if defined(_BIG_ENDIAN) 48 uint32_t hdw; 49 #endif 50 struct { 51 #if defined(_BIT_FIELDS_HTOL) 52 uint32_t res1_1:16; 53 uint32_t cnt:16; 54 #elif defined(_BIT_FIELDS_LTOH) 55 uint32_t cnt:16; 56 uint32_t res1_1:16; 57 #endif 58 } ldw; 59 #if !defined(_BIG_ENDIAN) 60 uint32_t hdw; 61 #endif 62 } bits; 63 } rx_dma_ck_div_t, *p_rx_dma_ck_div_t; 64 65 66 /* 67 * Default Port Receive DMA Channel (RDC) 68 */ 69 #define DEF_PT_RDC_REG(port) (FZC_DMC + 0x00008 * (port + 1)) 70 #define DEF_PT0_RDC_REG (FZC_DMC + 0x00008) 71 #define DEF_PT1_RDC_REG (FZC_DMC + 0x00010) 72 #define DEF_PT2_RDC_REG (FZC_DMC + 0x00018) 73 #define DEF_PT3_RDC_REG (FZC_DMC + 0x00020) 74 #define DEF_PT_RDC_SHIFT 0 /* bits 4:0 */ 75 #define DEF_PT_RDC_MASK 0x000000000000001FULL 76 77 78 #define RDC_TBL_REG (FZC_ZCP + 0x10000) 79 #define RDC_TBL_SHIFT 0 /* bits 4:0 */ 80 #define RDC_TBL_MASK 0x000000000000001FULL 81 82 /* For the default port RDC and RDC table */ 83 typedef union _def_pt_rdc_t { 84 uint64_t value; 85 struct { 86 #if defined(_BIG_ENDIAN) 87 uint32_t hdw; 88 #endif 89 struct { 90 #if defined(_BIT_FIELDS_HTOL) 91 uint32_t res1_1:27; 92 uint32_t rdc:5; 93 #elif defined(_BIT_FIELDS_LTOH) 94 uint32_t rdc:5; 95 uint32_t res1_1:27; 96 #endif 97 } ldw; 98 #if !defined(_BIG_ENDIAN) 99 uint32_t hdw; 100 #endif 101 } bits; 102 } def_pt_rdc_t, *p_def_pt_rdc_t; 103 104 typedef union _rdc_tbl_t { 105 uint64_t value; 106 struct { 107 #if defined(_BIG_ENDIAN) 108 uint32_t hdw; 109 #endif 110 struct { 111 #if defined(_BIT_FIELDS_HTOL) 112 uint32_t res1_1:28; 113 uint32_t rdc:4; 114 #elif defined(_BIT_FIELDS_LTOH) 115 uint32_t rdc:4; 116 uint32_t res1_1:28; 117 #endif 118 } ldw; 119 #if !defined(_BIG_ENDIAN) 120 uint32_t hdw; 121 #endif 122 } bits; 123 } rdc_tbl_t, *p_rdc_tbl_t; 124 125 /* 126 * RDC: 32 bit Addressing mode 127 */ 128 #define RX_ADDR_MD_REG (FZC_DMC + 0x00070) 129 #define RX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 130 #define RX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 131 #define RX_ADDR_MD_MASK 0x0000000000000001ULL 132 133 typedef union _rx_addr_md_t { 134 uint64_t value; 135 struct { 136 #if defined(_BIG_ENDIAN) 137 uint32_t hdw; 138 #endif 139 struct { 140 #if defined(_BIT_FIELDS_HTOL) 141 uint32_t res1_1:28; 142 uint32_t dbg_pt_mux_sel:2; 143 uint32_t ram_acc:1; 144 uint32_t mode32:1; 145 #elif defined(_BIT_FIELDS_LTOH) 146 uint32_t mode32:1; 147 uint32_t ram_acc:1; 148 uint32_t dbg_pt_mux_sel:2; 149 uint32_t res1_1:28; 150 #endif 151 } ldw; 152 #if !defined(_BIG_ENDIAN) 153 uint32_t hdw; 154 #endif 155 } bits; 156 } rx_addr_md_t, *p_rx_addr_md_t; 157 158 /* 159 * RDC: Port Scheduler 160 */ 161 162 #define PT_DRR_WT_REG(portnm) ((FZC_DMC + 0x00028) + (portnm * 8)) 163 #define PT_DRR_WT0_REG (FZC_DMC + 0x00028) 164 #define PT_DRR_WT1_REG (FZC_DMC + 0x00030) 165 #define PT_DRR_WT2_REG (FZC_DMC + 0x00038) 166 #define PT_DRR_WT3_REG (FZC_DMC + 0x00040) 167 #define PT_DRR_WT_SHIFT 0 168 #define PT_DRR_WT_MASK 0x000000000000FFFFULL /* bits 15:0 */ 169 #define PT_DRR_WT_DEFAULT_10G 0x0400 170 #define PT_DRR_WT_DEFAULT_1G 0x0066 171 typedef union _pt_drr_wt_t { 172 uint64_t value; 173 struct { 174 #if defined(_BIG_ENDIAN) 175 uint32_t hdw; 176 #endif 177 struct { 178 #if defined(_BIT_FIELDS_HTOL) 179 uint32_t res1_1:16; 180 uint32_t wt:16; 181 #elif defined(_BIT_FIELDS_LTOH) 182 uint32_t wt:16; 183 uint32_t res1_1:16; 184 #endif 185 } ldw; 186 #if !defined(_BIG_ENDIAN) 187 uint32_t hdw; 188 #endif 189 } bits; 190 } pt_drr_wt_t, *p_pt_drr_wt_t; 191 192 #define NXGE_RX_DRR_WT_10G 0x400 193 #define NXGE_RX_DRR_WT_1G 0x066 194 195 /* Port FIFO Usage */ 196 #define PT_USE_REG(portnum) ((FZC_DMC + 0x00048) + (portnum * 8)) 197 #define PT_USE0_REG (FZC_DMC + 0x00048) 198 #define PT_USE1_REG (FZC_DMC + 0x00050) 199 #define PT_USE2_REG (FZC_DMC + 0x00058) 200 #define PT_USE3_REG (FZC_DMC + 0x00060) 201 #define PT_USE_SHIFT 0 /* bits 19:0 */ 202 #define PT_USE_MASK 0x00000000000FFFFFULL 203 204 typedef union _pt_use_t { 205 uint64_t value; 206 struct { 207 #if defined(_BIG_ENDIAN) 208 uint32_t hdw; 209 #endif 210 struct { 211 #if defined(_BIT_FIELDS_HTOL) 212 uint32_t res1_1:12; 213 uint32_t cnt:20; 214 #elif defined(_BIT_FIELDS_LTOH) 215 uint32_t cnt:20; 216 uint32_t res1_1:12; 217 #endif 218 } ldw; 219 #if !defined(_BIG_ENDIAN) 220 uint32_t hdw; 221 #endif 222 } bits; 223 } pt_use_t, *p_pt_use_t; 224 225 /* 226 * RDC: Partitioning Support 227 * (Each of the following registers is for each RDC) 228 * Please refer to nxge_hw.h for the common logical 229 * page configuration register definitions. 230 */ 231 #define RX_LOG_REG_SIZE 0x40 232 #define RX_LOG_DMA_OFFSET(channel) (channel * RX_LOG_REG_SIZE) 233 234 #define RX_LOG_PAGE_VLD_REG (FZC_DMC + 0x20000) 235 #define RX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x20008) 236 #define RX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x20010) 237 #define RX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x20018) 238 #define RX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x20020) 239 #define RX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x20028) 240 #define RX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x20030) 241 #define RX_LOG_PAGE_HDL_REG (FZC_DMC + 0x20038) 242 243 /* RX and TX have the same definitions */ 244 #define RX_LOG_PAGE1_VLD_SHIFT 1 /* bit 1 */ 245 #define RX_LOG_PAGE0_VLD_SHIFT 0 /* bit 0 */ 246 #define RX_LOG_PAGE1_VLD 0x0000000000000002ULL 247 #define RX_LOG_PAGE0_VLD 0x0000000000000001ULL 248 #define RX_LOG_PAGE1_VLD_MASK 0x0000000000000002ULL 249 #define RX_LOG_PAGE0_VLD_MASK 0x0000000000000001ULL 250 #define RX_LOG_FUNC_VLD_SHIFT 2 /* bit 3:2 */ 251 #define RX_LOG_FUNC_VLD_MASK 0x000000000000000CULL 252 253 #define LOG_PAGE_ADDR_SHIFT 12 /* bits[43:12] --> bits[31:0] */ 254 255 /* RDC: Weighted Random Early Discard */ 256 #define RED_RAN_INIT_REG (FZC_DMC + 0x00068) 257 258 #define RED_RAN_INIT_SHIFT 0 /* bits 15:0 */ 259 #define RED_RAN_INIT_MASK 0x000000000000ffffULL 260 261 /* Weighted Random */ 262 typedef union _red_ran_init_t { 263 uint64_t value; 264 struct { 265 #if defined(_BIG_ENDIAN) 266 uint32_t hdw; 267 #endif 268 struct { 269 #if defined(_BIT_FIELDS_HTOL) 270 uint32_t res1_1:15; 271 uint32_t enable:1; 272 uint32_t init:16; 273 #elif defined(_BIT_FIELDS_LTOH) 274 uint32_t init:16; 275 uint32_t enable:1; 276 uint32_t res1_1:15; 277 #endif 278 } ldw; 279 #if !defined(_BIG_ENDIAN) 280 uint32_t hdw; 281 #endif 282 } bits; 283 } red_ran_init_t, *p_red_ran_init_t; 284 285 /* 286 * Buffer block descriptor 287 */ 288 typedef struct _rx_desc_t { 289 uint32_t block_addr; 290 } rx_desc_t, *p_rx_desc_t; 291 292 /* 293 * RDC: RED Parameter 294 * (Each DMC has one RED register) 295 */ 296 #define RDC_RED_CHANNEL_SIZE (0x40) 297 #define RDC_RED_CHANNEL_OFFSET(channel) (channel * RDC_RED_CHANNEL_SIZE) 298 299 #define RDC_RED_PARA_REG (FZC_DMC + 0x30000) 300 #define RDC_RED_RDC_PARA_REG(rdc) \ 301 (RDC_RED_PARA_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 302 303 /* the layout of this register is rx_disc_cnt_t */ 304 #define RDC_RED_DISC_CNT_REG (FZC_DMC + 0x30008) 305 #define RDC_RED_RDC_DISC_REG(rdc) \ 306 (RDC_RED_DISC_CNT_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 307 308 309 #define RDC_RED_PARA1_RBR_SCL_SHIFT 0 /* bits 2:0 */ 310 #define RDC_RED_PARA1_RBR_SCL_MASK 0x0000000000000007ULL 311 #define RDC_RED_PARA1_ENB_SHIFT 3 /* bit 3 */ 312 #define RDC_RED_PARA1_ENB 0x0000000000000008ULL 313 #define RDC_RED_PARA1_ENB_MASK 0x0000000000000008ULL 314 315 #define RDC_RED_PARA_WIN_SHIFT 0 /* bits 3:0 */ 316 #define RDC_RED_PARA_WIN_MASK 0x000000000000000fULL 317 #define RDC_RED_PARA_THRE_SHIFT 4 /* bits 15:4 */ 318 #define RDC_RED_PARA_THRE_MASK 0x00000000000000f0ULL 319 #define RDC_RED_PARA_WIN_SYN_SHIFT 16 /* bits 19:16 */ 320 #define RDC_RED_PARA_WIN_SYN_MASK 0x00000000000000f0ULL 321 #define RDC_RED_PARA_THRE_SYN_SHIFT 20 /* bits 31:20 */ 322 #define RDC_RED_PARA_THRE_SYN_MASK 0x00000000000fff00ULL 323 324 /* RDC: RED parameters */ 325 typedef union _rdc_red_para_t { 326 uint64_t value; 327 struct { 328 #if defined(_BIG_ENDIAN) 329 uint32_t hdw; 330 #endif 331 struct { 332 #if defined(_BIT_FIELDS_HTOL) 333 uint32_t thre_sync:12; 334 uint32_t win_syn:4; 335 uint32_t thre:12; 336 uint32_t win:4; 337 #elif defined(_BIT_FIELDS_LTOH) 338 uint32_t win:4; 339 uint32_t thre:12; 340 uint32_t win_syn:4; 341 uint32_t thre_sync:12; 342 #endif 343 } ldw; 344 #if !defined(_BIG_ENDIAN) 345 uint32_t hdw; 346 #endif 347 } bits; 348 } rdc_red_para_t, *p_rdc_red_para_t; 349 350 /* 351 * RDC: Receive DMA Datapath Configuration 352 * The following register definitions are for 353 * each DMA channel. Each DMA CSR is 512 bytes 354 * (0x200). 355 */ 356 #define RXDMA_CFIG1_REG (DMC + 0x00000) 357 #define RXDMA_CFIG2_REG (DMC + 0x00008) 358 359 #define RXDMA_CFIG1_MBADDR_H_SHIFT 0 /* bits 11:0 */ 360 #define RXDMA_CFIG1_MBADDR_H_MASK 0x0000000000000fc0ULL 361 #define RXDMA_CFIG1_RST_SHIFT 30 /* bit 30 */ 362 #define RXDMA_CFIG1_RST 0x0000000040000000ULL 363 #define RXDMA_CFIG1_RST_MASK 0x0000000040000000ULL 364 #define RXDMA_CFIG1_EN_SHIFT 31 365 #define RXDMA_CFIG1_EN 0x0000000080000000ULL 366 #define RXDMA_CFIG1_EN_MASK 0x0000000080000000ULL 367 368 typedef union _rxdma_cfig1_t { 369 uint64_t value; 370 struct { 371 #if defined(_BIG_ENDIAN) 372 uint32_t hdw; 373 #endif 374 struct { 375 #if defined(_BIT_FIELDS_HTOL) 376 uint32_t en:1; 377 uint32_t rst:1; 378 uint32_t qst:1; 379 uint32_t res2:17; 380 uint32_t mbaddr_h:12; 381 #elif defined(_BIT_FIELDS_LTOH) 382 uint32_t mbaddr_h:12; 383 uint32_t res2:17; 384 uint32_t qst:1; 385 uint32_t rst:1; 386 uint32_t en:1; 387 #endif 388 } ldw; 389 #if !defined(_BIG_ENDIAN) 390 uint32_t hdw; 391 #endif 392 } bits; 393 } rxdma_cfig1_t, *p_rxdma_cfig1_t; 394 395 #define RXDMA_HDR_SIZE_DEFAULT 2 396 #define RXDMA_HDR_SIZE_FULL 18 397 398 #define RXDMA_CFIG2_FULL_HDR_SHIFT 0 /* Set to 1 */ 399 #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL 400 #define RXDMA_CFIG2_FULL_HDR_MASK 0x0000000000000001ULL 401 #define RXDMA_CFIG2_OFFSET_SHIFT 1 /* bit 3:1 */ 402 #define RXDMA_CFIG2_OFFSET_MASK 0x000000004000000eULL 403 #define RXDMA_CFIG2_MBADDR_L_SHIFT 6 /* bit 31:6 */ 404 #define RXDMA_CFIG2_MBADDR_L_MASK 0x00000000ffffffc0ULL 405 406 /* NOTE: offset256 valid only for Neptune-L and RF-NIU */ 407 typedef union _rxdma_cfig2_t { 408 uint64_t value; 409 struct { 410 #if defined(_BIG_ENDIAN) 411 uint32_t hdw; 412 #endif 413 struct { 414 #if defined(_BIT_FIELDS_HTOL) 415 uint32_t mbaddr:26; 416 uint32_t res2:2; 417 uint32_t offset256:1; 418 uint32_t offset:2; 419 uint32_t full_hdr:1; 420 421 #elif defined(_BIT_FIELDS_LTOH) 422 uint32_t full_hdr:1; 423 uint32_t offset:2; 424 uint32_t offset256:1; 425 uint32_t res2:2; 426 uint32_t mbaddr:26; 427 #endif 428 } ldw; 429 #if !defined(_BIG_ENDIAN) 430 uint32_t hdw; 431 #endif 432 } bits; 433 } rxdma_cfig2_t, *p_rxdma_cfig2_t; 434 435 /* 436 * RDC: Receive Block Ring Configuration 437 * The following register definitions are for 438 * each DMA channel. 439 */ 440 #define RBR_CFIG_A_REG (DMC + 0x00010) 441 #define RBR_CFIG_B_REG (DMC + 0x00018) 442 #define RBR_KICK_REG (DMC + 0x00020) 443 #define RBR_STAT_REG (DMC + 0x00028) 444 #define RBR_HDH_REG (DMC + 0x00030) 445 #define RBR_HDL_REG (DMC + 0x00038) 446 447 #define RBR_CFIG_A_STADDR_SHIFT 6 /* bits 17:6 */ 448 #define RBR_CFIG_A_STDADDR_MASK 0x000000000003ffc0ULL 449 #define RBR_CFIG_A_STADDR_BASE_SHIFT 18 /* bits 43:18 */ 450 #define RBR_CFIG_A_STDADDR_BASE_MASK 0x00000ffffffc0000ULL 451 #define RBR_CFIG_A_LEN_SHIFT 48 /* bits 63:48 */ 452 #define RBR_CFIG_A_LEN_MASK 0xFFFF000000000000ULL 453 454 typedef union _rbr_cfig_a_t { 455 uint64_t value; 456 struct { 457 #if defined(_BIG_ENDIAN) 458 struct { 459 #if defined(_BIT_FIELDS_HTOL) 460 uint32_t len:16; 461 uint32_t res1:4; 462 uint32_t staddr_base:12; 463 #elif defined(_BIT_FIELDS_LTOH) 464 uint32_t staddr_base:12; 465 uint32_t res1:4; 466 uint32_t len:16; 467 #endif 468 } hdw; 469 #endif 470 struct { 471 #if defined(_BIT_FIELDS_HTOL) 472 uint32_t staddr_base:14; 473 uint32_t staddr:12; 474 uint32_t res2:6; 475 #elif defined(_BIT_FIELDS_LTOH) 476 uint32_t res2:6; 477 uint32_t staddr:12; 478 uint32_t staddr_base:14; 479 #endif 480 } ldw; 481 #if !defined(_BIG_ENDIAN) 482 struct { 483 #if defined(_BIT_FIELDS_HTOL) 484 uint32_t len:16; 485 uint32_t res1:4; 486 uint32_t staddr_base:12; 487 #elif defined(_BIT_FIELDS_LTOH) 488 uint32_t staddr_base:12; 489 uint32_t res1:4; 490 uint32_t len:16; 491 #endif 492 } hdw; 493 #endif 494 } bits; 495 } rbr_cfig_a_t, *p_rbr_cfig_a_t; 496 497 498 #define RBR_CFIG_B_BUFSZ0_SHIFT 0 /* bit 1:0 */ 499 #define RBR_CFIG_B_BUFSZ0_MASK 0x0000000000000001ULL 500 #define RBR_CFIG_B_VLD0_SHIFT 7 /* bit 7 */ 501 #define RBR_CFIG_B_VLD0 0x0000000000000008ULL 502 #define RBR_CFIG_B_VLD0_MASK 0x0000000000000008ULL 503 #define RBR_CFIG_B_BUFSZ1_SHIFT 8 /* bit 9:8 */ 504 #define RBR_CFIG_B_BUFSZ1_MASK 0x0000000000000300ULL 505 #define RBR_CFIG_B_VLD1_SHIFT 15 /* bit 15 */ 506 #define RBR_CFIG_B_VLD1 0x0000000000008000ULL 507 #define RBR_CFIG_B_VLD1_MASK 0x0000000000008000ULL 508 #define RBR_CFIG_B_BUFSZ2_SHIFT 16 /* bit 17:16 */ 509 #define RBR_CFIG_B_BUFSZ2_MASK 0x0000000000030000ULL 510 #define RBR_CFIG_B_VLD2_SHIFT 23 /* bit 23 */ 511 #define RBR_CFIG_B_VLD2 0x0000000000800000ULL 512 #define RBR_CFIG_B_BKSIZE_SHIFT 24 /* bit 25:24 */ 513 #define RBR_CFIG_B_BKSIZE_MASK 0x0000000003000000ULL 514 515 516 typedef union _rbr_cfig_b_t { 517 uint64_t value; 518 struct { 519 #if defined(_BIG_ENDIAN) 520 uint32_t hdw; 521 #endif 522 struct { 523 #if defined(_BIT_FIELDS_HTOL) 524 uint32_t res1_1:6; 525 uint32_t bksize:2; 526 uint32_t vld2:1; 527 uint32_t res2:5; 528 uint32_t bufsz2:2; 529 uint32_t vld1:1; 530 uint32_t res3:5; 531 uint32_t bufsz1:2; 532 uint32_t vld0:1; 533 uint32_t res4:5; 534 uint32_t bufsz0:2; 535 #elif defined(_BIT_FIELDS_LTOH) 536 uint32_t bufsz0:2; 537 uint32_t res4:5; 538 uint32_t vld0:1; 539 uint32_t bufsz1:2; 540 uint32_t res3:5; 541 uint32_t vld1:1; 542 uint32_t bufsz2:2; 543 uint32_t res2:5; 544 uint32_t vld2:1; 545 uint32_t bksize:2; 546 uint32_t res1_1:6; 547 #endif 548 } ldw; 549 #if !defined(_BIG_ENDIAN) 550 uint32_t hdw; 551 #endif 552 } bits; 553 } rbr_cfig_b_t, *p_rbr_cfig_b_t; 554 555 556 #define RBR_KICK_SHIFT 0 /* bit 15:0 */ 557 #define RBR_KICK_MASK 0x00000000000ffff1ULL 558 559 560 typedef union _rbr_kick_t { 561 uint64_t value; 562 struct { 563 #if defined(_BIG_ENDIAN) 564 uint32_t hdw; 565 #endif 566 struct { 567 #if defined(_BIT_FIELDS_HTOL) 568 uint32_t res1_1:16; 569 uint32_t bkadd:16; 570 #elif defined(_BIT_FIELDS_LTOH) 571 uint32_t bkadd:16; 572 uint32_t res1_1:16; 573 #endif 574 } ldw; 575 #if !defined(_BIG_ENDIAN) 576 uint32_t hdw; 577 #endif 578 } bits; 579 } rbr_kick_t, *p_rbr_kick_t; 580 581 #define RBR_STAT_QLEN_SHIFT 0 /* bit bit 15:0 */ 582 #define RBR_STAT_QLEN_MASK 0x000000000000ffffULL 583 #define RBR_STAT_OFLOW_SHIFT 16 /* bit 16 */ 584 #define RBR_STAT_OFLOW 0x0000000000010000ULL 585 #define RBR_STAT_OFLOW_MASK 0x0000000000010000ULL 586 587 typedef union _rbr_stat_t { 588 uint64_t value; 589 struct { 590 #if defined(_BIG_ENDIAN) 591 uint32_t hdw; 592 #endif 593 struct { 594 #if defined(_BIT_FIELDS_HTOL) 595 uint32_t res1_1:15; 596 uint32_t oflow:1; 597 uint32_t qlen:16; 598 #elif defined(_BIT_FIELDS_LTOH) 599 uint32_t qlen:16; 600 uint32_t oflow:1; 601 uint32_t res1_1:15; 602 #endif 603 } ldw; 604 #if !defined(_BIG_ENDIAN) 605 uint32_t hdw; 606 #endif 607 } bits; 608 } rbr_stat_t, *p_rbr_stat_t; 609 610 611 #define RBR_HDH_HEAD_H_SHIFT 0 /* bit 11:0 */ 612 #define RBR_HDH_HEAD_H_MASK 0x0000000000000fffULL 613 typedef union _rbr_hdh_t { 614 uint64_t value; 615 struct { 616 #if defined(_BIG_ENDIAN) 617 uint32_t hdw; 618 #endif 619 struct { 620 #if defined(_BIT_FIELDS_HTOL) 621 uint32_t res1_1:20; 622 uint32_t head_h:12; 623 #elif defined(_BIT_FIELDS_LTOH) 624 uint32_t head_h:12; 625 uint32_t res1_1:20; 626 #endif 627 } ldw; 628 #if !defined(_BIG_ENDIAN) 629 uint32_t hdw; 630 #endif 631 } bits; 632 } rbr_hdh_t, *p_rbr_hdh_t; 633 634 #define RBR_HDL_HEAD_L_SHIFT 2 /* bit 31:2 */ 635 #define RBR_HDL_HEAD_L_MASK 0x00000000FFFFFFFCULL 636 637 typedef union _rbr_hdl_t { 638 uint64_t value; 639 struct { 640 #if defined(_BIG_ENDIAN) 641 uint32_t hdw; 642 #endif 643 struct { 644 #if defined(_BIT_FIELDS_HTOL) 645 uint32_t head_l:30; 646 uint32_t res2:2; 647 #elif defined(_BIT_FIELDS_LTOH) 648 uint32_t res2:2; 649 uint32_t head_l:30; 650 #endif 651 } ldw; 652 #if !defined(_BIG_ENDIAN) 653 uint32_t hdw; 654 #endif 655 } bits; 656 } rbr_hdl_t, *p_rbr_hdl_t; 657 658 /* 659 * Receive Completion Ring (RCR) 660 */ 661 #define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */ 662 #define RCR_PKT_BUF_ADDR_SHIFT_FULL 6 /* fulll buffer address */ 663 #define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL 664 #define RCR_PKTBUFSZ_SHIFT 38 /* bit 39:38 */ 665 #define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL 666 #define RCR_L2_LEN_SHIFT 40 /* bit 39:38 */ 667 #define RCR_L2_LEN_MASK 0x003fff0000000000ULL 668 #define RCR_DCF_ERROR_SHIFT 54 /* bit 54 */ 669 #define RCR_DCF_ERROR_MASK 0x0040000000000000ULL 670 #define RCR_ERROR_SHIFT 55 /* bit 57:55 */ 671 #define RCR_ERROR_MASK 0x0380000000000000ULL 672 #define RCR_PROMIS_SHIFT 58 /* bit 58 */ 673 #define RCR_PROMIS_MASK 0x0400000000000000ULL 674 #define RCR_FRAG_SHIFT 59 /* bit 59 */ 675 #define RCR_FRAG_MASK 0x0800000000000000ULL 676 #define RCR_ZERO_COPY_SHIFT 60 /* bit 60 */ 677 #define RCR_ZERO_COPY_MASK 0x1000000000000000ULL 678 #define RCR_PKT_TYPE_SHIFT 61 /* bit 62:61 */ 679 #define RCR_PKT_TYPE_MASK 0x6000000000000000ULL 680 #define RCR_MULTI_SHIFT 63 /* bit 63 */ 681 #define RCR_MULTI_MASK 0x8000000000000000ULL 682 683 #define RCR_PKTBUFSZ_0 0x00 684 #define RCR_PKTBUFSZ_1 0x01 685 #define RCR_PKTBUFSZ_2 0x02 686 #define RCR_SINGLE_BLOCK 0x03 687 #define RCR_N_PKTBUF_SZ 0x04 688 689 #define RCR_NO_ERROR 0x0 690 #define RCR_L2_ERROR 0x1 691 #define RCR_L4_CSUM_ERROR 0x3 692 #define RCR_FFLP_SOFT_ERROR 0x4 693 #define RCR_ZCP_SOFT_ERROR 0x5 694 #define RCR_ERROR_RESERVE 0x6 695 #define RCR_ERROR_RESERVE_END 0x7 696 697 #define RCR_PKT_TYPE_UDP 0x1 698 #define RCR_PKT_TYPE_TCP 0x2 699 #define RCR_PKT_TYPE_SCTP 0x3 700 #define RCR_PKT_TYPE_OTHERS 0x0 701 #define RCR_PKT_IS_TCP 0x2000000000000000ULL 702 #define RCR_PKT_IS_UDP 0x4000000000000000ULL 703 #define RCR_PKT_IS_SCTP 0x6000000000000000ULL 704 705 706 typedef union _rcr_entry_t { 707 uint64_t value; 708 struct { 709 #if defined(_BIG_ENDIAN) 710 struct { 711 #if defined(_BIT_FIELDS_HTOL) 712 uint32_t multi:1; 713 uint32_t pkt_type:2; 714 uint32_t zero_copy:1; 715 uint32_t noport:1; 716 uint32_t promis:1; 717 uint32_t error:3; 718 uint32_t dcf_err:1; 719 uint32_t l2_len:14; 720 uint32_t pktbufsz:2; 721 uint32_t pkt_buf_addr:6; 722 #elif defined(_BIT_FIELDS_LTOH) 723 uint32_t pkt_buf_addr:6; 724 uint32_t pktbufsz:2; 725 uint32_t l2_len:14; 726 uint32_t dcf_err:1; 727 uint32_t error:3; 728 uint32_t promis:1; 729 uint32_t noport:1; 730 uint32_t zero_copy:1; 731 uint32_t pkt_type:2; 732 uint32_t multi:1; 733 #endif 734 } hdw; 735 #endif 736 struct { 737 #if defined(_BIT_FIELDS_HTOL) 738 uint32_t pkt_buf_addr:32; 739 #elif defined(_BIT_FIELDS_LTOH) 740 uint32_t pkt_buf_addr:32; 741 #endif 742 } ldw; 743 #if !defined(_BIG_ENDIAN) 744 struct { 745 #if defined(_BIT_FIELDS_HTOL) 746 uint32_t multi:1; 747 uint32_t pkt_type:2; 748 uint32_t zero_copy:1; 749 uint32_t noport:1; 750 uint32_t promis:1; 751 uint32_t error:3; 752 uint32_t dcf_err:1; 753 uint32_t l2_len:14; 754 uint32_t pktbufsz:2; 755 uint32_t pkt_buf_addr:6; 756 #elif defined(_BIT_FIELDS_LTOH) 757 uint32_t pkt_buf_addr:6; 758 uint32_t pktbufsz:2; 759 uint32_t l2_len:14; 760 uint32_t dcf_err:1; 761 uint32_t error:3; 762 uint32_t promis:1; 763 uint32_t noport:1; 764 uint32_t zero_copy:1; 765 uint32_t pkt_type:2; 766 uint32_t multi:1; 767 #endif 768 } hdw; 769 #endif 770 } bits; 771 } rcr_entry_t, *p_rcr_entry_t; 772 773 /* 774 * Receive Completion Ring Configuration. 775 * (for each DMA channel) 776 */ 777 #define RCRCFIG_A_REG (DMC + 0x00040) 778 #define RCRCFIG_B_REG (DMC + 0x00048) 779 #define RCRSTAT_A_REG (DMC + 0x00050) 780 #define RCRSTAT_B_REG (DMC + 0x00058) 781 #define RCRSTAT_C_REG (DMC + 0x00060) 782 #define RX_DMA_ENT_MSK_REG (DMC + 0x00068) 783 #define RX_DMA_CTL_STAT_REG (DMC + 0x00070) 784 #define RCR_FLSH_REG (DMC + 0x00078) 785 #if OLD 786 #define RX_DMA_LOGA_REG (DMC + 0x00080) 787 #define RX_DMA_LOGB_REG (DMC + 0x00088) 788 #endif 789 #define RX_DMA_CTL_STAT_DBG_REG (DMC + 0x00098) 790 791 /* (DMC + 0x00050) */ 792 #define RCRCFIG_A_STADDR_SHIFT 6 /* bit 18:6 */ 793 #define RCRCFIG_A_STADDR_MASK 0x000000000007FFC0ULL 794 #define RCRCFIG_A_STADDR_BASE_SHIF 19 /* bit 43:19 */ 795 #define RCRCFIG_A_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 796 #define RCRCFIG_A_LEN_SHIF 48 /* bit 63:48 */ 797 #define RCRCFIG_A_LEN__MASK 0xFFFF000000000000ULL 798 799 /* (DMC + 0x00058) */ 800 #define RCRCFIG_B_TIMEOUT_SHIFT 0 /* bit 5:0 */ 801 #define RCRCFIG_B_TIMEOUT_MASK 0x000000000000003FULL 802 #define RCRCFIG_B_ENTOUT_SHIFT 15 /* bit 15 */ 803 #define RCRCFIG_B_TIMEOUT 0x0000000000008000ULL 804 #define RCRCFIG_B_PTHRES_SHIFT 16 /* bit 31:16 */ 805 #define RCRCFIG_B_PTHRES_MASK 0x00000000FFFF0000ULL 806 807 /* (DMC + 0x00060) */ 808 #define RCRSTAT_A_QLEN_SHIFT 0 /* bit 15:0 */ 809 #define RCRSTAT_A_QLEN_MASK 0x000000000000FFFFULL 810 #define RCRSTAT_A_PKT_OFL_SHIFT 16 /* bit 16 */ 811 #define RCRSTAT_A_PKT_OFL_MASK 0x0000000000010000ULL 812 #define RCRSTAT_A_ENT_OFL_SHIFT 17 /* bit 17 */ 813 #define RCRSTAT_A_ENT_QFL_MASK 0x0000000000020000ULL 814 815 #define RCRSTAT_C_TLPTR_H_SHIFT 0 /* bit 11:0 */ 816 #define RCRSTAT_C_TLPTR_H_MASK 0x0000000000000FFFULL 817 818 #define RCRSTAT_D_TLPTR_L_SHIFT 3 /* bit 31:3 */ 819 #define RCRSTAT_D_TLPTR_L_MASK 0x00000000FFFFFFF8ULL 820 821 /* Receive DMA Interrupt Behavior: Event Mask (DMC + 0x00068) */ 822 #define RX_DMA_ENT_MSK_CFIGLOGPGE_SHIFT 0 /* bit 0: 0 to flag */ 823 #define RX_DMA_ENT_MSK_CFIGLOGPGE_MASK 0x0000000000000001ULL 824 #define RX_DMA_ENT_MSK_RBRLOGPGE_SHIFT 1 /* bit 1: 0 to flag */ 825 #define RX_DMA_ENT_MSK_RBRLOGPGE_MASK 0x0000000000000002ULL 826 #define RX_DMA_ENT_MSK_RBRFULL_SHIFT 2 /* bit 2: 0 to flag */ 827 #define RX_DMA_ENT_MSK_RBRFULL_MASK 0x0000000000000004ULL 828 #define RX_DMA_ENT_MSK_RBREMPTY_SHIFT 3 /* bit 3: 0 to flag */ 829 #define RX_DMA_ENT_MSK_RBREMPTY_MASK 0x0000000000000008ULL 830 #define RX_DMA_ENT_MSK_RCRFULL_SHIFT 4 /* bit 4: 0 to flag */ 831 #define RX_DMA_ENT_MSK_RCRFULL_MASK 0x0000000000000010ULL 832 #define RX_DMA_ENT_MSK_RCRINCON_SHIFT 5 /* bit 5: 0 to flag */ 833 #define RX_DMA_ENT_MSK_RCRINCON_MASK 0x0000000000000020ULL 834 #define RX_DMA_ENT_MSK_CONFIG_ERR_SHIFT 6 /* bit 6: 0 to flag */ 835 #define RX_DMA_ENT_MSK_CONFIG_ERR_MASK 0x0000000000000040ULL 836 #define RX_DMA_ENT_MSK_RCRSH_FULL_SHIFT 7 /* bit 7: 0 to flag */ 837 #define RX_DMA_ENT_MSK_RCRSH_FULL_MASK 0x0000000000000080ULL 838 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_SHIFT 8 /* bit 8: 0 to flag */ 839 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK 0x0000000000000100ULL 840 #define RX_DMA_ENT_MSK_WRED_DROP_SHIFT 9 /* bit 9: 0 to flag */ 841 #define RX_DMA_ENT_MSK_WRED_DROP_MASK 0x0000000000000200ULL 842 #define RX_DMA_ENT_MSK_PTDROP_PKT_SHIFT 10 /* bit 10: 0 to flag */ 843 #define RX_DMA_ENT_MSK_PTDROP_PKT_MASK 0x0000000000000400ULL 844 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_SHIFT 11 /* bit 11: 0 to flag */ 845 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK 0x0000000000000800ULL 846 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_SHIFT 12 /* bit 12: 0 to flag */ 847 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK 0x0000000000001000ULL 848 #define RX_DMA_ENT_MSK_RCRTO_SHIFT 13 /* bit 13: 0 to flag */ 849 #define RX_DMA_ENT_MSK_RCRTO_MASK 0x0000000000002000ULL 850 #define RX_DMA_ENT_MSK_THRES_SHIFT 14 /* bit 14: 0 to flag */ 851 #define RX_DMA_ENT_MSK_THRES_MASK 0x0000000000004000ULL 852 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_SHIFT 16 /* bit 16: 0 to flag */ 853 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK 0x0000000000010000ULL 854 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_SHIFT 17 /* bit 17: 0 to flag */ 855 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK 0x0000000000020000ULL 856 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_SHIFT 18 /* bit 18: 0 to flag */ 857 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK 0x0000000000040000ULL 858 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_SHIFT 19 /* bit 19: 0 to flag */ 859 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK 0x0000000000080000ULL 860 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_SHIFT 20 /* bit 20: 0 to flag */ 861 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK 0x0000000000100000ULL 862 #define RX_DMA_ENT_MSK_RBR_TMOUT_SHIFT 21 /* bit 21: 0 to flag */ 863 #define RX_DMA_ENT_MSK_RBR_TMOUT_MASK 0x0000000000200000ULL 864 #define RX_DMA_ENT_MSK_ALL (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | \ 865 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | \ 866 RX_DMA_ENT_MSK_RBRFULL_MASK | \ 867 RX_DMA_ENT_MSK_RBREMPTY_MASK | \ 868 RX_DMA_ENT_MSK_RCRFULL_MASK | \ 869 RX_DMA_ENT_MSK_RCRINCON_MASK | \ 870 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | \ 871 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | \ 872 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | \ 873 RX_DMA_ENT_MSK_WRED_DROP_MASK | \ 874 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 875 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 876 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | \ 877 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | \ 878 RX_DMA_ENT_MSK_RCRTO_MASK | \ 879 RX_DMA_ENT_MSK_THRES_MASK | \ 880 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | \ 881 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | \ 882 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | \ 883 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | \ 884 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | \ 885 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 886 887 /* Receive DMA Control and Status (DMC + 0x00070) */ 888 #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */ 889 #define RX_DMA_CTL_STAT_PKTREAD_MASK 0x000000000000ffffULL 890 #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16 /* WO, bit 31:16 */ 891 #define RX_DMA_CTL_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL 892 #define RX_DMA_CTL_STAT_CFIGLOGPG_SHIFT 32 /* RO, bit 32 */ 893 #define RX_DMA_CTL_STAT_CFIGLOGPG 0x0000000100000000ULL 894 #define RX_DMA_CTL_STAT_CFIGLOGPG_MASK 0x0000000100000000ULL 895 #define RX_DMA_CTL_STAT_RBRLOGPG_SHIFT 33 /* RO, bit 33 */ 896 #define RX_DMA_CTL_STAT_RBRLOGPG 0x0000000200000000ULL 897 #define RX_DMA_CTL_STAT_RBRLOGPG_MASK 0x0000000200000000ULL 898 #define RX_DMA_CTL_STAT_RBRFULL_SHIFT 34 /* RO, bit 34 */ 899 #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL 900 #define RX_DMA_CTL_STAT_RBRFULL_MASK 0x0000000400000000ULL 901 #define RX_DMA_CTL_STAT_RBREMPTY_SHIFT 35 /* RW1C, bit 35 */ 902 #define RX_DMA_CTL_STAT_RBREMPTY 0x0000000800000000ULL 903 #define RX_DMA_CTL_STAT_RBREMPTY_MASK 0x0000000800000000ULL 904 #define RX_DMA_CTL_STAT_RCRFULL_SHIFT 36 /* RW1C, bit 36 */ 905 #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL 906 #define RX_DMA_CTL_STAT_RCRFULL_MASK 0x0000001000000000ULL 907 #define RX_DMA_CTL_STAT_RCRINCON_SHIFT 37 /* RO, bit 37 */ 908 #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL 909 #define RX_DMA_CTL_STAT_RCRINCON_MASK 0x0000002000000000ULL 910 #define RX_DMA_CTL_STAT_CONFIG_ERR_SHIFT 38 /* RO, bit 38 */ 911 #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL 912 #define RX_DMA_CTL_STAT_CONFIG_ERR_MASK 0x0000004000000000ULL 913 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_SHIFT 39 /* RO, bit 39 */ 914 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL 0x0000008000000000ULL 915 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL 916 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 917 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_SHIFT 40 /* RO, bit 40 */ 918 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL 919 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 920 #define RX_DMA_CTL_STAT_WRED_DROP_SHIFT 41 /* RO, bit 41 */ 921 #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL 922 #define RX_DMA_CTL_STAT_WRED_DROP_MASK 0x0000020000000000ULL 923 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_SHIFT 42 /* RO, bit 42 */ 924 #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL 925 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_MASK 0x0000040000000000ULL 926 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_SHIFT 43 /* RO, bit 43 */ 927 #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL 928 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL 929 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_SHIFT 44 /* RO, bit 44 */ 930 #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL 931 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL 932 #define RX_DMA_CTL_STAT_RCRTO_SHIFT 45 /* RW1C, bit 45 */ 933 #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL 934 #define RX_DMA_CTL_STAT_RCRTO_MASK 0x0000200000000000ULL 935 #define RX_DMA_CTL_STAT_RCRTHRES_SHIFT 46 /* RO, bit 46 */ 936 #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL 937 #define RX_DMA_CTL_STAT_RCRTHRES_MASK 0x0000400000000000ULL 938 #define RX_DMA_CTL_STAT_MEX_SHIFT 47 /* RW, bit 47 */ 939 #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL 940 #define RX_DMA_CTL_STAT_MEX_MASK 0x0000800000000000ULL 941 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_SHIFT 48 /* RW1C, bit 48 */ 942 #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL 943 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_MASK 0x0001000000000000ULL 944 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_SHIFT 49 /* RO, bit 49 */ 945 #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL 946 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_MASK 0x0002000000000000ULL 947 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_SHIFT 50 /* RO, bit 50 */ 948 #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL 949 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_MASK 0x0004000000000000ULL 950 951 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_SHIFT 51 /* RO, bit 51 */ 952 #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL 953 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_MASK 0x0008000000000000ULL 954 955 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_SHIFT 52 /* RO, bit 52 */ 956 #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL 957 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_MASK 0x0010000000000000ULL 958 959 #define RX_DMA_CTL_STAT_RBR_TMOUT_SHIFT 53 /* RO, bit 53 */ 960 #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL 961 #define RX_DMA_CTL_STAT_RBR_TMOUT_MASK 0x0020000000000000ULL 962 #define RX_DMA_CTRL_STAT_ENT_MASK_SHIFT 32 963 #define RX_DMA_CTL_STAT_ERROR (RX_DMA_ENT_MSK_ALL << \ 964 RX_DMA_CTRL_STAT_ENT_MASK_SHIFT) 965 966 /* the following are write 1 to clear bits */ 967 #define RX_DMA_CTL_STAT_WR1C RX_DMA_CTL_STAT_RBREMPTY | \ 968 RX_DMA_CTL_STAT_RCR_SHDW_FULL | \ 969 RX_DMA_CTL_STAT_RBR_PRE_EMTY | \ 970 RX_DMA_CTL_STAT_WRED_DROP | \ 971 RX_DMA_CTL_STAT_PORT_DROP_PKT | \ 972 RX_DMA_CTL_STAT_RCRTO | \ 973 RX_DMA_CTL_STAT_RCRTHRES | \ 974 RX_DMA_CTL_STAT_DC_FIFO_ERR 975 976 /* Receive DMA Interrupt Behavior: Force an update to RCR (DMC + 0x00078 */ 977 #define RCR_FLSH_SHIFT 0 /* RW, bit 0:0 */ 978 #define RCR_FLSH_SET 0x0000000000000001ULL 979 #define RCR_FLSH_MASK 0x0000000000000001ULL 980 981 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00080 */ 982 #define RX_DMA_LOGA_ADDR_SHIFT 0 /* RO, bit 11:0 */ 983 #define RX_DMA_LOGA_ADDR 0x0000000000000FFFULL 984 #define RX_DMA_LOGA_ADDR_MASK 0x0000000000000FFFULL 985 #define RX_DMA_LOGA_TYPE_SHIFT 28 /* RO, bit 30:28 */ 986 #define RX_DMA_LOGA_TYPE 0x0000000070000000ULL 987 #define RX_DMA_LOGA_TYPE_MASK 0x0000000070000FFFULL 988 #define RX_DMA_LOGA_MULTI_SHIFT 28 /* RO, bit 30:28 */ 989 #define RX_DMA_LOGA_MULTI 0x0000000080000000ULL 990 #define RX_DMA_LOGA_MULTI_MASK 0x0000000080000FFFULL 991 992 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00088 */ 993 #define RX_DMA_LOGA_ADDR_L_SHIFT 0 /* RO, bit 31:0 */ 994 #define RX_DMA_LOGA_ADDRL_L 0x00000000FFFFFFFFULL 995 #define RX_DMA_LOGA_ADDR_LMASK 0x00000000FFFFFFFFULL 996 997 typedef union _rcrcfig_a_t { 998 uint64_t value; 999 struct { 1000 #if defined(_BIG_ENDIAN) 1001 struct { 1002 #if defined(_BIT_FIELDS_HTOL) 1003 uint32_t len:16; 1004 uint32_t res1:4; 1005 uint32_t staddr_base:12; 1006 #elif defined(_BIT_FIELDS_LTOH) 1007 uint32_t staddr_base:12; 1008 uint32_t res1:4; 1009 uint32_t len:16; 1010 #endif 1011 } hdw; 1012 #endif 1013 struct { 1014 #if defined(_BIT_FIELDS_HTOL) 1015 uint32_t staddr_base:13; 1016 uint32_t staddr:13; 1017 uint32_t res2:6; 1018 #elif defined(_BIT_FIELDS_LTOH) 1019 uint32_t res2:6; 1020 uint32_t staddr:13; 1021 uint32_t staddr_base:13; 1022 #endif 1023 } ldw; 1024 #if !defined(_BIG_ENDIAN) 1025 struct { 1026 #if defined(_BIT_FIELDS_HTOL) 1027 uint32_t len:16; 1028 uint32_t res1:4; 1029 uint32_t staddr_base:12; 1030 #elif defined(_BIT_FIELDS_LTOH) 1031 uint32_t staddr_base:12; 1032 uint32_t res1:4; 1033 uint32_t len:16; 1034 #endif 1035 } hdw; 1036 #endif 1037 } bits; 1038 } rcrcfig_a_t, *p_rcrcfig_a_t; 1039 1040 1041 typedef union _rcrcfig_b_t { 1042 uint64_t value; 1043 struct { 1044 #if defined(_BIG_ENDIAN) 1045 uint32_t hdw; 1046 #endif 1047 struct { 1048 #if defined(_BIT_FIELDS_HTOL) 1049 uint32_t pthres:16; 1050 uint32_t entout:1; 1051 uint32_t res1:9; 1052 uint32_t timeout:6; 1053 #elif defined(_BIT_FIELDS_LTOH) 1054 uint32_t timeout:6; 1055 uint32_t res1:9; 1056 uint32_t entout:1; 1057 uint32_t pthres:16; 1058 #endif 1059 } ldw; 1060 #if !defined(_BIG_ENDIAN) 1061 uint32_t hdw; 1062 #endif 1063 } bits; 1064 } rcrcfig_b_t, *p_rcrcfig_b_t; 1065 1066 1067 typedef union _rcrstat_a_t { 1068 uint64_t value; 1069 struct { 1070 #if defined(_BIG_ENDIAN) 1071 uint32_t hdw; 1072 #endif 1073 struct { 1074 #if defined(_BIT_FIELDS_HTOL) 1075 uint32_t res1:16; 1076 uint32_t qlen:16; 1077 #elif defined(_BIT_FIELDS_LTOH) 1078 uint32_t qlen:16; 1079 uint32_t res1:16; 1080 #endif 1081 } ldw; 1082 #if !defined(_BIG_ENDIAN) 1083 uint32_t hdw; 1084 #endif 1085 } bits; 1086 } rcrstat_a_t, *p_rcrstat_a_t; 1087 1088 1089 typedef union _rcrstat_b_t { 1090 uint64_t value; 1091 struct { 1092 #if defined(_BIG_ENDIAN) 1093 uint32_t hdw; 1094 #endif 1095 struct { 1096 #if defined(_BIT_FIELDS_HTOL) 1097 uint32_t res1:20; 1098 uint32_t tlptr_h:12; 1099 #elif defined(_BIT_FIELDS_LTOH) 1100 uint32_t tlptr_h:12; 1101 uint32_t res1:20; 1102 #endif 1103 } ldw; 1104 #if !defined(_BIG_ENDIAN) 1105 uint32_t hdw; 1106 #endif 1107 } bits; 1108 } rcrstat_b_t, *p_rcrstat_b_t; 1109 1110 1111 typedef union _rcrstat_c_t { 1112 uint64_t value; 1113 struct { 1114 #if defined(_BIG_ENDIAN) 1115 uint32_t hdw; 1116 #endif 1117 struct { 1118 #if defined(_BIT_FIELDS_HTOL) 1119 uint32_t tlptr_l:29; 1120 uint32_t res1:3; 1121 #elif defined(_BIT_FIELDS_LTOH) 1122 uint32_t res1:3; 1123 uint32_t tlptr_l:29; 1124 #endif 1125 } ldw; 1126 #if !defined(_BIG_ENDIAN) 1127 uint32_t hdw; 1128 #endif 1129 } bits; 1130 } rcrstat_c_t, *p_rcrstat_c_t; 1131 1132 1133 /* Receive DMA Event Mask */ 1134 typedef union _rx_dma_ent_msk_t { 1135 uint64_t value; 1136 struct { 1137 #if defined(_BIG_ENDIAN) 1138 uint32_t hdw; 1139 #endif 1140 struct { 1141 #if defined(_BIT_FIELDS_HTOL) 1142 uint32_t rsrvd2:10; 1143 uint32_t rbr_tmout:1; 1144 uint32_t rsp_cnt_err:1; 1145 uint32_t byte_en_bus:1; 1146 uint32_t rsp_dat_err:1; 1147 uint32_t rcr_ack_err:1; 1148 uint32_t dc_fifo_err:1; 1149 uint32_t rsrvd:1; 1150 uint32_t rcrthres:1; 1151 uint32_t rcrto:1; 1152 uint32_t rcr_sha_par:1; 1153 uint32_t rbr_pre_par:1; 1154 uint32_t port_drop_pkt:1; 1155 uint32_t wred_drop:1; 1156 uint32_t rbr_pre_empty:1; 1157 uint32_t rcr_shadow_full:1; 1158 uint32_t config_err:1; 1159 uint32_t rcrincon:1; 1160 uint32_t rcrfull:1; 1161 uint32_t rbr_empty:1; 1162 uint32_t rbrfull:1; 1163 uint32_t rbrlogpage:1; 1164 uint32_t cfiglogpage:1; 1165 #elif defined(_BIT_FIELDS_LTOH) 1166 uint32_t cfiglogpage:1; 1167 uint32_t rbrlogpage:1; 1168 uint32_t rbrfull:1; 1169 uint32_t rbr_empty:1; 1170 uint32_t rcrfull:1; 1171 uint32_t rcrincon:1; 1172 uint32_t config_err:1; 1173 uint32_t rcr_shadow_full:1; 1174 uint32_t rbr_pre_empty:1; 1175 uint32_t wred_drop:1; 1176 uint32_t port_drop_pkt:1; 1177 uint32_t rbr_pre_par:1; 1178 uint32_t rcr_sha_par:1; 1179 uint32_t rcrto:1; 1180 uint32_t rcrthres:1; 1181 uint32_t rsrvd:1; 1182 uint32_t dc_fifo_err:1; 1183 uint32_t rcr_ack_err:1; 1184 uint32_t rsp_dat_err:1; 1185 uint32_t byte_en_bus:1; 1186 uint32_t rsp_cnt_err:1; 1187 uint32_t rbr_tmout:1; 1188 uint32_t rsrvd2:10; 1189 #endif 1190 } ldw; 1191 #if !defined(_BIG_ENDIAN) 1192 uint32_t hdw; 1193 #endif 1194 } bits; 1195 } rx_dma_ent_msk_t, *p_rx_dma_ent_msk_t; 1196 1197 1198 /* Receive DMA Control and Status */ 1199 typedef union _rx_dma_ctl_stat_t { 1200 uint64_t value; 1201 struct { 1202 #if defined(_BIG_ENDIAN) 1203 struct { 1204 #if defined(_BIT_FIELDS_HTOL) 1205 uint32_t rsrvd:10; 1206 uint32_t rbr_tmout:1; 1207 uint32_t rsp_cnt_err:1; 1208 uint32_t byte_en_bus:1; 1209 uint32_t rsp_dat_err:1; 1210 uint32_t rcr_ack_err:1; 1211 uint32_t dc_fifo_err:1; 1212 uint32_t mex:1; 1213 uint32_t rcrthres:1; 1214 uint32_t rcrto:1; 1215 uint32_t rcr_sha_par:1; 1216 uint32_t rbr_pre_par:1; 1217 uint32_t port_drop_pkt:1; 1218 uint32_t wred_drop:1; 1219 uint32_t rbr_pre_empty:1; 1220 uint32_t rcr_shadow_full:1; 1221 uint32_t config_err:1; 1222 uint32_t rcrincon:1; 1223 uint32_t rcrfull:1; 1224 uint32_t rbr_empty:1; 1225 uint32_t rbrfull:1; 1226 uint32_t rbrlogpage:1; 1227 uint32_t cfiglogpage:1; 1228 #elif defined(_BIT_FIELDS_LTOH) 1229 uint32_t cfiglogpage:1; 1230 uint32_t rbrlogpage:1; 1231 uint32_t rbrfull:1; 1232 uint32_t rbr_empty:1; 1233 uint32_t rcrfull:1; 1234 uint32_t rcrincon:1; 1235 uint32_t config_err:1; 1236 uint32_t rcr_shadow_full:1; 1237 uint32_t rbr_pre_empty:1; 1238 uint32_t wred_drop:1; 1239 uint32_t port_drop_pkt:1; 1240 uint32_t rbr_pre_par:1; 1241 uint32_t rcr_sha_par:1; 1242 uint32_t rcrto:1; 1243 uint32_t rcrthres:1; 1244 uint32_t mex:1; 1245 uint32_t dc_fifo_err:1; 1246 uint32_t rcr_ack_err:1; 1247 uint32_t rsp_dat_err:1; 1248 uint32_t byte_en_bus:1; 1249 uint32_t rsp_cnt_err:1; 1250 uint32_t rbr_tmout:1; 1251 uint32_t rsrvd:10; 1252 #endif 1253 } hdw; 1254 1255 #endif 1256 struct { 1257 #if defined(_BIT_FIELDS_HTOL) 1258 uint32_t ptrread:16; 1259 uint32_t pktread:16; 1260 #elif defined(_BIT_FIELDS_LTOH) 1261 uint32_t pktread:16; 1262 uint32_t ptrread:16; 1263 1264 #endif 1265 } ldw; 1266 #if !defined(_BIG_ENDIAN) 1267 struct { 1268 #if defined(_BIT_FIELDS_HTOL) 1269 uint32_t rsrvd:10; 1270 uint32_t rbr_tmout:1; 1271 uint32_t rsp_cnt_err:1; 1272 uint32_t byte_en_bus:1; 1273 uint32_t rsp_dat_err:1; 1274 uint32_t rcr_ack_err:1; 1275 uint32_t dc_fifo_err:1; 1276 uint32_t mex:1; 1277 uint32_t rcrthres:1; 1278 uint32_t rcrto:1; 1279 uint32_t rcr_sha_par:1; 1280 uint32_t rbr_pre_par:1; 1281 uint32_t port_drop_pkt:1; 1282 uint32_t wred_drop:1; 1283 uint32_t rbr_pre_empty:1; 1284 uint32_t rcr_shadow_full:1; 1285 uint32_t config_err:1; 1286 uint32_t rcrincon:1; 1287 uint32_t rcrfull:1; 1288 uint32_t rbr_empty:1; 1289 uint32_t rbrfull:1; 1290 uint32_t rbrlogpage:1; 1291 uint32_t cfiglogpage:1; 1292 #elif defined(_BIT_FIELDS_LTOH) 1293 uint32_t cfiglogpage:1; 1294 uint32_t rbrlogpage:1; 1295 uint32_t rbrfull:1; 1296 uint32_t rbr_empty:1; 1297 uint32_t rcrfull:1; 1298 uint32_t rcrincon:1; 1299 uint32_t config_err:1; 1300 uint32_t rcr_shadow_full:1; 1301 uint32_t rbr_pre_empty:1; 1302 uint32_t wred_drop:1; 1303 uint32_t port_drop_pkt:1; 1304 uint32_t rbr_pre_par:1; 1305 uint32_t rcr_sha_par:1; 1306 uint32_t rcrto:1; 1307 uint32_t rcrthres:1; 1308 uint32_t mex:1; 1309 uint32_t dc_fifo_err:1; 1310 uint32_t rcr_ack_err:1; 1311 uint32_t rsp_dat_err:1; 1312 uint32_t byte_en_bus:1; 1313 uint32_t rsp_cnt_err:1; 1314 uint32_t rbr_tmout:1; 1315 uint32_t rsrvd:10; 1316 #endif 1317 } hdw; 1318 #endif 1319 } bits; 1320 } rx_dma_ctl_stat_t, *p_rx_dma_ctl_stat_t; 1321 1322 typedef union _rcr_flsh_t { 1323 uint64_t value; 1324 struct { 1325 #if defined(_BIG_ENDIAN) 1326 uint32_t hdw; 1327 #endif 1328 struct { 1329 #if defined(_BIT_FIELDS_HTOL) 1330 uint32_t res1_1:31; 1331 uint32_t flsh:1; 1332 #elif defined(_BIT_FIELDS_LTOH) 1333 uint32_t flsh:1; 1334 uint32_t res1_1:31; 1335 #endif 1336 } ldw; 1337 #if !defined(_BIG_ENDIAN) 1338 uint32_t hdw; 1339 #endif 1340 } bits; 1341 } rcr_flsh_t, *p_rcr_flsh_t; 1342 1343 1344 typedef union _rx_dma_loga_t { 1345 uint64_t value; 1346 struct { 1347 #if defined(_BIG_ENDIAN) 1348 uint32_t hdw; 1349 #endif 1350 struct { 1351 #if defined(_BIT_FIELDS_HTOL) 1352 uint32_t multi:1; 1353 uint32_t type:3; 1354 uint32_t res1:16; 1355 uint32_t addr:12; 1356 #elif defined(_BIT_FIELDS_LTOH) 1357 uint32_t addr:12; 1358 uint32_t res1:16; 1359 uint32_t type:3; 1360 uint32_t multi:1; 1361 #endif 1362 } ldw; 1363 #if !defined(_BIG_ENDIAN) 1364 uint32_t hdw; 1365 #endif 1366 } bits; 1367 } rx_dma_loga_t, *p_rx_dma_loga_t; 1368 1369 1370 typedef union _rx_dma_logb_t { 1371 uint64_t value; 1372 struct { 1373 #if defined(_BIG_ENDIAN) 1374 uint32_t hdw; 1375 #endif 1376 struct { 1377 #if defined(_BIT_FIELDS_HTOL) 1378 uint32_t addr_l:32; 1379 #elif defined(_BIT_FIELDS_LTOH) 1380 uint32_t addr_l:32; 1381 #endif 1382 } ldw; 1383 #if !defined(_BIG_ENDIAN) 1384 uint32_t hdw; 1385 #endif 1386 } bits; 1387 } rx_dma_logb_t, *p_rx_dma_logb_t; 1388 1389 1390 #define RX_DMA_MAILBOX_BYTE_LENGTH 64 1391 #define RX_DMA_MBOX_UNUSED_1 8 1392 #define RX_DMA_MBOX_UNUSED_2 16 1393 1394 typedef struct _rxdma_mailbox_t { 1395 rx_dma_ctl_stat_t rxdma_ctl_stat; /* 8 bytes */ 1396 rbr_stat_t rbr_stat; /* 8 bytes */ 1397 uint32_t rbr_hdl; /* 4 bytes (31:0) */ 1398 uint32_t rbr_hdh; /* 4 bytes (31:0) */ 1399 uint32_t resv_1[RX_DMA_MBOX_UNUSED_1]; 1400 uint32_t rcrstat_c; /* 4 bytes (31:0) */ 1401 uint32_t rcrstat_b; /* 4 bytes (31:0) */ 1402 rcrstat_a_t rcrstat_a; /* 8 bytes */ 1403 uint32_t resv_2[RX_DMA_MBOX_UNUSED_2]; 1404 } rxdma_mailbox_t, *p_rxdma_mailbox_t; 1405 1406 1407 1408 typedef union _rx_disc_cnt_t { 1409 uint64_t value; 1410 struct { 1411 #if defined(_BIG_ENDIAN) 1412 uint32_t hdw; 1413 #endif 1414 struct { 1415 #if defined(_BIT_FIELDS_HTOL) 1416 uint32_t res_1:15; 1417 uint32_t oflow:1; 1418 uint32_t count:16; 1419 #elif defined(_BIT_FIELDS_LTOH) 1420 uint32_t count:16; 1421 uint32_t oflow:1; 1422 uint32_t res_1:15; 1423 #endif 1424 } ldw; 1425 #if !defined(_BIG_ENDIAN) 1426 uint32_t hdw; 1427 #endif 1428 } bits; 1429 } rx_disc_cnt_t, *p_rx_disc_cnt_t; 1430 1431 #define RXMISC_DISCARD_REG (DMC + 0x00090) 1432 1433 #if OLD 1434 /* 1435 * RBR Empty: If the RBR is empty or the prefetch buffer is empty, 1436 * packets will be discarded (Each RBR has one). 1437 * (16 channels, 0x200) 1438 */ 1439 #define RDC_PRE_EMPTY_REG (DMC + 0x000B0) 1440 #define RDC_PRE_EMPTY_OFFSET(channel) (RDC_PRE_EMPTY_REG + \ 1441 (DMC_OFFSET(channel)) 1442 1443 typedef union _rdc_pre_empty_t { 1444 uint64_t value; 1445 struct { 1446 #if defined(_BIG_ENDIAN) 1447 uint32_t hdw; 1448 #endif 1449 struct { 1450 #if defined(_BIT_FIELDS_HTOL) 1451 uint32_t res_1:15; 1452 uint32_t oflow:1; 1453 uint32_t count:16; 1454 #elif defined(_BIT_FIELDS_LTOH) 1455 uint32_t count:16; 1456 uint32_t oflow:1; 1457 uint32_t res_1:15; 1458 #endif 1459 } ldw; 1460 #if !defined(_BIG_ENDIAN) 1461 uint32_t hdw; 1462 #endif 1463 } bits; 1464 } rdc_pre_empty_t, *p_rdc_pre_empty_t; 1465 #endif 1466 1467 1468 #define FZC_DMC_REG_SIZE 0x20 1469 #define FZC_DMC_OFFSET(channel) (FZC_DMC_REG_SIZE * channel) 1470 1471 /* WRED discard count register (16, 0x40) */ 1472 #define RED_DIS_CNT_REG (FZC_DMC + 0x30008) 1473 #define RED_DMC_OFFSET(channel) (0x40 * channel) 1474 #define RDC_DIS_CNT_OFFSET(rdc) (RED_DIS_CNT_REG + RED_DMC_OFFSET(rdc)) 1475 1476 typedef union _red_disc_cnt_t { 1477 uint64_t value; 1478 struct { 1479 #if defined(_BIG_ENDIAN) 1480 uint32_t hdw; 1481 #endif 1482 struct { 1483 #if defined(_BIT_FIELDS_HTOL) 1484 uint32_t res_1:15; 1485 uint32_t oflow:1; 1486 uint32_t count:16; 1487 #elif defined(_BIT_FIELDS_LTOH) 1488 uint32_t count:16; 1489 uint32_t oflow:1; 1490 uint32_t res_1:15; 1491 #endif 1492 } ldw; 1493 #if !defined(_BIG_ENDIAN) 1494 uint32_t hdw; 1495 #endif 1496 } bits; 1497 } red_disc_cnt_t, *p_red_disc_cnt_t; 1498 1499 1500 #define RDMC_PRE_PAR_ERR_REG (FZC_DMC + 0x00078) 1501 #define RDMC_SHA_PAR_ERR_REG (FZC_DMC + 0x00080) 1502 1503 typedef union _rdmc_par_err_log { 1504 uint64_t value; 1505 struct { 1506 #if defined(_BIG_ENDIAN) 1507 uint32_t hdw; 1508 #endif 1509 struct { 1510 #if defined(_BIT_FIELDS_HTOL) 1511 uint32_t res_1:16; 1512 uint32_t err:1; 1513 uint32_t merr:1; 1514 uint32_t res:6; 1515 uint32_t addr:8; 1516 #elif defined(_BIT_FIELDS_LTOH) 1517 uint32_t addr:8; 1518 uint32_t res:6; 1519 uint32_t merr:1; 1520 uint32_t err:1; 1521 uint32_t res_1:16; 1522 #endif 1523 } ldw; 1524 #if !defined(_BIG_ENDIAN) 1525 uint32_t hdw; 1526 #endif 1527 } bits; 1528 } rdmc_par_err_log_t, *p_rdmc_par_err_log_t; 1529 1530 1531 /* Used for accessing RDMC Memory */ 1532 #define RDMC_MEM_ADDR_REG (FZC_DMC + 0x00088) 1533 1534 1535 typedef union _rdmc_mem_addr { 1536 uint64_t value; 1537 struct { 1538 #if defined(_BIG_ENDIAN) 1539 uint32_t hdw; 1540 #endif 1541 1542 #define RDMC_MEM_ADDR_PREFETCH 0 1543 #define RDMC_MEM_ADDR_SHADOW 1 1544 1545 struct { 1546 #if defined(_BIT_FIELDS_HTOL) 1547 uint32_t res_1:23; 1548 uint32_t pre_shad:1; 1549 uint32_t addr:8; 1550 #elif defined(_BIT_FIELDS_LTOH) 1551 uint32_t addr:8; 1552 uint32_t pre_shad:1; 1553 uint32_t res_1:23; 1554 #endif 1555 } ldw; 1556 #if !defined(_BIG_ENDIAN) 1557 uint32_t hdw; 1558 #endif 1559 } bits; 1560 } rdmc_mem_addr_t, *p_rdmc_mem_addr_t; 1561 1562 1563 #define RDMC_MEM_DATA0_REG (FZC_DMC + 0x00090) 1564 #define RDMC_MEM_DATA1_REG (FZC_DMC + 0x00098) 1565 #define RDMC_MEM_DATA2_REG (FZC_DMC + 0x000A0) 1566 #define RDMC_MEM_DATA3_REG (FZC_DMC + 0x000A8) 1567 #define RDMC_MEM_DATA4_REG (FZC_DMC + 0x000B0) 1568 1569 typedef union _rdmc_mem_data { 1570 uint64_t value; 1571 struct { 1572 #if defined(_BIG_ENDIAN) 1573 uint32_t hdw; 1574 #endif 1575 1576 struct { 1577 #if defined(_BIT_FIELDS_HTOL) 1578 uint32_t data; 1579 #elif defined(_BIT_FIELDS_LTOH) 1580 uint32_t data; 1581 #endif 1582 } ldw; 1583 #if !defined(_BIG_ENDIAN) 1584 uint32_t hdw; 1585 #endif 1586 } bits; 1587 } rdmc_mem_data_t, *p_rdmc_mem_data_t; 1588 1589 1590 typedef union _rdmc_mem_access { 1591 #define RDMC_MEM_READ 1 1592 #define RDMC_MEM_WRITE 2 1593 uint32_t data[5]; 1594 uint8_t addr; 1595 uint8_t location; 1596 } rdmc_mem_access_t, *p_rdmc_mem_access_t; 1597 1598 1599 #define RX_CTL_DAT_FIFO_STAT_REG (FZC_DMC + 0x000B8) 1600 #define RX_CTL_DAT_FIFO_MASK_REG (FZC_DMC + 0x000C0) 1601 #define RX_CTL_DAT_FIFO_STAT_DBG_REG (FZC_DMC + 0x000D0) 1602 1603 typedef union _rx_ctl_dat_fifo { 1604 #define FIFO_EOP_PORT0 0x1 1605 #define FIFO_EOP_PORT1 0x2 1606 #define FIFO_EOP_PORT2 0x4 1607 #define FIFO_EOP_PORT3 0x8 1608 #define FIFO_EOP_ALL 0xF 1609 uint64_t value; 1610 struct { 1611 #if defined(_BIG_ENDIAN) 1612 uint32_t hdw; 1613 #endif 1614 struct { 1615 #if defined(_BIT_FIELDS_HTOL) 1616 uint32_t res_1:23; 1617 uint32_t id_mismatch:1; 1618 uint32_t zcp_eop_err:4; 1619 uint32_t ipp_eop_err:4; 1620 #elif defined(_BIT_FIELDS_LTOH) 1621 uint32_t ipp_eop_err:4; 1622 uint32_t zcp_eop_err:4; 1623 uint32_t id_mismatch:1; 1624 uint32_t res_1:23; 1625 #endif 1626 } ldw; 1627 #if !defined(_BIG_ENDIAN) 1628 uint32_t hdw; 1629 #endif 1630 } bits; 1631 } rx_ctl_dat_fifo_mask_t, rx_ctl_dat_fifo_stat_t, 1632 rx_ctl_dat_fifo_stat_dbg_t, *p_rx_ctl_dat_fifo_t; 1633 1634 1635 1636 #define RDMC_TRAINING_VECTOR_REG (FZC_DMC + 0x000C8) 1637 1638 typedef union _rx_training_vect { 1639 uint64_t value; 1640 struct { 1641 #if defined(_BIG_ENDIAN) 1642 uint32_t hdw; 1643 #endif 1644 struct { 1645 uint32_t tv; 1646 } ldw; 1647 #if !defined(_BIG_ENDIAN) 1648 uint32_t hdw; 1649 #endif 1650 } bits; 1651 } rx_training_vect_t, *p_rx_training_vect_t; 1652 1653 #define RXCTL_IPP_EOP_ERR_MASK 0x0000000FULL 1654 #define RXCTL_IPP_EOP_ERR_SHIFT 0x0 1655 #define RXCTL_ZCP_EOP_ERR_MASK 0x000000F0ULL 1656 #define RXCTL_ZCP_EOP_ERR_SHIFT 0x4 1657 #define RXCTL_ID_MISMATCH_MASK 0x00000100ULL 1658 #define RXCTL_ID_MISMATCH_SHIFT 0x8 1659 1660 1661 /* 1662 * Receive Packet Header Format 1663 * Packet header before the packet. 1664 * The minimum is 2 bytes and the max size is 18 bytes. 1665 */ 1666 /* 1667 * Packet header format 0 (2 bytes). 1668 */ 1669 typedef union _rx_pkt_hdr0_t { 1670 uint16_t value; 1671 struct { 1672 #if defined(_BIT_FIELDS_HTOL) 1673 uint16_t inputport:2; 1674 uint16_t maccheck:1; 1675 uint16_t class:5; 1676 uint16_t vlan:1; 1677 uint16_t llcsnap:1; 1678 uint16_t noport:1; 1679 uint16_t badip:1; 1680 uint16_t tcamhit:1; 1681 uint16_t tres:2; 1682 uint16_t tzfvld:1; 1683 #elif defined(_BIT_FIELDS_LTOH) 1684 uint16_t tzfvld:1; 1685 uint16_t tres:2; 1686 uint16_t tcamhit:1; 1687 uint16_t badip:1; 1688 uint16_t noport:1; 1689 uint16_t llcsnap:1; 1690 uint16_t vlan:1; 1691 uint16_t class:5; 1692 uint16_t maccheck:1; 1693 uint16_t inputport:2; 1694 #endif 1695 } bits; 1696 } rx_pkt_hdr0_t, *p_rx_pkt_hdr0_t; 1697 1698 1699 /* 1700 * Packet header format 1. 1701 */ 1702 typedef union _rx_pkt_hdr1_b0_t { 1703 uint8_t value; 1704 struct { 1705 #if defined(_BIT_FIELDS_HTOL) 1706 uint8_t hwrsvd:8; 1707 #elif defined(_BIT_FIELDS_LTOH) 1708 uint8_t hwrsvd:8; 1709 #endif 1710 } bits; 1711 } rx_pkt_hdr1_b0_t, *p_rx_pkt_hdr1_b0_t; 1712 1713 typedef union _rx_pkt_hdr1_b1_t { 1714 uint8_t value; 1715 struct { 1716 #if defined(_BIT_FIELDS_HTOL) 1717 uint8_t tcammatch:8; 1718 #elif defined(_BIT_FIELDS_LTOH) 1719 uint8_t tcammatch:8; 1720 #endif 1721 } bits; 1722 } rx_pkt_hdr1_b1_t, *p_rx_pkt_hdr1_b1_t; 1723 1724 typedef union _rx_pkt_hdr1_b2_t { 1725 uint8_t value; 1726 struct { 1727 #if defined(_BIT_FIELDS_HTOL) 1728 uint8_t resv:2; 1729 uint8_t hashhit:1; 1730 uint8_t exact:1; 1731 uint8_t hzfvld:1; 1732 uint8_t hashidx:3; 1733 #elif defined(_BIT_FIELDS_LTOH) 1734 uint8_t hashidx:3; 1735 uint8_t hzfvld:1; 1736 uint8_t exact:1; 1737 uint8_t hashhit:1; 1738 uint8_t resv:2; 1739 #endif 1740 } bits; 1741 } rx_pkt_hdr1_b2_t, *p_rx_pkt_hdr1_b2_t; 1742 1743 typedef union _rx_pkt_hdr1_b3_t { 1744 uint8_t value; 1745 struct { 1746 #if defined(_BIT_FIELDS_HTOL) 1747 uint8_t zc_resv:8; 1748 #elif defined(_BIT_FIELDS_LTOH) 1749 uint8_t zc_resv:8; 1750 #endif 1751 } bits; 1752 } rx_pkt_hdr1_b3_t, *p_rx_pkt_hdr1_b3_t; 1753 1754 typedef union _rx_pkt_hdr1_b4_t { 1755 uint8_t value; 1756 struct { 1757 #if defined(_BIT_FIELDS_HTOL) 1758 uint8_t resv:4; 1759 uint8_t zflowid:4; 1760 #elif defined(_BIT_FIELDS_LTOH) 1761 uint8_t zflowid:4; 1762 uint8_t resv:4; 1763 #endif 1764 } bits; 1765 } rx_pkt_hdr1_b4_t, *p_rx_pkt_hdr1_b4_t; 1766 1767 typedef union _rx_pkt_hdr1_b5_t { 1768 uint8_t value; 1769 struct { 1770 #if defined(_BIT_FIELDS_HTOL) 1771 uint8_t zflowid:8; 1772 #elif defined(_BIT_FIELDS_LTOH) 1773 uint8_t zflowid:8; 1774 #endif 1775 } bits; 1776 } rx_pkt_hdr1_b5_t, *p_rx_pkt_hdr1_b5_t; 1777 1778 typedef union _rx_pkt_hdr1_b6_t { 1779 uint8_t value; 1780 struct { 1781 #if defined(_BIT_FIELDS_HTOL) 1782 uint8_t hashval2:8; 1783 #elif defined(_BIT_FIELDS_LTOH) 1784 uint8_t hashval2:8; 1785 #endif 1786 } bits; 1787 } rx_pkt_hdr1_b6_t, *p_rx_pkt_hdr1_b6_t; 1788 1789 typedef union _rx_pkt_hdr1_b7_t { 1790 uint8_t value; 1791 struct { 1792 #if defined(_BIT_FIELDS_HTOL) 1793 uint8_t hashval2:8; 1794 #elif defined(_BIT_FIELDS_LTOH) 1795 uint8_t hashval2:8; 1796 #endif 1797 } bits; 1798 } rx_pkt_hdr1_b7_t, *p_rx_pkt_hdr1_b7_t; 1799 1800 typedef union _rx_pkt_hdr1_b8_t { 1801 uint8_t value; 1802 struct { 1803 #if defined(_BIT_FIELDS_HTOL) 1804 uint8_t resv:4; 1805 uint8_t h1:4; 1806 #elif defined(_BIT_FIELDS_LTOH) 1807 uint8_t h1:4; 1808 uint8_t resv:4; 1809 #endif 1810 } bits; 1811 } rx_pkt_hdr1_b8_t, *p_rx_pkt_hdr1_b8_t; 1812 1813 typedef union _rx_pkt_hdr1_b9_t { 1814 uint8_t value; 1815 struct { 1816 #if defined(_BIT_FIELDS_HTOL) 1817 uint8_t h1:8; 1818 #elif defined(_BIT_FIELDS_LTOH) 1819 uint8_t h1:8; 1820 #endif 1821 } bits; 1822 } rx_pkt_hdr1_b9_t, *p_rx_pkt_hdr1_b9_t; 1823 1824 typedef union _rx_pkt_hdr1_b10_t { 1825 uint8_t value; 1826 struct { 1827 #if defined(_BIT_FIELDS_HTOL) 1828 uint8_t resv:4; 1829 uint8_t h1:4; 1830 #elif defined(_BIT_FIELDS_LTOH) 1831 uint8_t h1:4; 1832 uint8_t resv:4; 1833 #endif 1834 } bits; 1835 } rx_pkt_hdr1_b10_t, *p_rx_pkt_hdr1_b10_t; 1836 1837 typedef union _rx_pkt_hdr1_b11_b12_t { 1838 uint16_t value; 1839 struct { 1840 #if defined(_BIT_FIELDS_HTOL) 1841 uint16_t h1_1:8; 1842 uint16_t h1_2:8; 1843 #elif defined(_BIT_FIELDS_LTOH) 1844 uint16_t h1_2:8; 1845 uint16_t h1_1:8; 1846 #endif 1847 } bits; 1848 } rx_pkt_hdr1_b11_b12_t, *p_rx_pkt_hdr1_b11_b12_t; 1849 1850 typedef union _rx_pkt_hdr1_b13_t { 1851 uint8_t value; 1852 struct { 1853 #if defined(_BIT_FIELDS_HTOL) 1854 uint8_t usr_data:8; 1855 #elif defined(_BIT_FIELDS_LTOH) 1856 uint8_t usr_data:8; 1857 #endif 1858 } bits; 1859 } rx_pkt_hdr1_b13_t, *p_rx_pkt_hdr1_b13_t; 1860 1861 typedef union _rx_pkt_hdr1_b14_b17_t { 1862 uint32_t value; 1863 struct { 1864 #if defined(_BIT_FIELDS_HTOL) 1865 uint32_t usr_data_1:8; 1866 uint32_t usr_data_2:8; 1867 uint32_t usr_data_3:8; 1868 uint32_t usr_data_4:8; 1869 #elif defined(_BIT_FIELDS_LTOH) 1870 uint32_t usr_data_4:8; 1871 uint32_t usr_data_3:8; 1872 uint32_t usr_data_2:8; 1873 uint32_t usr_data_1:8; 1874 #endif 1875 } bits; 1876 } rx_pkt_hdr1_b14_b17_t, *p_rx_pkt_hdr1_b14_b17_t; 1877 1878 /* Receive packet header 1 format (18 bytes) */ 1879 typedef struct _rx_pkt_hdr_t { 1880 rx_pkt_hdr1_b0_t rx_hdr1_b0; 1881 rx_pkt_hdr1_b1_t rx_hdr1_b1; 1882 rx_pkt_hdr1_b2_t rx_hdr1_b2; 1883 rx_pkt_hdr1_b3_t rx_hdr1_b3; 1884 rx_pkt_hdr1_b4_t rx_hdr1_b4; 1885 rx_pkt_hdr1_b5_t rx_hdr1_b5; 1886 rx_pkt_hdr1_b6_t rx_hdr1_b6; 1887 rx_pkt_hdr1_b7_t rx_hdr1_b7; 1888 rx_pkt_hdr1_b8_t rx_hdr1_b8; 1889 rx_pkt_hdr1_b9_t rx_hdr1_b9; 1890 rx_pkt_hdr1_b10_t rx_hdr1_b10; 1891 rx_pkt_hdr1_b11_b12_t rx_hdr1_b11_b12; 1892 rx_pkt_hdr1_b13_t rx_hdr1_b13; 1893 rx_pkt_hdr1_b14_b17_t rx_hdr1_b14_b17; 1894 } rx_pkt_hdr1_t, *p_rx_pkt_hdr1_t; 1895 1896 1897 #ifdef __cplusplus 1898 } 1899 #endif 1900 1901 #endif /* _SYS_NXGE_NXGE_RXDMA_HW_H */ 1902