1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_RXDMA_HW_H 27 #define _SYS_NXGE_NXGE_RXDMA_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 #include <nxge_hw.h> 35 36 /* 37 * NIU: Receive DMA Channels 38 */ 39 /* Receive DMA Clock Divider */ 40 #define RX_DMA_CK_DIV_REG (FZC_DMC + 0x00000) 41 #define RX_DMA_CK_DIV_SHIFT 0 /* bits 15:0 */ 42 #define RX_DMA_CK_DIV_MASK 0x000000000000FFFFULL 43 44 typedef union _rx_dma_ck_div_t { 45 uint64_t value; 46 struct { 47 #if defined(_BIG_ENDIAN) 48 uint32_t hdw; 49 #endif 50 struct { 51 #if defined(_BIT_FIELDS_HTOL) 52 uint32_t res1_1:16; 53 uint32_t cnt:16; 54 #elif defined(_BIT_FIELDS_LTOH) 55 uint32_t cnt:16; 56 uint32_t res1_1:16; 57 #endif 58 } ldw; 59 #if !defined(_BIG_ENDIAN) 60 uint32_t hdw; 61 #endif 62 } bits; 63 } rx_dma_ck_div_t, *p_rx_dma_ck_div_t; 64 65 66 /* 67 * Default Port Receive DMA Channel (RDC) 68 */ 69 #define DEF_PT_RDC_REG(port) (FZC_DMC + 0x00008 * (port + 1)) 70 #define DEF_PT0_RDC_REG (FZC_DMC + 0x00008) 71 #define DEF_PT1_RDC_REG (FZC_DMC + 0x00010) 72 #define DEF_PT2_RDC_REG (FZC_DMC + 0x00018) 73 #define DEF_PT3_RDC_REG (FZC_DMC + 0x00020) 74 #define DEF_PT_RDC_SHIFT 0 /* bits 4:0 */ 75 #define DEF_PT_RDC_MASK 0x000000000000001FULL 76 77 78 #define RDC_TBL_REG (FZC_ZCP + 0x10000) 79 #define RDC_TBL_SHIFT 0 /* bits 4:0 */ 80 #define RDC_TBL_MASK 0x000000000000001FULL 81 82 /* For the default port RDC and RDC table */ 83 typedef union _def_pt_rdc_t { 84 uint64_t value; 85 struct { 86 #if defined(_BIG_ENDIAN) 87 uint32_t hdw; 88 #endif 89 struct { 90 #if defined(_BIT_FIELDS_HTOL) 91 uint32_t res1_1:27; 92 uint32_t rdc:5; 93 #elif defined(_BIT_FIELDS_LTOH) 94 uint32_t rdc:5; 95 uint32_t res1_1:27; 96 #endif 97 } ldw; 98 #if !defined(_BIG_ENDIAN) 99 uint32_t hdw; 100 #endif 101 } bits; 102 } def_pt_rdc_t, *p_def_pt_rdc_t; 103 104 typedef union _rdc_tbl_t { 105 uint64_t value; 106 struct { 107 #if defined(_BIG_ENDIAN) 108 uint32_t hdw; 109 #endif 110 struct { 111 #if defined(_BIT_FIELDS_HTOL) 112 uint32_t res1_1:28; 113 uint32_t rdc:4; 114 #elif defined(_BIT_FIELDS_LTOH) 115 uint32_t rdc:4; 116 uint32_t res1_1:28; 117 #endif 118 } ldw; 119 #if !defined(_BIG_ENDIAN) 120 uint32_t hdw; 121 #endif 122 } bits; 123 } rdc_tbl_t, *p_rdc_tbl_t; 124 125 /* 126 * RDC: 32 bit Addressing mode 127 */ 128 #define RX_ADDR_MD_REG (FZC_DMC + 0x00070) 129 #define RX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 130 #define RX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 131 #define RX_ADDR_MD_MASK 0x0000000000000001ULL 132 133 typedef union _rx_addr_md_t { 134 uint64_t value; 135 struct { 136 #if defined(_BIG_ENDIAN) 137 uint32_t hdw; 138 #endif 139 struct { 140 #if defined(_BIT_FIELDS_HTOL) 141 uint32_t res1_1:28; 142 uint32_t dbg_pt_mux_sel:2; 143 uint32_t ram_acc:1; 144 uint32_t mode32:1; 145 #elif defined(_BIT_FIELDS_LTOH) 146 uint32_t mode32:1; 147 uint32_t ram_acc:1; 148 uint32_t dbg_pt_mux_sel:2; 149 uint32_t res1_1:28; 150 #endif 151 } ldw; 152 #if !defined(_BIG_ENDIAN) 153 uint32_t hdw; 154 #endif 155 } bits; 156 } rx_addr_md_t, *p_rx_addr_md_t; 157 158 /* 159 * RDC: Port Scheduler 160 */ 161 162 #define PT_DRR_WT_REG(portnm) ((FZC_DMC + 0x00028) + (portnm * 8)) 163 #define PT_DRR_WT0_REG (FZC_DMC + 0x00028) 164 #define PT_DRR_WT1_REG (FZC_DMC + 0x00030) 165 #define PT_DRR_WT2_REG (FZC_DMC + 0x00038) 166 #define PT_DRR_WT3_REG (FZC_DMC + 0x00040) 167 #define PT_DRR_WT_SHIFT 0 168 #define PT_DRR_WT_MASK 0x000000000000FFFFULL /* bits 15:0 */ 169 #define PT_DRR_WT_DEFAULT_10G 0x0400 170 #define PT_DRR_WT_DEFAULT_1G 0x0066 171 typedef union _pt_drr_wt_t { 172 uint64_t value; 173 struct { 174 #if defined(_BIG_ENDIAN) 175 uint32_t hdw; 176 #endif 177 struct { 178 #if defined(_BIT_FIELDS_HTOL) 179 uint32_t res1_1:16; 180 uint32_t wt:16; 181 #elif defined(_BIT_FIELDS_LTOH) 182 uint32_t wt:16; 183 uint32_t res1_1:16; 184 #endif 185 } ldw; 186 #if !defined(_BIG_ENDIAN) 187 uint32_t hdw; 188 #endif 189 } bits; 190 } pt_drr_wt_t, *p_pt_drr_wt_t; 191 192 #define NXGE_RX_DRR_WT_10G 0x400 193 #define NXGE_RX_DRR_WT_1G 0x066 194 195 /* Port FIFO Usage */ 196 #define PT_USE_REG(portnum) ((FZC_DMC + 0x00048) + (portnum * 8)) 197 #define PT_USE0_REG (FZC_DMC + 0x00048) 198 #define PT_USE1_REG (FZC_DMC + 0x00050) 199 #define PT_USE2_REG (FZC_DMC + 0x00058) 200 #define PT_USE3_REG (FZC_DMC + 0x00060) 201 #define PT_USE_SHIFT 0 /* bits 19:0 */ 202 #define PT_USE_MASK 0x00000000000FFFFFULL 203 204 typedef union _pt_use_t { 205 uint64_t value; 206 struct { 207 #if defined(_BIG_ENDIAN) 208 uint32_t hdw; 209 #endif 210 struct { 211 #if defined(_BIT_FIELDS_HTOL) 212 uint32_t res1_1:12; 213 uint32_t cnt:20; 214 #elif defined(_BIT_FIELDS_LTOH) 215 uint32_t cnt:20; 216 uint32_t res1_1:12; 217 #endif 218 } ldw; 219 #if !defined(_BIG_ENDIAN) 220 uint32_t hdw; 221 #endif 222 } bits; 223 } pt_use_t, *p_pt_use_t; 224 225 /* 226 * RDC: Partitioning Support 227 * (Each of the following registers is for each RDC) 228 * Please refer to nxge_hw.h for the common logical 229 * page configuration register definitions. 230 */ 231 #define RX_LOG_REG_SIZE 0x40 232 #define RX_LOG_DMA_OFFSET(channel) (channel * RX_LOG_REG_SIZE) 233 234 #define RX_LOG_PAGE_VLD_REG (FZC_DMC + 0x20000) 235 #define RX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x20008) 236 #define RX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x20010) 237 #define RX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x20018) 238 #define RX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x20020) 239 #define RX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x20028) 240 #define RX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x20030) 241 #define RX_LOG_PAGE_HDL_REG (FZC_DMC + 0x20038) 242 243 /* RX and TX have the same definitions */ 244 #define RX_LOG_PAGE1_VLD_SHIFT 1 /* bit 1 */ 245 #define RX_LOG_PAGE0_VLD_SHIFT 0 /* bit 0 */ 246 #define RX_LOG_PAGE1_VLD 0x0000000000000002ULL 247 #define RX_LOG_PAGE0_VLD 0x0000000000000001ULL 248 #define RX_LOG_PAGE1_VLD_MASK 0x0000000000000002ULL 249 #define RX_LOG_PAGE0_VLD_MASK 0x0000000000000001ULL 250 #define RX_LOG_FUNC_VLD_SHIFT 2 /* bit 3:2 */ 251 #define RX_LOG_FUNC_VLD_MASK 0x000000000000000CULL 252 253 #define LOG_PAGE_ADDR_SHIFT 12 /* bits[43:12] --> bits[31:0] */ 254 255 /* RDC: Weighted Random Early Discard */ 256 #define RED_RAN_INIT_REG (FZC_DMC + 0x00068) 257 258 #define RED_RAN_INIT_SHIFT 0 /* bits 15:0 */ 259 #define RED_RAN_INIT_MASK 0x000000000000ffffULL 260 261 /* Weighted Random */ 262 typedef union _red_ran_init_t { 263 uint64_t value; 264 struct { 265 #if defined(_BIG_ENDIAN) 266 uint32_t hdw; 267 #endif 268 struct { 269 #if defined(_BIT_FIELDS_HTOL) 270 uint32_t res1_1:15; 271 uint32_t enable:1; 272 uint32_t init:16; 273 #elif defined(_BIT_FIELDS_LTOH) 274 uint32_t init:16; 275 uint32_t enable:1; 276 uint32_t res1_1:15; 277 #endif 278 } ldw; 279 #if !defined(_BIG_ENDIAN) 280 uint32_t hdw; 281 #endif 282 } bits; 283 } red_ran_init_t, *p_red_ran_init_t; 284 285 /* 286 * Buffer block descriptor 287 */ 288 typedef struct _rx_desc_t { 289 uint32_t block_addr; 290 } rx_desc_t, *p_rx_desc_t; 291 292 /* 293 * RDC: RED Parameter 294 * (Each DMC has one RED register) 295 */ 296 #define RDC_RED_CHANNEL_SIZE (0x40) 297 #define RDC_RED_CHANNEL_OFFSET(channel) (channel * RDC_RED_CHANNEL_SIZE) 298 299 #define RDC_RED_PARA_REG (FZC_DMC + 0x30000) 300 #define RDC_RED_RDC_PARA_REG(rdc) \ 301 (RDC_RED_PARA_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 302 303 /* the layout of this register is rx_disc_cnt_t */ 304 #define RDC_RED_DISC_CNT_REG (FZC_DMC + 0x30008) 305 #define RDC_RED_RDC_DISC_REG(rdc) \ 306 (RDC_RED_DISC_CNT_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 307 308 309 #define RDC_RED_PARA1_RBR_SCL_SHIFT 0 /* bits 2:0 */ 310 #define RDC_RED_PARA1_RBR_SCL_MASK 0x0000000000000007ULL 311 #define RDC_RED_PARA1_ENB_SHIFT 3 /* bit 3 */ 312 #define RDC_RED_PARA1_ENB 0x0000000000000008ULL 313 #define RDC_RED_PARA1_ENB_MASK 0x0000000000000008ULL 314 315 #define RDC_RED_PARA_WIN_SHIFT 0 /* bits 3:0 */ 316 #define RDC_RED_PARA_WIN_MASK 0x000000000000000fULL 317 #define RDC_RED_PARA_THRE_SHIFT 4 /* bits 15:4 */ 318 #define RDC_RED_PARA_THRE_MASK 0x00000000000000f0ULL 319 #define RDC_RED_PARA_WIN_SYN_SHIFT 16 /* bits 19:16 */ 320 #define RDC_RED_PARA_WIN_SYN_MASK 0x00000000000000f0ULL 321 #define RDC_RED_PARA_THRE_SYN_SHIFT 20 /* bits 31:20 */ 322 #define RDC_RED_PARA_THRE_SYN_MASK 0x00000000000fff00ULL 323 324 /* RDC: RED parameters */ 325 typedef union _rdc_red_para_t { 326 uint64_t value; 327 struct { 328 #if defined(_BIG_ENDIAN) 329 uint32_t hdw; 330 #endif 331 struct { 332 #if defined(_BIT_FIELDS_HTOL) 333 uint32_t thre_sync:12; 334 uint32_t win_syn:4; 335 uint32_t thre:12; 336 uint32_t win:4; 337 #elif defined(_BIT_FIELDS_LTOH) 338 uint32_t win:4; 339 uint32_t thre:12; 340 uint32_t win_syn:4; 341 uint32_t thre_sync:12; 342 #endif 343 } ldw; 344 #if !defined(_BIG_ENDIAN) 345 uint32_t hdw; 346 #endif 347 } bits; 348 } rdc_red_para_t, *p_rdc_red_para_t; 349 350 /* 351 * RDC: Receive DMA Datapath Configuration 352 * The following register definitions are for 353 * each DMA channel. Each DMA CSR is 512 bytes 354 * (0x200). 355 */ 356 #define RXDMA_CFIG1_REG (DMC + 0x00000) 357 #define RXDMA_CFIG2_REG (DMC + 0x00008) 358 359 #define RXDMA_CFIG1_MBADDR_H_SHIFT 0 /* bits 11:0 */ 360 #define RXDMA_CFIG1_MBADDR_H_MASK 0x0000000000000fc0ULL 361 #define RXDMA_CFIG1_RST_SHIFT 30 /* bit 30 */ 362 #define RXDMA_CFIG1_RST 0x0000000040000000ULL 363 #define RXDMA_CFIG1_RST_MASK 0x0000000040000000ULL 364 #define RXDMA_CFIG1_EN_SHIFT 31 365 #define RXDMA_CFIG1_EN 0x0000000080000000ULL 366 #define RXDMA_CFIG1_EN_MASK 0x0000000080000000ULL 367 368 typedef union _rxdma_cfig1_t { 369 uint64_t value; 370 struct { 371 #if defined(_BIG_ENDIAN) 372 uint32_t hdw; 373 #endif 374 struct { 375 #if defined(_BIT_FIELDS_HTOL) 376 uint32_t en:1; 377 uint32_t rst:1; 378 uint32_t qst:1; 379 uint32_t res2:17; 380 uint32_t mbaddr_h:12; 381 #elif defined(_BIT_FIELDS_LTOH) 382 uint32_t mbaddr_h:12; 383 uint32_t res2:17; 384 uint32_t qst:1; 385 uint32_t rst:1; 386 uint32_t en:1; 387 #endif 388 } ldw; 389 #if !defined(_BIG_ENDIAN) 390 uint32_t hdw; 391 #endif 392 } bits; 393 } rxdma_cfig1_t, *p_rxdma_cfig1_t; 394 395 #define RXDMA_HDR_SIZE_DEFAULT 2 396 #define RXDMA_HDR_SIZE_FULL 18 397 398 #define RXDMA_CFIG2_FULL_HDR_SHIFT 0 /* Set to 1 */ 399 #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL 400 #define RXDMA_CFIG2_FULL_HDR_MASK 0x0000000000000001ULL 401 #define RXDMA_CFIG2_OFFSET_SHIFT 1 /* bit 3:1 */ 402 #define RXDMA_CFIG2_OFFSET_MASK 0x000000004000000eULL 403 #define RXDMA_CFIG2_MBADDR_L_SHIFT 6 /* bit 31:6 */ 404 #define RXDMA_CFIG2_MBADDR_L_MASK 0x00000000ffffffc0ULL 405 406 typedef union _rxdma_cfig2_t { 407 uint64_t value; 408 struct { 409 #if defined(_BIG_ENDIAN) 410 uint32_t hdw; 411 #endif 412 struct { 413 #if defined(_BIT_FIELDS_HTOL) 414 uint32_t mbaddr:26; 415 uint32_t res2:3; 416 uint32_t offset:2; 417 uint32_t full_hdr:1; 418 419 #elif defined(_BIT_FIELDS_LTOH) 420 uint32_t full_hdr:1; 421 uint32_t offset:2; 422 uint32_t res2:3; 423 uint32_t mbaddr:26; 424 #endif 425 } ldw; 426 #if !defined(_BIG_ENDIAN) 427 uint32_t hdw; 428 #endif 429 } bits; 430 } rxdma_cfig2_t, *p_rxdma_cfig2_t; 431 432 /* 433 * RDC: Receive Block Ring Configuration 434 * The following register definitions are for 435 * each DMA channel. 436 */ 437 #define RBR_CFIG_A_REG (DMC + 0x00010) 438 #define RBR_CFIG_B_REG (DMC + 0x00018) 439 #define RBR_KICK_REG (DMC + 0x00020) 440 #define RBR_STAT_REG (DMC + 0x00028) 441 #define RBR_HDH_REG (DMC + 0x00030) 442 #define RBR_HDL_REG (DMC + 0x00038) 443 444 #define RBR_CFIG_A_STADDR_SHIFT 6 /* bits 17:6 */ 445 #define RBR_CFIG_A_STDADDR_MASK 0x000000000003ffc0ULL 446 #define RBR_CFIG_A_STADDR_BASE_SHIFT 18 /* bits 43:18 */ 447 #define RBR_CFIG_A_STDADDR_BASE_MASK 0x00000ffffffc0000ULL 448 #define RBR_CFIG_A_LEN_SHIFT 48 /* bits 63:48 */ 449 #define RBR_CFIG_A_LEN_MASK 0xFFFF000000000000ULL 450 451 typedef union _rbr_cfig_a_t { 452 uint64_t value; 453 struct { 454 #if defined(_BIG_ENDIAN) 455 struct { 456 #if defined(_BIT_FIELDS_HTOL) 457 uint32_t len:16; 458 uint32_t res1:4; 459 uint32_t staddr_base:12; 460 #elif defined(_BIT_FIELDS_LTOH) 461 uint32_t staddr_base:12; 462 uint32_t res1:4; 463 uint32_t len:16; 464 #endif 465 } hdw; 466 #endif 467 struct { 468 #if defined(_BIT_FIELDS_HTOL) 469 uint32_t staddr_base:14; 470 uint32_t staddr:12; 471 uint32_t res2:6; 472 #elif defined(_BIT_FIELDS_LTOH) 473 uint32_t res2:6; 474 uint32_t staddr:12; 475 uint32_t staddr_base:14; 476 #endif 477 } ldw; 478 #if !defined(_BIG_ENDIAN) 479 struct { 480 #if defined(_BIT_FIELDS_HTOL) 481 uint32_t len:16; 482 uint32_t res1:4; 483 uint32_t staddr_base:12; 484 #elif defined(_BIT_FIELDS_LTOH) 485 uint32_t staddr_base:12; 486 uint32_t res1:4; 487 uint32_t len:16; 488 #endif 489 } hdw; 490 #endif 491 } bits; 492 } rbr_cfig_a_t, *p_rbr_cfig_a_t; 493 494 495 #define RBR_CFIG_B_BUFSZ0_SHIFT 0 /* bit 1:0 */ 496 #define RBR_CFIG_B_BUFSZ0_MASK 0x0000000000000001ULL 497 #define RBR_CFIG_B_VLD0_SHIFT 7 /* bit 7 */ 498 #define RBR_CFIG_B_VLD0 0x0000000000000008ULL 499 #define RBR_CFIG_B_VLD0_MASK 0x0000000000000008ULL 500 #define RBR_CFIG_B_BUFSZ1_SHIFT 8 /* bit 9:8 */ 501 #define RBR_CFIG_B_BUFSZ1_MASK 0x0000000000000300ULL 502 #define RBR_CFIG_B_VLD1_SHIFT 15 /* bit 15 */ 503 #define RBR_CFIG_B_VLD1 0x0000000000008000ULL 504 #define RBR_CFIG_B_VLD1_MASK 0x0000000000008000ULL 505 #define RBR_CFIG_B_BUFSZ2_SHIFT 16 /* bit 17:16 */ 506 #define RBR_CFIG_B_BUFSZ2_MASK 0x0000000000030000ULL 507 #define RBR_CFIG_B_VLD2_SHIFT 23 /* bit 23 */ 508 #define RBR_CFIG_B_VLD2 0x0000000000800000ULL 509 #define RBR_CFIG_B_BKSIZE_SHIFT 24 /* bit 25:24 */ 510 #define RBR_CFIG_B_BKSIZE_MASK 0x0000000003000000ULL 511 512 513 typedef union _rbr_cfig_b_t { 514 uint64_t value; 515 struct { 516 #if defined(_BIG_ENDIAN) 517 uint32_t hdw; 518 #endif 519 struct { 520 #if defined(_BIT_FIELDS_HTOL) 521 uint32_t res1_1:6; 522 uint32_t bksize:2; 523 uint32_t vld2:1; 524 uint32_t res2:5; 525 uint32_t bufsz2:2; 526 uint32_t vld1:1; 527 uint32_t res3:5; 528 uint32_t bufsz1:2; 529 uint32_t vld0:1; 530 uint32_t res4:5; 531 uint32_t bufsz0:2; 532 #elif defined(_BIT_FIELDS_LTOH) 533 uint32_t bufsz0:2; 534 uint32_t res4:5; 535 uint32_t vld0:1; 536 uint32_t bufsz1:2; 537 uint32_t res3:5; 538 uint32_t vld1:1; 539 uint32_t bufsz2:2; 540 uint32_t res2:5; 541 uint32_t vld2:1; 542 uint32_t bksize:2; 543 uint32_t res1_1:6; 544 #endif 545 } ldw; 546 #if !defined(_BIG_ENDIAN) 547 uint32_t hdw; 548 #endif 549 } bits; 550 } rbr_cfig_b_t, *p_rbr_cfig_b_t; 551 552 553 #define RBR_KICK_SHIFT 0 /* bit 15:0 */ 554 #define RBR_KICK_MASK 0x00000000000ffff1ULL 555 556 557 typedef union _rbr_kick_t { 558 uint64_t value; 559 struct { 560 #if defined(_BIG_ENDIAN) 561 uint32_t hdw; 562 #endif 563 struct { 564 #if defined(_BIT_FIELDS_HTOL) 565 uint32_t res1_1:16; 566 uint32_t bkadd:16; 567 #elif defined(_BIT_FIELDS_LTOH) 568 uint32_t bkadd:16; 569 uint32_t res1_1:16; 570 #endif 571 } ldw; 572 #if !defined(_BIG_ENDIAN) 573 uint32_t hdw; 574 #endif 575 } bits; 576 } rbr_kick_t, *p_rbr_kick_t; 577 578 #define RBR_STAT_QLEN_SHIFT 0 /* bit bit 15:0 */ 579 #define RBR_STAT_QLEN_MASK 0x000000000000ffffULL 580 #define RBR_STAT_OFLOW_SHIFT 16 /* bit 16 */ 581 #define RBR_STAT_OFLOW 0x0000000000010000ULL 582 #define RBR_STAT_OFLOW_MASK 0x0000000000010000ULL 583 584 typedef union _rbr_stat_t { 585 uint64_t value; 586 struct { 587 #if defined(_BIG_ENDIAN) 588 uint32_t hdw; 589 #endif 590 struct { 591 #if defined(_BIT_FIELDS_HTOL) 592 uint32_t res1_1:15; 593 uint32_t oflow:1; 594 uint32_t qlen:16; 595 #elif defined(_BIT_FIELDS_LTOH) 596 uint32_t qlen:16; 597 uint32_t oflow:1; 598 uint32_t res1_1:15; 599 #endif 600 } ldw; 601 #if !defined(_BIG_ENDIAN) 602 uint32_t hdw; 603 #endif 604 } bits; 605 } rbr_stat_t, *p_rbr_stat_t; 606 607 608 #define RBR_HDH_HEAD_H_SHIFT 0 /* bit 11:0 */ 609 #define RBR_HDH_HEAD_H_MASK 0x0000000000000fffULL 610 typedef union _rbr_hdh_t { 611 uint64_t value; 612 struct { 613 #if defined(_BIG_ENDIAN) 614 uint32_t hdw; 615 #endif 616 struct { 617 #if defined(_BIT_FIELDS_HTOL) 618 uint32_t res1_1:20; 619 uint32_t head_h:12; 620 #elif defined(_BIT_FIELDS_LTOH) 621 uint32_t head_h:12; 622 uint32_t res1_1:20; 623 #endif 624 } ldw; 625 #if !defined(_BIG_ENDIAN) 626 uint32_t hdw; 627 #endif 628 } bits; 629 } rbr_hdh_t, *p_rbr_hdh_t; 630 631 #define RBR_HDL_HEAD_L_SHIFT 2 /* bit 31:2 */ 632 #define RBR_HDL_HEAD_L_MASK 0x00000000FFFFFFFCULL 633 634 typedef union _rbr_hdl_t { 635 uint64_t value; 636 struct { 637 #if defined(_BIG_ENDIAN) 638 uint32_t hdw; 639 #endif 640 struct { 641 #if defined(_BIT_FIELDS_HTOL) 642 uint32_t head_l:30; 643 uint32_t res2:2; 644 #elif defined(_BIT_FIELDS_LTOH) 645 uint32_t res2:2; 646 uint32_t head_l:30; 647 #endif 648 } ldw; 649 #if !defined(_BIG_ENDIAN) 650 uint32_t hdw; 651 #endif 652 } bits; 653 } rbr_hdl_t, *p_rbr_hdl_t; 654 655 /* 656 * Receive Completion Ring (RCR) 657 */ 658 #define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */ 659 #define RCR_PKT_BUF_ADDR_SHIFT_FULL 6 /* fulll buffer address */ 660 #define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL 661 #define RCR_PKTBUFSZ_SHIFT 38 /* bit 39:38 */ 662 #define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL 663 #define RCR_L2_LEN_SHIFT 40 /* bit 39:38 */ 664 #define RCR_L2_LEN_MASK 0x003fff0000000000ULL 665 #define RCR_DCF_ERROR_SHIFT 54 /* bit 54 */ 666 #define RCR_DCF_ERROR_MASK 0x0040000000000000ULL 667 #define RCR_ERROR_SHIFT 55 /* bit 57:55 */ 668 #define RCR_ERROR_MASK 0x0380000000000000ULL 669 #define RCR_PROMIS_SHIFT 58 /* bit 58 */ 670 #define RCR_PROMIS_MASK 0x0400000000000000ULL 671 #define RCR_FRAG_SHIFT 59 /* bit 59 */ 672 #define RCR_FRAG_MASK 0x0800000000000000ULL 673 #define RCR_ZERO_COPY_SHIFT 60 /* bit 60 */ 674 #define RCR_ZERO_COPY_MASK 0x1000000000000000ULL 675 #define RCR_PKT_TYPE_SHIFT 61 /* bit 62:61 */ 676 #define RCR_PKT_TYPE_MASK 0x6000000000000000ULL 677 #define RCR_MULTI_SHIFT 63 /* bit 63 */ 678 #define RCR_MULTI_MASK 0x8000000000000000ULL 679 680 #define RCR_PKTBUFSZ_0 0x00 681 #define RCR_PKTBUFSZ_1 0x01 682 #define RCR_PKTBUFSZ_2 0x02 683 #define RCR_SINGLE_BLOCK 0x03 684 #define RCR_N_PKTBUF_SZ 0x04 685 686 #define RCR_NO_ERROR 0x0 687 #define RCR_L2_ERROR 0x1 688 #define RCR_L4_CSUM_ERROR 0x3 689 #define RCR_FFLP_SOFT_ERROR 0x4 690 #define RCR_ZCP_SOFT_ERROR 0x5 691 #define RCR_ERROR_RESERVE 0x6 692 #define RCR_ERROR_RESERVE_END 0x7 693 694 #define RCR_PKT_TYPE_UDP 0x1 695 #define RCR_PKT_TYPE_TCP 0x2 696 #define RCR_PKT_TYPE_SCTP 0x3 697 #define RCR_PKT_TYPE_OTHERS 0x0 698 #define RCR_PKT_IS_TCP 0x2000000000000000ULL 699 #define RCR_PKT_IS_UDP 0x4000000000000000ULL 700 #define RCR_PKT_IS_SCTP 0x6000000000000000ULL 701 702 703 typedef union _rcr_entry_t { 704 uint64_t value; 705 struct { 706 #if defined(_BIG_ENDIAN) 707 struct { 708 #if defined(_BIT_FIELDS_HTOL) 709 uint32_t multi:1; 710 uint32_t pkt_type:2; 711 uint32_t zero_copy:1; 712 uint32_t noport:1; 713 uint32_t promis:1; 714 uint32_t error:3; 715 uint32_t dcf_err:1; 716 uint32_t l2_len:14; 717 uint32_t pktbufsz:2; 718 uint32_t pkt_buf_addr:6; 719 #elif defined(_BIT_FIELDS_LTOH) 720 uint32_t pkt_buf_addr:6; 721 uint32_t pktbufsz:2; 722 uint32_t l2_len:14; 723 uint32_t dcf_err:1; 724 uint32_t error:3; 725 uint32_t promis:1; 726 uint32_t noport:1; 727 uint32_t zero_copy:1; 728 uint32_t pkt_type:2; 729 uint32_t multi:1; 730 #endif 731 } hdw; 732 #endif 733 struct { 734 #if defined(_BIT_FIELDS_HTOL) 735 uint32_t pkt_buf_addr:32; 736 #elif defined(_BIT_FIELDS_LTOH) 737 uint32_t pkt_buf_addr:32; 738 #endif 739 } ldw; 740 #if !defined(_BIG_ENDIAN) 741 struct { 742 #if defined(_BIT_FIELDS_HTOL) 743 uint32_t multi:1; 744 uint32_t pkt_type:2; 745 uint32_t zero_copy:1; 746 uint32_t noport:1; 747 uint32_t promis:1; 748 uint32_t error:3; 749 uint32_t dcf_err:1; 750 uint32_t l2_len:14; 751 uint32_t pktbufsz:2; 752 uint32_t pkt_buf_addr:6; 753 #elif defined(_BIT_FIELDS_LTOH) 754 uint32_t pkt_buf_addr:6; 755 uint32_t pktbufsz:2; 756 uint32_t l2_len:14; 757 uint32_t dcf_err:1; 758 uint32_t error:3; 759 uint32_t promis:1; 760 uint32_t noport:1; 761 uint32_t zero_copy:1; 762 uint32_t pkt_type:2; 763 uint32_t multi:1; 764 #endif 765 } hdw; 766 #endif 767 } bits; 768 } rcr_entry_t, *p_rcr_entry_t; 769 770 /* 771 * Receive Completion Ring Configuration. 772 * (for each DMA channel) 773 */ 774 #define RCRCFIG_A_REG (DMC + 0x00040) 775 #define RCRCFIG_B_REG (DMC + 0x00048) 776 #define RCRSTAT_A_REG (DMC + 0x00050) 777 #define RCRSTAT_B_REG (DMC + 0x00058) 778 #define RCRSTAT_C_REG (DMC + 0x00060) 779 #define RX_DMA_ENT_MSK_REG (DMC + 0x00068) 780 #define RX_DMA_CTL_STAT_REG (DMC + 0x00070) 781 #define RCR_FLSH_REG (DMC + 0x00078) 782 #if OLD 783 #define RX_DMA_LOGA_REG (DMC + 0x00080) 784 #define RX_DMA_LOGB_REG (DMC + 0x00088) 785 #endif 786 #define RX_DMA_CTL_STAT_DBG_REG (DMC + 0x00098) 787 788 /* (DMC + 0x00050) */ 789 #define RCRCFIG_A_STADDR_SHIFT 6 /* bit 18:6 */ 790 #define RCRCFIG_A_STADDR_MASK 0x000000000007FFC0ULL 791 #define RCRCFIG_A_STADDR_BASE_SHIF 19 /* bit 43:19 */ 792 #define RCRCFIG_A_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 793 #define RCRCFIG_A_LEN_SHIF 48 /* bit 63:48 */ 794 #define RCRCFIG_A_LEN__MASK 0xFFFF000000000000ULL 795 796 /* (DMC + 0x00058) */ 797 #define RCRCFIG_B_TIMEOUT_SHIFT 0 /* bit 5:0 */ 798 #define RCRCFIG_B_TIMEOUT_MASK 0x000000000000003FULL 799 #define RCRCFIG_B_ENTOUT_SHIFT 15 /* bit 15 */ 800 #define RCRCFIG_B_TIMEOUT 0x0000000000008000ULL 801 #define RCRCFIG_B_PTHRES_SHIFT 16 /* bit 31:16 */ 802 #define RCRCFIG_B_PTHRES_MASK 0x00000000FFFF0000ULL 803 804 /* (DMC + 0x00060) */ 805 #define RCRSTAT_A_QLEN_SHIFT 0 /* bit 15:0 */ 806 #define RCRSTAT_A_QLEN_MASK 0x000000000000FFFFULL 807 #define RCRSTAT_A_PKT_OFL_SHIFT 16 /* bit 16 */ 808 #define RCRSTAT_A_PKT_OFL_MASK 0x0000000000010000ULL 809 #define RCRSTAT_A_ENT_OFL_SHIFT 17 /* bit 17 */ 810 #define RCRSTAT_A_ENT_QFL_MASK 0x0000000000020000ULL 811 812 #define RCRSTAT_C_TLPTR_H_SHIFT 0 /* bit 11:0 */ 813 #define RCRSTAT_C_TLPTR_H_MASK 0x0000000000000FFFULL 814 815 #define RCRSTAT_D_TLPTR_L_SHIFT 3 /* bit 31:3 */ 816 #define RCRSTAT_D_TLPTR_L_MASK 0x00000000FFFFFFF8ULL 817 818 /* Receive DMA Interrupt Behavior: Event Mask (DMC + 0x00068) */ 819 #define RX_DMA_ENT_MSK_CFIGLOGPGE_SHIFT 0 /* bit 0: 0 to flag */ 820 #define RX_DMA_ENT_MSK_CFIGLOGPGE_MASK 0x0000000000000001ULL 821 #define RX_DMA_ENT_MSK_RBRLOGPGE_SHIFT 1 /* bit 1: 0 to flag */ 822 #define RX_DMA_ENT_MSK_RBRLOGPGE_MASK 0x0000000000000002ULL 823 #define RX_DMA_ENT_MSK_RBRFULL_SHIFT 2 /* bit 2: 0 to flag */ 824 #define RX_DMA_ENT_MSK_RBRFULL_MASK 0x0000000000000004ULL 825 #define RX_DMA_ENT_MSK_RBREMPTY_SHIFT 3 /* bit 3: 0 to flag */ 826 #define RX_DMA_ENT_MSK_RBREMPTY_MASK 0x0000000000000008ULL 827 #define RX_DMA_ENT_MSK_RCRFULL_SHIFT 4 /* bit 4: 0 to flag */ 828 #define RX_DMA_ENT_MSK_RCRFULL_MASK 0x0000000000000010ULL 829 #define RX_DMA_ENT_MSK_RCRINCON_SHIFT 5 /* bit 5: 0 to flag */ 830 #define RX_DMA_ENT_MSK_RCRINCON_MASK 0x0000000000000020ULL 831 #define RX_DMA_ENT_MSK_CONFIG_ERR_SHIFT 6 /* bit 6: 0 to flag */ 832 #define RX_DMA_ENT_MSK_CONFIG_ERR_MASK 0x0000000000000040ULL 833 #define RX_DMA_ENT_MSK_RCRSH_FULL_SHIFT 7 /* bit 7: 0 to flag */ 834 #define RX_DMA_ENT_MSK_RCRSH_FULL_MASK 0x0000000000000080ULL 835 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_SHIFT 8 /* bit 8: 0 to flag */ 836 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK 0x0000000000000100ULL 837 #define RX_DMA_ENT_MSK_WRED_DROP_SHIFT 9 /* bit 9: 0 to flag */ 838 #define RX_DMA_ENT_MSK_WRED_DROP_MASK 0x0000000000000200ULL 839 #define RX_DMA_ENT_MSK_PTDROP_PKT_SHIFT 10 /* bit 10: 0 to flag */ 840 #define RX_DMA_ENT_MSK_PTDROP_PKT_MASK 0x0000000000000400ULL 841 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_SHIFT 11 /* bit 11: 0 to flag */ 842 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK 0x0000000000000800ULL 843 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_SHIFT 12 /* bit 12: 0 to flag */ 844 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK 0x0000000000001000ULL 845 #define RX_DMA_ENT_MSK_RCRTO_SHIFT 13 /* bit 13: 0 to flag */ 846 #define RX_DMA_ENT_MSK_RCRTO_MASK 0x0000000000002000ULL 847 #define RX_DMA_ENT_MSK_THRES_SHIFT 14 /* bit 14: 0 to flag */ 848 #define RX_DMA_ENT_MSK_THRES_MASK 0x0000000000004000ULL 849 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_SHIFT 16 /* bit 16: 0 to flag */ 850 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK 0x0000000000010000ULL 851 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_SHIFT 17 /* bit 17: 0 to flag */ 852 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK 0x0000000000020000ULL 853 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_SHIFT 18 /* bit 18: 0 to flag */ 854 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK 0x0000000000040000ULL 855 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_SHIFT 19 /* bit 19: 0 to flag */ 856 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK 0x0000000000080000ULL 857 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_SHIFT 20 /* bit 20: 0 to flag */ 858 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK 0x0000000000100000ULL 859 #define RX_DMA_ENT_MSK_RBR_TMOUT_SHIFT 21 /* bit 21: 0 to flag */ 860 #define RX_DMA_ENT_MSK_RBR_TMOUT_MASK 0x0000000000200000ULL 861 #define RX_DMA_ENT_MSK_ALL (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | \ 862 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | \ 863 RX_DMA_ENT_MSK_RBRFULL_MASK | \ 864 RX_DMA_ENT_MSK_RBREMPTY_MASK | \ 865 RX_DMA_ENT_MSK_RCRFULL_MASK | \ 866 RX_DMA_ENT_MSK_RCRINCON_MASK | \ 867 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | \ 868 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | \ 869 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | \ 870 RX_DMA_ENT_MSK_WRED_DROP_MASK | \ 871 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 872 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 873 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | \ 874 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | \ 875 RX_DMA_ENT_MSK_RCRTO_MASK | \ 876 RX_DMA_ENT_MSK_THRES_MASK | \ 877 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | \ 878 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | \ 879 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | \ 880 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | \ 881 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | \ 882 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 883 884 /* Receive DMA Control and Status (DMC + 0x00070) */ 885 #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */ 886 #define RX_DMA_CTL_STAT_PKTREAD_MASK 0x000000000000ffffULL 887 #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16 /* WO, bit 31:16 */ 888 #define RX_DMA_CTL_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL 889 #define RX_DMA_CTL_STAT_CFIGLOGPG_SHIFT 32 /* RO, bit 32 */ 890 #define RX_DMA_CTL_STAT_CFIGLOGPG 0x0000000100000000ULL 891 #define RX_DMA_CTL_STAT_CFIGLOGPG_MASK 0x0000000100000000ULL 892 #define RX_DMA_CTL_STAT_RBRLOGPG_SHIFT 33 /* RO, bit 33 */ 893 #define RX_DMA_CTL_STAT_RBRLOGPG 0x0000000200000000ULL 894 #define RX_DMA_CTL_STAT_RBRLOGPG_MASK 0x0000000200000000ULL 895 #define RX_DMA_CTL_STAT_RBRFULL_SHIFT 34 /* RO, bit 34 */ 896 #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL 897 #define RX_DMA_CTL_STAT_RBRFULL_MASK 0x0000000400000000ULL 898 #define RX_DMA_CTL_STAT_RBREMPTY_SHIFT 35 /* RW1C, bit 35 */ 899 #define RX_DMA_CTL_STAT_RBREMPTY 0x0000000800000000ULL 900 #define RX_DMA_CTL_STAT_RBREMPTY_MASK 0x0000000800000000ULL 901 #define RX_DMA_CTL_STAT_RCRFULL_SHIFT 36 /* RW1C, bit 36 */ 902 #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL 903 #define RX_DMA_CTL_STAT_RCRFULL_MASK 0x0000001000000000ULL 904 #define RX_DMA_CTL_STAT_RCRINCON_SHIFT 37 /* RO, bit 37 */ 905 #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL 906 #define RX_DMA_CTL_STAT_RCRINCON_MASK 0x0000002000000000ULL 907 #define RX_DMA_CTL_STAT_CONFIG_ERR_SHIFT 38 /* RO, bit 38 */ 908 #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL 909 #define RX_DMA_CTL_STAT_CONFIG_ERR_MASK 0x0000004000000000ULL 910 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_SHIFT 39 /* RO, bit 39 */ 911 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL 0x0000008000000000ULL 912 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL 913 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 914 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_SHIFT 40 /* RO, bit 40 */ 915 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL 916 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 917 #define RX_DMA_CTL_STAT_WRED_DROP_SHIFT 41 /* RO, bit 41 */ 918 #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL 919 #define RX_DMA_CTL_STAT_WRED_DROP_MASK 0x0000020000000000ULL 920 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_SHIFT 42 /* RO, bit 42 */ 921 #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL 922 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_MASK 0x0000040000000000ULL 923 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_SHIFT 43 /* RO, bit 43 */ 924 #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL 925 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL 926 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_SHIFT 44 /* RO, bit 44 */ 927 #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL 928 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL 929 #define RX_DMA_CTL_STAT_RCRTO_SHIFT 45 /* RW1C, bit 45 */ 930 #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL 931 #define RX_DMA_CTL_STAT_RCRTO_MASK 0x0000200000000000ULL 932 #define RX_DMA_CTL_STAT_RCRTHRES_SHIFT 46 /* RO, bit 46 */ 933 #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL 934 #define RX_DMA_CTL_STAT_RCRTHRES_MASK 0x0000400000000000ULL 935 #define RX_DMA_CTL_STAT_MEX_SHIFT 47 /* RW, bit 47 */ 936 #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL 937 #define RX_DMA_CTL_STAT_MEX_MASK 0x0000800000000000ULL 938 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_SHIFT 48 /* RW1C, bit 48 */ 939 #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL 940 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_MASK 0x0001000000000000ULL 941 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_SHIFT 49 /* RO, bit 49 */ 942 #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL 943 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_MASK 0x0002000000000000ULL 944 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_SHIFT 50 /* RO, bit 50 */ 945 #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL 946 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_MASK 0x0004000000000000ULL 947 948 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_SHIFT 51 /* RO, bit 51 */ 949 #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL 950 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_MASK 0x0008000000000000ULL 951 952 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_SHIFT 52 /* RO, bit 52 */ 953 #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL 954 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_MASK 0x0010000000000000ULL 955 956 #define RX_DMA_CTL_STAT_RBR_TMOUT_SHIFT 53 /* RO, bit 53 */ 957 #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL 958 #define RX_DMA_CTL_STAT_RBR_TMOUT_MASK 0x0020000000000000ULL 959 #define RX_DMA_CTRL_STAT_ENT_MASK_SHIFT 32 960 #define RX_DMA_CTL_STAT_ERROR (RX_DMA_ENT_MSK_ALL << \ 961 RX_DMA_CTRL_STAT_ENT_MASK_SHIFT) 962 963 /* the following are write 1 to clear bits */ 964 #define RX_DMA_CTL_STAT_WR1C RX_DMA_CTL_STAT_RBREMPTY | \ 965 RX_DMA_CTL_STAT_RCR_SHDW_FULL | \ 966 RX_DMA_CTL_STAT_RBR_PRE_EMTY | \ 967 RX_DMA_CTL_STAT_WRED_DROP | \ 968 RX_DMA_CTL_STAT_PORT_DROP_PKT | \ 969 RX_DMA_CTL_STAT_RCRTO | \ 970 RX_DMA_CTL_STAT_RCRTHRES | \ 971 RX_DMA_CTL_STAT_DC_FIFO_ERR 972 973 /* Receive DMA Interrupt Behavior: Force an update to RCR (DMC + 0x00078 */ 974 #define RCR_FLSH_SHIFT 0 /* RW, bit 0:0 */ 975 #define RCR_FLSH_SET 0x0000000000000001ULL 976 #define RCR_FLSH_MASK 0x0000000000000001ULL 977 978 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00080 */ 979 #define RX_DMA_LOGA_ADDR_SHIFT 0 /* RO, bit 11:0 */ 980 #define RX_DMA_LOGA_ADDR 0x0000000000000FFFULL 981 #define RX_DMA_LOGA_ADDR_MASK 0x0000000000000FFFULL 982 #define RX_DMA_LOGA_TYPE_SHIFT 28 /* RO, bit 30:28 */ 983 #define RX_DMA_LOGA_TYPE 0x0000000070000000ULL 984 #define RX_DMA_LOGA_TYPE_MASK 0x0000000070000FFFULL 985 #define RX_DMA_LOGA_MULTI_SHIFT 28 /* RO, bit 30:28 */ 986 #define RX_DMA_LOGA_MULTI 0x0000000080000000ULL 987 #define RX_DMA_LOGA_MULTI_MASK 0x0000000080000FFFULL 988 989 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00088 */ 990 #define RX_DMA_LOGA_ADDR_L_SHIFT 0 /* RO, bit 31:0 */ 991 #define RX_DMA_LOGA_ADDRL_L 0x00000000FFFFFFFFULL 992 #define RX_DMA_LOGA_ADDR_LMASK 0x00000000FFFFFFFFULL 993 994 typedef union _rcrcfig_a_t { 995 uint64_t value; 996 struct { 997 #if defined(_BIG_ENDIAN) 998 struct { 999 #if defined(_BIT_FIELDS_HTOL) 1000 uint32_t len:16; 1001 uint32_t res1:4; 1002 uint32_t staddr_base:12; 1003 #elif defined(_BIT_FIELDS_LTOH) 1004 uint32_t staddr_base:12; 1005 uint32_t res1:4; 1006 uint32_t len:16; 1007 #endif 1008 } hdw; 1009 #endif 1010 struct { 1011 #if defined(_BIT_FIELDS_HTOL) 1012 uint32_t staddr_base:13; 1013 uint32_t staddr:13; 1014 uint32_t res2:6; 1015 #elif defined(_BIT_FIELDS_LTOH) 1016 uint32_t res2:6; 1017 uint32_t staddr:13; 1018 uint32_t staddr_base:13; 1019 #endif 1020 } ldw; 1021 #if !defined(_BIG_ENDIAN) 1022 struct { 1023 #if defined(_BIT_FIELDS_HTOL) 1024 uint32_t len:16; 1025 uint32_t res1:4; 1026 uint32_t staddr_base:12; 1027 #elif defined(_BIT_FIELDS_LTOH) 1028 uint32_t staddr_base:12; 1029 uint32_t res1:4; 1030 uint32_t len:16; 1031 #endif 1032 } hdw; 1033 #endif 1034 } bits; 1035 } rcrcfig_a_t, *p_rcrcfig_a_t; 1036 1037 1038 typedef union _rcrcfig_b_t { 1039 uint64_t value; 1040 struct { 1041 #if defined(_BIG_ENDIAN) 1042 uint32_t hdw; 1043 #endif 1044 struct { 1045 #if defined(_BIT_FIELDS_HTOL) 1046 uint32_t pthres:16; 1047 uint32_t entout:1; 1048 uint32_t res1:9; 1049 uint32_t timeout:6; 1050 #elif defined(_BIT_FIELDS_LTOH) 1051 uint32_t timeout:6; 1052 uint32_t res1:9; 1053 uint32_t entout:1; 1054 uint32_t pthres:16; 1055 #endif 1056 } ldw; 1057 #if !defined(_BIG_ENDIAN) 1058 uint32_t hdw; 1059 #endif 1060 } bits; 1061 } rcrcfig_b_t, *p_rcrcfig_b_t; 1062 1063 1064 typedef union _rcrstat_a_t { 1065 uint64_t value; 1066 struct { 1067 #if defined(_BIG_ENDIAN) 1068 uint32_t hdw; 1069 #endif 1070 struct { 1071 #if defined(_BIT_FIELDS_HTOL) 1072 uint32_t res1:16; 1073 uint32_t qlen:16; 1074 #elif defined(_BIT_FIELDS_LTOH) 1075 uint32_t qlen:16; 1076 uint32_t res1:16; 1077 #endif 1078 } ldw; 1079 #if !defined(_BIG_ENDIAN) 1080 uint32_t hdw; 1081 #endif 1082 } bits; 1083 } rcrstat_a_t, *p_rcrstat_a_t; 1084 1085 1086 typedef union _rcrstat_b_t { 1087 uint64_t value; 1088 struct { 1089 #if defined(_BIG_ENDIAN) 1090 uint32_t hdw; 1091 #endif 1092 struct { 1093 #if defined(_BIT_FIELDS_HTOL) 1094 uint32_t res1:20; 1095 uint32_t tlptr_h:12; 1096 #elif defined(_BIT_FIELDS_LTOH) 1097 uint32_t tlptr_h:12; 1098 uint32_t res1:20; 1099 #endif 1100 } ldw; 1101 #if !defined(_BIG_ENDIAN) 1102 uint32_t hdw; 1103 #endif 1104 } bits; 1105 } rcrstat_b_t, *p_rcrstat_b_t; 1106 1107 1108 typedef union _rcrstat_c_t { 1109 uint64_t value; 1110 struct { 1111 #if defined(_BIG_ENDIAN) 1112 uint32_t hdw; 1113 #endif 1114 struct { 1115 #if defined(_BIT_FIELDS_HTOL) 1116 uint32_t tlptr_l:29; 1117 uint32_t res1:3; 1118 #elif defined(_BIT_FIELDS_LTOH) 1119 uint32_t res1:3; 1120 uint32_t tlptr_l:29; 1121 #endif 1122 } ldw; 1123 #if !defined(_BIG_ENDIAN) 1124 uint32_t hdw; 1125 #endif 1126 } bits; 1127 } rcrstat_c_t, *p_rcrstat_c_t; 1128 1129 1130 /* Receive DMA Event Mask */ 1131 typedef union _rx_dma_ent_msk_t { 1132 uint64_t value; 1133 struct { 1134 #if defined(_BIG_ENDIAN) 1135 uint32_t hdw; 1136 #endif 1137 struct { 1138 #if defined(_BIT_FIELDS_HTOL) 1139 uint32_t rsrvd2:10; 1140 uint32_t rbr_tmout:1; 1141 uint32_t rsp_cnt_err:1; 1142 uint32_t byte_en_bus:1; 1143 uint32_t rsp_dat_err:1; 1144 uint32_t rcr_ack_err:1; 1145 uint32_t dc_fifo_err:1; 1146 uint32_t rsrvd:1; 1147 uint32_t rcrthres:1; 1148 uint32_t rcrto:1; 1149 uint32_t rcr_sha_par:1; 1150 uint32_t rbr_pre_par:1; 1151 uint32_t port_drop_pkt:1; 1152 uint32_t wred_drop:1; 1153 uint32_t rbr_pre_empty:1; 1154 uint32_t rcr_shadow_full:1; 1155 uint32_t config_err:1; 1156 uint32_t rcrincon:1; 1157 uint32_t rcrfull:1; 1158 uint32_t rbr_empty:1; 1159 uint32_t rbrfull:1; 1160 uint32_t rbrlogpage:1; 1161 uint32_t cfiglogpage:1; 1162 #elif defined(_BIT_FIELDS_LTOH) 1163 uint32_t cfiglogpage:1; 1164 uint32_t rbrlogpage:1; 1165 uint32_t rbrfull:1; 1166 uint32_t rbr_empty:1; 1167 uint32_t rcrfull:1; 1168 uint32_t rcrincon:1; 1169 uint32_t config_err:1; 1170 uint32_t rcr_shadow_full:1; 1171 uint32_t rbr_pre_empty:1; 1172 uint32_t wred_drop:1; 1173 uint32_t port_drop_pkt:1; 1174 uint32_t rbr_pre_par:1; 1175 uint32_t rcr_sha_par:1; 1176 uint32_t rcrto:1; 1177 uint32_t rcrthres:1; 1178 uint32_t rsrvd:1; 1179 uint32_t dc_fifo_err:1; 1180 uint32_t rcr_ack_err:1; 1181 uint32_t rsp_dat_err:1; 1182 uint32_t byte_en_bus:1; 1183 uint32_t rsp_cnt_err:1; 1184 uint32_t rbr_tmout:1; 1185 uint32_t rsrvd2:10; 1186 #endif 1187 } ldw; 1188 #if !defined(_BIG_ENDIAN) 1189 uint32_t hdw; 1190 #endif 1191 } bits; 1192 } rx_dma_ent_msk_t, *p_rx_dma_ent_msk_t; 1193 1194 1195 /* Receive DMA Control and Status */ 1196 typedef union _rx_dma_ctl_stat_t { 1197 uint64_t value; 1198 struct { 1199 #if defined(_BIG_ENDIAN) 1200 struct { 1201 #if defined(_BIT_FIELDS_HTOL) 1202 uint32_t rsrvd:10; 1203 uint32_t rbr_tmout:1; 1204 uint32_t rsp_cnt_err:1; 1205 uint32_t byte_en_bus:1; 1206 uint32_t rsp_dat_err:1; 1207 uint32_t rcr_ack_err:1; 1208 uint32_t dc_fifo_err:1; 1209 uint32_t mex:1; 1210 uint32_t rcrthres:1; 1211 uint32_t rcrto:1; 1212 uint32_t rcr_sha_par:1; 1213 uint32_t rbr_pre_par:1; 1214 uint32_t port_drop_pkt:1; 1215 uint32_t wred_drop:1; 1216 uint32_t rbr_pre_empty:1; 1217 uint32_t rcr_shadow_full:1; 1218 uint32_t config_err:1; 1219 uint32_t rcrincon:1; 1220 uint32_t rcrfull:1; 1221 uint32_t rbr_empty:1; 1222 uint32_t rbrfull:1; 1223 uint32_t rbrlogpage:1; 1224 uint32_t cfiglogpage:1; 1225 #elif defined(_BIT_FIELDS_LTOH) 1226 uint32_t cfiglogpage:1; 1227 uint32_t rbrlogpage:1; 1228 uint32_t rbrfull:1; 1229 uint32_t rbr_empty:1; 1230 uint32_t rcrfull:1; 1231 uint32_t rcrincon:1; 1232 uint32_t config_err:1; 1233 uint32_t rcr_shadow_full:1; 1234 uint32_t rbr_pre_empty:1; 1235 uint32_t wred_drop:1; 1236 uint32_t port_drop_pkt:1; 1237 uint32_t rbr_pre_par:1; 1238 uint32_t rcr_sha_par:1; 1239 uint32_t rcrto:1; 1240 uint32_t rcrthres:1; 1241 uint32_t mex:1; 1242 uint32_t dc_fifo_err:1; 1243 uint32_t rcr_ack_err:1; 1244 uint32_t rsp_dat_err:1; 1245 uint32_t byte_en_bus:1; 1246 uint32_t rsp_cnt_err:1; 1247 uint32_t rbr_tmout:1; 1248 uint32_t rsrvd:10; 1249 #endif 1250 } hdw; 1251 1252 #endif 1253 struct { 1254 #if defined(_BIT_FIELDS_HTOL) 1255 uint32_t ptrread:16; 1256 uint32_t pktread:16; 1257 #elif defined(_BIT_FIELDS_LTOH) 1258 uint32_t pktread:16; 1259 uint32_t ptrread:16; 1260 1261 #endif 1262 } ldw; 1263 #if !defined(_BIG_ENDIAN) 1264 struct { 1265 #if defined(_BIT_FIELDS_HTOL) 1266 uint32_t rsrvd:10; 1267 uint32_t rbr_tmout:1; 1268 uint32_t rsp_cnt_err:1; 1269 uint32_t byte_en_bus:1; 1270 uint32_t rsp_dat_err:1; 1271 uint32_t rcr_ack_err:1; 1272 uint32_t dc_fifo_err:1; 1273 uint32_t mex:1; 1274 uint32_t rcrthres:1; 1275 uint32_t rcrto:1; 1276 uint32_t rcr_sha_par:1; 1277 uint32_t rbr_pre_par:1; 1278 uint32_t port_drop_pkt:1; 1279 uint32_t wred_drop:1; 1280 uint32_t rbr_pre_empty:1; 1281 uint32_t rcr_shadow_full:1; 1282 uint32_t config_err:1; 1283 uint32_t rcrincon:1; 1284 uint32_t rcrfull:1; 1285 uint32_t rbr_empty:1; 1286 uint32_t rbrfull:1; 1287 uint32_t rbrlogpage:1; 1288 uint32_t cfiglogpage:1; 1289 #elif defined(_BIT_FIELDS_LTOH) 1290 uint32_t cfiglogpage:1; 1291 uint32_t rbrlogpage:1; 1292 uint32_t rbrfull:1; 1293 uint32_t rbr_empty:1; 1294 uint32_t rcrfull:1; 1295 uint32_t rcrincon:1; 1296 uint32_t config_err:1; 1297 uint32_t rcr_shadow_full:1; 1298 uint32_t rbr_pre_empty:1; 1299 uint32_t wred_drop:1; 1300 uint32_t port_drop_pkt:1; 1301 uint32_t rbr_pre_par:1; 1302 uint32_t rcr_sha_par:1; 1303 uint32_t rcrto:1; 1304 uint32_t rcrthres:1; 1305 uint32_t mex:1; 1306 uint32_t dc_fifo_err:1; 1307 uint32_t rcr_ack_err:1; 1308 uint32_t rsp_dat_err:1; 1309 uint32_t byte_en_bus:1; 1310 uint32_t rsp_cnt_err:1; 1311 uint32_t rbr_tmout:1; 1312 uint32_t rsrvd:10; 1313 #endif 1314 } hdw; 1315 #endif 1316 } bits; 1317 } rx_dma_ctl_stat_t, *p_rx_dma_ctl_stat_t; 1318 1319 typedef union _rcr_flsh_t { 1320 uint64_t value; 1321 struct { 1322 #if defined(_BIG_ENDIAN) 1323 uint32_t hdw; 1324 #endif 1325 struct { 1326 #if defined(_BIT_FIELDS_HTOL) 1327 uint32_t res1_1:31; 1328 uint32_t flsh:1; 1329 #elif defined(_BIT_FIELDS_LTOH) 1330 uint32_t flsh:1; 1331 uint32_t res1_1:31; 1332 #endif 1333 } ldw; 1334 #if !defined(_BIG_ENDIAN) 1335 uint32_t hdw; 1336 #endif 1337 } bits; 1338 } rcr_flsh_t, *p_rcr_flsh_t; 1339 1340 1341 typedef union _rx_dma_loga_t { 1342 uint64_t value; 1343 struct { 1344 #if defined(_BIG_ENDIAN) 1345 uint32_t hdw; 1346 #endif 1347 struct { 1348 #if defined(_BIT_FIELDS_HTOL) 1349 uint32_t multi:1; 1350 uint32_t type:3; 1351 uint32_t res1:16; 1352 uint32_t addr:12; 1353 #elif defined(_BIT_FIELDS_LTOH) 1354 uint32_t addr:12; 1355 uint32_t res1:16; 1356 uint32_t type:3; 1357 uint32_t multi:1; 1358 #endif 1359 } ldw; 1360 #if !defined(_BIG_ENDIAN) 1361 uint32_t hdw; 1362 #endif 1363 } bits; 1364 } rx_dma_loga_t, *p_rx_dma_loga_t; 1365 1366 1367 typedef union _rx_dma_logb_t { 1368 uint64_t value; 1369 struct { 1370 #if defined(_BIG_ENDIAN) 1371 uint32_t hdw; 1372 #endif 1373 struct { 1374 #if defined(_BIT_FIELDS_HTOL) 1375 uint32_t addr_l:32; 1376 #elif defined(_BIT_FIELDS_LTOH) 1377 uint32_t addr_l:32; 1378 #endif 1379 } ldw; 1380 #if !defined(_BIG_ENDIAN) 1381 uint32_t hdw; 1382 #endif 1383 } bits; 1384 } rx_dma_logb_t, *p_rx_dma_logb_t; 1385 1386 1387 #define RX_DMA_MAILBOX_BYTE_LENGTH 64 1388 #define RX_DMA_MBOX_UNUSED_1 8 1389 #define RX_DMA_MBOX_UNUSED_2 16 1390 1391 typedef struct _rxdma_mailbox_t { 1392 rx_dma_ctl_stat_t rxdma_ctl_stat; /* 8 bytes */ 1393 rbr_stat_t rbr_stat; /* 8 bytes */ 1394 uint32_t rbr_hdl; /* 4 bytes (31:0) */ 1395 uint32_t rbr_hdh; /* 4 bytes (31:0) */ 1396 uint32_t resv_1[RX_DMA_MBOX_UNUSED_1]; 1397 uint32_t rcrstat_c; /* 4 bytes (31:0) */ 1398 uint32_t rcrstat_b; /* 4 bytes (31:0) */ 1399 rcrstat_a_t rcrstat_a; /* 8 bytes */ 1400 uint32_t resv_2[RX_DMA_MBOX_UNUSED_2]; 1401 } rxdma_mailbox_t, *p_rxdma_mailbox_t; 1402 1403 1404 1405 typedef union _rx_disc_cnt_t { 1406 uint64_t value; 1407 struct { 1408 #if defined(_BIG_ENDIAN) 1409 uint32_t hdw; 1410 #endif 1411 struct { 1412 #if defined(_BIT_FIELDS_HTOL) 1413 uint32_t res_1:15; 1414 uint32_t oflow:1; 1415 uint32_t count:16; 1416 #elif defined(_BIT_FIELDS_LTOH) 1417 uint32_t count:16; 1418 uint32_t oflow:1; 1419 uint32_t res_1:15; 1420 #endif 1421 } ldw; 1422 #if !defined(_BIG_ENDIAN) 1423 uint32_t hdw; 1424 #endif 1425 } bits; 1426 } rx_disc_cnt_t, *p_rx_disc_cnt_t; 1427 1428 #define RXMISC_DISCARD_REG (DMC + 0x00090) 1429 1430 #if OLD 1431 /* 1432 * RBR Empty: If the RBR is empty or the prefetch buffer is empty, 1433 * packets will be discarded (Each RBR has one). 1434 * (16 channels, 0x200) 1435 */ 1436 #define RDC_PRE_EMPTY_REG (DMC + 0x000B0) 1437 #define RDC_PRE_EMPTY_OFFSET(channel) (RDC_PRE_EMPTY_REG + \ 1438 (DMC_OFFSET(channel)) 1439 1440 typedef union _rdc_pre_empty_t { 1441 uint64_t value; 1442 struct { 1443 #if defined(_BIG_ENDIAN) 1444 uint32_t hdw; 1445 #endif 1446 struct { 1447 #if defined(_BIT_FIELDS_HTOL) 1448 uint32_t res_1:15; 1449 uint32_t oflow:1; 1450 uint32_t count:16; 1451 #elif defined(_BIT_FIELDS_LTOH) 1452 uint32_t count:16; 1453 uint32_t oflow:1; 1454 uint32_t res_1:15; 1455 #endif 1456 } ldw; 1457 #if !defined(_BIG_ENDIAN) 1458 uint32_t hdw; 1459 #endif 1460 } bits; 1461 } rdc_pre_empty_t, *p_rdc_pre_empty_t; 1462 #endif 1463 1464 1465 #define FZC_DMC_REG_SIZE 0x20 1466 #define FZC_DMC_OFFSET(channel) (FZC_DMC_REG_SIZE * channel) 1467 1468 /* WRED discard count register (16, 0x40) */ 1469 #define RED_DIS_CNT_REG (FZC_DMC + 0x30008) 1470 #define RED_DMC_OFFSET(channel) (0x40 * channel) 1471 #define RDC_DIS_CNT_OFFSET(rdc) (RED_DIS_CNT_REG + RED_DMC_OFFSET(rdc)) 1472 1473 typedef union _red_disc_cnt_t { 1474 uint64_t value; 1475 struct { 1476 #if defined(_BIG_ENDIAN) 1477 uint32_t hdw; 1478 #endif 1479 struct { 1480 #if defined(_BIT_FIELDS_HTOL) 1481 uint32_t res_1:15; 1482 uint32_t oflow:1; 1483 uint32_t count:16; 1484 #elif defined(_BIT_FIELDS_LTOH) 1485 uint32_t count:16; 1486 uint32_t oflow:1; 1487 uint32_t res_1:15; 1488 #endif 1489 } ldw; 1490 #if !defined(_BIG_ENDIAN) 1491 uint32_t hdw; 1492 #endif 1493 } bits; 1494 } red_disc_cnt_t, *p_red_disc_cnt_t; 1495 1496 1497 #define RDMC_PRE_PAR_ERR_REG (FZC_DMC + 0x00078) 1498 #define RDMC_SHA_PAR_ERR_REG (FZC_DMC + 0x00080) 1499 1500 typedef union _rdmc_par_err_log { 1501 uint64_t value; 1502 struct { 1503 #if defined(_BIG_ENDIAN) 1504 uint32_t hdw; 1505 #endif 1506 struct { 1507 #if defined(_BIT_FIELDS_HTOL) 1508 uint32_t res_1:16; 1509 uint32_t err:1; 1510 uint32_t merr:1; 1511 uint32_t res:6; 1512 uint32_t addr:8; 1513 #elif defined(_BIT_FIELDS_LTOH) 1514 uint32_t addr:8; 1515 uint32_t res:6; 1516 uint32_t merr:1; 1517 uint32_t err:1; 1518 uint32_t res_1:16; 1519 #endif 1520 } ldw; 1521 #if !defined(_BIG_ENDIAN) 1522 uint32_t hdw; 1523 #endif 1524 } bits; 1525 } rdmc_par_err_log_t, *p_rdmc_par_err_log_t; 1526 1527 1528 /* Used for accessing RDMC Memory */ 1529 #define RDMC_MEM_ADDR_REG (FZC_DMC + 0x00088) 1530 1531 1532 typedef union _rdmc_mem_addr { 1533 uint64_t value; 1534 struct { 1535 #if defined(_BIG_ENDIAN) 1536 uint32_t hdw; 1537 #endif 1538 1539 #define RDMC_MEM_ADDR_PREFETCH 0 1540 #define RDMC_MEM_ADDR_SHADOW 1 1541 1542 struct { 1543 #if defined(_BIT_FIELDS_HTOL) 1544 uint32_t res_1:23; 1545 uint32_t pre_shad:1; 1546 uint32_t addr:8; 1547 #elif defined(_BIT_FIELDS_LTOH) 1548 uint32_t addr:8; 1549 uint32_t pre_shad:1; 1550 uint32_t res_1:23; 1551 #endif 1552 } ldw; 1553 #if !defined(_BIG_ENDIAN) 1554 uint32_t hdw; 1555 #endif 1556 } bits; 1557 } rdmc_mem_addr_t, *p_rdmc_mem_addr_t; 1558 1559 1560 #define RDMC_MEM_DATA0_REG (FZC_DMC + 0x00090) 1561 #define RDMC_MEM_DATA1_REG (FZC_DMC + 0x00098) 1562 #define RDMC_MEM_DATA2_REG (FZC_DMC + 0x000A0) 1563 #define RDMC_MEM_DATA3_REG (FZC_DMC + 0x000A8) 1564 #define RDMC_MEM_DATA4_REG (FZC_DMC + 0x000B0) 1565 1566 typedef union _rdmc_mem_data { 1567 uint64_t value; 1568 struct { 1569 #if defined(_BIG_ENDIAN) 1570 uint32_t hdw; 1571 #endif 1572 1573 struct { 1574 #if defined(_BIT_FIELDS_HTOL) 1575 uint32_t data; 1576 #elif defined(_BIT_FIELDS_LTOH) 1577 uint32_t data; 1578 #endif 1579 } ldw; 1580 #if !defined(_BIG_ENDIAN) 1581 uint32_t hdw; 1582 #endif 1583 } bits; 1584 } rdmc_mem_data_t, *p_rdmc_mem_data_t; 1585 1586 1587 typedef union _rdmc_mem_access { 1588 #define RDMC_MEM_READ 1 1589 #define RDMC_MEM_WRITE 2 1590 uint32_t data[5]; 1591 uint8_t addr; 1592 uint8_t location; 1593 } rdmc_mem_access_t, *p_rdmc_mem_access_t; 1594 1595 1596 #define RX_CTL_DAT_FIFO_STAT_REG (FZC_DMC + 0x000B8) 1597 #define RX_CTL_DAT_FIFO_MASK_REG (FZC_DMC + 0x000C0) 1598 #define RX_CTL_DAT_FIFO_STAT_DBG_REG (FZC_DMC + 0x000D0) 1599 1600 typedef union _rx_ctl_dat_fifo { 1601 #define FIFO_EOP_PORT0 0x1 1602 #define FIFO_EOP_PORT1 0x2 1603 #define FIFO_EOP_PORT2 0x4 1604 #define FIFO_EOP_PORT3 0x8 1605 #define FIFO_EOP_ALL 0xF 1606 uint64_t value; 1607 struct { 1608 #if defined(_BIG_ENDIAN) 1609 uint32_t hdw; 1610 #endif 1611 struct { 1612 #if defined(_BIT_FIELDS_HTOL) 1613 uint32_t res_1:23; 1614 uint32_t id_mismatch:1; 1615 uint32_t zcp_eop_err:4; 1616 uint32_t ipp_eop_err:4; 1617 #elif defined(_BIT_FIELDS_LTOH) 1618 uint32_t ipp_eop_err:4; 1619 uint32_t zcp_eop_err:4; 1620 uint32_t id_mismatch:1; 1621 uint32_t res_1:23; 1622 #endif 1623 } ldw; 1624 #if !defined(_BIG_ENDIAN) 1625 uint32_t hdw; 1626 #endif 1627 } bits; 1628 } rx_ctl_dat_fifo_mask_t, rx_ctl_dat_fifo_stat_t, 1629 rx_ctl_dat_fifo_stat_dbg_t, *p_rx_ctl_dat_fifo_t; 1630 1631 1632 1633 #define RDMC_TRAINING_VECTOR_REG (FZC_DMC + 0x000C8) 1634 1635 typedef union _rx_training_vect { 1636 uint64_t value; 1637 struct { 1638 #if defined(_BIG_ENDIAN) 1639 uint32_t hdw; 1640 #endif 1641 struct { 1642 uint32_t tv; 1643 } ldw; 1644 #if !defined(_BIG_ENDIAN) 1645 uint32_t hdw; 1646 #endif 1647 } bits; 1648 } rx_training_vect_t, *p_rx_training_vect_t; 1649 1650 #define RXCTL_IPP_EOP_ERR_MASK 0x0000000FULL 1651 #define RXCTL_IPP_EOP_ERR_SHIFT 0x0 1652 #define RXCTL_ZCP_EOP_ERR_MASK 0x000000F0ULL 1653 #define RXCTL_ZCP_EOP_ERR_SHIFT 0x4 1654 #define RXCTL_ID_MISMATCH_MASK 0x00000100ULL 1655 #define RXCTL_ID_MISMATCH_SHIFT 0x8 1656 1657 1658 /* 1659 * Receive Packet Header Format 1660 * Packet header before the packet. 1661 * The minimum is 2 bytes and the max size is 18 bytes. 1662 */ 1663 /* 1664 * Packet header format 0 (2 bytes). 1665 */ 1666 typedef union _rx_pkt_hdr0_t { 1667 uint16_t value; 1668 struct { 1669 #if defined(_BIT_FIELDS_HTOL) 1670 uint16_t inputport:2; 1671 uint16_t maccheck:1; 1672 uint16_t class:5; 1673 uint16_t vlan:1; 1674 uint16_t llcsnap:1; 1675 uint16_t noport:1; 1676 uint16_t badip:1; 1677 uint16_t tcamhit:1; 1678 uint16_t tres:2; 1679 uint16_t tzfvld:1; 1680 #elif defined(_BIT_FIELDS_LTOH) 1681 uint16_t tzfvld:1; 1682 uint16_t tres:2; 1683 uint16_t tcamhit:1; 1684 uint16_t badip:1; 1685 uint16_t noport:1; 1686 uint16_t llcsnap:1; 1687 uint16_t vlan:1; 1688 uint16_t class:5; 1689 uint16_t maccheck:1; 1690 uint16_t inputport:2; 1691 #endif 1692 } bits; 1693 } rx_pkt_hdr0_t, *p_rx_pkt_hdr0_t; 1694 1695 1696 /* 1697 * Packet header format 1. 1698 */ 1699 typedef union _rx_pkt_hdr1_b0_t { 1700 uint8_t value; 1701 struct { 1702 #if defined(_BIT_FIELDS_HTOL) 1703 uint8_t hwrsvd:8; 1704 #elif defined(_BIT_FIELDS_LTOH) 1705 uint8_t hwrsvd:8; 1706 #endif 1707 } bits; 1708 } rx_pkt_hdr1_b0_t, *p_rx_pkt_hdr1_b0_t; 1709 1710 typedef union _rx_pkt_hdr1_b1_t { 1711 uint8_t value; 1712 struct { 1713 #if defined(_BIT_FIELDS_HTOL) 1714 uint8_t tcammatch:8; 1715 #elif defined(_BIT_FIELDS_LTOH) 1716 uint8_t tcammatch:8; 1717 #endif 1718 } bits; 1719 } rx_pkt_hdr1_b1_t, *p_rx_pkt_hdr1_b1_t; 1720 1721 typedef union _rx_pkt_hdr1_b2_t { 1722 uint8_t value; 1723 struct { 1724 #if defined(_BIT_FIELDS_HTOL) 1725 uint8_t resv:2; 1726 uint8_t hashhit:1; 1727 uint8_t exact:1; 1728 uint8_t hzfvld:1; 1729 uint8_t hashidx:3; 1730 #elif defined(_BIT_FIELDS_LTOH) 1731 uint8_t hashidx:3; 1732 uint8_t hzfvld:1; 1733 uint8_t exact:1; 1734 uint8_t hashhit:1; 1735 uint8_t resv:2; 1736 #endif 1737 } bits; 1738 } rx_pkt_hdr1_b2_t, *p_rx_pkt_hdr1_b2_t; 1739 1740 typedef union _rx_pkt_hdr1_b3_t { 1741 uint8_t value; 1742 struct { 1743 #if defined(_BIT_FIELDS_HTOL) 1744 uint8_t zc_resv:8; 1745 #elif defined(_BIT_FIELDS_LTOH) 1746 uint8_t zc_resv:8; 1747 #endif 1748 } bits; 1749 } rx_pkt_hdr1_b3_t, *p_rx_pkt_hdr1_b3_t; 1750 1751 typedef union _rx_pkt_hdr1_b4_t { 1752 uint8_t value; 1753 struct { 1754 #if defined(_BIT_FIELDS_HTOL) 1755 uint8_t resv:4; 1756 uint8_t zflowid:4; 1757 #elif defined(_BIT_FIELDS_LTOH) 1758 uint8_t zflowid:4; 1759 uint8_t resv:4; 1760 #endif 1761 } bits; 1762 } rx_pkt_hdr1_b4_t, *p_rx_pkt_hdr1_b4_t; 1763 1764 typedef union _rx_pkt_hdr1_b5_t { 1765 uint8_t value; 1766 struct { 1767 #if defined(_BIT_FIELDS_HTOL) 1768 uint8_t zflowid:8; 1769 #elif defined(_BIT_FIELDS_LTOH) 1770 uint8_t zflowid:8; 1771 #endif 1772 } bits; 1773 } rx_pkt_hdr1_b5_t, *p_rx_pkt_hdr1_b5_t; 1774 1775 typedef union _rx_pkt_hdr1_b6_t { 1776 uint8_t value; 1777 struct { 1778 #if defined(_BIT_FIELDS_HTOL) 1779 uint8_t hashval2:8; 1780 #elif defined(_BIT_FIELDS_LTOH) 1781 uint8_t hashval2:8; 1782 #endif 1783 } bits; 1784 } rx_pkt_hdr1_b6_t, *p_rx_pkt_hdr1_b6_t; 1785 1786 typedef union _rx_pkt_hdr1_b7_t { 1787 uint8_t value; 1788 struct { 1789 #if defined(_BIT_FIELDS_HTOL) 1790 uint8_t hashval2:8; 1791 #elif defined(_BIT_FIELDS_LTOH) 1792 uint8_t hashval2:8; 1793 #endif 1794 } bits; 1795 } rx_pkt_hdr1_b7_t, *p_rx_pkt_hdr1_b7_t; 1796 1797 typedef union _rx_pkt_hdr1_b8_t { 1798 uint8_t value; 1799 struct { 1800 #if defined(_BIT_FIELDS_HTOL) 1801 uint8_t resv:4; 1802 uint8_t h1:4; 1803 #elif defined(_BIT_FIELDS_LTOH) 1804 uint8_t h1:4; 1805 uint8_t resv:4; 1806 #endif 1807 } bits; 1808 } rx_pkt_hdr1_b8_t, *p_rx_pkt_hdr1_b8_t; 1809 1810 typedef union _rx_pkt_hdr1_b9_t { 1811 uint8_t value; 1812 struct { 1813 #if defined(_BIT_FIELDS_HTOL) 1814 uint8_t h1:8; 1815 #elif defined(_BIT_FIELDS_LTOH) 1816 uint8_t h1:8; 1817 #endif 1818 } bits; 1819 } rx_pkt_hdr1_b9_t, *p_rx_pkt_hdr1_b9_t; 1820 1821 typedef union _rx_pkt_hdr1_b10_t { 1822 uint8_t value; 1823 struct { 1824 #if defined(_BIT_FIELDS_HTOL) 1825 uint8_t resv:4; 1826 uint8_t h1:4; 1827 #elif defined(_BIT_FIELDS_LTOH) 1828 uint8_t h1:4; 1829 uint8_t resv:4; 1830 #endif 1831 } bits; 1832 } rx_pkt_hdr1_b10_t, *p_rx_pkt_hdr1_b10_t; 1833 1834 typedef union _rx_pkt_hdr1_b11_b12_t { 1835 uint16_t value; 1836 struct { 1837 #if defined(_BIT_FIELDS_HTOL) 1838 uint16_t h1_1:8; 1839 uint16_t h1_2:8; 1840 #elif defined(_BIT_FIELDS_LTOH) 1841 uint16_t h1_2:8; 1842 uint16_t h1_1:8; 1843 #endif 1844 } bits; 1845 } rx_pkt_hdr1_b11_b12_t, *p_rx_pkt_hdr1_b11_b12_t; 1846 1847 typedef union _rx_pkt_hdr1_b13_t { 1848 uint8_t value; 1849 struct { 1850 #if defined(_BIT_FIELDS_HTOL) 1851 uint8_t usr_data:8; 1852 #elif defined(_BIT_FIELDS_LTOH) 1853 uint8_t usr_data:8; 1854 #endif 1855 } bits; 1856 } rx_pkt_hdr1_b13_t, *p_rx_pkt_hdr1_b13_t; 1857 1858 typedef union _rx_pkt_hdr1_b14_b17_t { 1859 uint32_t value; 1860 struct { 1861 #if defined(_BIT_FIELDS_HTOL) 1862 uint32_t usr_data_1:8; 1863 uint32_t usr_data_2:8; 1864 uint32_t usr_data_3:8; 1865 uint32_t usr_data_4:8; 1866 #elif defined(_BIT_FIELDS_LTOH) 1867 uint32_t usr_data_4:8; 1868 uint32_t usr_data_3:8; 1869 uint32_t usr_data_2:8; 1870 uint32_t usr_data_1:8; 1871 #endif 1872 } bits; 1873 } rx_pkt_hdr1_b14_b17_t, *p_rx_pkt_hdr1_b14_b17_t; 1874 1875 /* Receive packet header 1 format (18 bytes) */ 1876 typedef struct _rx_pkt_hdr_t { 1877 rx_pkt_hdr1_b0_t rx_hdr1_b0; 1878 rx_pkt_hdr1_b1_t rx_hdr1_b1; 1879 rx_pkt_hdr1_b2_t rx_hdr1_b2; 1880 rx_pkt_hdr1_b3_t rx_hdr1_b3; 1881 rx_pkt_hdr1_b4_t rx_hdr1_b4; 1882 rx_pkt_hdr1_b5_t rx_hdr1_b5; 1883 rx_pkt_hdr1_b6_t rx_hdr1_b6; 1884 rx_pkt_hdr1_b7_t rx_hdr1_b7; 1885 rx_pkt_hdr1_b8_t rx_hdr1_b8; 1886 rx_pkt_hdr1_b9_t rx_hdr1_b9; 1887 rx_pkt_hdr1_b10_t rx_hdr1_b10; 1888 rx_pkt_hdr1_b11_b12_t rx_hdr1_b11_b12; 1889 rx_pkt_hdr1_b13_t rx_hdr1_b13; 1890 rx_pkt_hdr1_b14_b17_t rx_hdr1_b14_b17; 1891 } rx_pkt_hdr1_t, *p_rx_pkt_hdr1_t; 1892 1893 1894 #ifdef __cplusplus 1895 } 1896 #endif 1897 1898 #endif /* _SYS_NXGE_NXGE_RXDMA_HW_H */ 1899