1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_RXDMA_HW_H 27 #define _SYS_NXGE_NXGE_RXDMA_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 #include <nxge_hw.h> 37 38 /* 39 * NIU: Receive DMA Channels 40 */ 41 /* Receive DMA Clock Divider */ 42 #define RX_DMA_CK_DIV_REG (FZC_DMC + 0x00000) 43 #define RX_DMA_CK_DIV_SHIFT 0 /* bits 15:0 */ 44 #define RX_DMA_CK_DIV_MASK 0x000000000000FFFFULL 45 46 typedef union _rx_dma_ck_div_t { 47 uint64_t value; 48 struct { 49 #if defined(_BIG_ENDIAN) 50 uint32_t hdw; 51 #endif 52 struct { 53 #if defined(_BIT_FIELDS_HTOL) 54 uint32_t res1_1:16; 55 uint32_t cnt:16; 56 #elif defined(_BIT_FIELDS_LTOH) 57 uint32_t cnt:16; 58 uint32_t res1_1:16; 59 #endif 60 } ldw; 61 #if !defined(_BIG_ENDIAN) 62 uint32_t hdw; 63 #endif 64 } bits; 65 } rx_dma_ck_div_t, *p_rx_dma_ck_div_t; 66 67 68 /* 69 * Default Port Receive DMA Channel (RDC) 70 */ 71 #define DEF_PT_RDC_REG(port) (FZC_DMC + 0x00008 * (port + 1)) 72 #define DEF_PT0_RDC_REG (FZC_DMC + 0x00008) 73 #define DEF_PT1_RDC_REG (FZC_DMC + 0x00010) 74 #define DEF_PT2_RDC_REG (FZC_DMC + 0x00018) 75 #define DEF_PT3_RDC_REG (FZC_DMC + 0x00020) 76 #define DEF_PT_RDC_SHIFT 0 /* bits 4:0 */ 77 #define DEF_PT_RDC_MASK 0x000000000000001FULL 78 79 80 #define RDC_TBL_REG (FZC_ZCP + 0x10000) 81 #define RDC_TBL_SHIFT 0 /* bits 4:0 */ 82 #define RDC_TBL_MASK 0x000000000000001FULL 83 84 /* For the default port RDC and RDC table */ 85 typedef union _def_pt_rdc_t { 86 uint64_t value; 87 struct { 88 #if defined(_BIG_ENDIAN) 89 uint32_t hdw; 90 #endif 91 struct { 92 #if defined(_BIT_FIELDS_HTOL) 93 uint32_t res1_1:27; 94 uint32_t rdc:5; 95 #elif defined(_BIT_FIELDS_LTOH) 96 uint32_t rdc:5; 97 uint32_t res1_1:27; 98 #endif 99 } ldw; 100 #if !defined(_BIG_ENDIAN) 101 uint32_t hdw; 102 #endif 103 } bits; 104 } def_pt_rdc_t, *p_def_pt_rdc_t; 105 106 typedef union _rdc_tbl_t { 107 uint64_t value; 108 struct { 109 #if defined(_BIG_ENDIAN) 110 uint32_t hdw; 111 #endif 112 struct { 113 #if defined(_BIT_FIELDS_HTOL) 114 uint32_t res1_1:28; 115 uint32_t rdc:4; 116 #elif defined(_BIT_FIELDS_LTOH) 117 uint32_t rdc:4; 118 uint32_t res1_1:28; 119 #endif 120 } ldw; 121 #if !defined(_BIG_ENDIAN) 122 uint32_t hdw; 123 #endif 124 } bits; 125 } rdc_tbl_t, *p_rdc_tbl_t; 126 127 /* 128 * RDC: 32 bit Addressing mode 129 */ 130 #define RX_ADDR_MD_REG (FZC_DMC + 0x00070) 131 #define RX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 132 #define RX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 133 #define RX_ADDR_MD_MASK 0x0000000000000001ULL 134 135 typedef union _rx_addr_md_t { 136 uint64_t value; 137 struct { 138 #if defined(_BIG_ENDIAN) 139 uint32_t hdw; 140 #endif 141 struct { 142 #if defined(_BIT_FIELDS_HTOL) 143 uint32_t res1_1:28; 144 uint32_t dbg_pt_mux_sel:2; 145 uint32_t ram_acc:1; 146 uint32_t mode32:1; 147 #elif defined(_BIT_FIELDS_LTOH) 148 uint32_t mode32:1; 149 uint32_t ram_acc:1; 150 uint32_t dbg_pt_mux_sel:2; 151 uint32_t res1_1:28; 152 #endif 153 } ldw; 154 #if !defined(_BIG_ENDIAN) 155 uint32_t hdw; 156 #endif 157 } bits; 158 } rx_addr_md_t, *p_rx_addr_md_t; 159 160 /* 161 * RDC: Port Scheduler 162 */ 163 164 #define PT_DRR_WT_REG(portnm) ((FZC_DMC + 0x00028) + (portnm * 8)) 165 #define PT_DRR_WT0_REG (FZC_DMC + 0x00028) 166 #define PT_DRR_WT1_REG (FZC_DMC + 0x00030) 167 #define PT_DRR_WT2_REG (FZC_DMC + 0x00038) 168 #define PT_DRR_WT3_REG (FZC_DMC + 0x00040) 169 #define PT_DRR_WT_SHIFT 0 170 #define PT_DRR_WT_MASK 0x000000000000FFFFULL /* bits 15:0 */ 171 #define PT_DRR_WT_DEFAULT_10G 0x0400 172 #define PT_DRR_WT_DEFAULT_1G 0x0066 173 typedef union _pt_drr_wt_t { 174 uint64_t value; 175 struct { 176 #if defined(_BIG_ENDIAN) 177 uint32_t hdw; 178 #endif 179 struct { 180 #if defined(_BIT_FIELDS_HTOL) 181 uint32_t res1_1:16; 182 uint32_t wt:16; 183 #elif defined(_BIT_FIELDS_LTOH) 184 uint32_t wt:16; 185 uint32_t res1_1:16; 186 #endif 187 } ldw; 188 #if !defined(_BIG_ENDIAN) 189 uint32_t hdw; 190 #endif 191 } bits; 192 } pt_drr_wt_t, *p_pt_drr_wt_t; 193 194 #define NXGE_RX_DRR_WT_10G 0x400 195 #define NXGE_RX_DRR_WT_1G 0x066 196 197 /* Port FIFO Usage */ 198 #define PT_USE_REG(portnum) ((FZC_DMC + 0x00048) + (portnum * 8)) 199 #define PT_USE0_REG (FZC_DMC + 0x00048) 200 #define PT_USE1_REG (FZC_DMC + 0x00050) 201 #define PT_USE2_REG (FZC_DMC + 0x00058) 202 #define PT_USE3_REG (FZC_DMC + 0x00060) 203 #define PT_USE_SHIFT 0 /* bits 19:0 */ 204 #define PT_USE_MASK 0x00000000000FFFFFULL 205 206 typedef union _pt_use_t { 207 uint64_t value; 208 struct { 209 #if defined(_BIG_ENDIAN) 210 uint32_t hdw; 211 #endif 212 struct { 213 #if defined(_BIT_FIELDS_HTOL) 214 uint32_t res1_1:12; 215 uint32_t cnt:20; 216 #elif defined(_BIT_FIELDS_LTOH) 217 uint32_t cnt:20; 218 uint32_t res1_1:12; 219 #endif 220 } ldw; 221 #if !defined(_BIG_ENDIAN) 222 uint32_t hdw; 223 #endif 224 } bits; 225 } pt_use_t, *p_pt_use_t; 226 227 /* 228 * RDC: Partitioning Support 229 * (Each of the following registers is for each RDC) 230 * Please refer to nxge_hw.h for the common logical 231 * page configuration register definitions. 232 */ 233 #define RX_LOG_REG_SIZE 0x40 234 #define RX_LOG_DMA_OFFSET(channel) (channel * RX_LOG_REG_SIZE) 235 236 #define RX_LOG_PAGE_VLD_REG (FZC_DMC + 0x20000) 237 #define RX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x20008) 238 #define RX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x20010) 239 #define RX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x20018) 240 #define RX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x20020) 241 #define RX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x20028) 242 #define RX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x20030) 243 #define RX_LOG_PAGE_HDL_REG (FZC_DMC + 0x20038) 244 245 /* RX and TX have the same definitions */ 246 #define RX_LOG_PAGE1_VLD_SHIFT 1 /* bit 1 */ 247 #define RX_LOG_PAGE0_VLD_SHIFT 0 /* bit 0 */ 248 #define RX_LOG_PAGE1_VLD 0x0000000000000002ULL 249 #define RX_LOG_PAGE0_VLD 0x0000000000000001ULL 250 #define RX_LOG_PAGE1_VLD_MASK 0x0000000000000002ULL 251 #define RX_LOG_PAGE0_VLD_MASK 0x0000000000000001ULL 252 #define RX_LOG_FUNC_VLD_SHIFT 2 /* bit 3:2 */ 253 #define RX_LOG_FUNC_VLD_MASK 0x000000000000000CULL 254 255 #define LOG_PAGE_ADDR_SHIFT 12 /* bits[43:12] --> bits[31:0] */ 256 257 /* RDC: Weighted Random Early Discard */ 258 #define RED_RAN_INIT_REG (FZC_DMC + 0x00068) 259 260 #define RED_RAN_INIT_SHIFT 0 /* bits 15:0 */ 261 #define RED_RAN_INIT_MASK 0x000000000000ffffULL 262 263 /* Weighted Random */ 264 typedef union _red_ran_init_t { 265 uint64_t value; 266 struct { 267 #if defined(_BIG_ENDIAN) 268 uint32_t hdw; 269 #endif 270 struct { 271 #if defined(_BIT_FIELDS_HTOL) 272 uint32_t res1_1:15; 273 uint32_t enable:1; 274 uint32_t init:16; 275 #elif defined(_BIT_FIELDS_LTOH) 276 uint32_t init:16; 277 uint32_t enable:1; 278 uint32_t res1_1:15; 279 #endif 280 } ldw; 281 #if !defined(_BIG_ENDIAN) 282 uint32_t hdw; 283 #endif 284 } bits; 285 } red_ran_init_t, *p_red_ran_init_t; 286 287 /* 288 * Buffer block descriptor 289 */ 290 typedef struct _rx_desc_t { 291 uint32_t block_addr; 292 } rx_desc_t, *p_rx_desc_t; 293 294 /* 295 * RDC: RED Parameter 296 * (Each DMC has one RED register) 297 */ 298 #define RDC_RED_CHANNEL_SIZE (0x40) 299 #define RDC_RED_CHANNEL_OFFSET(channel) (channel * RDC_RED_CHANNEL_SIZE) 300 301 #define RDC_RED_PARA_REG (FZC_DMC + 0x30000) 302 #define RDC_RED_RDC_PARA_REG(rdc) \ 303 (RDC_RED_PARA_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 304 305 /* the layout of this register is rx_disc_cnt_t */ 306 #define RDC_RED_DISC_CNT_REG (FZC_DMC + 0x30008) 307 #define RDC_RED_RDC_DISC_REG(rdc) \ 308 (RDC_RED_DISC_CNT_REG + (rdc * RDC_RED_CHANNEL_SIZE)) 309 310 311 #define RDC_RED_PARA1_RBR_SCL_SHIFT 0 /* bits 2:0 */ 312 #define RDC_RED_PARA1_RBR_SCL_MASK 0x0000000000000007ULL 313 #define RDC_RED_PARA1_ENB_SHIFT 3 /* bit 3 */ 314 #define RDC_RED_PARA1_ENB 0x0000000000000008ULL 315 #define RDC_RED_PARA1_ENB_MASK 0x0000000000000008ULL 316 317 #define RDC_RED_PARA_WIN_SHIFT 0 /* bits 3:0 */ 318 #define RDC_RED_PARA_WIN_MASK 0x000000000000000fULL 319 #define RDC_RED_PARA_THRE_SHIFT 4 /* bits 15:4 */ 320 #define RDC_RED_PARA_THRE_MASK 0x00000000000000f0ULL 321 #define RDC_RED_PARA_WIN_SYN_SHIFT 16 /* bits 19:16 */ 322 #define RDC_RED_PARA_WIN_SYN_MASK 0x00000000000000f0ULL 323 #define RDC_RED_PARA_THRE_SYN_SHIFT 20 /* bits 31:20 */ 324 #define RDC_RED_PARA_THRE_SYN_MASK 0x00000000000fff00ULL 325 326 /* RDC: RED parameters */ 327 typedef union _rdc_red_para_t { 328 uint64_t value; 329 struct { 330 #if defined(_BIG_ENDIAN) 331 uint32_t hdw; 332 #endif 333 struct { 334 #if defined(_BIT_FIELDS_HTOL) 335 uint32_t thre_sync:12; 336 uint32_t win_syn:4; 337 uint32_t thre:12; 338 uint32_t win:4; 339 #elif defined(_BIT_FIELDS_LTOH) 340 uint32_t win:4; 341 uint32_t thre:12; 342 uint32_t win_syn:4; 343 uint32_t thre_sync:12; 344 #endif 345 } ldw; 346 #if !defined(_BIG_ENDIAN) 347 uint32_t hdw; 348 #endif 349 } bits; 350 } rdc_red_para_t, *p_rdc_red_para_t; 351 352 /* 353 * RDC: Receive DMA Datapath Configuration 354 * The following register definitions are for 355 * each DMA channel. Each DMA CSR is 512 bytes 356 * (0x200). 357 */ 358 #define RXDMA_CFIG1_REG (DMC + 0x00000) 359 #define RXDMA_CFIG2_REG (DMC + 0x00008) 360 361 #define RXDMA_CFIG1_MBADDR_H_SHIFT 0 /* bits 11:0 */ 362 #define RXDMA_CFIG1_MBADDR_H_MASK 0x0000000000000fc0ULL 363 #define RXDMA_CFIG1_RST_SHIFT 30 /* bit 30 */ 364 #define RXDMA_CFIG1_RST 0x0000000040000000ULL 365 #define RXDMA_CFIG1_RST_MASK 0x0000000040000000ULL 366 #define RXDMA_CFIG1_EN_SHIFT 31 367 #define RXDMA_CFIG1_EN 0x0000000080000000ULL 368 #define RXDMA_CFIG1_EN_MASK 0x0000000080000000ULL 369 370 typedef union _rxdma_cfig1_t { 371 uint64_t value; 372 struct { 373 #if defined(_BIG_ENDIAN) 374 uint32_t hdw; 375 #endif 376 struct { 377 #if defined(_BIT_FIELDS_HTOL) 378 uint32_t en:1; 379 uint32_t rst:1; 380 uint32_t qst:1; 381 uint32_t res2:17; 382 uint32_t mbaddr_h:12; 383 #elif defined(_BIT_FIELDS_LTOH) 384 uint32_t mbaddr_h:12; 385 uint32_t res2:17; 386 uint32_t qst:1; 387 uint32_t rst:1; 388 uint32_t en:1; 389 #endif 390 } ldw; 391 #if !defined(_BIG_ENDIAN) 392 uint32_t hdw; 393 #endif 394 } bits; 395 } rxdma_cfig1_t, *p_rxdma_cfig1_t; 396 397 #define RXDMA_HDR_SIZE_DEFAULT 2 398 #define RXDMA_HDR_SIZE_FULL 18 399 400 #define RXDMA_CFIG2_FULL_HDR_SHIFT 0 /* Set to 1 */ 401 #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL 402 #define RXDMA_CFIG2_FULL_HDR_MASK 0x0000000000000001ULL 403 #define RXDMA_CFIG2_OFFSET_SHIFT 1 /* bit 3:1 */ 404 #define RXDMA_CFIG2_OFFSET_MASK 0x000000004000000eULL 405 #define RXDMA_CFIG2_MBADDR_L_SHIFT 6 /* bit 31:6 */ 406 #define RXDMA_CFIG2_MBADDR_L_MASK 0x00000000ffffffc0ULL 407 408 typedef union _rxdma_cfig2_t { 409 uint64_t value; 410 struct { 411 #if defined(_BIG_ENDIAN) 412 uint32_t hdw; 413 #endif 414 struct { 415 #if defined(_BIT_FIELDS_HTOL) 416 uint32_t mbaddr:26; 417 uint32_t res2:3; 418 uint32_t offset:2; 419 uint32_t full_hdr:1; 420 421 #elif defined(_BIT_FIELDS_LTOH) 422 uint32_t full_hdr:1; 423 uint32_t offset:2; 424 uint32_t res2:3; 425 uint32_t mbaddr:26; 426 #endif 427 } ldw; 428 #if !defined(_BIG_ENDIAN) 429 uint32_t hdw; 430 #endif 431 } bits; 432 } rxdma_cfig2_t, *p_rxdma_cfig2_t; 433 434 /* 435 * RDC: Receive Block Ring Configuration 436 * The following register definitions are for 437 * each DMA channel. 438 */ 439 #define RBR_CFIG_A_REG (DMC + 0x00010) 440 #define RBR_CFIG_B_REG (DMC + 0x00018) 441 #define RBR_KICK_REG (DMC + 0x00020) 442 #define RBR_STAT_REG (DMC + 0x00028) 443 #define RBR_HDH_REG (DMC + 0x00030) 444 #define RBR_HDL_REG (DMC + 0x00038) 445 446 #define RBR_CFIG_A_STADDR_SHIFT 6 /* bits 17:6 */ 447 #define RBR_CFIG_A_STDADDR_MASK 0x000000000003ffc0ULL 448 #define RBR_CFIG_A_STADDR_BASE_SHIFT 18 /* bits 43:18 */ 449 #define RBR_CFIG_A_STDADDR_BASE_MASK 0x00000ffffffc0000ULL 450 #define RBR_CFIG_A_LEN_SHIFT 48 /* bits 63:48 */ 451 #define RBR_CFIG_A_LEN_MASK 0xFFFF000000000000ULL 452 453 typedef union _rbr_cfig_a_t { 454 uint64_t value; 455 struct { 456 #if defined(_BIG_ENDIAN) 457 struct { 458 #if defined(_BIT_FIELDS_HTOL) 459 uint32_t len:16; 460 uint32_t res1:4; 461 uint32_t staddr_base:12; 462 #elif defined(_BIT_FIELDS_LTOH) 463 uint32_t staddr_base:12; 464 uint32_t res1:4; 465 uint32_t len:16; 466 #endif 467 } hdw; 468 #endif 469 struct { 470 #if defined(_BIT_FIELDS_HTOL) 471 uint32_t staddr_base:14; 472 uint32_t staddr:12; 473 uint32_t res2:6; 474 #elif defined(_BIT_FIELDS_LTOH) 475 uint32_t res2:6; 476 uint32_t staddr:12; 477 uint32_t staddr_base:14; 478 #endif 479 } ldw; 480 #if !defined(_BIG_ENDIAN) 481 struct { 482 #if defined(_BIT_FIELDS_HTOL) 483 uint32_t len:16; 484 uint32_t res1:4; 485 uint32_t staddr_base:12; 486 #elif defined(_BIT_FIELDS_LTOH) 487 uint32_t staddr_base:12; 488 uint32_t res1:4; 489 uint32_t len:16; 490 #endif 491 } hdw; 492 #endif 493 } bits; 494 } rbr_cfig_a_t, *p_rbr_cfig_a_t; 495 496 497 #define RBR_CFIG_B_BUFSZ0_SHIFT 0 /* bit 1:0 */ 498 #define RBR_CFIG_B_BUFSZ0_MASK 0x0000000000000001ULL 499 #define RBR_CFIG_B_VLD0_SHIFT 7 /* bit 7 */ 500 #define RBR_CFIG_B_VLD0 0x0000000000000008ULL 501 #define RBR_CFIG_B_VLD0_MASK 0x0000000000000008ULL 502 #define RBR_CFIG_B_BUFSZ1_SHIFT 8 /* bit 9:8 */ 503 #define RBR_CFIG_B_BUFSZ1_MASK 0x0000000000000300ULL 504 #define RBR_CFIG_B_VLD1_SHIFT 15 /* bit 15 */ 505 #define RBR_CFIG_B_VLD1 0x0000000000008000ULL 506 #define RBR_CFIG_B_VLD1_MASK 0x0000000000008000ULL 507 #define RBR_CFIG_B_BUFSZ2_SHIFT 16 /* bit 17:16 */ 508 #define RBR_CFIG_B_BUFSZ2_MASK 0x0000000000030000ULL 509 #define RBR_CFIG_B_VLD2_SHIFT 23 /* bit 23 */ 510 #define RBR_CFIG_B_VLD2 0x0000000000800000ULL 511 #define RBR_CFIG_B_BKSIZE_SHIFT 24 /* bit 25:24 */ 512 #define RBR_CFIG_B_BKSIZE_MASK 0x0000000003000000ULL 513 514 515 typedef union _rbr_cfig_b_t { 516 uint64_t value; 517 struct { 518 #if defined(_BIG_ENDIAN) 519 uint32_t hdw; 520 #endif 521 struct { 522 #if defined(_BIT_FIELDS_HTOL) 523 uint32_t res1_1:6; 524 uint32_t bksize:2; 525 uint32_t vld2:1; 526 uint32_t res2:5; 527 uint32_t bufsz2:2; 528 uint32_t vld1:1; 529 uint32_t res3:5; 530 uint32_t bufsz1:2; 531 uint32_t vld0:1; 532 uint32_t res4:5; 533 uint32_t bufsz0:2; 534 #elif defined(_BIT_FIELDS_LTOH) 535 uint32_t bufsz0:2; 536 uint32_t res4:5; 537 uint32_t vld0:1; 538 uint32_t bufsz1:2; 539 uint32_t res3:5; 540 uint32_t vld1:1; 541 uint32_t bufsz2:2; 542 uint32_t res2:5; 543 uint32_t vld2:1; 544 uint32_t bksize:2; 545 uint32_t res1_1:6; 546 #endif 547 } ldw; 548 #if !defined(_BIG_ENDIAN) 549 uint32_t hdw; 550 #endif 551 } bits; 552 } rbr_cfig_b_t, *p_rbr_cfig_b_t; 553 554 555 #define RBR_KICK_SHIFT 0 /* bit 15:0 */ 556 #define RBR_KICK_MASK 0x00000000000ffff1ULL 557 558 559 typedef union _rbr_kick_t { 560 uint64_t value; 561 struct { 562 #if defined(_BIG_ENDIAN) 563 uint32_t hdw; 564 #endif 565 struct { 566 #if defined(_BIT_FIELDS_HTOL) 567 uint32_t res1_1:16; 568 uint32_t bkadd:16; 569 #elif defined(_BIT_FIELDS_LTOH) 570 uint32_t bkadd:16; 571 uint32_t res1_1:16; 572 #endif 573 } ldw; 574 #if !defined(_BIG_ENDIAN) 575 uint32_t hdw; 576 #endif 577 } bits; 578 } rbr_kick_t, *p_rbr_kick_t; 579 580 #define RBR_STAT_QLEN_SHIFT 0 /* bit bit 15:0 */ 581 #define RBR_STAT_QLEN_MASK 0x000000000000ffffULL 582 #define RBR_STAT_OFLOW_SHIFT 16 /* bit 16 */ 583 #define RBR_STAT_OFLOW 0x0000000000010000ULL 584 #define RBR_STAT_OFLOW_MASK 0x0000000000010000ULL 585 586 typedef union _rbr_stat_t { 587 uint64_t value; 588 struct { 589 #if defined(_BIG_ENDIAN) 590 uint32_t hdw; 591 #endif 592 struct { 593 #if defined(_BIT_FIELDS_HTOL) 594 uint32_t res1_1:15; 595 uint32_t oflow:1; 596 uint32_t qlen:16; 597 #elif defined(_BIT_FIELDS_LTOH) 598 uint32_t qlen:16; 599 uint32_t oflow:1; 600 uint32_t res1_1:15; 601 #endif 602 } ldw; 603 #if !defined(_BIG_ENDIAN) 604 uint32_t hdw; 605 #endif 606 } bits; 607 } rbr_stat_t, *p_rbr_stat_t; 608 609 610 #define RBR_HDH_HEAD_H_SHIFT 0 /* bit 11:0 */ 611 #define RBR_HDH_HEAD_H_MASK 0x0000000000000fffULL 612 typedef union _rbr_hdh_t { 613 uint64_t value; 614 struct { 615 #if defined(_BIG_ENDIAN) 616 uint32_t hdw; 617 #endif 618 struct { 619 #if defined(_BIT_FIELDS_HTOL) 620 uint32_t res1_1:20; 621 uint32_t head_h:12; 622 #elif defined(_BIT_FIELDS_LTOH) 623 uint32_t head_h:12; 624 uint32_t res1_1:20; 625 #endif 626 } ldw; 627 #if !defined(_BIG_ENDIAN) 628 uint32_t hdw; 629 #endif 630 } bits; 631 } rbr_hdh_t, *p_rbr_hdh_t; 632 633 #define RBR_HDL_HEAD_L_SHIFT 2 /* bit 31:2 */ 634 #define RBR_HDL_HEAD_L_MASK 0x00000000FFFFFFFCULL 635 636 typedef union _rbr_hdl_t { 637 uint64_t value; 638 struct { 639 #if defined(_BIG_ENDIAN) 640 uint32_t hdw; 641 #endif 642 struct { 643 #if defined(_BIT_FIELDS_HTOL) 644 uint32_t head_l:30; 645 uint32_t res2:2; 646 #elif defined(_BIT_FIELDS_LTOH) 647 uint32_t res2:2; 648 uint32_t head_l:30; 649 #endif 650 } ldw; 651 #if !defined(_BIG_ENDIAN) 652 uint32_t hdw; 653 #endif 654 } bits; 655 } rbr_hdl_t, *p_rbr_hdl_t; 656 657 /* 658 * Receive Completion Ring (RCR) 659 */ 660 #define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */ 661 #define RCR_PKT_BUF_ADDR_SHIFT_FULL 6 /* fulll buffer address */ 662 #define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL 663 #define RCR_PKTBUFSZ_SHIFT 38 /* bit 39:38 */ 664 #define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL 665 #define RCR_L2_LEN_SHIFT 40 /* bit 39:38 */ 666 #define RCR_L2_LEN_MASK 0x003fff0000000000ULL 667 #define RCR_DCF_ERROR_SHIFT 54 /* bit 54 */ 668 #define RCR_DCF_ERROR_MASK 0x0040000000000000ULL 669 #define RCR_ERROR_SHIFT 55 /* bit 57:55 */ 670 #define RCR_ERROR_MASK 0x0380000000000000ULL 671 #define RCR_PROMIS_SHIFT 58 /* bit 58 */ 672 #define RCR_PROMIS_MASK 0x0400000000000000ULL 673 #define RCR_FRAG_SHIFT 59 /* bit 59 */ 674 #define RCR_FRAG_MASK 0x0800000000000000ULL 675 #define RCR_ZERO_COPY_SHIFT 60 /* bit 60 */ 676 #define RCR_ZERO_COPY_MASK 0x1000000000000000ULL 677 #define RCR_PKT_TYPE_SHIFT 61 /* bit 62:61 */ 678 #define RCR_PKT_TYPE_MASK 0x6000000000000000ULL 679 #define RCR_MULTI_SHIFT 63 /* bit 63 */ 680 #define RCR_MULTI_MASK 0x8000000000000000ULL 681 682 #define RCR_PKTBUFSZ_0 0x00 683 #define RCR_PKTBUFSZ_1 0x01 684 #define RCR_PKTBUFSZ_2 0x02 685 #define RCR_SINGLE_BLOCK 0x03 686 687 #define RCR_NO_ERROR 0x0 688 #define RCR_L2_ERROR 0x1 689 #define RCR_L4_CSUM_ERROR 0x3 690 #define RCR_FFLP_SOFT_ERROR 0x4 691 #define RCR_ZCP_SOFT_ERROR 0x5 692 #define RCR_ERROR_RESERVE 0x6 693 #define RCR_ERROR_RESERVE_END 0x7 694 695 #define RCR_PKT_TYPE_UDP 0x1 696 #define RCR_PKT_TYPE_TCP 0x2 697 #define RCR_PKT_TYPE_SCTP 0x3 698 #define RCR_PKT_TYPE_OTHERS 0x0 699 #define RCR_PKT_IS_TCP 0x2000000000000000ULL 700 #define RCR_PKT_IS_UDP 0x4000000000000000ULL 701 #define RCR_PKT_IS_SCTP 0x6000000000000000ULL 702 703 704 typedef union _rcr_entry_t { 705 uint64_t value; 706 struct { 707 #if defined(_BIG_ENDIAN) 708 struct { 709 #if defined(_BIT_FIELDS_HTOL) 710 uint32_t multi:1; 711 uint32_t pkt_type:2; 712 uint32_t zero_copy:1; 713 uint32_t noport:1; 714 uint32_t promis:1; 715 uint32_t error:3; 716 uint32_t dcf_err:1; 717 uint32_t l2_len:14; 718 uint32_t pktbufsz:2; 719 uint32_t pkt_buf_addr:6; 720 #elif defined(_BIT_FIELDS_LTOH) 721 uint32_t pkt_buf_addr:6; 722 uint32_t pktbufsz:2; 723 uint32_t l2_len:14; 724 uint32_t dcf_err:1; 725 uint32_t error:3; 726 uint32_t promis:1; 727 uint32_t noport:1; 728 uint32_t zero_copy:1; 729 uint32_t pkt_type:2; 730 uint32_t multi:1; 731 #endif 732 } hdw; 733 #endif 734 struct { 735 #if defined(_BIT_FIELDS_HTOL) 736 uint32_t pkt_buf_addr:32; 737 #elif defined(_BIT_FIELDS_LTOH) 738 uint32_t pkt_buf_addr:32; 739 #endif 740 } ldw; 741 #if !defined(_BIG_ENDIAN) 742 struct { 743 #if defined(_BIT_FIELDS_HTOL) 744 uint32_t multi:1; 745 uint32_t pkt_type:2; 746 uint32_t zero_copy:1; 747 uint32_t noport:1; 748 uint32_t promis:1; 749 uint32_t error:3; 750 uint32_t dcf_err:1; 751 uint32_t l2_len:14; 752 uint32_t pktbufsz:2; 753 uint32_t pkt_buf_addr:6; 754 #elif defined(_BIT_FIELDS_LTOH) 755 uint32_t pkt_buf_addr:6; 756 uint32_t pktbufsz:2; 757 uint32_t l2_len:14; 758 uint32_t dcf_err:1; 759 uint32_t error:3; 760 uint32_t promis:1; 761 uint32_t noport:1; 762 uint32_t zero_copy:1; 763 uint32_t pkt_type:2; 764 uint32_t multi:1; 765 #endif 766 } hdw; 767 #endif 768 } bits; 769 } rcr_entry_t, *p_rcr_entry_t; 770 771 /* 772 * Receive Completion Ring Configuration. 773 * (for each DMA channel) 774 */ 775 #define RCRCFIG_A_REG (DMC + 0x00040) 776 #define RCRCFIG_B_REG (DMC + 0x00048) 777 #define RCRSTAT_A_REG (DMC + 0x00050) 778 #define RCRSTAT_B_REG (DMC + 0x00058) 779 #define RCRSTAT_C_REG (DMC + 0x00060) 780 #define RX_DMA_ENT_MSK_REG (DMC + 0x00068) 781 #define RX_DMA_CTL_STAT_REG (DMC + 0x00070) 782 #define RCR_FLSH_REG (DMC + 0x00078) 783 #if OLD 784 #define RX_DMA_LOGA_REG (DMC + 0x00080) 785 #define RX_DMA_LOGB_REG (DMC + 0x00088) 786 #endif 787 #define RX_DMA_CTL_STAT_DBG_REG (DMC + 0x00098) 788 789 /* (DMC + 0x00050) */ 790 #define RCRCFIG_A_STADDR_SHIFT 6 /* bit 18:6 */ 791 #define RCRCFIG_A_STADDR_MASK 0x000000000007FFC0ULL 792 #define RCRCFIG_A_STADDR_BASE_SHIF 19 /* bit 43:19 */ 793 #define RCRCFIG_A_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 794 #define RCRCFIG_A_LEN_SHIF 48 /* bit 63:48 */ 795 #define RCRCFIG_A_LEN__MASK 0xFFFF000000000000ULL 796 797 /* (DMC + 0x00058) */ 798 #define RCRCFIG_B_TIMEOUT_SHIFT 0 /* bit 5:0 */ 799 #define RCRCFIG_B_TIMEOUT_MASK 0x000000000000003FULL 800 #define RCRCFIG_B_ENTOUT_SHIFT 15 /* bit 15 */ 801 #define RCRCFIG_B_TIMEOUT 0x0000000000008000ULL 802 #define RCRCFIG_B_PTHRES_SHIFT 16 /* bit 31:16 */ 803 #define RCRCFIG_B_PTHRES_MASK 0x00000000FFFF0000ULL 804 805 /* (DMC + 0x00060) */ 806 #define RCRSTAT_A_QLEN_SHIFT 0 /* bit 15:0 */ 807 #define RCRSTAT_A_QLEN_MASK 0x000000000000FFFFULL 808 #define RCRSTAT_A_PKT_OFL_SHIFT 16 /* bit 16 */ 809 #define RCRSTAT_A_PKT_OFL_MASK 0x0000000000010000ULL 810 #define RCRSTAT_A_ENT_OFL_SHIFT 17 /* bit 17 */ 811 #define RCRSTAT_A_ENT_QFL_MASK 0x0000000000020000ULL 812 813 #define RCRSTAT_C_TLPTR_H_SHIFT 0 /* bit 11:0 */ 814 #define RCRSTAT_C_TLPTR_H_MASK 0x0000000000000FFFULL 815 816 #define RCRSTAT_D_TLPTR_L_SHIFT 3 /* bit 31:3 */ 817 #define RCRSTAT_D_TLPTR_L_MASK 0x00000000FFFFFFF8ULL 818 819 /* Receive DMA Interrupt Behavior: Event Mask (DMC + 0x00068) */ 820 #define RX_DMA_ENT_MSK_CFIGLOGPGE_SHIFT 0 /* bit 0: 0 to flag */ 821 #define RX_DMA_ENT_MSK_CFIGLOGPGE_MASK 0x0000000000000001ULL 822 #define RX_DMA_ENT_MSK_RBRLOGPGE_SHIFT 1 /* bit 1: 0 to flag */ 823 #define RX_DMA_ENT_MSK_RBRLOGPGE_MASK 0x0000000000000002ULL 824 #define RX_DMA_ENT_MSK_RBRFULL_SHIFT 2 /* bit 2: 0 to flag */ 825 #define RX_DMA_ENT_MSK_RBRFULL_MASK 0x0000000000000004ULL 826 #define RX_DMA_ENT_MSK_RBREMPTY_SHIFT 3 /* bit 3: 0 to flag */ 827 #define RX_DMA_ENT_MSK_RBREMPTY_MASK 0x0000000000000008ULL 828 #define RX_DMA_ENT_MSK_RCRFULL_SHIFT 4 /* bit 4: 0 to flag */ 829 #define RX_DMA_ENT_MSK_RCRFULL_MASK 0x0000000000000010ULL 830 #define RX_DMA_ENT_MSK_RCRINCON_SHIFT 5 /* bit 5: 0 to flag */ 831 #define RX_DMA_ENT_MSK_RCRINCON_MASK 0x0000000000000020ULL 832 #define RX_DMA_ENT_MSK_CONFIG_ERR_SHIFT 6 /* bit 6: 0 to flag */ 833 #define RX_DMA_ENT_MSK_CONFIG_ERR_MASK 0x0000000000000040ULL 834 #define RX_DMA_ENT_MSK_RCRSH_FULL_SHIFT 7 /* bit 7: 0 to flag */ 835 #define RX_DMA_ENT_MSK_RCRSH_FULL_MASK 0x0000000000000080ULL 836 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_SHIFT 8 /* bit 8: 0 to flag */ 837 #define RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK 0x0000000000000100ULL 838 #define RX_DMA_ENT_MSK_WRED_DROP_SHIFT 9 /* bit 9: 0 to flag */ 839 #define RX_DMA_ENT_MSK_WRED_DROP_MASK 0x0000000000000200ULL 840 #define RX_DMA_ENT_MSK_PTDROP_PKT_SHIFT 10 /* bit 10: 0 to flag */ 841 #define RX_DMA_ENT_MSK_PTDROP_PKT_MASK 0x0000000000000400ULL 842 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_SHIFT 11 /* bit 11: 0 to flag */ 843 #define RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK 0x0000000000000800ULL 844 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_SHIFT 12 /* bit 12: 0 to flag */ 845 #define RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK 0x0000000000001000ULL 846 #define RX_DMA_ENT_MSK_RCRTO_SHIFT 13 /* bit 13: 0 to flag */ 847 #define RX_DMA_ENT_MSK_RCRTO_MASK 0x0000000000002000ULL 848 #define RX_DMA_ENT_MSK_THRES_SHIFT 14 /* bit 14: 0 to flag */ 849 #define RX_DMA_ENT_MSK_THRES_MASK 0x0000000000004000ULL 850 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_SHIFT 16 /* bit 16: 0 to flag */ 851 #define RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK 0x0000000000010000ULL 852 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_SHIFT 17 /* bit 17: 0 to flag */ 853 #define RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK 0x0000000000020000ULL 854 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_SHIFT 18 /* bit 18: 0 to flag */ 855 #define RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK 0x0000000000040000ULL 856 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_SHIFT 19 /* bit 19: 0 to flag */ 857 #define RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK 0x0000000000080000ULL 858 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_SHIFT 20 /* bit 20: 0 to flag */ 859 #define RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK 0x0000000000100000ULL 860 #define RX_DMA_ENT_MSK_RBR_TMOUT_SHIFT 21 /* bit 21: 0 to flag */ 861 #define RX_DMA_ENT_MSK_RBR_TMOUT_MASK 0x0000000000200000ULL 862 #define RX_DMA_ENT_MSK_ALL (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | \ 863 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | \ 864 RX_DMA_ENT_MSK_RBRFULL_MASK | \ 865 RX_DMA_ENT_MSK_RBREMPTY_MASK | \ 866 RX_DMA_ENT_MSK_RCRFULL_MASK | \ 867 RX_DMA_ENT_MSK_RCRINCON_MASK | \ 868 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | \ 869 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | \ 870 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | \ 871 RX_DMA_ENT_MSK_WRED_DROP_MASK | \ 872 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 873 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | \ 874 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | \ 875 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | \ 876 RX_DMA_ENT_MSK_RCRTO_MASK | \ 877 RX_DMA_ENT_MSK_THRES_MASK | \ 878 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | \ 879 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | \ 880 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | \ 881 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | \ 882 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | \ 883 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 884 885 /* Receive DMA Control and Status (DMC + 0x00070) */ 886 #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */ 887 #define RX_DMA_CTL_STAT_PKTREAD_MASK 0x000000000000ffffULL 888 #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16 /* WO, bit 31:16 */ 889 #define RX_DMA_CTL_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL 890 #define RX_DMA_CTL_STAT_CFIGLOGPG_SHIFT 32 /* RO, bit 32 */ 891 #define RX_DMA_CTL_STAT_CFIGLOGPG 0x0000000100000000ULL 892 #define RX_DMA_CTL_STAT_CFIGLOGPG_MASK 0x0000000100000000ULL 893 #define RX_DMA_CTL_STAT_RBRLOGPG_SHIFT 33 /* RO, bit 33 */ 894 #define RX_DMA_CTL_STAT_RBRLOGPG 0x0000000200000000ULL 895 #define RX_DMA_CTL_STAT_RBRLOGPG_MASK 0x0000000200000000ULL 896 #define RX_DMA_CTL_STAT_RBRFULL_SHIFT 34 /* RO, bit 34 */ 897 #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL 898 #define RX_DMA_CTL_STAT_RBRFULL_MASK 0x0000000400000000ULL 899 #define RX_DMA_CTL_STAT_RBREMPTY_SHIFT 35 /* RW1C, bit 35 */ 900 #define RX_DMA_CTL_STAT_RBREMPTY 0x0000000800000000ULL 901 #define RX_DMA_CTL_STAT_RBREMPTY_MASK 0x0000000800000000ULL 902 #define RX_DMA_CTL_STAT_RCRFULL_SHIFT 36 /* RW1C, bit 36 */ 903 #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL 904 #define RX_DMA_CTL_STAT_RCRFULL_MASK 0x0000001000000000ULL 905 #define RX_DMA_CTL_STAT_RCRINCON_SHIFT 37 /* RO, bit 37 */ 906 #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL 907 #define RX_DMA_CTL_STAT_RCRINCON_MASK 0x0000002000000000ULL 908 #define RX_DMA_CTL_STAT_CONFIG_ERR_SHIFT 38 /* RO, bit 38 */ 909 #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL 910 #define RX_DMA_CTL_STAT_CONFIG_ERR_MASK 0x0000004000000000ULL 911 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_SHIFT 39 /* RO, bit 39 */ 912 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL 0x0000008000000000ULL 913 #define RX_DMA_CTL_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL 914 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 915 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_SHIFT 40 /* RO, bit 40 */ 916 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL 917 #define RX_DMA_CTL_STAT_RBR_PRE_EMTY_MASK 0x0000010000000000ULL 918 #define RX_DMA_CTL_STAT_WRED_DROP_SHIFT 41 /* RO, bit 41 */ 919 #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL 920 #define RX_DMA_CTL_STAT_WRED_DROP_MASK 0x0000020000000000ULL 921 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_SHIFT 42 /* RO, bit 42 */ 922 #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL 923 #define RX_DMA_CTL_STAT_PORT_DROP_PKT_MASK 0x0000040000000000ULL 924 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_SHIFT 43 /* RO, bit 43 */ 925 #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL 926 #define RX_DMA_CTL_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL 927 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_SHIFT 44 /* RO, bit 44 */ 928 #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL 929 #define RX_DMA_CTL_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL 930 #define RX_DMA_CTL_STAT_RCRTO_SHIFT 45 /* RW1C, bit 45 */ 931 #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL 932 #define RX_DMA_CTL_STAT_RCRTO_MASK 0x0000200000000000ULL 933 #define RX_DMA_CTL_STAT_RCRTHRES_SHIFT 46 /* RO, bit 46 */ 934 #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL 935 #define RX_DMA_CTL_STAT_RCRTHRES_MASK 0x0000400000000000ULL 936 #define RX_DMA_CTL_STAT_MEX_SHIFT 47 /* RW, bit 47 */ 937 #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL 938 #define RX_DMA_CTL_STAT_MEX_MASK 0x0000800000000000ULL 939 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_SHIFT 48 /* RW1C, bit 48 */ 940 #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL 941 #define RX_DMA_CTL_STAT_DC_FIFO_ERR_MASK 0x0001000000000000ULL 942 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_SHIFT 49 /* RO, bit 49 */ 943 #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL 944 #define RX_DMA_CTL_STAT_RCR_ACK_ERR_MASK 0x0002000000000000ULL 945 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_SHIFT 50 /* RO, bit 50 */ 946 #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL 947 #define RX_DMA_CTL_STAT_RSP_DAT_ERR_MASK 0x0004000000000000ULL 948 949 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_SHIFT 51 /* RO, bit 51 */ 950 #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL 951 #define RX_DMA_CTL_STAT_BYTE_EN_BUS_MASK 0x0008000000000000ULL 952 953 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_SHIFT 52 /* RO, bit 52 */ 954 #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL 955 #define RX_DMA_CTL_STAT_RSP_CNT_ERR_MASK 0x0010000000000000ULL 956 957 #define RX_DMA_CTL_STAT_RBR_TMOUT_SHIFT 53 /* RO, bit 53 */ 958 #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL 959 #define RX_DMA_CTL_STAT_RBR_TMOUT_MASK 0x0020000000000000ULL 960 #define RX_DMA_CTRL_STAT_ENT_MASK_SHIFT 32 961 #define RX_DMA_CTL_STAT_ERROR (RX_DMA_ENT_MSK_ALL << \ 962 RX_DMA_CTRL_STAT_ENT_MASK_SHIFT) 963 964 /* the following are write 1 to clear bits */ 965 #define RX_DMA_CTL_STAT_WR1C RX_DMA_CTL_STAT_RBREMPTY | \ 966 RX_DMA_CTL_STAT_RCR_SHDW_FULL | \ 967 RX_DMA_CTL_STAT_RBR_PRE_EMTY | \ 968 RX_DMA_CTL_STAT_WRED_DROP | \ 969 RX_DMA_CTL_STAT_PORT_DROP_PKT | \ 970 RX_DMA_CTL_STAT_RCRTO | \ 971 RX_DMA_CTL_STAT_RCRTHRES | \ 972 RX_DMA_CTL_STAT_DC_FIFO_ERR 973 974 /* Receive DMA Interrupt Behavior: Force an update to RCR (DMC + 0x00078 */ 975 #define RCR_FLSH_SHIFT 0 /* RW, bit 0:0 */ 976 #define RCR_FLSH_SET 0x0000000000000001ULL 977 #define RCR_FLSH_MASK 0x0000000000000001ULL 978 979 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00080 */ 980 #define RX_DMA_LOGA_ADDR_SHIFT 0 /* RO, bit 11:0 */ 981 #define RX_DMA_LOGA_ADDR 0x0000000000000FFFULL 982 #define RX_DMA_LOGA_ADDR_MASK 0x0000000000000FFFULL 983 #define RX_DMA_LOGA_TYPE_SHIFT 28 /* RO, bit 30:28 */ 984 #define RX_DMA_LOGA_TYPE 0x0000000070000000ULL 985 #define RX_DMA_LOGA_TYPE_MASK 0x0000000070000FFFULL 986 #define RX_DMA_LOGA_MULTI_SHIFT 28 /* RO, bit 30:28 */ 987 #define RX_DMA_LOGA_MULTI 0x0000000080000000ULL 988 #define RX_DMA_LOGA_MULTI_MASK 0x0000000080000FFFULL 989 990 /* Receive DMA Interrupt Behavior: the first error log (DMC + 0x00088 */ 991 #define RX_DMA_LOGA_ADDR_L_SHIFT 0 /* RO, bit 31:0 */ 992 #define RX_DMA_LOGA_ADDRL_L 0x00000000FFFFFFFFULL 993 #define RX_DMA_LOGA_ADDR_LMASK 0x00000000FFFFFFFFULL 994 995 typedef union _rcrcfig_a_t { 996 uint64_t value; 997 struct { 998 #if defined(_BIG_ENDIAN) 999 struct { 1000 #if defined(_BIT_FIELDS_HTOL) 1001 uint32_t len:16; 1002 uint32_t res1:4; 1003 uint32_t staddr_base:12; 1004 #elif defined(_BIT_FIELDS_LTOH) 1005 uint32_t staddr_base:12; 1006 uint32_t res1:4; 1007 uint32_t len:16; 1008 #endif 1009 } hdw; 1010 #endif 1011 struct { 1012 #if defined(_BIT_FIELDS_HTOL) 1013 uint32_t staddr_base:13; 1014 uint32_t staddr:13; 1015 uint32_t res2:6; 1016 #elif defined(_BIT_FIELDS_LTOH) 1017 uint32_t res2:6; 1018 uint32_t staddr:13; 1019 uint32_t staddr_base:13; 1020 #endif 1021 } ldw; 1022 #if !defined(_BIG_ENDIAN) 1023 struct { 1024 #if defined(_BIT_FIELDS_HTOL) 1025 uint32_t len:16; 1026 uint32_t res1:4; 1027 uint32_t staddr_base:12; 1028 #elif defined(_BIT_FIELDS_LTOH) 1029 uint32_t staddr_base:12; 1030 uint32_t res1:4; 1031 uint32_t len:16; 1032 #endif 1033 } hdw; 1034 #endif 1035 } bits; 1036 } rcrcfig_a_t, *p_rcrcfig_a_t; 1037 1038 1039 typedef union _rcrcfig_b_t { 1040 uint64_t value; 1041 struct { 1042 #if defined(_BIG_ENDIAN) 1043 uint32_t hdw; 1044 #endif 1045 struct { 1046 #if defined(_BIT_FIELDS_HTOL) 1047 uint32_t pthres:16; 1048 uint32_t entout:1; 1049 uint32_t res1:9; 1050 uint32_t timeout:6; 1051 #elif defined(_BIT_FIELDS_LTOH) 1052 uint32_t timeout:6; 1053 uint32_t res1:9; 1054 uint32_t entout:1; 1055 uint32_t pthres:16; 1056 #endif 1057 } ldw; 1058 #if !defined(_BIG_ENDIAN) 1059 uint32_t hdw; 1060 #endif 1061 } bits; 1062 } rcrcfig_b_t, *p_rcrcfig_b_t; 1063 1064 1065 typedef union _rcrstat_a_t { 1066 uint64_t value; 1067 struct { 1068 #if defined(_BIG_ENDIAN) 1069 uint32_t hdw; 1070 #endif 1071 struct { 1072 #if defined(_BIT_FIELDS_HTOL) 1073 uint32_t res1:16; 1074 uint32_t qlen:16; 1075 #elif defined(_BIT_FIELDS_LTOH) 1076 uint32_t qlen:16; 1077 uint32_t res1:16; 1078 #endif 1079 } ldw; 1080 #if !defined(_BIG_ENDIAN) 1081 uint32_t hdw; 1082 #endif 1083 } bits; 1084 } rcrstat_a_t, *p_rcrstat_a_t; 1085 1086 1087 typedef union _rcrstat_b_t { 1088 uint64_t value; 1089 struct { 1090 #if defined(_BIG_ENDIAN) 1091 uint32_t hdw; 1092 #endif 1093 struct { 1094 #if defined(_BIT_FIELDS_HTOL) 1095 uint32_t res1:20; 1096 uint32_t tlptr_h:12; 1097 #elif defined(_BIT_FIELDS_LTOH) 1098 uint32_t tlptr_h:12; 1099 uint32_t res1:20; 1100 #endif 1101 } ldw; 1102 #if !defined(_BIG_ENDIAN) 1103 uint32_t hdw; 1104 #endif 1105 } bits; 1106 } rcrstat_b_t, *p_rcrstat_b_t; 1107 1108 1109 typedef union _rcrstat_c_t { 1110 uint64_t value; 1111 struct { 1112 #if defined(_BIG_ENDIAN) 1113 uint32_t hdw; 1114 #endif 1115 struct { 1116 #if defined(_BIT_FIELDS_HTOL) 1117 uint32_t tlptr_l:29; 1118 uint32_t res1:3; 1119 #elif defined(_BIT_FIELDS_LTOH) 1120 uint32_t res1:3; 1121 uint32_t tlptr_l:29; 1122 #endif 1123 } ldw; 1124 #if !defined(_BIG_ENDIAN) 1125 uint32_t hdw; 1126 #endif 1127 } bits; 1128 } rcrstat_c_t, *p_rcrstat_c_t; 1129 1130 1131 /* Receive DMA Event Mask */ 1132 typedef union _rx_dma_ent_msk_t { 1133 uint64_t value; 1134 struct { 1135 #if defined(_BIG_ENDIAN) 1136 uint32_t hdw; 1137 #endif 1138 struct { 1139 #if defined(_BIT_FIELDS_HTOL) 1140 uint32_t rsrvd2:10; 1141 uint32_t rbr_tmout:1; 1142 uint32_t rsp_cnt_err:1; 1143 uint32_t byte_en_bus:1; 1144 uint32_t rsp_dat_err:1; 1145 uint32_t rcr_ack_err:1; 1146 uint32_t dc_fifo_err:1; 1147 uint32_t rsrvd:1; 1148 uint32_t rcrthres:1; 1149 uint32_t rcrto:1; 1150 uint32_t rcr_sha_par:1; 1151 uint32_t rbr_pre_par:1; 1152 uint32_t port_drop_pkt:1; 1153 uint32_t wred_drop:1; 1154 uint32_t rbr_pre_empty:1; 1155 uint32_t rcr_shadow_full:1; 1156 uint32_t config_err:1; 1157 uint32_t rcrincon:1; 1158 uint32_t rcrfull:1; 1159 uint32_t rbr_empty:1; 1160 uint32_t rbrfull:1; 1161 uint32_t rbrlogpage:1; 1162 uint32_t cfiglogpage:1; 1163 #elif defined(_BIT_FIELDS_LTOH) 1164 uint32_t cfiglogpage:1; 1165 uint32_t rbrlogpage:1; 1166 uint32_t rbrfull:1; 1167 uint32_t rbr_empty:1; 1168 uint32_t rcrfull:1; 1169 uint32_t rcrincon:1; 1170 uint32_t config_err:1; 1171 uint32_t rcr_shadow_full:1; 1172 uint32_t rbr_pre_empty:1; 1173 uint32_t wred_drop:1; 1174 uint32_t port_drop_pkt:1; 1175 uint32_t rbr_pre_par:1; 1176 uint32_t rcr_sha_par:1; 1177 uint32_t rcrto:1; 1178 uint32_t rcrthres:1; 1179 uint32_t rsrvd:1; 1180 uint32_t dc_fifo_err:1; 1181 uint32_t rcr_ack_err:1; 1182 uint32_t rsp_dat_err:1; 1183 uint32_t byte_en_bus:1; 1184 uint32_t rsp_cnt_err:1; 1185 uint32_t rbr_tmout:1; 1186 uint32_t rsrvd2:10; 1187 #endif 1188 } ldw; 1189 #if !defined(_BIG_ENDIAN) 1190 uint32_t hdw; 1191 #endif 1192 } bits; 1193 } rx_dma_ent_msk_t, *p_rx_dma_ent_msk_t; 1194 1195 1196 /* Receive DMA Control and Status */ 1197 typedef union _rx_dma_ctl_stat_t { 1198 uint64_t value; 1199 struct { 1200 #if defined(_BIG_ENDIAN) 1201 struct { 1202 #if defined(_BIT_FIELDS_HTOL) 1203 uint32_t rsrvd:10; 1204 uint32_t rbr_tmout:1; 1205 uint32_t rsp_cnt_err:1; 1206 uint32_t byte_en_bus:1; 1207 uint32_t rsp_dat_err:1; 1208 uint32_t rcr_ack_err:1; 1209 uint32_t dc_fifo_err:1; 1210 uint32_t mex:1; 1211 uint32_t rcrthres:1; 1212 uint32_t rcrto:1; 1213 uint32_t rcr_sha_par:1; 1214 uint32_t rbr_pre_par:1; 1215 uint32_t port_drop_pkt:1; 1216 uint32_t wred_drop:1; 1217 uint32_t rbr_pre_empty:1; 1218 uint32_t rcr_shadow_full:1; 1219 uint32_t config_err:1; 1220 uint32_t rcrincon:1; 1221 uint32_t rcrfull:1; 1222 uint32_t rbr_empty:1; 1223 uint32_t rbrfull:1; 1224 uint32_t rbrlogpage:1; 1225 uint32_t cfiglogpage:1; 1226 #elif defined(_BIT_FIELDS_LTOH) 1227 uint32_t cfiglogpage:1; 1228 uint32_t rbrlogpage:1; 1229 uint32_t rbrfull:1; 1230 uint32_t rbr_empty:1; 1231 uint32_t rcrfull:1; 1232 uint32_t rcrincon:1; 1233 uint32_t config_err:1; 1234 uint32_t rcr_shadow_full:1; 1235 uint32_t rbr_pre_empty:1; 1236 uint32_t wred_drop:1; 1237 uint32_t port_drop_pkt:1; 1238 uint32_t rbr_pre_par:1; 1239 uint32_t rcr_sha_par:1; 1240 uint32_t rcrto:1; 1241 uint32_t rcrthres:1; 1242 uint32_t mex:1; 1243 uint32_t dc_fifo_err:1; 1244 uint32_t rcr_ack_err:1; 1245 uint32_t rsp_dat_err:1; 1246 uint32_t byte_en_bus:1; 1247 uint32_t rsp_cnt_err:1; 1248 uint32_t rbr_tmout:1; 1249 uint32_t rsrvd:10; 1250 #endif 1251 } hdw; 1252 1253 #endif 1254 struct { 1255 #if defined(_BIT_FIELDS_HTOL) 1256 uint32_t ptrread:16; 1257 uint32_t pktread:16; 1258 #elif defined(_BIT_FIELDS_LTOH) 1259 uint32_t pktread:16; 1260 uint32_t ptrread:16; 1261 1262 #endif 1263 } ldw; 1264 #if !defined(_BIG_ENDIAN) 1265 struct { 1266 #if defined(_BIT_FIELDS_HTOL) 1267 uint32_t rsrvd:10; 1268 uint32_t rbr_tmout:1; 1269 uint32_t rsp_cnt_err:1; 1270 uint32_t byte_en_bus:1; 1271 uint32_t rsp_dat_err:1; 1272 uint32_t rcr_ack_err:1; 1273 uint32_t dc_fifo_err:1; 1274 uint32_t mex:1; 1275 uint32_t rcrthres:1; 1276 uint32_t rcrto:1; 1277 uint32_t rcr_sha_par:1; 1278 uint32_t rbr_pre_par:1; 1279 uint32_t port_drop_pkt:1; 1280 uint32_t wred_drop:1; 1281 uint32_t rbr_pre_empty:1; 1282 uint32_t rcr_shadow_full:1; 1283 uint32_t config_err:1; 1284 uint32_t rcrincon:1; 1285 uint32_t rcrfull:1; 1286 uint32_t rbr_empty:1; 1287 uint32_t rbrfull:1; 1288 uint32_t rbrlogpage:1; 1289 uint32_t cfiglogpage:1; 1290 #elif defined(_BIT_FIELDS_LTOH) 1291 uint32_t cfiglogpage:1; 1292 uint32_t rbrlogpage:1; 1293 uint32_t rbrfull:1; 1294 uint32_t rbr_empty:1; 1295 uint32_t rcrfull:1; 1296 uint32_t rcrincon:1; 1297 uint32_t config_err:1; 1298 uint32_t rcr_shadow_full:1; 1299 uint32_t rbr_pre_empty:1; 1300 uint32_t wred_drop:1; 1301 uint32_t port_drop_pkt:1; 1302 uint32_t rbr_pre_par:1; 1303 uint32_t rcr_sha_par:1; 1304 uint32_t rcrto:1; 1305 uint32_t rcrthres:1; 1306 uint32_t mex:1; 1307 uint32_t dc_fifo_err:1; 1308 uint32_t rcr_ack_err:1; 1309 uint32_t rsp_dat_err:1; 1310 uint32_t byte_en_bus:1; 1311 uint32_t rsp_cnt_err:1; 1312 uint32_t rbr_tmout:1; 1313 uint32_t rsrvd:10; 1314 #endif 1315 } hdw; 1316 #endif 1317 } bits; 1318 } rx_dma_ctl_stat_t, *p_rx_dma_ctl_stat_t; 1319 1320 typedef union _rcr_flsh_t { 1321 uint64_t value; 1322 struct { 1323 #if defined(_BIG_ENDIAN) 1324 uint32_t hdw; 1325 #endif 1326 struct { 1327 #if defined(_BIT_FIELDS_HTOL) 1328 uint32_t res1_1:31; 1329 uint32_t flsh:1; 1330 #elif defined(_BIT_FIELDS_LTOH) 1331 uint32_t flsh:1; 1332 uint32_t res1_1:31; 1333 #endif 1334 } ldw; 1335 #if !defined(_BIG_ENDIAN) 1336 uint32_t hdw; 1337 #endif 1338 } bits; 1339 } rcr_flsh_t, *p_rcr_flsh_t; 1340 1341 1342 typedef union _rx_dma_loga_t { 1343 uint64_t value; 1344 struct { 1345 #if defined(_BIG_ENDIAN) 1346 uint32_t hdw; 1347 #endif 1348 struct { 1349 #if defined(_BIT_FIELDS_HTOL) 1350 uint32_t multi:1; 1351 uint32_t type:3; 1352 uint32_t res1:16; 1353 uint32_t addr:12; 1354 #elif defined(_BIT_FIELDS_LTOH) 1355 uint32_t addr:12; 1356 uint32_t res1:16; 1357 uint32_t type:3; 1358 uint32_t multi:1; 1359 #endif 1360 } ldw; 1361 #if !defined(_BIG_ENDIAN) 1362 uint32_t hdw; 1363 #endif 1364 } bits; 1365 } rx_dma_loga_t, *p_rx_dma_loga_t; 1366 1367 1368 typedef union _rx_dma_logb_t { 1369 uint64_t value; 1370 struct { 1371 #if defined(_BIG_ENDIAN) 1372 uint32_t hdw; 1373 #endif 1374 struct { 1375 #if defined(_BIT_FIELDS_HTOL) 1376 uint32_t addr_l:32; 1377 #elif defined(_BIT_FIELDS_LTOH) 1378 uint32_t addr_l:32; 1379 #endif 1380 } ldw; 1381 #if !defined(_BIG_ENDIAN) 1382 uint32_t hdw; 1383 #endif 1384 } bits; 1385 } rx_dma_logb_t, *p_rx_dma_logb_t; 1386 1387 1388 #define RX_DMA_MAILBOX_BYTE_LENGTH 64 1389 #define RX_DMA_MBOX_UNUSED_1 8 1390 #define RX_DMA_MBOX_UNUSED_2 16 1391 1392 typedef struct _rxdma_mailbox_t { 1393 rx_dma_ctl_stat_t rxdma_ctl_stat; /* 8 bytes */ 1394 rbr_stat_t rbr_stat; /* 8 bytes */ 1395 uint32_t rbr_hdl; /* 4 bytes (31:0) */ 1396 uint32_t rbr_hdh; /* 4 bytes (31:0) */ 1397 uint32_t resv_1[RX_DMA_MBOX_UNUSED_1]; 1398 uint32_t rcrstat_c; /* 4 bytes (31:0) */ 1399 uint32_t rcrstat_b; /* 4 bytes (31:0) */ 1400 rcrstat_a_t rcrstat_a; /* 8 bytes */ 1401 uint32_t resv_2[RX_DMA_MBOX_UNUSED_2]; 1402 } rxdma_mailbox_t, *p_rxdma_mailbox_t; 1403 1404 1405 1406 typedef union _rx_disc_cnt_t { 1407 uint64_t value; 1408 struct { 1409 #if defined(_BIG_ENDIAN) 1410 uint32_t hdw; 1411 #endif 1412 struct { 1413 #if defined(_BIT_FIELDS_HTOL) 1414 uint32_t res_1:15; 1415 uint32_t oflow:1; 1416 uint32_t count:16; 1417 #elif defined(_BIT_FIELDS_LTOH) 1418 uint32_t count:16; 1419 uint32_t oflow:1; 1420 uint32_t res_1:15; 1421 #endif 1422 } ldw; 1423 #if !defined(_BIG_ENDIAN) 1424 uint32_t hdw; 1425 #endif 1426 } bits; 1427 } rx_disc_cnt_t, *p_rx_disc_cnt_t; 1428 1429 #define RXMISC_DISCARD_REG (DMC + 0x00090) 1430 1431 #if OLD 1432 /* 1433 * RBR Empty: If the RBR is empty or the prefetch buffer is empty, 1434 * packets will be discarded (Each RBR has one). 1435 * (16 channels, 0x200) 1436 */ 1437 #define RDC_PRE_EMPTY_REG (DMC + 0x000B0) 1438 #define RDC_PRE_EMPTY_OFFSET(channel) (RDC_PRE_EMPTY_REG + \ 1439 (DMC_OFFSET(channel)) 1440 1441 typedef union _rdc_pre_empty_t { 1442 uint64_t value; 1443 struct { 1444 #if defined(_BIG_ENDIAN) 1445 uint32_t hdw; 1446 #endif 1447 struct { 1448 #if defined(_BIT_FIELDS_HTOL) 1449 uint32_t res_1:15; 1450 uint32_t oflow:1; 1451 uint32_t count:16; 1452 #elif defined(_BIT_FIELDS_LTOH) 1453 uint32_t count:16; 1454 uint32_t oflow:1; 1455 uint32_t res_1:15; 1456 #endif 1457 } ldw; 1458 #if !defined(_BIG_ENDIAN) 1459 uint32_t hdw; 1460 #endif 1461 } bits; 1462 } rdc_pre_empty_t, *p_rdc_pre_empty_t; 1463 #endif 1464 1465 1466 #define FZC_DMC_REG_SIZE 0x20 1467 #define FZC_DMC_OFFSET(channel) (FZC_DMC_REG_SIZE * channel) 1468 1469 /* WRED discard count register (16, 0x40) */ 1470 #define RED_DIS_CNT_REG (FZC_DMC + 0x30008) 1471 #define RED_DMC_OFFSET(channel) (0x40 * channel) 1472 #define RDC_DIS_CNT_OFFSET(rdc) (RED_DIS_CNT_REG + RED_DMC_OFFSET(rdc)) 1473 1474 typedef union _red_disc_cnt_t { 1475 uint64_t value; 1476 struct { 1477 #if defined(_BIG_ENDIAN) 1478 uint32_t hdw; 1479 #endif 1480 struct { 1481 #if defined(_BIT_FIELDS_HTOL) 1482 uint32_t res_1:15; 1483 uint32_t oflow:1; 1484 uint32_t count:16; 1485 #elif defined(_BIT_FIELDS_LTOH) 1486 uint32_t count:16; 1487 uint32_t oflow:1; 1488 uint32_t res_1:15; 1489 #endif 1490 } ldw; 1491 #if !defined(_BIG_ENDIAN) 1492 uint32_t hdw; 1493 #endif 1494 } bits; 1495 } red_disc_cnt_t, *p_red_disc_cnt_t; 1496 1497 1498 #define RDMC_PRE_PAR_ERR_REG (FZC_DMC + 0x00078) 1499 #define RDMC_SHA_PAR_ERR_REG (FZC_DMC + 0x00080) 1500 1501 typedef union _rdmc_par_err_log { 1502 uint64_t value; 1503 struct { 1504 #if defined(_BIG_ENDIAN) 1505 uint32_t hdw; 1506 #endif 1507 struct { 1508 #if defined(_BIT_FIELDS_HTOL) 1509 uint32_t res_1:16; 1510 uint32_t err:1; 1511 uint32_t merr:1; 1512 uint32_t res:6; 1513 uint32_t addr:8; 1514 #elif defined(_BIT_FIELDS_LTOH) 1515 uint32_t addr:8; 1516 uint32_t res:6; 1517 uint32_t merr:1; 1518 uint32_t err:1; 1519 uint32_t res_1:16; 1520 #endif 1521 } ldw; 1522 #if !defined(_BIG_ENDIAN) 1523 uint32_t hdw; 1524 #endif 1525 } bits; 1526 } rdmc_par_err_log_t, *p_rdmc_par_err_log_t; 1527 1528 1529 /* Used for accessing RDMC Memory */ 1530 #define RDMC_MEM_ADDR_REG (FZC_DMC + 0x00088) 1531 1532 1533 typedef union _rdmc_mem_addr { 1534 uint64_t value; 1535 struct { 1536 #if defined(_BIG_ENDIAN) 1537 uint32_t hdw; 1538 #endif 1539 1540 #define RDMC_MEM_ADDR_PREFETCH 0 1541 #define RDMC_MEM_ADDR_SHADOW 1 1542 1543 struct { 1544 #if defined(_BIT_FIELDS_HTOL) 1545 uint32_t res_1:23; 1546 uint32_t pre_shad:1; 1547 uint32_t addr:8; 1548 #elif defined(_BIT_FIELDS_LTOH) 1549 uint32_t addr:8; 1550 uint32_t pre_shad:1; 1551 uint32_t res_1:23; 1552 #endif 1553 } ldw; 1554 #if !defined(_BIG_ENDIAN) 1555 uint32_t hdw; 1556 #endif 1557 } bits; 1558 } rdmc_mem_addr_t, *p_rdmc_mem_addr_t; 1559 1560 1561 #define RDMC_MEM_DATA0_REG (FZC_DMC + 0x00090) 1562 #define RDMC_MEM_DATA1_REG (FZC_DMC + 0x00098) 1563 #define RDMC_MEM_DATA2_REG (FZC_DMC + 0x000A0) 1564 #define RDMC_MEM_DATA3_REG (FZC_DMC + 0x000A8) 1565 #define RDMC_MEM_DATA4_REG (FZC_DMC + 0x000B0) 1566 1567 typedef union _rdmc_mem_data { 1568 uint64_t value; 1569 struct { 1570 #if defined(_BIG_ENDIAN) 1571 uint32_t hdw; 1572 #endif 1573 1574 struct { 1575 #if defined(_BIT_FIELDS_HTOL) 1576 uint32_t data; 1577 #elif defined(_BIT_FIELDS_LTOH) 1578 uint32_t data; 1579 #endif 1580 } ldw; 1581 #if !defined(_BIG_ENDIAN) 1582 uint32_t hdw; 1583 #endif 1584 } bits; 1585 } rdmc_mem_data_t, *p_rdmc_mem_data_t; 1586 1587 1588 typedef union _rdmc_mem_access { 1589 #define RDMC_MEM_READ 1 1590 #define RDMC_MEM_WRITE 2 1591 uint32_t data[5]; 1592 uint8_t addr; 1593 uint8_t location; 1594 } rdmc_mem_access_t, *p_rdmc_mem_access_t; 1595 1596 1597 #define RX_CTL_DAT_FIFO_STAT_REG (FZC_DMC + 0x000B8) 1598 #define RX_CTL_DAT_FIFO_MASK_REG (FZC_DMC + 0x000C0) 1599 #define RX_CTL_DAT_FIFO_STAT_DBG_REG (FZC_DMC + 0x000D0) 1600 1601 typedef union _rx_ctl_dat_fifo { 1602 #define FIFO_EOP_PORT0 0x1 1603 #define FIFO_EOP_PORT1 0x2 1604 #define FIFO_EOP_PORT2 0x4 1605 #define FIFO_EOP_PORT3 0x8 1606 #define FIFO_EOP_ALL 0xF 1607 uint64_t value; 1608 struct { 1609 #if defined(_BIG_ENDIAN) 1610 uint32_t hdw; 1611 #endif 1612 struct { 1613 #if defined(_BIT_FIELDS_HTOL) 1614 uint32_t res_1:23; 1615 uint32_t id_mismatch:1; 1616 uint32_t zcp_eop_err:4; 1617 uint32_t ipp_eop_err:4; 1618 #elif defined(_BIT_FIELDS_LTOH) 1619 uint32_t ipp_eop_err:4; 1620 uint32_t zcp_eop_err:4; 1621 uint32_t id_mismatch:1; 1622 uint32_t res_1:23; 1623 #endif 1624 } ldw; 1625 #if !defined(_BIG_ENDIAN) 1626 uint32_t hdw; 1627 #endif 1628 } bits; 1629 } rx_ctl_dat_fifo_mask_t, rx_ctl_dat_fifo_stat_t, 1630 rx_ctl_dat_fifo_stat_dbg_t, *p_rx_ctl_dat_fifo_t; 1631 1632 1633 1634 #define RDMC_TRAINING_VECTOR_REG (FZC_DMC + 0x000C8) 1635 1636 typedef union _rx_training_vect { 1637 uint64_t value; 1638 struct { 1639 #if defined(_BIG_ENDIAN) 1640 uint32_t hdw; 1641 #endif 1642 struct { 1643 uint32_t tv; 1644 } ldw; 1645 #if !defined(_BIG_ENDIAN) 1646 uint32_t hdw; 1647 #endif 1648 } bits; 1649 } rx_training_vect_t, *p_rx_training_vect_t; 1650 1651 #define RXCTL_IPP_EOP_ERR_MASK 0x0000000FULL 1652 #define RXCTL_IPP_EOP_ERR_SHIFT 0x0 1653 #define RXCTL_ZCP_EOP_ERR_MASK 0x000000F0ULL 1654 #define RXCTL_ZCP_EOP_ERR_SHIFT 0x4 1655 #define RXCTL_ID_MISMATCH_MASK 0x00000100ULL 1656 #define RXCTL_ID_MISMATCH_SHIFT 0x8 1657 1658 1659 /* 1660 * Receive Packet Header Format 1661 * Packet header before the packet. 1662 * The minimum is 2 bytes and the max size is 18 bytes. 1663 */ 1664 /* 1665 * Packet header format 0 (2 bytes). 1666 */ 1667 typedef union _rx_pkt_hdr0_t { 1668 uint16_t value; 1669 struct { 1670 #if defined(_BIT_FIELDS_HTOL) 1671 uint16_t inputport:2; 1672 uint16_t maccheck:1; 1673 uint16_t class:5; 1674 uint16_t vlan:1; 1675 uint16_t llcsnap:1; 1676 uint16_t noport:1; 1677 uint16_t badip:1; 1678 uint16_t tcamhit:1; 1679 uint16_t tres:2; 1680 uint16_t tzfvld:1; 1681 #elif defined(_BIT_FIELDS_LTOH) 1682 uint16_t tzfvld:1; 1683 uint16_t tres:2; 1684 uint16_t tcamhit:1; 1685 uint16_t badip:1; 1686 uint16_t noport:1; 1687 uint16_t llcsnap:1; 1688 uint16_t vlan:1; 1689 uint16_t class:5; 1690 uint16_t maccheck:1; 1691 uint16_t inputport:2; 1692 #endif 1693 } bits; 1694 } rx_pkt_hdr0_t, *p_rx_pkt_hdr0_t; 1695 1696 1697 /* 1698 * Packet header format 1. 1699 */ 1700 typedef union _rx_pkt_hdr1_b0_t { 1701 uint8_t value; 1702 struct { 1703 #if defined(_BIT_FIELDS_HTOL) 1704 uint8_t hwrsvd:8; 1705 #elif defined(_BIT_FIELDS_LTOH) 1706 uint8_t hwrsvd:8; 1707 #endif 1708 } bits; 1709 } rx_pkt_hdr1_b0_t, *p_rx_pkt_hdr1_b0_t; 1710 1711 typedef union _rx_pkt_hdr1_b1_t { 1712 uint8_t value; 1713 struct { 1714 #if defined(_BIT_FIELDS_HTOL) 1715 uint8_t tcammatch:8; 1716 #elif defined(_BIT_FIELDS_LTOH) 1717 uint8_t tcammatch:8; 1718 #endif 1719 } bits; 1720 } rx_pkt_hdr1_b1_t, *p_rx_pkt_hdr1_b1_t; 1721 1722 typedef union _rx_pkt_hdr1_b2_t { 1723 uint8_t value; 1724 struct { 1725 #if defined(_BIT_FIELDS_HTOL) 1726 uint8_t resv:2; 1727 uint8_t hashhit:1; 1728 uint8_t exact:1; 1729 uint8_t hzfvld:1; 1730 uint8_t hashidx:3; 1731 #elif defined(_BIT_FIELDS_LTOH) 1732 uint8_t hashidx:3; 1733 uint8_t hzfvld:1; 1734 uint8_t exact:1; 1735 uint8_t hashhit:1; 1736 uint8_t resv:2; 1737 #endif 1738 } bits; 1739 } rx_pkt_hdr1_b2_t, *p_rx_pkt_hdr1_b2_t; 1740 1741 typedef union _rx_pkt_hdr1_b3_t { 1742 uint8_t value; 1743 struct { 1744 #if defined(_BIT_FIELDS_HTOL) 1745 uint8_t zc_resv:8; 1746 #elif defined(_BIT_FIELDS_LTOH) 1747 uint8_t zc_resv:8; 1748 #endif 1749 } bits; 1750 } rx_pkt_hdr1_b3_t, *p_rx_pkt_hdr1_b3_t; 1751 1752 typedef union _rx_pkt_hdr1_b4_t { 1753 uint8_t value; 1754 struct { 1755 #if defined(_BIT_FIELDS_HTOL) 1756 uint8_t resv:4; 1757 uint8_t zflowid:4; 1758 #elif defined(_BIT_FIELDS_LTOH) 1759 uint8_t zflowid:4; 1760 uint8_t resv:4; 1761 #endif 1762 } bits; 1763 } rx_pkt_hdr1_b4_t, *p_rx_pkt_hdr1_b4_t; 1764 1765 typedef union _rx_pkt_hdr1_b5_t { 1766 uint8_t value; 1767 struct { 1768 #if defined(_BIT_FIELDS_HTOL) 1769 uint8_t zflowid:8; 1770 #elif defined(_BIT_FIELDS_LTOH) 1771 uint8_t zflowid:8; 1772 #endif 1773 } bits; 1774 } rx_pkt_hdr1_b5_t, *p_rx_pkt_hdr1_b5_t; 1775 1776 typedef union _rx_pkt_hdr1_b6_t { 1777 uint8_t value; 1778 struct { 1779 #if defined(_BIT_FIELDS_HTOL) 1780 uint8_t hashval2:8; 1781 #elif defined(_BIT_FIELDS_LTOH) 1782 uint8_t hashval2:8; 1783 #endif 1784 } bits; 1785 } rx_pkt_hdr1_b6_t, *p_rx_pkt_hdr1_b6_t; 1786 1787 typedef union _rx_pkt_hdr1_b7_t { 1788 uint8_t value; 1789 struct { 1790 #if defined(_BIT_FIELDS_HTOL) 1791 uint8_t hashval2:8; 1792 #elif defined(_BIT_FIELDS_LTOH) 1793 uint8_t hashval2:8; 1794 #endif 1795 } bits; 1796 } rx_pkt_hdr1_b7_t, *p_rx_pkt_hdr1_b7_t; 1797 1798 typedef union _rx_pkt_hdr1_b8_t { 1799 uint8_t value; 1800 struct { 1801 #if defined(_BIT_FIELDS_HTOL) 1802 uint8_t resv:4; 1803 uint8_t h1:4; 1804 #elif defined(_BIT_FIELDS_LTOH) 1805 uint8_t h1:4; 1806 uint8_t resv:4; 1807 #endif 1808 } bits; 1809 } rx_pkt_hdr1_b8_t, *p_rx_pkt_hdr1_b8_t; 1810 1811 typedef union _rx_pkt_hdr1_b9_t { 1812 uint8_t value; 1813 struct { 1814 #if defined(_BIT_FIELDS_HTOL) 1815 uint8_t h1:8; 1816 #elif defined(_BIT_FIELDS_LTOH) 1817 uint8_t h1:8; 1818 #endif 1819 } bits; 1820 } rx_pkt_hdr1_b9_t, *p_rx_pkt_hdr1_b9_t; 1821 1822 typedef union _rx_pkt_hdr1_b10_t { 1823 uint8_t value; 1824 struct { 1825 #if defined(_BIT_FIELDS_HTOL) 1826 uint8_t resv:4; 1827 uint8_t h1:4; 1828 #elif defined(_BIT_FIELDS_LTOH) 1829 uint8_t h1:4; 1830 uint8_t resv:4; 1831 #endif 1832 } bits; 1833 } rx_pkt_hdr1_b10_t, *p_rx_pkt_hdr1_b10_t; 1834 1835 typedef union _rx_pkt_hdr1_b11_b12_t { 1836 uint16_t value; 1837 struct { 1838 #if defined(_BIT_FIELDS_HTOL) 1839 uint16_t h1_1:8; 1840 uint16_t h1_2:8; 1841 #elif defined(_BIT_FIELDS_LTOH) 1842 uint16_t h1_2:8; 1843 uint16_t h1_1:8; 1844 #endif 1845 } bits; 1846 } rx_pkt_hdr1_b11_b12_t, *p_rx_pkt_hdr1_b11_b12_t; 1847 1848 typedef union _rx_pkt_hdr1_b13_t { 1849 uint8_t value; 1850 struct { 1851 #if defined(_BIT_FIELDS_HTOL) 1852 uint8_t usr_data:8; 1853 #elif defined(_BIT_FIELDS_LTOH) 1854 uint8_t usr_data:8; 1855 #endif 1856 } bits; 1857 } rx_pkt_hdr1_b13_t, *p_rx_pkt_hdr1_b13_t; 1858 1859 typedef union _rx_pkt_hdr1_b14_b17_t { 1860 uint32_t value; 1861 struct { 1862 #if defined(_BIT_FIELDS_HTOL) 1863 uint32_t usr_data_1:8; 1864 uint32_t usr_data_2:8; 1865 uint32_t usr_data_3:8; 1866 uint32_t usr_data_4:8; 1867 #elif defined(_BIT_FIELDS_LTOH) 1868 uint32_t usr_data_4:8; 1869 uint32_t usr_data_3:8; 1870 uint32_t usr_data_2:8; 1871 uint32_t usr_data_1:8; 1872 #endif 1873 } bits; 1874 } rx_pkt_hdr1_b14_b17_t, *p_rx_pkt_hdr1_b14_b17_t; 1875 1876 /* Receive packet header 1 format (18 bytes) */ 1877 typedef struct _rx_pkt_hdr_t { 1878 rx_pkt_hdr1_b0_t rx_hdr1_b0; 1879 rx_pkt_hdr1_b1_t rx_hdr1_b1; 1880 rx_pkt_hdr1_b2_t rx_hdr1_b2; 1881 rx_pkt_hdr1_b3_t rx_hdr1_b3; 1882 rx_pkt_hdr1_b4_t rx_hdr1_b4; 1883 rx_pkt_hdr1_b5_t rx_hdr1_b5; 1884 rx_pkt_hdr1_b6_t rx_hdr1_b6; 1885 rx_pkt_hdr1_b7_t rx_hdr1_b7; 1886 rx_pkt_hdr1_b8_t rx_hdr1_b8; 1887 rx_pkt_hdr1_b9_t rx_hdr1_b9; 1888 rx_pkt_hdr1_b10_t rx_hdr1_b10; 1889 rx_pkt_hdr1_b11_b12_t rx_hdr1_b11_b12; 1890 rx_pkt_hdr1_b13_t rx_hdr1_b13; 1891 rx_pkt_hdr1_b14_b17_t rx_hdr1_b14_b17; 1892 } rx_pkt_hdr1_t, *p_rx_pkt_hdr1_t; 1893 1894 1895 #ifdef __cplusplus 1896 } 1897 #endif 1898 1899 #endif /* _SYS_NXGE_NXGE_RXDMA_HW_H */ 1900