1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <nxge_defs.h> 37 38 /* 39 * Clause 45 and Clause 22 port/phy addresses 0 through 7 are reserved 40 * for on-chip serdes. So here the starting port is 8. 41 */ 42 #define NXGE_MAX_PHY_PORTS 32 43 #define NXGE_EXT_PHY_PORT_ST 8 44 45 #define NXGE_PMA_PMD_DEV_ADDR 1 46 #define NXGE_PCS_DEV_ADDR 3 47 #define NXGE_DEV_ID_REG_1 2 48 #define NXGE_DEV_ID_REG_2 3 49 #define NXGE_PHY_ID_REG_1 2 50 #define NXGE_PHY_ID_REG_2 3 51 52 #define BCM8704_CHIP_ID 0x8704 53 #define BCM8706_CHIP_ID 0x8706 54 #define MRVL88X201X_CHIP_ID 0x5043 55 56 /* 57 * Description of BCM_PHY_ID_MASK: 58 * The first nibble (bits 0 through 3) is changed with every revision 59 * of the silicon. So these bits are masked out to support future revisions 60 * of the same chip. The third nibble (bits 8 through 11) is changed for 61 * different chips of the same family. So these bits are masked out to 62 * support chips of the same family. 63 */ 64 #define BCM_PHY_ID_MASK 0xfffff0f0 65 #define BCM8704_DEV_ID 0x206033 66 #define BCM5464R_PHY_ID 0x2060b1 67 #define BCM8706_DEV_ID 0x206035 68 #define BCM5482_PHY_ID 0x143bcb1 69 #define MARVELL_88X_201X_DEV_ID 0x1410d24 70 #define MARVELL_88X201X_PHY_ID (MARVELL_88X_201X_DEV_ID & BCM_PHY_ID_MASK) 71 #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 72 #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 73 #define PHY_BCM5482_FAMILY (BCM5482_PHY_ID & BCM_PHY_ID_MASK) 74 /* 75 * The default value is 0xa19410, after masking out model and revision 76 * (bits[9:0]) use 0xa19400 for any model or revision of the TN1010 77 */ 78 #define TN1010_DEV_ID 0xa19400 79 /* 80 * Description of TN1010_DEV_ID_MASK: 81 * The device ID assigned to Teranetics is stored in TN1010 register 82 * 1.2 and register 1.3 except bits[9:4] of register 1.3 for model number 83 * and bits[3:0] of register 1.3 for revision numbers. Use mask 0xfffffc00 84 * to mask off model number and revision number and keep TN1010's device 85 * identifier 86 */ 87 #define TN1010_DEV_ID_MASK 0xfffffc00 88 89 #define CLAUSE_45_TYPE 1 90 #define CLAUSE_22_TYPE 2 91 92 /* IEEE802.3 Clause45 and Clause22 MDIO port addresses */ 93 #define NEPTUNE_CLAUSE22_PORT_ADDR_BASE 10 94 #define NEPTUNE_CLAUSE45_PORT_ADDR_BASE 8 95 #define N2_CLAUSE45_PORT_ADDR_BASE 16 96 #define MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 8 97 98 /* 99 * Phy address for the second NIU port on Goa NEM card can be either 100 * 20 or 17 101 */ 102 #define GOA_CLAUSE45_PORT_ADDR_BASE 16 103 #define ALT_GOA_CLAUSE45_PORT1_ADDR 20 104 /* 105 * Phy addresses for Maramba support. Support for P0 will eventually 106 * be removed. 107 */ 108 #define MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE 10 109 #define MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE 26 110 #define MARAMBA_CLAUSE45_PORT_ADDR_BASE 16 111 112 #define BCM8704_PMA_PMD_DEV_ADDR 1 113 #define BCM8704_PCS_DEV_ADDR 3 114 #define BCM8704_USER_DEV3_ADDR 3 115 #define BCM8704_PHYXS_ADDR 4 116 #define BCM8704_USER_DEV4_ADDR 4 117 118 /* Definitions for BCM 5464R PHY chip */ 119 120 #define BCM5464R_PHY_ECR 16 121 #define BCM5464R_PHY_ESR 17 122 #define BCM5464R_RXERR_CNT 18 123 #define BCM5464R_FALSECS_CNT 19 124 #define BCM5464R_RX_NOTOK_CNT 20 125 #define BCM5464R_ER_DATA 21 126 #define BCM5464R_RES 22 127 #define BCM5464R_ER_ACC 23 128 #define BCM5464R_AUX_CTL 24 129 #define BCM5464R_AUX_S 25 130 #define BCM5464R_INTR_S 26 131 #define BCM5464R_INTR_M 27 132 #define BCM5464R_MISC 28 133 #define BCM5464R_MISC1 29 134 #define BCM5464R_TESTR1 30 135 136 #define PHY_BCM_5464R_OUI 0x001018 137 #define PHY_BCM_5464R_MODEL 0x0B 138 139 /* MARVELL PHY Definitions */ 140 /* REG Offsets */ 141 #define MRVL_88X2011_USER_DEV1_ADDR 1 142 #define MRVL_88X2011_USER_DEV2_ADDR 2 143 #define MRVL_88X2011_USER_DEV3_ADDR 3 144 #define MRVL_88X2011_USER_DEV4_ADDR 4 145 #define MRVL_88X2011_PMA_PMD_CTL_1 0x0000 146 #define MRVL_88X2011_PMA_PMD_STAT_1 0x0001 147 #define MRVL_88X2011_10G_PMD_STAT_2 0x0008 148 #define MRVL_88X2011_10G_PMD_TX_DIS 0x0009 149 #define MRVL_88X2011_10G_XGXS_LANE_STAT 0x0018 150 #define MRVL_88X2011_GEN_CTL 0x8300 151 #define MRVL_88X2011_LED_BLINK_CTL 0x8303 152 #define MRVL_88X2011_LED_8_TO_11_CTL 0x8306 153 154 /* MRVL88X2011 register control */ 155 #define MRVL_88X2011_ENA_PMDTX 0x0000 156 #define MRVL_88X2011_ENA_XFPREFCLK 0x0001 157 #define MRVL_88X2011_LOOPBACK 0x1 158 #define MRVL_88X2011_LED_ACT 0x1 159 #define MRVL_88X2011_LNK_STATUS_OK 0x4 160 #define MRVL_88X2011_LED_BLK_MASK 0x70 161 #define MRVL_88X2011_LED_BLK_SHIFT 4 162 #define MRVL_88X2011_LED_BLK34MS 0x0 163 #define MRVL_88X2011_LED_BLK67MS 0x1 164 #define MRVL_88X2011_LED_BLK134MS 0x2 165 #define MRVL_88X2011_LED_BLK269MS 0x3 166 #define MRVL_88X2011_LED_BLK538MS 0x4 167 #define MRVL_88X2011_LED_CTL_OFF 0x0 168 #define MRVL_88X2011_LED_CTL_PCS_ERR 0x2 169 #define MRVL_88X2011_LED_CTL_PCS_ACT 0x5 170 #define MRVL_88X2011_LED_CTL_MASK 0x7 171 #define MRVL_88X2011_LED(n, v) ((v)<<((n)*4)) 172 #define MRVL_88X2011_LED_STAT(n, v) ((v)>>((n)*4)) 173 174 /* 175 * MII Register 16: PHY Extended Control Register 176 */ 177 178 typedef union _mii_phy_ecr_t { 179 uint16_t value; 180 struct { 181 #ifdef _BIT_FIELDS_HTOL 182 uint16_t mac_phy_if_mode : 1; 183 uint16_t dis_automdicross : 1; 184 uint16_t tx_dis : 1; 185 uint16_t intr_dis : 1; 186 uint16_t force_intr : 1; 187 uint16_t bypass_encdec : 1; 188 uint16_t bypass_scrdes : 1; 189 uint16_t bypass_mlt3 : 1; 190 uint16_t bypass_rx_sym : 1; 191 uint16_t reset_scr : 1; 192 uint16_t en_led_traffic : 1; 193 uint16_t force_leds_on : 1; 194 uint16_t force_leds_off : 1; 195 uint16_t res : 2; 196 uint16_t gmii_fifo_elas : 1; 197 #else 198 uint16_t gmii_fifo_elas : 1; 199 uint16_t res : 2; 200 uint16_t force_leds_off : 1; 201 uint16_t force_leds_on : 1; 202 uint16_t en_led_traffic : 1; 203 uint16_t reset_scr : 1; 204 uint16_t bypass_rx_sym : 1; 205 uint16_t bypass_mlt3 : 1; 206 uint16_t bypass_scrdes : 1; 207 uint16_t bypass_encdec : 1; 208 uint16_t force_intr : 1; 209 uint16_t intr_dis : 1; 210 uint16_t tx_dis : 1; 211 uint16_t dis_automdicross : 1; 212 uint16_t mac_phy_if_mode : 1; 213 #endif 214 } bits; 215 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 216 217 /* 218 * MII Register 17: PHY Extended Status Register 219 */ 220 typedef union _mii_phy_esr_t { 221 uint16_t value; 222 struct { 223 #ifdef _BIT_FIELDS_HTOL 224 uint16_t anbpsfm : 1; 225 uint16_t wsdwngr : 1; 226 uint16_t mdi_crst : 1; 227 uint16_t intr_s : 1; 228 uint16_t rmt_rx_s : 1; 229 uint16_t loc_rx_s : 1; 230 uint16_t locked : 1; 231 uint16_t link_s : 1; 232 uint16_t crc_err : 1; 233 uint16_t cext_err : 1; 234 uint16_t bad_ssd : 1; 235 uint16_t bad_esd : 1; 236 uint16_t rx_err : 1; 237 uint16_t tx_err : 1; 238 uint16_t lock_err : 1; 239 uint16_t mlt3_cerr : 1; 240 #else 241 uint16_t mlt3_cerr : 1; 242 uint16_t lock_err : 1; 243 uint16_t tx_err : 1; 244 uint16_t rx_err : 1; 245 uint16_t bad_esd : 1; 246 uint16_t bad_ssd : 1; 247 uint16_t cext_err : 1; 248 uint16_t crc_err : 1; 249 uint16_t link_s : 1; 250 uint16_t locked : 1; 251 uint16_t loc_rx_s : 1; 252 uint16_t rmt_rx_s : 1; 253 uint16_t intr_s : 1; 254 uint16_t mdi_crst : 1; 255 uint16_t wsdwngr : 1; 256 uint16_t anbpsfm : 1; 257 #endif 258 } bits; 259 } mii_phy_esr_t, *p_mii_phy_esr_t; 260 261 /* 262 * MII Register 18: Receive Error Counter Register 263 */ 264 typedef union _mii_rxerr_cnt_t { 265 uint16_t value; 266 struct { 267 uint16_t rx_err_cnt : 16; 268 } bits; 269 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 270 271 /* 272 * MII Register 19: False Carrier Sense Counter Register 273 */ 274 typedef union _mii_falsecs_cnt_t { 275 uint16_t value; 276 struct { 277 #ifdef _BIT_FIELDS_HTOL 278 uint16_t res : 8; 279 uint16_t false_cs_cnt : 8; 280 #else 281 uint16_t false_cs_cnt : 8; 282 uint16_t res : 8; 283 #endif 284 } bits; 285 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 286 287 /* 288 * MII Register 20: Receiver NOT_OK Counter Register 289 */ 290 typedef union _mii_rx_notok_cnt_t { 291 uint16_t value; 292 struct { 293 #ifdef _BIT_FIELDS_HTOL 294 uint16_t l_rx_notok_cnt : 8; 295 uint16_t r_rx_notok_cnt : 8; 296 #else 297 uint16_t r_rx_notok_cnt : 8; 298 uint16_t l_rx_notok_cnt : 8; 299 #endif 300 } bits; 301 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 302 303 /* 304 * MII Register 21: Expansion Register Data Register 305 */ 306 typedef union _mii_er_data_t { 307 uint16_t value; 308 struct { 309 uint16_t reg_data; 310 } bits; 311 } mii_er_data_t, *p_mii_er_data_t; 312 313 /* 314 * MII Register 23: Expansion Register Access Register 315 */ 316 typedef union _mii_er_acc_t { 317 struct { 318 #ifdef _BIT_FIELDS_HTOL 319 uint16_t res : 4; 320 uint16_t er_sel : 4; 321 uint16_t er_acc : 8; 322 #else 323 uint16_t er_acc : 8; 324 uint16_t er_sel : 4; 325 uint16_t res : 4; 326 #endif 327 } bits; 328 } mii_er_acc_t, *p_mii_er_acc_t; 329 330 #define EXP_RXTX_PKT_CNT 0x0 331 #define EXP_INTR_STAT 0x1 332 #define MULTICOL_LED_SEL 0x4 333 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 334 #define MULTICOL_LED_BLINK_CTL 0x6 335 #define CABLE_DIAG_CTL 0x10 336 #define CABLE_DIAG_RES 0x11 337 #define CABLE_DIAG_LEN_CH_2_1 0x12 338 #define CABLE_DIAG_LEN_CH_4_3 0x13 339 340 /* 341 * MII Register 24: Auxiliary Control Register 342 */ 343 typedef union _mii_aux_ctl_t { 344 uint16_t value; 345 struct { 346 #ifdef _BIT_FIELDS_HTOL 347 uint16_t ext_lb : 1; 348 uint16_t ext_pkt_len : 1; 349 uint16_t edge_rate_ctl_1000 : 2; 350 uint16_t res : 1; 351 uint16_t write_1 : 1; 352 uint16_t res1 : 2; 353 uint16_t dis_partial_resp : 1; 354 uint16_t res2 : 1; 355 uint16_t edge_rate_ctl_100 : 2; 356 uint16_t diag_mode : 1; 357 uint16_t shadow_reg_sel : 3; 358 #else 359 uint16_t shadow_reg_sel : 3; 360 uint16_t diag_mode : 1; 361 uint16_t edge_rate_ctl_100 : 2; 362 uint16_t res2 : 1; 363 uint16_t dis_partial_resp : 1; 364 uint16_t res1 : 2; 365 uint16_t write_1 : 1; 366 uint16_t res : 1; 367 uint16_t edge_rate_ctl_1000 : 2; 368 uint16_t ext_pkt_len : 1; 369 uint16_t ext_lb : 1; 370 #endif 371 } bits; 372 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 373 374 #define AUX_REG 0x0 375 #define AUX_10BASET 0x1 376 #define AUX_PWR_CTL 0x2 377 #define AUX_MISC_TEST 0x4 378 #define AUX_MISC_CTL 0x7 379 380 /* 381 * MII Register 25: Auxiliary Status Summary Register 382 */ 383 typedef union _mii_aux_s_t { 384 uint16_t value; 385 struct { 386 #ifdef _BIT_FIELDS_HTOL 387 uint16_t an_complete : 1; 388 uint16_t an_complete_ack : 1; 389 uint16_t an_ack_detect : 1; 390 uint16_t an_ability_detect : 1; 391 uint16_t an_np_wait : 1; 392 uint16_t an_hcd : 3; 393 uint16_t pd_fault : 1; 394 uint16_t rmt_fault : 1; 395 uint16_t an_page_rx : 1; 396 uint16_t lp_an_ability : 1; 397 uint16_t lp_np_ability : 1; 398 uint16_t link_s : 1; 399 uint16_t pause_res_rx_dir : 1; 400 uint16_t pause_res_tx_dir : 1; 401 #else 402 uint16_t pause_res_tx_dir : 1; 403 uint16_t pause_res_rx_dir : 1; 404 uint16_t link_s : 1; 405 uint16_t lp_np_ability : 1; 406 uint16_t lp_an_ability : 1; 407 uint16_t an_page_rx : 1; 408 uint16_t rmt_fault : 1; 409 uint16_t pd_fault : 1; 410 uint16_t an_hcd : 3; 411 uint16_t an_np_wait : 1; 412 uint16_t an_ability_detect : 1; 413 uint16_t an_ack_detect : 1; 414 uint16_t an_complete_ack : 1; 415 uint16_t an_complete : 1; 416 #endif 417 } bits; 418 } mii_aux_s_t, *p_mii_aux_s_t; 419 420 /* 421 * MII Register 26, 27: Interrupt Status and Mask Registers 422 */ 423 typedef union _mii_intr_t { 424 uint16_t value; 425 struct { 426 #ifdef _BIT_FIELDS_HTOL 427 uint16_t res : 1; 428 uint16_t illegal_pair_swap : 1; 429 uint16_t mdix_status_change : 1; 430 uint16_t exceed_hicnt_thres : 1; 431 uint16_t exceed_locnt_thres : 1; 432 uint16_t an_page_rx : 1; 433 uint16_t hcd_nolink : 1; 434 uint16_t no_hcd : 1; 435 uint16_t neg_unsupported_hcd : 1; 436 uint16_t scr_sync_err : 1; 437 uint16_t rmt_rx_status_change : 1; 438 uint16_t loc_rx_status_change : 1; 439 uint16_t duplex_mode_change : 1; 440 uint16_t link_speed_change : 1; 441 uint16_t link_status_change : 1; 442 uint16_t crc_err : 1; 443 #else 444 uint16_t crc_err : 1; 445 uint16_t link_status_change : 1; 446 uint16_t link_speed_change : 1; 447 uint16_t duplex_mode_change : 1; 448 uint16_t loc_rx_status_change : 1; 449 uint16_t rmt_rx_status_change : 1; 450 uint16_t scr_sync_err : 1; 451 uint16_t neg_unsupported_hcd : 1; 452 uint16_t no_hcd : 1; 453 uint16_t hcd_nolink : 1; 454 uint16_t an_page_rx : 1; 455 uint16_t exceed_locnt_thres : 1; 456 uint16_t exceed_hicnt_thres : 1; 457 uint16_t mdix_status_change : 1; 458 uint16_t illegal_pair_swap : 1; 459 uint16_t res : 1; 460 #endif 461 } bits; 462 } mii_intr_t, *p_mii_intr_t; 463 464 /* 465 * MII Register 28: Register 1C Access Register 466 */ 467 typedef union _mii_misc_t { 468 uint16_t value; 469 struct { 470 #ifdef _BIT_FIELDS_HTOL 471 uint16_t w_en : 1; 472 uint16_t shadow_reg_sel : 5; 473 uint16_t data : 10; 474 #else 475 uint16_t data : 10; 476 uint16_t shadow_reg_sel : 5; 477 uint16_t w_en : 1; 478 #endif 479 } bits; 480 } mii_misc_t, *p_mii_misc_t; 481 482 #define LINK_LED_MODE 0x2 483 #define CLK_ALIGN_CTL 0x3 484 #define WIRE_SP_RETRY 0x4 485 #define CLK125 0x5 486 #define LED_STATUS 0x8 487 #define LED_CONTROL 0x9 488 #define AUTO_PWR_DOWN 0xA 489 #define LED_SEL1 0xD 490 #define LED_SEL2 0xE 491 492 /* 493 * MII Register 29: Master/Slave Seed / HCD Status Register 494 */ 495 496 typedef union _mii_misc1_t { 497 uint16_t value; 498 struct { 499 #ifdef _BIT_FIELDS_HTOL 500 uint16_t en_shadow_reg : 1; 501 uint16_t data : 15; 502 #else 503 uint16_t data : 15; 504 uint16_t en_shadow_reg : 1; 505 #endif 506 } bits; 507 } mii_misc1_t, *p_mii_misc1_t; 508 509 /* 510 * MII Register 30: Test Register 1 511 */ 512 513 typedef union _mii_test1_t { 514 uint16_t value; 515 struct { 516 #ifdef _BIT_FIELDS_HTOL 517 uint16_t crc_err_cnt_sel : 1; 518 uint16_t res : 7; 519 uint16_t manual_swap_mdi_st : 1; 520 uint16_t res1 : 7; 521 #else 522 uint16_t res1 : 7; 523 uint16_t manual_swap_mdi_st : 1; 524 uint16_t res : 7; 525 uint16_t crc_err_cnt_sel : 1; 526 #endif 527 } bits; 528 } mii_test1_t, *p_mii_test1_t; 529 530 531 /* Definitions of BCM8704 */ 532 533 #define BCM8704_PMD_CONTROL_REG 0 534 #define BCM8704_PMD_STATUS_REG 0x1 535 #define BCM8704_PMD_ID_0_REG 0x2 536 #define BCM8704_PMD_ID_1_REG 0x3 537 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 538 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 539 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 540 #define BCM8704_PMD_CONTROL2_REG 0x7 541 #define BCM8704_PMD_STATUS2_REG 0x8 542 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 543 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 544 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 545 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 546 #define BCM8704_PCS_CONTROL_REG 0 547 #define BCM8704_PCS_STATUS1_REG 0x1 548 #define BCM8704_PCS_ID_0_REG 0x2 549 #define BCM8704_PCS_ID_1_REG 0x3 550 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 551 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 552 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 553 #define BCM8704_PCS_CONTROL2_REG 0x7 554 #define BCM8704_PCS_STATUS2_REG 0x8 555 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 556 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 557 #define BCM8704_PCS_STATUS_REG 0x18 558 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 559 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 560 #define BCM8704_PHYXS_CONTROL_REG 0 561 #define BCM8704_PHYXS_STATUS_REG 0x1 562 #define BCM8704_PHY_ID_0_REG 0x2 563 #define BCM8704_PHY_ID_1_REG 0x3 564 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 565 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 566 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 567 #define BCM8704_PHYXS_STATUS2_REG 0x8 568 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 569 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 570 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 571 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 572 #define BCM8704_USER_CONTROL_REG 0xC800 573 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 574 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 575 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 576 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 577 #define BCM8704_CHIP_ID_REG 0xC807 578 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 579 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 580 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 581 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 582 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 583 584 /* Rx Channel Control1 Register bits */ 585 #define BCM8704_RXPOL_FLIP 0x20 586 587 typedef union _phyxs_control { 588 uint16_t value; 589 struct { 590 #ifdef _BIT_FIELDS_HTOL 591 uint16_t reset : 1; 592 uint16_t loopback : 1; 593 uint16_t speed_sel2 : 1; 594 uint16_t res2 : 1; 595 uint16_t low_power : 1; 596 uint16_t res1 : 4; 597 uint16_t speed_sel1 : 1; 598 uint16_t speed_sel0 : 4; 599 uint16_t res0 : 2; 600 #else 601 uint16_t res0 : 2; 602 uint16_t speed_sel0 : 4; 603 uint16_t speed_sel1 : 1; 604 uint16_t res1 : 4; 605 uint16_t low_power : 1; 606 uint16_t res2 : 1; 607 uint16_t speed_sel2 : 1; 608 uint16_t loopback : 1; 609 uint16_t reset : 1; 610 #endif 611 } bits; 612 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 613 614 615 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 616 617 typedef union _control { 618 uint16_t value; 619 struct { 620 #ifdef _BIT_FIELDS_HTOL 621 uint16_t optxenb_lvl : 1; 622 uint16_t optxrst_lvl : 1; 623 uint16_t opbiasflt_lvl : 1; 624 uint16_t obtmpflt_lvl : 1; 625 uint16_t opprflt_lvl : 1; 626 uint16_t optxflt_lvl : 1; 627 uint16_t optrxlos_lvl : 1; 628 uint16_t oprxflt_lvl : 1; 629 uint16_t optxon_lvl : 1; 630 uint16_t res1 : 7; 631 #else 632 uint16_t res1 : 7; 633 uint16_t optxon_lvl : 1; 634 uint16_t oprxflt_lvl : 1; 635 uint16_t optrxlos_lvl : 1; 636 uint16_t optxflt_lvl : 1; 637 uint16_t opprflt_lvl : 1; 638 uint16_t obtmpflt_lvl : 1; 639 uint16_t opbiasflt_lvl : 1; 640 uint16_t optxrst_lvl : 1; 641 uint16_t optxenb_lvl : 1; 642 #endif 643 } bits; 644 } control_t, *p_control_t; 645 646 typedef union _pmd_tx_control { 647 uint16_t value; 648 struct { 649 #ifdef _BIT_FIELDS_HTOL 650 uint16_t res1 : 7; 651 uint16_t xfp_clken : 1; 652 uint16_t tx_dac_txd : 2; 653 uint16_t tx_dac_txck : 2; 654 uint16_t tsd_lpwren : 1; 655 uint16_t tsck_lpwren : 1; 656 uint16_t cmu_lpwren : 1; 657 uint16_t sfiforst : 1; 658 #else 659 uint16_t sfiforst : 1; 660 uint16_t cmu_lpwren : 1; 661 uint16_t tsck_lpwren : 1; 662 uint16_t tsd_lpwren : 1; 663 uint16_t tx_dac_txck : 2; 664 uint16_t tx_dac_txd : 2; 665 uint16_t xfp_clken : 1; 666 uint16_t res1 : 7; 667 #endif 668 } bits; 669 } pmd_tx_control_t, *p_pmd_tx_control_t; 670 671 672 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 673 674 typedef union _optics_dcntr { 675 uint16_t value; 676 struct { 677 #ifdef _BIT_FIELDS_HTOL 678 uint16_t fault_mode : 1; 679 uint16_t tx_pwrdown : 1; 680 uint16_t rx_pwrdown : 1; 681 uint16_t ext_flt_en : 1; 682 uint16_t opt_rst : 1; 683 uint16_t pcs_tx_inv_b : 1; 684 uint16_t pcs_rx_inv : 1; 685 uint16_t res3 : 2; 686 uint16_t gpio_sel : 2; 687 uint16_t res2 : 1; 688 uint16_t lpbk_err_dis : 1; 689 uint16_t res1 : 2; 690 uint16_t txonoff_pwdwn_dis : 1; 691 #else 692 uint16_t txonoff_pwdwn_dis : 1; 693 uint16_t res1 : 2; 694 uint16_t lpbk_err_dis : 1; 695 uint16_t res2 : 1; 696 uint16_t gpio_sel : 2; 697 uint16_t res3 : 2; 698 uint16_t pcs_rx_inv : 1; 699 uint16_t pcs_tx_inv_b : 1; 700 uint16_t opt_rst : 1; 701 uint16_t ext_flt_en : 1; 702 uint16_t rx_pwrdown : 1; 703 uint16_t tx_pwrdown : 1; 704 uint16_t fault_mode : 1; 705 #endif 706 } bits; 707 } optics_dcntr_t, *p_optics_dcntr_t; 708 709 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 710 711 #define PMD_RX_SIG_DET3 0x10 712 #define PMD_RX_SIG_DET2 0x08 713 #define PMD_RX_SIG_DET1 0x04 714 #define PMD_RX_SIG_DET0 0x02 715 #define GLOB_PMD_RX_SIG_OK 0x01 716 717 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 718 719 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 720 #define PCS_PRBS31_ABLE 0x0004 721 #define PCS_10GBASE_R_HI_BER 0x0002 722 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 723 724 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 725 726 #define XGXS_LANE_ALIGN_STATUS 0x1000 727 #define XGXS_PATTERN_TEST_ABILITY 0x0800 728 #define XGXS_LANE3_SYNC 0x0008 729 #define XGXS_LANE2_SYNC 0x0004 730 #define XGXS_LANE1_SYNC 0x0002 731 #define XGXS_LANE0_SYNC 0x0001 732 #define XGXS_LANE_STAT_MAGIC 0x0400 733 734 735 /* Teranetics TN1010 Definitions */ 736 737 /* Teranetics TN1010 PHY MMD Addresses */ 738 #define TN1010_PMA_PMD_DEV_ADDR 1 739 #define TN1010_PCS_DEV_ADDR 3 740 #define TN1010_PHYXS_DEV_ADDR 4 741 #define TN1010_AUTONEG_DEV_ADDR 7 742 #define TN1010_VENDOR_MMD1_DEV_ADDR 30 743 744 /* TN1010 PCS Control Register */ 745 typedef union _tn1010_pcs_ctrl { 746 uint16_t value; 747 struct { 748 #ifdef _BIT_FIELDS_HTOL 749 uint16_t reset : 1; /* bit 15 */ 750 uint16_t loopback : 1; /* bit 14 */ 751 uint16_t speed_sel2 : 1; 752 uint16_t res2 : 1; 753 uint16_t low_power : 1; 754 uint16_t res1 : 4; 755 uint16_t speed_sel1 : 1; /* bit 6 */ 756 uint16_t speed_sel0 : 4; /* bits[5:2] */ 757 uint16_t res0 : 2; 758 #else 759 uint16_t res0 : 2; 760 uint16_t speed_sel0 : 4; /* bits[5:2] */ 761 uint16_t speed_sel1 : 1; /* bit 6 */ 762 uint16_t res1 : 4; 763 uint16_t low_power : 1; 764 uint16_t res2 : 1; 765 uint16_t speed_sel2 : 1; 766 uint16_t loopback : 1; /* bit 14 */ 767 uint16_t reset : 1; /* bit 15 */ 768 #endif 769 } bits; 770 } tn1010_phyxs_ctrl_t, *p_tn1010_phyxs_ctrl_t; 771 772 /* TN1010 PHY XS Control Register */ 773 typedef union _tn1010_phyxs_ctrl { 774 uint16_t value; 775 struct { 776 #ifdef _BIT_FIELDS_HTOL 777 uint16_t reset : 1; /* bit 15 */ 778 uint16_t loopback : 1; /* bit 14 */ 779 uint16_t speed_sel2 : 1; 780 uint16_t res2 : 1; 781 uint16_t low_power : 1; 782 uint16_t res1 : 4; 783 uint16_t speed_sel1 : 1; /* bit 6 */ 784 uint16_t speed_sel0 : 4; /* bits[5:2] */ 785 uint16_t res0 : 2; 786 #else 787 uint16_t res0 : 2; 788 uint16_t speed_sel0 : 4; /* bits[5:2] */ 789 uint16_t speed_sel1 : 1; /* bit 6 */ 790 uint16_t res1 : 4; 791 uint16_t low_power : 1; 792 uint16_t res2 : 1; 793 uint16_t speed_sel2 : 1; 794 uint16_t loopback : 1; /* bit 14 */ 795 uint16_t reset : 1; /* bit 15 */ 796 #endif 797 } bits; 798 } tn1010_pcs_ctrl_t, *p_tn1010_pcs_ctrl_t; 799 800 /* TN1010 VENDOR MMD1 GPHY Control register 30.310 */ 801 #define TN1010_SGMII_LOOPBACK 1 802 #define TN1010_DEEP_LOOPBACK 2 803 804 #define TN1010_PMD_CONTROL_REG 0 805 #define TN1010_PMD_STATUS_REG 1 806 #define TN1010_PMD_ID_HIGH_REG 2 807 #define TN1010_PMD_ID_LOW_REG 3 808 #define TN1010_PMD_SPEED_ABIL_REG 4 809 #define TN1010_PMD_DEV_IN_PKG1_REG 5 810 #define TN1010_PMD_DEV_IN_PKG2_REG 6 811 #define TN1010_PMD_CONTROL2_REG 7 812 #define TN1010_PMD_STATUS2_REG 8 813 #define TN1010_PMD_TRANSMIT_DIS_REG 9 814 #define TN1010_PMD_RECEIVE_SIG_DETECT 10 815 #define TN1010_PMD_ORG_UNIQUE_ID_0_REG 14 816 #define TN1010_PMD_ORG_UNIQUE_ID_1_REG 15 817 #define TN1010_PCS_CONTROL_REG 0 818 #define TN1010_PCS_STATUS1_REG 1 819 #define TN1010_PCS_ID_HIGH_REG 2 820 #define TN1010_PCS_ID_LOW_REG 3 821 #define TN1010_PCS_SPEED_ABILITY_REG 4 822 #define TN1010_PCS_DEV_IN_PKG1_REG 5 823 #define TN1010_PCS_DEV_IN_PKG2_REG 6 824 #define TN1010_PCS_CONTROL2_REG 7 825 #define TN1010_PCS_STATUS2_REG 8 826 #define TN1010_PCS_ORG_UNIQUE_ID_0_REG 14 827 #define TN1010_PCS_ORG_UNIQUE_ID_1_REG 15 828 #define TN1010_PCS_10GBASE_R_T_STATUS1_REG 32 829 #define TN1010_PCS_10GBASE_R_T_STATUS2_REG 33 830 #define TN1010_PHYXS_CONTROL_REG 0 831 #define TN1010_PHYXS_STATUS_REG 1 832 #define TN1010_PHY_ID_HIGH_REG 2 833 #define TN1010_PHY_ID_LOW_REG 3 834 #define TN1010_PHYXS_SPEED_ABILITY_REG 4 835 #define TN1010_PHYXS_DEV_IN_PKG2_REG 5 836 #define TN1010_PHYXS_DEV_IN_PKG1_REG 6 837 #define TN1010_PHYXS_STATUS2_REG 8 838 #define TN1010_PHYXS_ORG_UNIQUE_ID_0_REG 14 839 #define TN1010_PHYXS_ORG_UNIQUE_ID_1_REG 15 840 #define TN1010_PHYXS_XGXS_LANE_STATUS_REG 24 841 #define TN1010_PHYXS_XGXS_TEST_CONTROL_REG 25 842 843 #define TN1010_AUTONEG_CONTROL_REG 0 844 #define TN1010_AUTONEG_STATUS_REG 1 845 #define TN1010_AUTONEG_ID_HIGH_REG 2 846 #define TN1010_AUTONEG_ID_LOW_REG 3 847 #define TN1010_AUTONEG_DEV_IN_PKG1_REG 5 848 #define TN1010_AUTUNEG_DEV_IN_PKG2_REG 6 849 #define TN1010_AUTONEG_ORG_UNIQUE_ID_0_REG 14 850 #define TN1010_AUTONEG_ORG_UNIQUE_ID_1_REG 15 851 #define TN1010_AUTONEG_ADVERTISE_REG 16 852 #define TN1010_AUTONEG_PARTNER_ABILITY_REG 19 853 854 #define TN1010_VENDOR_MMD1_CONTROL_REG 0 855 #define TN1010_VENDOR_MMD1_STATUS_REG 1 856 #define TN1010_VENDOR_MMD1_ID_HIGH 2 857 #define TN1010_VENDOR_MMD1_ID_LOW 3 858 #define TN1010_VENDOR_MMD1_DEV_STATUS_REG 8 859 #define TN1010_VENDOR_MMD1_FNS_CONTROL_RER 9 860 #define TN1010_VENDOR_MMD1_PKG_ID_0_REG 14 861 #define TN1010_VENDOR_MMD1_PKG_ID_1_REG 15 862 #define TN1010_VENDOR_MMD1_GPHY_CTRL 310 863 864 /* Bits definitions of TN1010_AUTONEG_CONTROL_REG */ 865 #define TN1010_AN_CTRL_RESET_BIT 0x8000 /* Reset */ 866 #define TN1010_AN_CTRL_EN_BIT 0x1000 /* Enable autoneg */ 867 #define TN1010_AN_CTRL_RESTART_BIT 0x200 /* Restart autoneg */ 868 #define TN1010_AN_LINK_STAT_BIT 0x4 /* Link status */ 869 870 /* Bits definitions of TN1010_PHYXS_CONTROL_REG */ 871 #define TN1010_VENDOR_MMD1_AN_STAT_BITS 0xC0 872 873 /* 874 * Shift right 6 bits so bits[7:6] becomes [1:0]. 875 * Bits[7:6] of TN1010_VENDOR_MND1_STATUS_REG are for autoneg status 876 * 00 in progress 877 * 01 completed 878 * 10 reserved 879 * 11 failed 880 */ 881 #define TN1010_VENDOR_MMD1_AN_STAT_SHIFT 6 882 883 /* Bit 4 of TN1010_VENDOR_MMD1_STATUS_REG is speed. 0: 10G, 1: 1G */ 884 #define TN1010_VENDOR_MMD1_AN_SPEED_BIT 0x10 885 886 /* Shift right 4 bits so bit4 becomes bit0 */ 887 #define TN1010_VENDOR_MMD1_AN_SPEED_SHIFT 4 888 889 890 #ifdef __cplusplus 891 } 892 #endif 893 894 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 895