1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <nxge_defs.h> 37 38 #define NXGE_MAX_PHY_PORTS 32 39 #define NXGE_EXT_PHY_PORT_ST 8 40 41 #define NXGE_PMA_PMD_DEV_ADDR 1 42 #define NXGE_PCS_DEV_ADDR 3 43 #define NXGE_DEV_ID_REG_1 2 44 #define NXGE_DEV_ID_REG_2 3 45 #define NXGE_PHY_ID_REG_1 2 46 #define NXGE_PHY_ID_REG_2 3 47 48 /* 49 * The BCM_PHY_ID_MASK is explained below: 50 * The first nibble (bits 0 through 3) is changed with every revision 51 * of the silicon. So these bits are masked out to support future revisions 52 * of the same chip. The third nibble (bits 8 through 11) is changed for 53 * different chips of the same family. So these bits are masked out to 54 * support chips of the same family. 55 */ 56 #define BCM_PHY_ID_MASK 0xfffff0f0 57 #define BCM8704_DEV_ID 0x206033 58 #define BCM5464R_PHY_ID 0x2060b1 59 #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 60 #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 61 62 #define CLAUSE_45_TYPE 1 63 #define CLAUSE_22_TYPE 2 64 65 #define BCM5464_NEPTUNE_PORT_ADDR_BASE 10 66 #define BCM8704_NEPTUNE_PORT_ADDR_BASE 8 67 #define BCM8704_N2_PORT_ADDR_BASE 16 68 69 /* 70 * Phy addresses for Maramba support. Support for P0 will eventually 71 * be removed. 72 */ 73 #define BCM5464_MARAMBA_P0_PORT_ADDR_BASE 10 74 #define BCM5464_MARAMBA_P1_PORT_ADDR_BASE 26 75 #define BCM8704_MARAMBA_PORT_ADDR_BASE 16 76 77 #define BCM8704_PMA_PMD_DEV_ADDR 1 78 #define BCM8704_PCS_DEV_ADDR 3 79 #define BCM8704_USER_DEV3_ADDR 3 80 #define BCM8704_PHYXS_ADDR 4 81 #define BCM8704_USER_DEV4_ADDR 4 82 83 /* Definitions for BCM 5464R PHY chip */ 84 85 #define BCM5464R_PHY_ECR 16 86 #define BCM5464R_PHY_ESR 17 87 #define BCM5464R_RXERR_CNT 18 88 #define BCM5464R_FALSECS_CNT 19 89 #define BCM5464R_RX_NOTOK_CNT 20 90 #define BCM5464R_ER_DATA 21 91 #define BCM5464R_RES 22 92 #define BCM5464R_ER_ACC 23 93 #define BCM5464R_AUX_CTL 24 94 #define BCM5464R_AUX_S 25 95 #define BCM5464R_INTR_S 26 96 #define BCM5464R_INTR_M 27 97 #define BCM5464R_MISC 28 98 #define BCM5464R_MISC1 29 99 #define BCM5464R_TESTR1 30 100 101 #define PHY_BCM_5464R_OUI 0x001018 102 #define PHY_BCM_5464R_MODEL 0x0B 103 104 /* 105 * MII Register 16: PHY Extended Control Register 106 */ 107 108 typedef union _mii_phy_ecr_t { 109 uint16_t value; 110 struct { 111 #ifdef _BIT_FIELDS_HTOL 112 uint16_t mac_phy_if_mode : 1; 113 uint16_t dis_automdicross : 1; 114 uint16_t tx_dis : 1; 115 uint16_t intr_dis : 1; 116 uint16_t force_intr : 1; 117 uint16_t bypass_encdec : 1; 118 uint16_t bypass_scrdes : 1; 119 uint16_t bypass_mlt3 : 1; 120 uint16_t bypass_rx_sym : 1; 121 uint16_t reset_scr : 1; 122 uint16_t en_led_traffic : 1; 123 uint16_t force_leds_on : 1; 124 uint16_t force_leds_off : 1; 125 uint16_t res : 2; 126 uint16_t gmii_fifo_elas : 1; 127 #else 128 uint16_t gmii_fifo_elas : 1; 129 uint16_t res : 2; 130 uint16_t force_leds_off : 1; 131 uint16_t force_leds_on : 1; 132 uint16_t en_led_traffic : 1; 133 uint16_t reset_scr : 1; 134 uint16_t bypass_rx_sym : 1; 135 uint16_t bypass_mlt3 : 1; 136 uint16_t bypass_scrdes : 1; 137 uint16_t bypass_encdec : 1; 138 uint16_t force_intr : 1; 139 uint16_t intr_dis : 1; 140 uint16_t tx_dis : 1; 141 uint16_t dis_automdicross : 1; 142 uint16_t mac_phy_if_mode : 1; 143 #endif 144 } bits; 145 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 146 147 /* 148 * MII Register 17: PHY Extended Status Register 149 */ 150 typedef union _mii_phy_esr_t { 151 uint16_t value; 152 struct { 153 #ifdef _BIT_FIELDS_HTOL 154 uint16_t anbpsfm : 1; 155 uint16_t wsdwngr : 1; 156 uint16_t mdi_crst : 1; 157 uint16_t intr_s : 1; 158 uint16_t rmt_rx_s : 1; 159 uint16_t loc_rx_s : 1; 160 uint16_t locked : 1; 161 uint16_t link_s : 1; 162 uint16_t crc_err : 1; 163 uint16_t cext_err : 1; 164 uint16_t bad_ssd : 1; 165 uint16_t bad_esd : 1; 166 uint16_t rx_err : 1; 167 uint16_t tx_err : 1; 168 uint16_t lock_err : 1; 169 uint16_t mlt3_cerr : 1; 170 #else 171 uint16_t mlt3_cerr : 1; 172 uint16_t lock_err : 1; 173 uint16_t tx_err : 1; 174 uint16_t rx_err : 1; 175 uint16_t bad_esd : 1; 176 uint16_t bad_ssd : 1; 177 uint16_t cext_err : 1; 178 uint16_t crc_err : 1; 179 uint16_t link_s : 1; 180 uint16_t locked : 1; 181 uint16_t loc_rx_s : 1; 182 uint16_t rmt_rx_s : 1; 183 uint16_t intr_s : 1; 184 uint16_t mdi_crst : 1; 185 uint16_t wsdwngr : 1; 186 uint16_t anbpsfm : 1; 187 #endif 188 } bits; 189 } mii_phy_esr_t, *p_mii_phy_esr_t; 190 191 /* 192 * MII Register 18: Receive Error Counter Register 193 */ 194 typedef union _mii_rxerr_cnt_t { 195 uint16_t value; 196 struct { 197 uint16_t rx_err_cnt : 16; 198 } bits; 199 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 200 201 /* 202 * MII Register 19: False Carrier Sense Counter Register 203 */ 204 typedef union _mii_falsecs_cnt_t { 205 uint16_t value; 206 struct { 207 #ifdef _BIT_FIELDS_HTOL 208 uint16_t res : 8; 209 uint16_t false_cs_cnt : 8; 210 #else 211 uint16_t false_cs_cnt : 8; 212 uint16_t res : 8; 213 #endif 214 } bits; 215 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 216 217 /* 218 * MII Register 20: Receiver NOT_OK Counter Register 219 */ 220 typedef union _mii_rx_notok_cnt_t { 221 uint16_t value; 222 struct { 223 #ifdef _BIT_FIELDS_HTOL 224 uint16_t l_rx_notok_cnt : 8; 225 uint16_t r_rx_notok_cnt : 8; 226 #else 227 uint16_t r_rx_notok_cnt : 8; 228 uint16_t l_rx_notok_cnt : 8; 229 #endif 230 } bits; 231 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 232 233 /* 234 * MII Register 21: Expansion Register Data Register 235 */ 236 typedef union _mii_er_data_t { 237 uint16_t value; 238 struct { 239 uint16_t reg_data; 240 } bits; 241 } mii_er_data_t, *p_mii_er_data_t; 242 243 /* 244 * MII Register 23: Expansion Register Access Register 245 */ 246 typedef union _mii_er_acc_t { 247 struct { 248 #ifdef _BIT_FIELDS_HTOL 249 uint16_t res : 4; 250 uint16_t er_sel : 4; 251 uint16_t er_acc : 8; 252 #else 253 uint16_t er_acc : 8; 254 uint16_t er_sel : 4; 255 uint16_t res : 4; 256 #endif 257 } bits; 258 } mii_er_acc_t, *p_mii_er_acc_t; 259 260 #define EXP_RXTX_PKT_CNT 0x0 261 #define EXP_INTR_STAT 0x1 262 #define MULTICOL_LED_SEL 0x4 263 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 264 #define MULTICOL_LED_BLINK_CTL 0x6 265 #define CABLE_DIAG_CTL 0x10 266 #define CABLE_DIAG_RES 0x11 267 #define CABLE_DIAG_LEN_CH_2_1 0x12 268 #define CABLE_DIAG_LEN_CH_4_3 0x13 269 270 /* 271 * MII Register 24: Auxiliary Control Register 272 */ 273 typedef union _mii_aux_ctl_t { 274 uint16_t value; 275 struct { 276 #ifdef _BIT_FIELDS_HTOL 277 uint16_t ext_lb : 1; 278 uint16_t ext_pkt_len : 1; 279 uint16_t edge_rate_ctl_1000 : 2; 280 uint16_t res : 1; 281 uint16_t write_1 : 1; 282 uint16_t res1 : 2; 283 uint16_t dis_partial_resp : 1; 284 uint16_t res2 : 1; 285 uint16_t edge_rate_ctl_100 : 2; 286 uint16_t diag_mode : 1; 287 uint16_t shadow_reg_sel : 3; 288 #else 289 uint16_t shadow_reg_sel : 3; 290 uint16_t diag_mode : 1; 291 uint16_t edge_rate_ctl_100 : 2; 292 uint16_t res2 : 1; 293 uint16_t dis_partial_resp : 1; 294 uint16_t res1 : 2; 295 uint16_t write_1 : 1; 296 uint16_t res : 1; 297 uint16_t edge_rate_ctl_1000 : 2; 298 uint16_t ext_pkt_len : 1; 299 uint16_t ext_lb : 1; 300 #endif 301 } bits; 302 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 303 304 #define AUX_REG 0x0 305 #define AUX_10BASET 0x1 306 #define AUX_PWR_CTL 0x2 307 #define AUX_MISC_TEST 0x4 308 #define AUX_MISC_CTL 0x7 309 310 /* 311 * MII Register 25: Auxiliary Status Summary Register 312 */ 313 typedef union _mii_aux_s_t { 314 uint16_t value; 315 struct { 316 #ifdef _BIT_FIELDS_HTOL 317 uint16_t an_complete : 1; 318 uint16_t an_complete_ack : 1; 319 uint16_t an_ack_detect : 1; 320 uint16_t an_ability_detect : 1; 321 uint16_t an_np_wait : 1; 322 uint16_t an_hcd : 3; 323 uint16_t pd_fault : 1; 324 uint16_t rmt_fault : 1; 325 uint16_t an_page_rx : 1; 326 uint16_t lp_an_ability : 1; 327 uint16_t lp_np_ability : 1; 328 uint16_t link_s : 1; 329 uint16_t pause_res_rx_dir : 1; 330 uint16_t pause_res_tx_dir : 1; 331 #else 332 uint16_t pause_res_tx_dir : 1; 333 uint16_t pause_res_rx_dir : 1; 334 uint16_t link_s : 1; 335 uint16_t lp_np_ability : 1; 336 uint16_t lp_an_ability : 1; 337 uint16_t an_page_rx : 1; 338 uint16_t rmt_fault : 1; 339 uint16_t pd_fault : 1; 340 uint16_t an_hcd : 3; 341 uint16_t an_np_wait : 1; 342 uint16_t an_ability_detect : 1; 343 uint16_t an_ack_detect : 1; 344 uint16_t an_complete_ack : 1; 345 uint16_t an_complete : 1; 346 #endif 347 } bits; 348 } mii_aux_s_t, *p_mii_aux_s_t; 349 350 /* 351 * MII Register 26, 27: Interrupt Status and Mask Registers 352 */ 353 typedef union _mii_intr_t { 354 uint16_t value; 355 struct { 356 #ifdef _BIT_FIELDS_HTOL 357 uint16_t res : 1; 358 uint16_t illegal_pair_swap : 1; 359 uint16_t mdix_status_change : 1; 360 uint16_t exceed_hicnt_thres : 1; 361 uint16_t exceed_locnt_thres : 1; 362 uint16_t an_page_rx : 1; 363 uint16_t hcd_nolink : 1; 364 uint16_t no_hcd : 1; 365 uint16_t neg_unsupported_hcd : 1; 366 uint16_t scr_sync_err : 1; 367 uint16_t rmt_rx_status_change : 1; 368 uint16_t loc_rx_status_change : 1; 369 uint16_t duplex_mode_change : 1; 370 uint16_t link_speed_change : 1; 371 uint16_t link_status_change : 1; 372 uint16_t crc_err : 1; 373 #else 374 uint16_t crc_err : 1; 375 uint16_t link_status_change : 1; 376 uint16_t link_speed_change : 1; 377 uint16_t duplex_mode_change : 1; 378 uint16_t loc_rx_status_change : 1; 379 uint16_t rmt_rx_status_change : 1; 380 uint16_t scr_sync_err : 1; 381 uint16_t neg_unsupported_hcd : 1; 382 uint16_t no_hcd : 1; 383 uint16_t hcd_nolink : 1; 384 uint16_t an_page_rx : 1; 385 uint16_t exceed_locnt_thres : 1; 386 uint16_t exceed_hicnt_thres : 1; 387 uint16_t mdix_status_change : 1; 388 uint16_t illegal_pair_swap : 1; 389 uint16_t res : 1; 390 #endif 391 } bits; 392 } mii_intr_t, *p_mii_intr_t; 393 394 /* 395 * MII Register 28: Register 1C Access Register 396 */ 397 typedef union _mii_misc_t { 398 uint16_t value; 399 struct { 400 #ifdef _BIT_FIELDS_HTOL 401 uint16_t w_en : 1; 402 uint16_t shadow_reg_sel : 5; 403 uint16_t data : 10; 404 #else 405 uint16_t data : 10; 406 uint16_t shadow_reg_sel : 5; 407 uint16_t w_en : 1; 408 #endif 409 } bits; 410 } mii_misc_t, *p_mii_misc_t; 411 412 #define LINK_LED_MODE 0x2 413 #define CLK_ALIGN_CTL 0x3 414 #define WIRE_SP_RETRY 0x4 415 #define CLK125 0x5 416 #define LED_STATUS 0x8 417 #define LED_CONTROL 0x9 418 #define AUTO_PWR_DOWN 0xA 419 #define LED_SEL1 0xD 420 #define LED_SEL2 0xE 421 422 /* 423 * MII Register 29: Master/Slave Seed / HCD Status Register 424 */ 425 426 typedef union _mii_misc1_t { 427 uint16_t value; 428 struct { 429 #ifdef _BIT_FIELDS_HTOL 430 uint16_t en_shadow_reg : 1; 431 uint16_t data : 15; 432 #else 433 uint16_t data : 15; 434 uint16_t en_shadow_reg : 1; 435 #endif 436 } bits; 437 } mii_misc1_t, *p_mii_misc1_t; 438 439 /* 440 * MII Register 30: Test Register 1 441 */ 442 443 typedef union _mii_test1_t { 444 uint16_t value; 445 struct { 446 #ifdef _BIT_FIELDS_HTOL 447 uint16_t crc_err_cnt_sel : 1; 448 uint16_t res : 7; 449 uint16_t manual_swap_mdi_st : 1; 450 uint16_t res1 : 7; 451 #else 452 uint16_t res1 : 7; 453 uint16_t manual_swap_mdi_st : 1; 454 uint16_t res : 7; 455 uint16_t crc_err_cnt_sel : 1; 456 #endif 457 } bits; 458 } mii_test1_t, *p_mii_test1_t; 459 460 461 /* Definitions of BCM8704 */ 462 463 #define BCM8704_PMD_CONTROL_REG 0 464 #define BCM8704_PMD_STATUS_REG 0x1 465 #define BCM8704_PMD_ID_0_REG 0x2 466 #define BCM8704_PMD_ID_1_REG 0x3 467 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 468 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 469 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 470 #define BCM8704_PMD_CONTROL2_REG 0x7 471 #define BCM8704_PMD_STATUS2_REG 0x8 472 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 473 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 474 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 475 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 476 #define BCM8704_PCS_CONTROL_REG 0 477 #define BCM8704_PCS_STATUS1_REG 0x1 478 #define BCM8704_PCS_ID_0_REG 0x2 479 #define BCM8704_PCS_ID_1_REG 0x3 480 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 481 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 482 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 483 #define BCM8704_PCS_CONTROL2_REG 0x7 484 #define BCM8704_PCS_STATUS2_REG 0x8 485 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 486 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 487 #define BCM8704_PCS_STATUS_REG 0x18 488 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 489 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 490 #define BCM8704_PHYXS_CONTROL_REG 0 491 #define BCM8704_PHYXS_STATUS_REG 0x1 492 #define BCM8704_PHY_ID_0_REG 0x2 493 #define BCM8704_PHY_ID_1_REG 0x3 494 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 495 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 496 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 497 #define BCM8704_PHYXS_STATUS2_REG 0x8 498 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 499 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 500 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 501 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 502 #define BCM8704_USER_CONTROL_REG 0xC800 503 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 504 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 505 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 506 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 507 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 508 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 509 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 510 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 511 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 512 513 /* Rx Channel Control1 Register bits */ 514 #define BCM8704_RXPOL_FLIP 0x20 515 516 typedef union _phyxs_control { 517 uint16_t value; 518 struct { 519 #ifdef _BIT_FIELDS_HTOL 520 uint16_t reset : 1; 521 uint16_t loopback : 1; 522 uint16_t speed_sel2 : 1; 523 uint16_t res2 : 1; 524 uint16_t low_power : 1; 525 uint16_t res1 : 4; 526 uint16_t speed_sel1 : 1; 527 uint16_t speed_sel0 : 4; 528 uint16_t res0 : 2; 529 #else 530 uint16_t res0 : 2; 531 uint16_t speed_sel0 : 4; 532 uint16_t speed_sel1 : 1; 533 uint16_t res1 : 4; 534 uint16_t low_power : 1; 535 uint16_t res2 : 1; 536 uint16_t speed_sel2 : 1; 537 uint16_t loopback : 1; 538 uint16_t reset : 1; 539 #endif 540 } bits; 541 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 542 543 544 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 545 546 typedef union _control { 547 uint16_t value; 548 struct { 549 #ifdef _BIT_FIELDS_HTOL 550 uint16_t optxenb_lvl : 1; 551 uint16_t optxrst_lvl : 1; 552 uint16_t opbiasflt_lvl : 1; 553 uint16_t obtmpflt_lvl : 1; 554 uint16_t opprflt_lvl : 1; 555 uint16_t optxflt_lvl : 1; 556 uint16_t optrxlos_lvl : 1; 557 uint16_t oprxflt_lvl : 1; 558 uint16_t optxon_lvl : 1; 559 uint16_t res1 : 7; 560 #else 561 uint16_t res1 : 7; 562 uint16_t optxon_lvl : 1; 563 uint16_t oprxflt_lvl : 1; 564 uint16_t optrxlos_lvl : 1; 565 uint16_t optxflt_lvl : 1; 566 uint16_t opprflt_lvl : 1; 567 uint16_t obtmpflt_lvl : 1; 568 uint16_t opbiasflt_lvl : 1; 569 uint16_t optxrst_lvl : 1; 570 uint16_t optxenb_lvl : 1; 571 #endif 572 } bits; 573 } control_t, *p_control_t; 574 575 typedef union _pmd_tx_control { 576 uint16_t value; 577 struct { 578 #ifdef _BIT_FIELDS_HTOL 579 uint16_t res1 : 7; 580 uint16_t xfp_clken : 1; 581 uint16_t tx_dac_txd : 2; 582 uint16_t tx_dac_txck : 2; 583 uint16_t tsd_lpwren : 1; 584 uint16_t tsck_lpwren : 1; 585 uint16_t cmu_lpwren : 1; 586 uint16_t sfiforst : 1; 587 #else 588 uint16_t sfiforst : 1; 589 uint16_t cmu_lpwren : 1; 590 uint16_t tsck_lpwren : 1; 591 uint16_t tsd_lpwren : 1; 592 uint16_t tx_dac_txck : 2; 593 uint16_t tx_dac_txd : 2; 594 uint16_t xfp_clken : 1; 595 uint16_t res1 : 7; 596 #endif 597 } bits; 598 } pmd_tx_control_t, *p_pmd_tx_control_t; 599 600 601 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 602 603 604 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 605 606 typedef union _optics_dcntr { 607 uint16_t value; 608 struct { 609 #ifdef _BIT_FIELDS_HTOL 610 uint16_t fault_mode : 1; 611 uint16_t tx_pwrdown : 1; 612 uint16_t rx_pwrdown : 1; 613 uint16_t ext_flt_en : 1; 614 uint16_t opt_rst : 1; 615 uint16_t pcs_tx_inv_b : 1; 616 uint16_t pcs_rx_inv : 1; 617 uint16_t res3 : 2; 618 uint16_t gpio_sel : 2; 619 uint16_t res2 : 1; 620 uint16_t lpbk_err_dis : 1; 621 uint16_t res1 : 2; 622 uint16_t txonoff_pwdwn_dis : 1; 623 #else 624 uint16_t txonoff_pwdwn_dis : 1; 625 uint16_t res1 : 2; 626 uint16_t lpbk_err_dis : 1; 627 uint16_t res2 : 1; 628 uint16_t gpio_sel : 2; 629 uint16_t res3 : 2; 630 uint16_t pcs_rx_inv : 1; 631 uint16_t pcs_tx_inv_b : 1; 632 uint16_t opt_rst : 1; 633 uint16_t ext_flt_en : 1; 634 uint16_t rx_pwrdown : 1; 635 uint16_t tx_pwrdown : 1; 636 uint16_t fault_mode : 1; 637 #endif 638 } bits; 639 } optics_dcntr_t, *p_optics_dcntr_t; 640 641 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 642 643 #define PMD_RX_SIG_DET3 0x10 644 #define PMD_RX_SIG_DET2 0x08 645 #define PMD_RX_SIG_DET1 0x04 646 #define PMD_RX_SIG_DET0 0x02 647 #define GLOB_PMD_RX_SIG_OK 0x01 648 649 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 650 651 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 652 #define PCS_PRBS31_ABLE 0x0004 653 #define PCS_10GBASE_R_HI_BER 0x0002 654 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 655 656 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 657 658 #define XGXS_LANE_ALIGN_STATUS 0x1000 659 #define XGXS_PATTERN_TEST_ABILITY 0x0800 660 #define XGXS_LANE3_SYNC 0x0008 661 #define XGXS_LANE2_SYNC 0x0004 662 #define XGXS_LANE1_SYNC 0x0002 663 #define XGXS_LANE0_SYNC 0x0001 664 665 #ifdef __cplusplus 666 } 667 #endif 668 669 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 670