1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <nxge_defs.h> 37 38 #define NXGE_MAX_PHY_PORTS 32 39 #define NXGE_EXT_PHY_PORT_ST 8 40 41 #define NXGE_PMA_PMD_DEV_ADDR 1 42 #define NXGE_PCS_DEV_ADDR 3 43 #define NXGE_DEV_ID_REG_1 2 44 #define NXGE_DEV_ID_REG_2 3 45 #define NXGE_PHY_ID_REG_1 2 46 #define NXGE_PHY_ID_REG_2 3 47 48 #define BCM8704_CHIP_ID 0x8704 49 #define BCM8706_CHIP_ID 0x8706 50 51 /* 52 * The BCM_PHY_ID_MASK is explained below: 53 * The first nibble (bits 0 through 3) is changed with every revision 54 * of the silicon. So these bits are masked out to support future revisions 55 * of the same chip. The third nibble (bits 8 through 11) is changed for 56 * different chips of the same family. So these bits are masked out to 57 * support chips of the same family. 58 */ 59 #define BCM_PHY_ID_MASK 0xfffff0f0 60 #define BCM8704_DEV_ID 0x206033 61 #define BCM5464R_PHY_ID 0x2060b1 62 #define BCM8706_DEV_ID 0x206035 63 #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 64 #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 65 66 #define CLAUSE_45_TYPE 1 67 #define CLAUSE_22_TYPE 2 68 69 #define BCM5464_NEPTUNE_PORT_ADDR_BASE 10 70 #define BCM8704_NEPTUNE_PORT_ADDR_BASE 8 71 #define BCM8704_N2_PORT_ADDR_BASE 16 72 73 /* 74 * Phy address for the second NIU port on Goa NEM card can be either 75 * 20 or 17 76 */ 77 #define BCM8706_GOA_PORT_ADDR_BASE 16 78 #define BCM8706_ALT_GOA_PORT1_ADDR 20 79 /* 80 * Phy addresses for Maramba support. Support for P0 will eventually 81 * be removed. 82 */ 83 #define BCM5464_MARAMBA_P0_PORT_ADDR_BASE 10 84 #define BCM5464_MARAMBA_P1_PORT_ADDR_BASE 26 85 #define BCM8704_MARAMBA_PORT_ADDR_BASE 16 86 87 #define BCM8704_PMA_PMD_DEV_ADDR 1 88 #define BCM8704_PCS_DEV_ADDR 3 89 #define BCM8704_USER_DEV3_ADDR 3 90 #define BCM8704_PHYXS_ADDR 4 91 #define BCM8704_USER_DEV4_ADDR 4 92 93 /* Definitions for BCM 5464R PHY chip */ 94 95 #define BCM5464R_PHY_ECR 16 96 #define BCM5464R_PHY_ESR 17 97 #define BCM5464R_RXERR_CNT 18 98 #define BCM5464R_FALSECS_CNT 19 99 #define BCM5464R_RX_NOTOK_CNT 20 100 #define BCM5464R_ER_DATA 21 101 #define BCM5464R_RES 22 102 #define BCM5464R_ER_ACC 23 103 #define BCM5464R_AUX_CTL 24 104 #define BCM5464R_AUX_S 25 105 #define BCM5464R_INTR_S 26 106 #define BCM5464R_INTR_M 27 107 #define BCM5464R_MISC 28 108 #define BCM5464R_MISC1 29 109 #define BCM5464R_TESTR1 30 110 111 #define PHY_BCM_5464R_OUI 0x001018 112 #define PHY_BCM_5464R_MODEL 0x0B 113 114 /* 115 * MII Register 16: PHY Extended Control Register 116 */ 117 118 typedef union _mii_phy_ecr_t { 119 uint16_t value; 120 struct { 121 #ifdef _BIT_FIELDS_HTOL 122 uint16_t mac_phy_if_mode : 1; 123 uint16_t dis_automdicross : 1; 124 uint16_t tx_dis : 1; 125 uint16_t intr_dis : 1; 126 uint16_t force_intr : 1; 127 uint16_t bypass_encdec : 1; 128 uint16_t bypass_scrdes : 1; 129 uint16_t bypass_mlt3 : 1; 130 uint16_t bypass_rx_sym : 1; 131 uint16_t reset_scr : 1; 132 uint16_t en_led_traffic : 1; 133 uint16_t force_leds_on : 1; 134 uint16_t force_leds_off : 1; 135 uint16_t res : 2; 136 uint16_t gmii_fifo_elas : 1; 137 #else 138 uint16_t gmii_fifo_elas : 1; 139 uint16_t res : 2; 140 uint16_t force_leds_off : 1; 141 uint16_t force_leds_on : 1; 142 uint16_t en_led_traffic : 1; 143 uint16_t reset_scr : 1; 144 uint16_t bypass_rx_sym : 1; 145 uint16_t bypass_mlt3 : 1; 146 uint16_t bypass_scrdes : 1; 147 uint16_t bypass_encdec : 1; 148 uint16_t force_intr : 1; 149 uint16_t intr_dis : 1; 150 uint16_t tx_dis : 1; 151 uint16_t dis_automdicross : 1; 152 uint16_t mac_phy_if_mode : 1; 153 #endif 154 } bits; 155 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 156 157 /* 158 * MII Register 17: PHY Extended Status Register 159 */ 160 typedef union _mii_phy_esr_t { 161 uint16_t value; 162 struct { 163 #ifdef _BIT_FIELDS_HTOL 164 uint16_t anbpsfm : 1; 165 uint16_t wsdwngr : 1; 166 uint16_t mdi_crst : 1; 167 uint16_t intr_s : 1; 168 uint16_t rmt_rx_s : 1; 169 uint16_t loc_rx_s : 1; 170 uint16_t locked : 1; 171 uint16_t link_s : 1; 172 uint16_t crc_err : 1; 173 uint16_t cext_err : 1; 174 uint16_t bad_ssd : 1; 175 uint16_t bad_esd : 1; 176 uint16_t rx_err : 1; 177 uint16_t tx_err : 1; 178 uint16_t lock_err : 1; 179 uint16_t mlt3_cerr : 1; 180 #else 181 uint16_t mlt3_cerr : 1; 182 uint16_t lock_err : 1; 183 uint16_t tx_err : 1; 184 uint16_t rx_err : 1; 185 uint16_t bad_esd : 1; 186 uint16_t bad_ssd : 1; 187 uint16_t cext_err : 1; 188 uint16_t crc_err : 1; 189 uint16_t link_s : 1; 190 uint16_t locked : 1; 191 uint16_t loc_rx_s : 1; 192 uint16_t rmt_rx_s : 1; 193 uint16_t intr_s : 1; 194 uint16_t mdi_crst : 1; 195 uint16_t wsdwngr : 1; 196 uint16_t anbpsfm : 1; 197 #endif 198 } bits; 199 } mii_phy_esr_t, *p_mii_phy_esr_t; 200 201 /* 202 * MII Register 18: Receive Error Counter Register 203 */ 204 typedef union _mii_rxerr_cnt_t { 205 uint16_t value; 206 struct { 207 uint16_t rx_err_cnt : 16; 208 } bits; 209 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 210 211 /* 212 * MII Register 19: False Carrier Sense Counter Register 213 */ 214 typedef union _mii_falsecs_cnt_t { 215 uint16_t value; 216 struct { 217 #ifdef _BIT_FIELDS_HTOL 218 uint16_t res : 8; 219 uint16_t false_cs_cnt : 8; 220 #else 221 uint16_t false_cs_cnt : 8; 222 uint16_t res : 8; 223 #endif 224 } bits; 225 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 226 227 /* 228 * MII Register 20: Receiver NOT_OK Counter Register 229 */ 230 typedef union _mii_rx_notok_cnt_t { 231 uint16_t value; 232 struct { 233 #ifdef _BIT_FIELDS_HTOL 234 uint16_t l_rx_notok_cnt : 8; 235 uint16_t r_rx_notok_cnt : 8; 236 #else 237 uint16_t r_rx_notok_cnt : 8; 238 uint16_t l_rx_notok_cnt : 8; 239 #endif 240 } bits; 241 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 242 243 /* 244 * MII Register 21: Expansion Register Data Register 245 */ 246 typedef union _mii_er_data_t { 247 uint16_t value; 248 struct { 249 uint16_t reg_data; 250 } bits; 251 } mii_er_data_t, *p_mii_er_data_t; 252 253 /* 254 * MII Register 23: Expansion Register Access Register 255 */ 256 typedef union _mii_er_acc_t { 257 struct { 258 #ifdef _BIT_FIELDS_HTOL 259 uint16_t res : 4; 260 uint16_t er_sel : 4; 261 uint16_t er_acc : 8; 262 #else 263 uint16_t er_acc : 8; 264 uint16_t er_sel : 4; 265 uint16_t res : 4; 266 #endif 267 } bits; 268 } mii_er_acc_t, *p_mii_er_acc_t; 269 270 #define EXP_RXTX_PKT_CNT 0x0 271 #define EXP_INTR_STAT 0x1 272 #define MULTICOL_LED_SEL 0x4 273 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 274 #define MULTICOL_LED_BLINK_CTL 0x6 275 #define CABLE_DIAG_CTL 0x10 276 #define CABLE_DIAG_RES 0x11 277 #define CABLE_DIAG_LEN_CH_2_1 0x12 278 #define CABLE_DIAG_LEN_CH_4_3 0x13 279 280 /* 281 * MII Register 24: Auxiliary Control Register 282 */ 283 typedef union _mii_aux_ctl_t { 284 uint16_t value; 285 struct { 286 #ifdef _BIT_FIELDS_HTOL 287 uint16_t ext_lb : 1; 288 uint16_t ext_pkt_len : 1; 289 uint16_t edge_rate_ctl_1000 : 2; 290 uint16_t res : 1; 291 uint16_t write_1 : 1; 292 uint16_t res1 : 2; 293 uint16_t dis_partial_resp : 1; 294 uint16_t res2 : 1; 295 uint16_t edge_rate_ctl_100 : 2; 296 uint16_t diag_mode : 1; 297 uint16_t shadow_reg_sel : 3; 298 #else 299 uint16_t shadow_reg_sel : 3; 300 uint16_t diag_mode : 1; 301 uint16_t edge_rate_ctl_100 : 2; 302 uint16_t res2 : 1; 303 uint16_t dis_partial_resp : 1; 304 uint16_t res1 : 2; 305 uint16_t write_1 : 1; 306 uint16_t res : 1; 307 uint16_t edge_rate_ctl_1000 : 2; 308 uint16_t ext_pkt_len : 1; 309 uint16_t ext_lb : 1; 310 #endif 311 } bits; 312 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 313 314 #define AUX_REG 0x0 315 #define AUX_10BASET 0x1 316 #define AUX_PWR_CTL 0x2 317 #define AUX_MISC_TEST 0x4 318 #define AUX_MISC_CTL 0x7 319 320 /* 321 * MII Register 25: Auxiliary Status Summary Register 322 */ 323 typedef union _mii_aux_s_t { 324 uint16_t value; 325 struct { 326 #ifdef _BIT_FIELDS_HTOL 327 uint16_t an_complete : 1; 328 uint16_t an_complete_ack : 1; 329 uint16_t an_ack_detect : 1; 330 uint16_t an_ability_detect : 1; 331 uint16_t an_np_wait : 1; 332 uint16_t an_hcd : 3; 333 uint16_t pd_fault : 1; 334 uint16_t rmt_fault : 1; 335 uint16_t an_page_rx : 1; 336 uint16_t lp_an_ability : 1; 337 uint16_t lp_np_ability : 1; 338 uint16_t link_s : 1; 339 uint16_t pause_res_rx_dir : 1; 340 uint16_t pause_res_tx_dir : 1; 341 #else 342 uint16_t pause_res_tx_dir : 1; 343 uint16_t pause_res_rx_dir : 1; 344 uint16_t link_s : 1; 345 uint16_t lp_np_ability : 1; 346 uint16_t lp_an_ability : 1; 347 uint16_t an_page_rx : 1; 348 uint16_t rmt_fault : 1; 349 uint16_t pd_fault : 1; 350 uint16_t an_hcd : 3; 351 uint16_t an_np_wait : 1; 352 uint16_t an_ability_detect : 1; 353 uint16_t an_ack_detect : 1; 354 uint16_t an_complete_ack : 1; 355 uint16_t an_complete : 1; 356 #endif 357 } bits; 358 } mii_aux_s_t, *p_mii_aux_s_t; 359 360 /* 361 * MII Register 26, 27: Interrupt Status and Mask Registers 362 */ 363 typedef union _mii_intr_t { 364 uint16_t value; 365 struct { 366 #ifdef _BIT_FIELDS_HTOL 367 uint16_t res : 1; 368 uint16_t illegal_pair_swap : 1; 369 uint16_t mdix_status_change : 1; 370 uint16_t exceed_hicnt_thres : 1; 371 uint16_t exceed_locnt_thres : 1; 372 uint16_t an_page_rx : 1; 373 uint16_t hcd_nolink : 1; 374 uint16_t no_hcd : 1; 375 uint16_t neg_unsupported_hcd : 1; 376 uint16_t scr_sync_err : 1; 377 uint16_t rmt_rx_status_change : 1; 378 uint16_t loc_rx_status_change : 1; 379 uint16_t duplex_mode_change : 1; 380 uint16_t link_speed_change : 1; 381 uint16_t link_status_change : 1; 382 uint16_t crc_err : 1; 383 #else 384 uint16_t crc_err : 1; 385 uint16_t link_status_change : 1; 386 uint16_t link_speed_change : 1; 387 uint16_t duplex_mode_change : 1; 388 uint16_t loc_rx_status_change : 1; 389 uint16_t rmt_rx_status_change : 1; 390 uint16_t scr_sync_err : 1; 391 uint16_t neg_unsupported_hcd : 1; 392 uint16_t no_hcd : 1; 393 uint16_t hcd_nolink : 1; 394 uint16_t an_page_rx : 1; 395 uint16_t exceed_locnt_thres : 1; 396 uint16_t exceed_hicnt_thres : 1; 397 uint16_t mdix_status_change : 1; 398 uint16_t illegal_pair_swap : 1; 399 uint16_t res : 1; 400 #endif 401 } bits; 402 } mii_intr_t, *p_mii_intr_t; 403 404 /* 405 * MII Register 28: Register 1C Access Register 406 */ 407 typedef union _mii_misc_t { 408 uint16_t value; 409 struct { 410 #ifdef _BIT_FIELDS_HTOL 411 uint16_t w_en : 1; 412 uint16_t shadow_reg_sel : 5; 413 uint16_t data : 10; 414 #else 415 uint16_t data : 10; 416 uint16_t shadow_reg_sel : 5; 417 uint16_t w_en : 1; 418 #endif 419 } bits; 420 } mii_misc_t, *p_mii_misc_t; 421 422 #define LINK_LED_MODE 0x2 423 #define CLK_ALIGN_CTL 0x3 424 #define WIRE_SP_RETRY 0x4 425 #define CLK125 0x5 426 #define LED_STATUS 0x8 427 #define LED_CONTROL 0x9 428 #define AUTO_PWR_DOWN 0xA 429 #define LED_SEL1 0xD 430 #define LED_SEL2 0xE 431 432 /* 433 * MII Register 29: Master/Slave Seed / HCD Status Register 434 */ 435 436 typedef union _mii_misc1_t { 437 uint16_t value; 438 struct { 439 #ifdef _BIT_FIELDS_HTOL 440 uint16_t en_shadow_reg : 1; 441 uint16_t data : 15; 442 #else 443 uint16_t data : 15; 444 uint16_t en_shadow_reg : 1; 445 #endif 446 } bits; 447 } mii_misc1_t, *p_mii_misc1_t; 448 449 /* 450 * MII Register 30: Test Register 1 451 */ 452 453 typedef union _mii_test1_t { 454 uint16_t value; 455 struct { 456 #ifdef _BIT_FIELDS_HTOL 457 uint16_t crc_err_cnt_sel : 1; 458 uint16_t res : 7; 459 uint16_t manual_swap_mdi_st : 1; 460 uint16_t res1 : 7; 461 #else 462 uint16_t res1 : 7; 463 uint16_t manual_swap_mdi_st : 1; 464 uint16_t res : 7; 465 uint16_t crc_err_cnt_sel : 1; 466 #endif 467 } bits; 468 } mii_test1_t, *p_mii_test1_t; 469 470 471 /* Definitions of BCM8704 */ 472 473 #define BCM8704_PMD_CONTROL_REG 0 474 #define BCM8704_PMD_STATUS_REG 0x1 475 #define BCM8704_PMD_ID_0_REG 0x2 476 #define BCM8704_PMD_ID_1_REG 0x3 477 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 478 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 479 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 480 #define BCM8704_PMD_CONTROL2_REG 0x7 481 #define BCM8704_PMD_STATUS2_REG 0x8 482 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 483 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 484 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 485 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 486 #define BCM8704_PCS_CONTROL_REG 0 487 #define BCM8704_PCS_STATUS1_REG 0x1 488 #define BCM8704_PCS_ID_0_REG 0x2 489 #define BCM8704_PCS_ID_1_REG 0x3 490 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 491 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 492 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 493 #define BCM8704_PCS_CONTROL2_REG 0x7 494 #define BCM8704_PCS_STATUS2_REG 0x8 495 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 496 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 497 #define BCM8704_PCS_STATUS_REG 0x18 498 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 499 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 500 #define BCM8704_PHYXS_CONTROL_REG 0 501 #define BCM8704_PHYXS_STATUS_REG 0x1 502 #define BCM8704_PHY_ID_0_REG 0x2 503 #define BCM8704_PHY_ID_1_REG 0x3 504 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 505 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 506 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 507 #define BCM8704_PHYXS_STATUS2_REG 0x8 508 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 509 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 510 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 511 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 512 #define BCM8704_USER_CONTROL_REG 0xC800 513 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 514 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 515 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 516 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 517 #define BCM8704_CHIP_ID_REG 0xC807 518 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 519 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 520 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 521 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 522 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 523 524 /* Rx Channel Control1 Register bits */ 525 #define BCM8704_RXPOL_FLIP 0x20 526 527 typedef union _phyxs_control { 528 uint16_t value; 529 struct { 530 #ifdef _BIT_FIELDS_HTOL 531 uint16_t reset : 1; 532 uint16_t loopback : 1; 533 uint16_t speed_sel2 : 1; 534 uint16_t res2 : 1; 535 uint16_t low_power : 1; 536 uint16_t res1 : 4; 537 uint16_t speed_sel1 : 1; 538 uint16_t speed_sel0 : 4; 539 uint16_t res0 : 2; 540 #else 541 uint16_t res0 : 2; 542 uint16_t speed_sel0 : 4; 543 uint16_t speed_sel1 : 1; 544 uint16_t res1 : 4; 545 uint16_t low_power : 1; 546 uint16_t res2 : 1; 547 uint16_t speed_sel2 : 1; 548 uint16_t loopback : 1; 549 uint16_t reset : 1; 550 #endif 551 } bits; 552 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 553 554 555 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 556 557 typedef union _control { 558 uint16_t value; 559 struct { 560 #ifdef _BIT_FIELDS_HTOL 561 uint16_t optxenb_lvl : 1; 562 uint16_t optxrst_lvl : 1; 563 uint16_t opbiasflt_lvl : 1; 564 uint16_t obtmpflt_lvl : 1; 565 uint16_t opprflt_lvl : 1; 566 uint16_t optxflt_lvl : 1; 567 uint16_t optrxlos_lvl : 1; 568 uint16_t oprxflt_lvl : 1; 569 uint16_t optxon_lvl : 1; 570 uint16_t res1 : 7; 571 #else 572 uint16_t res1 : 7; 573 uint16_t optxon_lvl : 1; 574 uint16_t oprxflt_lvl : 1; 575 uint16_t optrxlos_lvl : 1; 576 uint16_t optxflt_lvl : 1; 577 uint16_t opprflt_lvl : 1; 578 uint16_t obtmpflt_lvl : 1; 579 uint16_t opbiasflt_lvl : 1; 580 uint16_t optxrst_lvl : 1; 581 uint16_t optxenb_lvl : 1; 582 #endif 583 } bits; 584 } control_t, *p_control_t; 585 586 typedef union _pmd_tx_control { 587 uint16_t value; 588 struct { 589 #ifdef _BIT_FIELDS_HTOL 590 uint16_t res1 : 7; 591 uint16_t xfp_clken : 1; 592 uint16_t tx_dac_txd : 2; 593 uint16_t tx_dac_txck : 2; 594 uint16_t tsd_lpwren : 1; 595 uint16_t tsck_lpwren : 1; 596 uint16_t cmu_lpwren : 1; 597 uint16_t sfiforst : 1; 598 #else 599 uint16_t sfiforst : 1; 600 uint16_t cmu_lpwren : 1; 601 uint16_t tsck_lpwren : 1; 602 uint16_t tsd_lpwren : 1; 603 uint16_t tx_dac_txck : 2; 604 uint16_t tx_dac_txd : 2; 605 uint16_t xfp_clken : 1; 606 uint16_t res1 : 7; 607 #endif 608 } bits; 609 } pmd_tx_control_t, *p_pmd_tx_control_t; 610 611 612 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 613 614 615 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 616 617 typedef union _optics_dcntr { 618 uint16_t value; 619 struct { 620 #ifdef _BIT_FIELDS_HTOL 621 uint16_t fault_mode : 1; 622 uint16_t tx_pwrdown : 1; 623 uint16_t rx_pwrdown : 1; 624 uint16_t ext_flt_en : 1; 625 uint16_t opt_rst : 1; 626 uint16_t pcs_tx_inv_b : 1; 627 uint16_t pcs_rx_inv : 1; 628 uint16_t res3 : 2; 629 uint16_t gpio_sel : 2; 630 uint16_t res2 : 1; 631 uint16_t lpbk_err_dis : 1; 632 uint16_t res1 : 2; 633 uint16_t txonoff_pwdwn_dis : 1; 634 #else 635 uint16_t txonoff_pwdwn_dis : 1; 636 uint16_t res1 : 2; 637 uint16_t lpbk_err_dis : 1; 638 uint16_t res2 : 1; 639 uint16_t gpio_sel : 2; 640 uint16_t res3 : 2; 641 uint16_t pcs_rx_inv : 1; 642 uint16_t pcs_tx_inv_b : 1; 643 uint16_t opt_rst : 1; 644 uint16_t ext_flt_en : 1; 645 uint16_t rx_pwrdown : 1; 646 uint16_t tx_pwrdown : 1; 647 uint16_t fault_mode : 1; 648 #endif 649 } bits; 650 } optics_dcntr_t, *p_optics_dcntr_t; 651 652 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 653 654 #define PMD_RX_SIG_DET3 0x10 655 #define PMD_RX_SIG_DET2 0x08 656 #define PMD_RX_SIG_DET1 0x04 657 #define PMD_RX_SIG_DET0 0x02 658 #define GLOB_PMD_RX_SIG_OK 0x01 659 660 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 661 662 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 663 #define PCS_PRBS31_ABLE 0x0004 664 #define PCS_10GBASE_R_HI_BER 0x0002 665 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 666 667 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 668 669 #define XGXS_LANE_ALIGN_STATUS 0x1000 670 #define XGXS_PATTERN_TEST_ABILITY 0x0800 671 #define XGXS_LANE3_SYNC 0x0008 672 #define XGXS_LANE2_SYNC 0x0004 673 #define XGXS_LANE1_SYNC 0x0002 674 #define XGXS_LANE0_SYNC 0x0001 675 676 #ifdef __cplusplus 677 } 678 #endif 679 680 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 681