1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <nxge_defs.h> 37 38 #define BCM5464_NEPTUNE_PORT_ADDR_BASE 10 39 #define BCM8704_NEPTUNE_PORT_ADDR_BASE 8 40 #define BCM8704_N2_PORT_ADDR_BASE 16 41 #define BCM8704_PMA_PMD_DEV_ADDR 1 42 #define BCM8704_PCS_DEV_ADDR 3 43 #define BCM8704_USER_DEV3_ADDR 3 44 #define BCM8704_PHYXS_ADDR 4 45 #define BCM8704_USER_DEV4_ADDR 4 46 47 /* Definitions for BCM 5464R PHY chip */ 48 49 #define BCM5464R_PHY_ECR 16 50 #define BCM5464R_PHY_ESR 17 51 #define BCM5464R_RXERR_CNT 18 52 #define BCM5464R_FALSECS_CNT 19 53 #define BCM5464R_RX_NOTOK_CNT 20 54 #define BCM5464R_ER_DATA 21 55 #define BCM5464R_RES 22 56 #define BCM5464R_ER_ACC 23 57 #define BCM5464R_AUX_CTL 24 58 #define BCM5464R_AUX_S 25 59 #define BCM5464R_INTR_S 26 60 #define BCM5464R_INTR_M 27 61 #define BCM5464R_MISC 28 62 #define BCM5464R_MISC1 29 63 #define BCM5464R_TESTR1 30 64 65 #define PHY_BCM_5464R_OUI 0x001018 66 #define PHY_BCM_5464R_MODEL 0x0B 67 68 /* 69 * MII Register 16: PHY Extended Control Register 70 */ 71 72 typedef union _mii_phy_ecr_t { 73 uint16_t value; 74 struct { 75 #ifdef _BIT_FIELDS_HTOL 76 uint16_t mac_phy_if_mode : 1; 77 uint16_t dis_automdicross : 1; 78 uint16_t tx_dis : 1; 79 uint16_t intr_dis : 1; 80 uint16_t force_intr : 1; 81 uint16_t bypass_encdec : 1; 82 uint16_t bypass_scrdes : 1; 83 uint16_t bypass_mlt3 : 1; 84 uint16_t bypass_rx_sym : 1; 85 uint16_t reset_scr : 1; 86 uint16_t en_led_traffic : 1; 87 uint16_t force_leds_on : 1; 88 uint16_t force_leds_off : 1; 89 uint16_t res : 2; 90 uint16_t gmii_fifo_elas : 1; 91 #else 92 uint16_t gmii_fifo_elas : 1; 93 uint16_t res : 2; 94 uint16_t force_leds_off : 1; 95 uint16_t force_leds_on : 1; 96 uint16_t en_led_traffic : 1; 97 uint16_t reset_scr : 1; 98 uint16_t bypass_rx_sym : 1; 99 uint16_t bypass_mlt3 : 1; 100 uint16_t bypass_scrdes : 1; 101 uint16_t bypass_encdec : 1; 102 uint16_t force_intr : 1; 103 uint16_t intr_dis : 1; 104 uint16_t tx_dis : 1; 105 uint16_t dis_automdicross : 1; 106 uint16_t mac_phy_if_mode : 1; 107 #endif 108 } bits; 109 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 110 111 /* 112 * MII Register 17: PHY Extended Status Register 113 */ 114 typedef union _mii_phy_esr_t { 115 uint16_t value; 116 struct { 117 #ifdef _BIT_FIELDS_HTOL 118 uint16_t anbpsfm : 1; 119 uint16_t wsdwngr : 1; 120 uint16_t mdi_crst : 1; 121 uint16_t intr_s : 1; 122 uint16_t rmt_rx_s : 1; 123 uint16_t loc_rx_s : 1; 124 uint16_t locked : 1; 125 uint16_t link_s : 1; 126 uint16_t crc_err : 1; 127 uint16_t cext_err : 1; 128 uint16_t bad_ssd : 1; 129 uint16_t bad_esd : 1; 130 uint16_t rx_err : 1; 131 uint16_t tx_err : 1; 132 uint16_t lock_err : 1; 133 uint16_t mlt3_cerr : 1; 134 #else 135 uint16_t mlt3_cerr : 1; 136 uint16_t lock_err : 1; 137 uint16_t tx_err : 1; 138 uint16_t rx_err : 1; 139 uint16_t bad_esd : 1; 140 uint16_t bad_ssd : 1; 141 uint16_t cext_err : 1; 142 uint16_t crc_err : 1; 143 uint16_t link_s : 1; 144 uint16_t locked : 1; 145 uint16_t loc_rx_s : 1; 146 uint16_t rmt_rx_s : 1; 147 uint16_t intr_s : 1; 148 uint16_t mdi_crst : 1; 149 uint16_t wsdwngr : 1; 150 uint16_t anbpsfm : 1; 151 #endif 152 } bits; 153 } mii_phy_esr_t, *p_mii_phy_esr_t; 154 155 /* 156 * MII Register 18: Receive Error Counter Register 157 */ 158 typedef union _mii_rxerr_cnt_t { 159 uint16_t value; 160 struct { 161 uint16_t rx_err_cnt : 16; 162 } bits; 163 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 164 165 /* 166 * MII Register 19: False Carrier Sense Counter Register 167 */ 168 typedef union _mii_falsecs_cnt_t { 169 uint16_t value; 170 struct { 171 #ifdef _BIT_FIELDS_HTOL 172 uint16_t res : 8; 173 uint16_t false_cs_cnt : 8; 174 #else 175 uint16_t false_cs_cnt : 8; 176 uint16_t res : 8; 177 #endif 178 } bits; 179 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 180 181 /* 182 * MII Register 20: Receiver NOT_OK Counter Register 183 */ 184 typedef union _mii_rx_notok_cnt_t { 185 uint16_t value; 186 struct { 187 #ifdef _BIT_FIELDS_HTOL 188 uint16_t l_rx_notok_cnt : 8; 189 uint16_t r_rx_notok_cnt : 8; 190 #else 191 uint16_t r_rx_notok_cnt : 8; 192 uint16_t l_rx_notok_cnt : 8; 193 #endif 194 } bits; 195 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 196 197 /* 198 * MII Register 21: Expansion Register Data Register 199 */ 200 typedef union _mii_er_data_t { 201 uint16_t value; 202 struct { 203 uint16_t reg_data; 204 } bits; 205 } mii_er_data_t, *p_mii_er_data_t; 206 207 /* 208 * MII Register 23: Expansion Register Access Register 209 */ 210 typedef union _mii_er_acc_t { 211 struct { 212 #ifdef _BIT_FIELDS_HTOL 213 uint16_t res : 4; 214 uint16_t er_sel : 4; 215 uint16_t er_acc : 8; 216 #else 217 uint16_t er_acc : 8; 218 uint16_t er_sel : 4; 219 uint16_t res : 4; 220 #endif 221 } bits; 222 } mii_er_acc_t, *p_mii_er_acc_t; 223 224 #define EXP_RXTX_PKT_CNT 0x0 225 #define EXP_INTR_STAT 0x1 226 #define MULTICOL_LED_SEL 0x4 227 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 228 #define MULTICOL_LED_BLINK_CTL 0x6 229 #define CABLE_DIAG_CTL 0x10 230 #define CABLE_DIAG_RES 0x11 231 #define CABLE_DIAG_LEN_CH_2_1 0x12 232 #define CABLE_DIAG_LEN_CH_4_3 0x13 233 234 /* 235 * MII Register 24: Auxiliary Control Register 236 */ 237 typedef union _mii_aux_ctl_t { 238 uint16_t value; 239 struct { 240 #ifdef _BIT_FIELDS_HTOL 241 uint16_t ext_lb : 1; 242 uint16_t ext_pkt_len : 1; 243 uint16_t edge_rate_ctl_1000 : 2; 244 uint16_t res : 1; 245 uint16_t write_1 : 1; 246 uint16_t res1 : 2; 247 uint16_t dis_partial_resp : 1; 248 uint16_t res2 : 1; 249 uint16_t edge_rate_ctl_100 : 2; 250 uint16_t diag_mode : 1; 251 uint16_t shadow_reg_sel : 3; 252 #else 253 uint16_t shadow_reg_sel : 3; 254 uint16_t diag_mode : 1; 255 uint16_t edge_rate_ctl_100 : 2; 256 uint16_t res2 : 1; 257 uint16_t dis_partial_resp : 1; 258 uint16_t res1 : 2; 259 uint16_t write_1 : 1; 260 uint16_t res : 1; 261 uint16_t edge_rate_ctl_1000 : 2; 262 uint16_t ext_pkt_len : 1; 263 uint16_t ext_lb : 1; 264 #endif 265 } bits; 266 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 267 268 #define AUX_REG 0x0 269 #define AUX_10BASET 0x1 270 #define AUX_PWR_CTL 0x2 271 #define AUX_MISC_TEST 0x4 272 #define AUX_MISC_CTL 0x7 273 274 /* 275 * MII Register 25: Auxiliary Status Summary Register 276 */ 277 typedef union _mii_aux_s_t { 278 uint16_t value; 279 struct { 280 #ifdef _BIT_FIELDS_HTOL 281 uint16_t an_complete : 1; 282 uint16_t an_complete_ack : 1; 283 uint16_t an_ack_detect : 1; 284 uint16_t an_ability_detect : 1; 285 uint16_t an_np_wait : 1; 286 uint16_t an_hcd : 3; 287 uint16_t pd_fault : 1; 288 uint16_t rmt_fault : 1; 289 uint16_t an_page_rx : 1; 290 uint16_t lp_an_ability : 1; 291 uint16_t lp_np_ability : 1; 292 uint16_t link_s : 1; 293 uint16_t pause_res_rx_dir : 1; 294 uint16_t pause_res_tx_dir : 1; 295 #else 296 uint16_t pause_res_tx_dir : 1; 297 uint16_t pause_res_rx_dir : 1; 298 uint16_t link_s : 1; 299 uint16_t lp_np_ability : 1; 300 uint16_t lp_an_ability : 1; 301 uint16_t an_page_rx : 1; 302 uint16_t rmt_fault : 1; 303 uint16_t pd_fault : 1; 304 uint16_t an_hcd : 3; 305 uint16_t an_np_wait : 1; 306 uint16_t an_ability_detect : 1; 307 uint16_t an_ack_detect : 1; 308 uint16_t an_complete_ack : 1; 309 uint16_t an_complete : 1; 310 #endif 311 } bits; 312 } mii_aux_s_t, *p_mii_aux_s_t; 313 314 /* 315 * MII Register 26, 27: Interrupt Status and Mask Registers 316 */ 317 typedef union _mii_intr_t { 318 uint16_t value; 319 struct { 320 #ifdef _BIT_FIELDS_HTOL 321 uint16_t res : 1; 322 uint16_t illegal_pair_swap : 1; 323 uint16_t mdix_status_change : 1; 324 uint16_t exceed_hicnt_thres : 1; 325 uint16_t exceed_locnt_thres : 1; 326 uint16_t an_page_rx : 1; 327 uint16_t hcd_nolink : 1; 328 uint16_t no_hcd : 1; 329 uint16_t neg_unsupported_hcd : 1; 330 uint16_t scr_sync_err : 1; 331 uint16_t rmt_rx_status_change : 1; 332 uint16_t loc_rx_status_change : 1; 333 uint16_t duplex_mode_change : 1; 334 uint16_t link_speed_change : 1; 335 uint16_t link_status_change : 1; 336 uint16_t crc_err : 1; 337 #else 338 uint16_t crc_err : 1; 339 uint16_t link_status_change : 1; 340 uint16_t link_speed_change : 1; 341 uint16_t duplex_mode_change : 1; 342 uint16_t loc_rx_status_change : 1; 343 uint16_t rmt_rx_status_change : 1; 344 uint16_t scr_sync_err : 1; 345 uint16_t neg_unsupported_hcd : 1; 346 uint16_t no_hcd : 1; 347 uint16_t hcd_nolink : 1; 348 uint16_t an_page_rx : 1; 349 uint16_t exceed_locnt_thres : 1; 350 uint16_t exceed_hicnt_thres : 1; 351 uint16_t mdix_status_change : 1; 352 uint16_t illegal_pair_swap : 1; 353 uint16_t res : 1; 354 #endif 355 } bits; 356 } mii_intr_t, *p_mii_intr_t; 357 358 /* 359 * MII Register 28: Register 1C Access Register 360 */ 361 typedef union _mii_misc_t { 362 uint16_t value; 363 struct { 364 #ifdef _BIT_FIELDS_HTOL 365 uint16_t w_en : 1; 366 uint16_t shadow_reg_sel : 5; 367 uint16_t data : 10; 368 #else 369 uint16_t data : 10; 370 uint16_t shadow_reg_sel : 5; 371 uint16_t w_en : 1; 372 #endif 373 } bits; 374 } mii_misc_t, *p_mii_misc_t; 375 376 #define LINK_LED_MODE 0x2 377 #define CLK_ALIGN_CTL 0x3 378 #define WIRE_SP_RETRY 0x4 379 #define CLK125 0x5 380 #define LED_STATUS 0x8 381 #define LED_CONTROL 0x9 382 #define AUTO_PWR_DOWN 0xA 383 #define LED_SEL1 0xD 384 #define LED_SEL2 0xE 385 386 /* 387 * MII Register 29: Master/Slave Seed / HCD Status Register 388 */ 389 390 typedef union _mii_misc1_t { 391 uint16_t value; 392 struct { 393 #ifdef _BIT_FIELDS_HTOL 394 uint16_t en_shadow_reg : 1; 395 uint16_t data : 15; 396 #else 397 uint16_t data : 15; 398 uint16_t en_shadow_reg : 1; 399 #endif 400 } bits; 401 } mii_misc1_t, *p_mii_misc1_t; 402 403 /* 404 * MII Register 30: Test Register 1 405 */ 406 407 typedef union _mii_test1_t { 408 uint16_t value; 409 struct { 410 #ifdef _BIT_FIELDS_HTOL 411 uint16_t crc_err_cnt_sel : 1; 412 uint16_t res : 7; 413 uint16_t manual_swap_mdi_st : 1; 414 uint16_t res1 : 7; 415 #else 416 uint16_t res1 : 7; 417 uint16_t manual_swap_mdi_st : 1; 418 uint16_t res : 7; 419 uint16_t crc_err_cnt_sel : 1; 420 #endif 421 } bits; 422 } mii_test1_t, *p_mii_test1_t; 423 424 425 /* Definitions of BCM8704 */ 426 427 #define BCM8704_PMD_CONTROL_REG 0 428 #define BCM8704_PMD_STATUS_REG 0x1 429 #define BCM8704_PMD_ID_0_REG 0x2 430 #define BCM8704_PMD_ID_1_REG 0x3 431 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 432 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 433 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 434 #define BCM8704_PMD_CONTROL2_REG 0x7 435 #define BCM8704_PMD_STATUS2_REG 0x8 436 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 437 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 438 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 439 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 440 #define BCM8704_PCS_CONTROL_REG 0 441 #define BCM8704_PCS_STATUS1_REG 0x1 442 #define BCM8704_PCS_ID_0_REG 0x2 443 #define BCM8704_PCS_ID_1_REG 0x3 444 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 445 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 446 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 447 #define BCM8704_PCS_CONTROL2_REG 0x7 448 #define BCM8704_PCS_STATUS2_REG 0x8 449 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 450 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 451 #define BCM8704_PCS_STATUS_REG 0x18 452 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 453 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 454 #define BCM8704_PHYXS_CONTROL_REG 0 455 #define BCM8704_PHYXS_STATUS_REG 0x1 456 #define BCM8704_PHY_ID_0_REG 0x2 457 #define BCM8704_PHY_ID_1_REG 0x3 458 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 459 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 460 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 461 #define BCM8704_PHYXS_STATUS2_REG 0x8 462 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 463 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 464 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 465 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 466 #define BCM8704_USER_CONTROL_REG 0xC800 467 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 468 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 469 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 470 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 471 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 472 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 473 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 474 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 475 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 476 477 /* Rx Channel Control1 Register bits */ 478 #define BCM8704_RXPOL_FLIP 0x20 479 480 typedef union _phyxs_control { 481 uint16_t value; 482 struct { 483 #ifdef _BIT_FIELDS_HTOL 484 uint16_t reset : 1; 485 uint16_t loopback : 1; 486 uint16_t speed_sel2 : 1; 487 uint16_t res2 : 1; 488 uint16_t low_power : 1; 489 uint16_t res1 : 4; 490 uint16_t speed_sel1 : 1; 491 uint16_t speed_sel0 : 4; 492 uint16_t res0 : 2; 493 #else 494 uint16_t res0 : 2; 495 uint16_t speed_sel0 : 4; 496 uint16_t speed_sel1 : 1; 497 uint16_t res1 : 4; 498 uint16_t low_power : 1; 499 uint16_t res2 : 1; 500 uint16_t speed_sel2 : 1; 501 uint16_t loopback : 1; 502 uint16_t reset : 1; 503 #endif 504 } bits; 505 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 506 507 508 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 509 510 typedef union _control { 511 uint16_t value; 512 struct { 513 #ifdef _BIT_FIELDS_HTOL 514 uint16_t optxenb_lvl : 1; 515 uint16_t optxrst_lvl : 1; 516 uint16_t opbiasflt_lvl : 1; 517 uint16_t obtmpflt_lvl : 1; 518 uint16_t opprflt_lvl : 1; 519 uint16_t optxflt_lvl : 1; 520 uint16_t optrxlos_lvl : 1; 521 uint16_t oprxflt_lvl : 1; 522 uint16_t optxon_lvl : 1; 523 uint16_t res1 : 7; 524 #else 525 uint16_t res1 : 7; 526 uint16_t optxon_lvl : 1; 527 uint16_t oprxflt_lvl : 1; 528 uint16_t optrxlos_lvl : 1; 529 uint16_t optxflt_lvl : 1; 530 uint16_t opprflt_lvl : 1; 531 uint16_t obtmpflt_lvl : 1; 532 uint16_t opbiasflt_lvl : 1; 533 uint16_t optxrst_lvl : 1; 534 uint16_t optxenb_lvl : 1; 535 #endif 536 } bits; 537 } control_t, *p_control_t; 538 539 typedef union _pmd_tx_control { 540 uint16_t value; 541 struct { 542 #ifdef _BIT_FIELDS_HTOL 543 uint16_t res1 : 7; 544 uint16_t xfp_clken : 1; 545 uint16_t tx_dac_txd : 2; 546 uint16_t tx_dac_txck : 2; 547 uint16_t tsd_lpwren : 1; 548 uint16_t tsck_lpwren : 1; 549 uint16_t cmu_lpwren : 1; 550 uint16_t sfiforst : 1; 551 #else 552 uint16_t sfiforst : 1; 553 uint16_t cmu_lpwren : 1; 554 uint16_t tsck_lpwren : 1; 555 uint16_t tsd_lpwren : 1; 556 uint16_t tx_dac_txck : 2; 557 uint16_t tx_dac_txd : 2; 558 uint16_t xfp_clken : 1; 559 uint16_t res1 : 7; 560 #endif 561 } bits; 562 } pmd_tx_control_t, *p_pmd_tx_control_t; 563 564 565 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 566 567 568 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 569 570 typedef union _optics_dcntr { 571 uint16_t value; 572 struct { 573 #ifdef _BIT_FIELDS_HTOL 574 uint16_t fault_mode : 1; 575 uint16_t tx_pwrdown : 1; 576 uint16_t rx_pwrdown : 1; 577 uint16_t ext_flt_en : 1; 578 uint16_t opt_rst : 1; 579 uint16_t pcs_tx_inv_b : 1; 580 uint16_t pcs_rx_inv : 1; 581 uint16_t res3 : 2; 582 uint16_t gpio_sel : 2; 583 uint16_t res2 : 1; 584 uint16_t lpbk_err_dis : 1; 585 uint16_t res1 : 2; 586 uint16_t txonoff_pwdwn_dis : 1; 587 #else 588 uint16_t txonoff_pwdwn_dis : 1; 589 uint16_t res1 : 2; 590 uint16_t lpbk_err_dis : 1; 591 uint16_t res2 : 1; 592 uint16_t gpio_sel : 2; 593 uint16_t res3 : 2; 594 uint16_t pcs_rx_inv : 1; 595 uint16_t pcs_tx_inv_b : 1; 596 uint16_t opt_rst : 1; 597 uint16_t ext_flt_en : 1; 598 uint16_t rx_pwrdown : 1; 599 uint16_t tx_pwrdown : 1; 600 uint16_t fault_mode : 1; 601 #endif 602 } bits; 603 } optics_dcntr_t, *p_optics_dcntr_t; 604 605 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 606 607 #define PMD_RX_SIG_DET3 0x10 608 #define PMD_RX_SIG_DET2 0x08 609 #define PMD_RX_SIG_DET1 0x04 610 #define PMD_RX_SIG_DET0 0x02 611 #define GLOB_PMD_RX_SIG_OK 0x01 612 613 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 614 615 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 616 #define PCS_PRBS31_ABLE 0x0004 617 #define PCS_10GBASE_R_HI_BER 0x0002 618 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 619 620 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 621 622 #define XGXS_LANE_ALIGN_STATUS 0x1000 623 #define XGXS_PATTERN_TEST_ABILITY 0x0800 624 #define XGXS_LANE3_SYNC 0x0008 625 #define XGXS_LANE2_SYNC 0x0004 626 #define XGXS_LANE1_SYNC 0x0002 627 #define XGXS_LANE0_SYNC 0x0001 628 629 #ifdef __cplusplus 630 } 631 #endif 632 633 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 634