1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <nxge_defs.h> 37 38 #define NXGE_MAX_PHY_PORTS 32 39 #define NXGE_EXT_PHY_PORT_ST 8 40 41 #define NXGE_PMA_PMD_DEV_ADDR 1 42 #define NXGE_PCS_DEV_ADDR 3 43 #define NXGE_DEV_ID_REG_1 2 44 #define NXGE_DEV_ID_REG_2 3 45 #define NXGE_PHY_ID_REG_1 2 46 #define NXGE_PHY_ID_REG_2 3 47 48 #define BCM8704_CHIP_ID 0x8704 49 #define BCM8706_CHIP_ID 0x8706 50 #define MRVL88X201X_CHIP_ID 0x5043 51 52 /* 53 * The BCM_PHY_ID_MASK is explained below: 54 * The first nibble (bits 0 through 3) is changed with every revision 55 * of the silicon. So these bits are masked out to support future revisions 56 * of the same chip. The third nibble (bits 8 through 11) is changed for 57 * different chips of the same family. So these bits are masked out to 58 * support chips of the same family. 59 */ 60 #define BCM_PHY_ID_MASK 0xfffff0f0 61 #define BCM8704_DEV_ID 0x206033 62 #define BCM5464R_PHY_ID 0x2060b1 63 #define BCM8706_DEV_ID 0x206035 64 #define BCM5482_PHY_ID 0x143bcb1 65 #define MARVELL_88X_201X_DEV_ID 0x1410d24 66 #define MARVELL_88X201X_PHY_ID (MARVELL_88X_201X_DEV_ID & BCM_PHY_ID_MASK) 67 #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 68 #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 69 #define PHY_BCM5482_FAMILY (BCM5482_PHY_ID & BCM_PHY_ID_MASK) 70 71 #define CLAUSE_45_TYPE 1 72 #define CLAUSE_22_TYPE 2 73 74 #define BCM5464_NEPTUNE_PORT_ADDR_BASE 10 75 #define BCM8704_NEPTUNE_PORT_ADDR_BASE 8 76 #define BCM8704_N2_PORT_ADDR_BASE 16 77 #define MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 8 78 79 /* 80 * Phy address for the second NIU port on Goa NEM card can be either 81 * 20 or 17 82 */ 83 #define BCM8706_GOA_PORT_ADDR_BASE 16 84 #define BCM8706_ALT_GOA_PORT1_ADDR 20 85 /* 86 * Phy addresses for Maramba support. Support for P0 will eventually 87 * be removed. 88 */ 89 #define BCM5464_MARAMBA_P0_PORT_ADDR_BASE 10 90 #define BCM5464_MARAMBA_P1_PORT_ADDR_BASE 26 91 #define BCM8704_MARAMBA_PORT_ADDR_BASE 16 92 93 #define BCM8704_PMA_PMD_DEV_ADDR 1 94 #define BCM8704_PCS_DEV_ADDR 3 95 #define BCM8704_USER_DEV3_ADDR 3 96 #define BCM8704_PHYXS_ADDR 4 97 #define BCM8704_USER_DEV4_ADDR 4 98 99 /* Definitions for BCM 5464R PHY chip */ 100 101 #define BCM5464R_PHY_ECR 16 102 #define BCM5464R_PHY_ESR 17 103 #define BCM5464R_RXERR_CNT 18 104 #define BCM5464R_FALSECS_CNT 19 105 #define BCM5464R_RX_NOTOK_CNT 20 106 #define BCM5464R_ER_DATA 21 107 #define BCM5464R_RES 22 108 #define BCM5464R_ER_ACC 23 109 #define BCM5464R_AUX_CTL 24 110 #define BCM5464R_AUX_S 25 111 #define BCM5464R_INTR_S 26 112 #define BCM5464R_INTR_M 27 113 #define BCM5464R_MISC 28 114 #define BCM5464R_MISC1 29 115 #define BCM5464R_TESTR1 30 116 117 #define PHY_BCM_5464R_OUI 0x001018 118 #define PHY_BCM_5464R_MODEL 0x0B 119 120 /* MARVELL PHY Definitions */ 121 /* REG Offsets */ 122 #define MRVL_88X2011_USER_DEV1_ADDR 1 123 #define MRVL_88X2011_USER_DEV2_ADDR 2 124 #define MRVL_88X2011_USER_DEV3_ADDR 3 125 #define MRVL_88X2011_USER_DEV4_ADDR 4 126 #define MRVL_88X2011_PMA_PMD_CTL_1 0x0000 127 #define MRVL_88X2011_PMA_PMD_STAT_1 0x0001 128 #define MRVL_88X2011_10G_PMD_STAT_2 0x0008 129 #define MRVL_88X2011_10G_PMD_TX_DIS 0x0009 130 #define MRVL_88X2011_10G_XGXS_LANE_STAT 0x0018 131 #define MRVL_88X2011_GEN_CTL 0x8300 132 #define MRVL_88X2011_LED_BLINK_CTL 0x8303 133 #define MRVL_88X2011_LED_8_TO_11_CTL 0x8306 134 135 /* MRVL88X2011 register control */ 136 #define MRVL_88X2011_ENA_PMDTX 0x0000 137 #define MRVL_88X2011_ENA_XFPREFCLK 0x0001 138 #define MRVL_88X2011_LOOPBACK 0x1 139 #define MRVL_88X2011_LED_ACT 0x1 140 #define MRVL_88X2011_LNK_STATUS_OK 0x4 141 #define MRVL_88X2011_LED_BLK_MASK 0x70 142 #define MRVL_88X2011_LED_BLK_SHIFT 4 143 #define MRVL_88X2011_LED_BLK34MS 0x0 144 #define MRVL_88X2011_LED_BLK67MS 0x1 145 #define MRVL_88X2011_LED_BLK134MS 0x2 146 #define MRVL_88X2011_LED_BLK269MS 0x3 147 #define MRVL_88X2011_LED_BLK538MS 0x4 148 #define MRVL_88X2011_LED_CTL_OFF 0x0 149 #define MRVL_88X2011_LED_CTL_PCS_ERR 0x2 150 #define MRVL_88X2011_LED_CTL_PCS_ACT 0x5 151 #define MRVL_88X2011_LED_CTL_MASK 0x7 152 #define MRVL_88X2011_LED(n, v) ((v)<<((n)*4)) 153 #define MRVL_88X2011_LED_STAT(n, v) ((v)>>((n)*4)) 154 155 /* 156 * MII Register 16: PHY Extended Control Register 157 */ 158 159 typedef union _mii_phy_ecr_t { 160 uint16_t value; 161 struct { 162 #ifdef _BIT_FIELDS_HTOL 163 uint16_t mac_phy_if_mode : 1; 164 uint16_t dis_automdicross : 1; 165 uint16_t tx_dis : 1; 166 uint16_t intr_dis : 1; 167 uint16_t force_intr : 1; 168 uint16_t bypass_encdec : 1; 169 uint16_t bypass_scrdes : 1; 170 uint16_t bypass_mlt3 : 1; 171 uint16_t bypass_rx_sym : 1; 172 uint16_t reset_scr : 1; 173 uint16_t en_led_traffic : 1; 174 uint16_t force_leds_on : 1; 175 uint16_t force_leds_off : 1; 176 uint16_t res : 2; 177 uint16_t gmii_fifo_elas : 1; 178 #else 179 uint16_t gmii_fifo_elas : 1; 180 uint16_t res : 2; 181 uint16_t force_leds_off : 1; 182 uint16_t force_leds_on : 1; 183 uint16_t en_led_traffic : 1; 184 uint16_t reset_scr : 1; 185 uint16_t bypass_rx_sym : 1; 186 uint16_t bypass_mlt3 : 1; 187 uint16_t bypass_scrdes : 1; 188 uint16_t bypass_encdec : 1; 189 uint16_t force_intr : 1; 190 uint16_t intr_dis : 1; 191 uint16_t tx_dis : 1; 192 uint16_t dis_automdicross : 1; 193 uint16_t mac_phy_if_mode : 1; 194 #endif 195 } bits; 196 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 197 198 /* 199 * MII Register 17: PHY Extended Status Register 200 */ 201 typedef union _mii_phy_esr_t { 202 uint16_t value; 203 struct { 204 #ifdef _BIT_FIELDS_HTOL 205 uint16_t anbpsfm : 1; 206 uint16_t wsdwngr : 1; 207 uint16_t mdi_crst : 1; 208 uint16_t intr_s : 1; 209 uint16_t rmt_rx_s : 1; 210 uint16_t loc_rx_s : 1; 211 uint16_t locked : 1; 212 uint16_t link_s : 1; 213 uint16_t crc_err : 1; 214 uint16_t cext_err : 1; 215 uint16_t bad_ssd : 1; 216 uint16_t bad_esd : 1; 217 uint16_t rx_err : 1; 218 uint16_t tx_err : 1; 219 uint16_t lock_err : 1; 220 uint16_t mlt3_cerr : 1; 221 #else 222 uint16_t mlt3_cerr : 1; 223 uint16_t lock_err : 1; 224 uint16_t tx_err : 1; 225 uint16_t rx_err : 1; 226 uint16_t bad_esd : 1; 227 uint16_t bad_ssd : 1; 228 uint16_t cext_err : 1; 229 uint16_t crc_err : 1; 230 uint16_t link_s : 1; 231 uint16_t locked : 1; 232 uint16_t loc_rx_s : 1; 233 uint16_t rmt_rx_s : 1; 234 uint16_t intr_s : 1; 235 uint16_t mdi_crst : 1; 236 uint16_t wsdwngr : 1; 237 uint16_t anbpsfm : 1; 238 #endif 239 } bits; 240 } mii_phy_esr_t, *p_mii_phy_esr_t; 241 242 /* 243 * MII Register 18: Receive Error Counter Register 244 */ 245 typedef union _mii_rxerr_cnt_t { 246 uint16_t value; 247 struct { 248 uint16_t rx_err_cnt : 16; 249 } bits; 250 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 251 252 /* 253 * MII Register 19: False Carrier Sense Counter Register 254 */ 255 typedef union _mii_falsecs_cnt_t { 256 uint16_t value; 257 struct { 258 #ifdef _BIT_FIELDS_HTOL 259 uint16_t res : 8; 260 uint16_t false_cs_cnt : 8; 261 #else 262 uint16_t false_cs_cnt : 8; 263 uint16_t res : 8; 264 #endif 265 } bits; 266 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 267 268 /* 269 * MII Register 20: Receiver NOT_OK Counter Register 270 */ 271 typedef union _mii_rx_notok_cnt_t { 272 uint16_t value; 273 struct { 274 #ifdef _BIT_FIELDS_HTOL 275 uint16_t l_rx_notok_cnt : 8; 276 uint16_t r_rx_notok_cnt : 8; 277 #else 278 uint16_t r_rx_notok_cnt : 8; 279 uint16_t l_rx_notok_cnt : 8; 280 #endif 281 } bits; 282 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 283 284 /* 285 * MII Register 21: Expansion Register Data Register 286 */ 287 typedef union _mii_er_data_t { 288 uint16_t value; 289 struct { 290 uint16_t reg_data; 291 } bits; 292 } mii_er_data_t, *p_mii_er_data_t; 293 294 /* 295 * MII Register 23: Expansion Register Access Register 296 */ 297 typedef union _mii_er_acc_t { 298 struct { 299 #ifdef _BIT_FIELDS_HTOL 300 uint16_t res : 4; 301 uint16_t er_sel : 4; 302 uint16_t er_acc : 8; 303 #else 304 uint16_t er_acc : 8; 305 uint16_t er_sel : 4; 306 uint16_t res : 4; 307 #endif 308 } bits; 309 } mii_er_acc_t, *p_mii_er_acc_t; 310 311 #define EXP_RXTX_PKT_CNT 0x0 312 #define EXP_INTR_STAT 0x1 313 #define MULTICOL_LED_SEL 0x4 314 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 315 #define MULTICOL_LED_BLINK_CTL 0x6 316 #define CABLE_DIAG_CTL 0x10 317 #define CABLE_DIAG_RES 0x11 318 #define CABLE_DIAG_LEN_CH_2_1 0x12 319 #define CABLE_DIAG_LEN_CH_4_3 0x13 320 321 /* 322 * MII Register 24: Auxiliary Control Register 323 */ 324 typedef union _mii_aux_ctl_t { 325 uint16_t value; 326 struct { 327 #ifdef _BIT_FIELDS_HTOL 328 uint16_t ext_lb : 1; 329 uint16_t ext_pkt_len : 1; 330 uint16_t edge_rate_ctl_1000 : 2; 331 uint16_t res : 1; 332 uint16_t write_1 : 1; 333 uint16_t res1 : 2; 334 uint16_t dis_partial_resp : 1; 335 uint16_t res2 : 1; 336 uint16_t edge_rate_ctl_100 : 2; 337 uint16_t diag_mode : 1; 338 uint16_t shadow_reg_sel : 3; 339 #else 340 uint16_t shadow_reg_sel : 3; 341 uint16_t diag_mode : 1; 342 uint16_t edge_rate_ctl_100 : 2; 343 uint16_t res2 : 1; 344 uint16_t dis_partial_resp : 1; 345 uint16_t res1 : 2; 346 uint16_t write_1 : 1; 347 uint16_t res : 1; 348 uint16_t edge_rate_ctl_1000 : 2; 349 uint16_t ext_pkt_len : 1; 350 uint16_t ext_lb : 1; 351 #endif 352 } bits; 353 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 354 355 #define AUX_REG 0x0 356 #define AUX_10BASET 0x1 357 #define AUX_PWR_CTL 0x2 358 #define AUX_MISC_TEST 0x4 359 #define AUX_MISC_CTL 0x7 360 361 /* 362 * MII Register 25: Auxiliary Status Summary Register 363 */ 364 typedef union _mii_aux_s_t { 365 uint16_t value; 366 struct { 367 #ifdef _BIT_FIELDS_HTOL 368 uint16_t an_complete : 1; 369 uint16_t an_complete_ack : 1; 370 uint16_t an_ack_detect : 1; 371 uint16_t an_ability_detect : 1; 372 uint16_t an_np_wait : 1; 373 uint16_t an_hcd : 3; 374 uint16_t pd_fault : 1; 375 uint16_t rmt_fault : 1; 376 uint16_t an_page_rx : 1; 377 uint16_t lp_an_ability : 1; 378 uint16_t lp_np_ability : 1; 379 uint16_t link_s : 1; 380 uint16_t pause_res_rx_dir : 1; 381 uint16_t pause_res_tx_dir : 1; 382 #else 383 uint16_t pause_res_tx_dir : 1; 384 uint16_t pause_res_rx_dir : 1; 385 uint16_t link_s : 1; 386 uint16_t lp_np_ability : 1; 387 uint16_t lp_an_ability : 1; 388 uint16_t an_page_rx : 1; 389 uint16_t rmt_fault : 1; 390 uint16_t pd_fault : 1; 391 uint16_t an_hcd : 3; 392 uint16_t an_np_wait : 1; 393 uint16_t an_ability_detect : 1; 394 uint16_t an_ack_detect : 1; 395 uint16_t an_complete_ack : 1; 396 uint16_t an_complete : 1; 397 #endif 398 } bits; 399 } mii_aux_s_t, *p_mii_aux_s_t; 400 401 /* 402 * MII Register 26, 27: Interrupt Status and Mask Registers 403 */ 404 typedef union _mii_intr_t { 405 uint16_t value; 406 struct { 407 #ifdef _BIT_FIELDS_HTOL 408 uint16_t res : 1; 409 uint16_t illegal_pair_swap : 1; 410 uint16_t mdix_status_change : 1; 411 uint16_t exceed_hicnt_thres : 1; 412 uint16_t exceed_locnt_thres : 1; 413 uint16_t an_page_rx : 1; 414 uint16_t hcd_nolink : 1; 415 uint16_t no_hcd : 1; 416 uint16_t neg_unsupported_hcd : 1; 417 uint16_t scr_sync_err : 1; 418 uint16_t rmt_rx_status_change : 1; 419 uint16_t loc_rx_status_change : 1; 420 uint16_t duplex_mode_change : 1; 421 uint16_t link_speed_change : 1; 422 uint16_t link_status_change : 1; 423 uint16_t crc_err : 1; 424 #else 425 uint16_t crc_err : 1; 426 uint16_t link_status_change : 1; 427 uint16_t link_speed_change : 1; 428 uint16_t duplex_mode_change : 1; 429 uint16_t loc_rx_status_change : 1; 430 uint16_t rmt_rx_status_change : 1; 431 uint16_t scr_sync_err : 1; 432 uint16_t neg_unsupported_hcd : 1; 433 uint16_t no_hcd : 1; 434 uint16_t hcd_nolink : 1; 435 uint16_t an_page_rx : 1; 436 uint16_t exceed_locnt_thres : 1; 437 uint16_t exceed_hicnt_thres : 1; 438 uint16_t mdix_status_change : 1; 439 uint16_t illegal_pair_swap : 1; 440 uint16_t res : 1; 441 #endif 442 } bits; 443 } mii_intr_t, *p_mii_intr_t; 444 445 /* 446 * MII Register 28: Register 1C Access Register 447 */ 448 typedef union _mii_misc_t { 449 uint16_t value; 450 struct { 451 #ifdef _BIT_FIELDS_HTOL 452 uint16_t w_en : 1; 453 uint16_t shadow_reg_sel : 5; 454 uint16_t data : 10; 455 #else 456 uint16_t data : 10; 457 uint16_t shadow_reg_sel : 5; 458 uint16_t w_en : 1; 459 #endif 460 } bits; 461 } mii_misc_t, *p_mii_misc_t; 462 463 #define LINK_LED_MODE 0x2 464 #define CLK_ALIGN_CTL 0x3 465 #define WIRE_SP_RETRY 0x4 466 #define CLK125 0x5 467 #define LED_STATUS 0x8 468 #define LED_CONTROL 0x9 469 #define AUTO_PWR_DOWN 0xA 470 #define LED_SEL1 0xD 471 #define LED_SEL2 0xE 472 473 /* 474 * MII Register 29: Master/Slave Seed / HCD Status Register 475 */ 476 477 typedef union _mii_misc1_t { 478 uint16_t value; 479 struct { 480 #ifdef _BIT_FIELDS_HTOL 481 uint16_t en_shadow_reg : 1; 482 uint16_t data : 15; 483 #else 484 uint16_t data : 15; 485 uint16_t en_shadow_reg : 1; 486 #endif 487 } bits; 488 } mii_misc1_t, *p_mii_misc1_t; 489 490 /* 491 * MII Register 30: Test Register 1 492 */ 493 494 typedef union _mii_test1_t { 495 uint16_t value; 496 struct { 497 #ifdef _BIT_FIELDS_HTOL 498 uint16_t crc_err_cnt_sel : 1; 499 uint16_t res : 7; 500 uint16_t manual_swap_mdi_st : 1; 501 uint16_t res1 : 7; 502 #else 503 uint16_t res1 : 7; 504 uint16_t manual_swap_mdi_st : 1; 505 uint16_t res : 7; 506 uint16_t crc_err_cnt_sel : 1; 507 #endif 508 } bits; 509 } mii_test1_t, *p_mii_test1_t; 510 511 512 /* Definitions of BCM8704 */ 513 514 #define BCM8704_PMD_CONTROL_REG 0 515 #define BCM8704_PMD_STATUS_REG 0x1 516 #define BCM8704_PMD_ID_0_REG 0x2 517 #define BCM8704_PMD_ID_1_REG 0x3 518 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 519 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 520 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 521 #define BCM8704_PMD_CONTROL2_REG 0x7 522 #define BCM8704_PMD_STATUS2_REG 0x8 523 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 524 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 525 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 526 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 527 #define BCM8704_PCS_CONTROL_REG 0 528 #define BCM8704_PCS_STATUS1_REG 0x1 529 #define BCM8704_PCS_ID_0_REG 0x2 530 #define BCM8704_PCS_ID_1_REG 0x3 531 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 532 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 533 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 534 #define BCM8704_PCS_CONTROL2_REG 0x7 535 #define BCM8704_PCS_STATUS2_REG 0x8 536 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 537 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 538 #define BCM8704_PCS_STATUS_REG 0x18 539 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 540 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 541 #define BCM8704_PHYXS_CONTROL_REG 0 542 #define BCM8704_PHYXS_STATUS_REG 0x1 543 #define BCM8704_PHY_ID_0_REG 0x2 544 #define BCM8704_PHY_ID_1_REG 0x3 545 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 546 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 547 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 548 #define BCM8704_PHYXS_STATUS2_REG 0x8 549 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 550 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 551 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 552 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 553 #define BCM8704_USER_CONTROL_REG 0xC800 554 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 555 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 556 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 557 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 558 #define BCM8704_CHIP_ID_REG 0xC807 559 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 560 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 561 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 562 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 563 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 564 565 /* Rx Channel Control1 Register bits */ 566 #define BCM8704_RXPOL_FLIP 0x20 567 568 typedef union _phyxs_control { 569 uint16_t value; 570 struct { 571 #ifdef _BIT_FIELDS_HTOL 572 uint16_t reset : 1; 573 uint16_t loopback : 1; 574 uint16_t speed_sel2 : 1; 575 uint16_t res2 : 1; 576 uint16_t low_power : 1; 577 uint16_t res1 : 4; 578 uint16_t speed_sel1 : 1; 579 uint16_t speed_sel0 : 4; 580 uint16_t res0 : 2; 581 #else 582 uint16_t res0 : 2; 583 uint16_t speed_sel0 : 4; 584 uint16_t speed_sel1 : 1; 585 uint16_t res1 : 4; 586 uint16_t low_power : 1; 587 uint16_t res2 : 1; 588 uint16_t speed_sel2 : 1; 589 uint16_t loopback : 1; 590 uint16_t reset : 1; 591 #endif 592 } bits; 593 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 594 595 596 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 597 598 typedef union _control { 599 uint16_t value; 600 struct { 601 #ifdef _BIT_FIELDS_HTOL 602 uint16_t optxenb_lvl : 1; 603 uint16_t optxrst_lvl : 1; 604 uint16_t opbiasflt_lvl : 1; 605 uint16_t obtmpflt_lvl : 1; 606 uint16_t opprflt_lvl : 1; 607 uint16_t optxflt_lvl : 1; 608 uint16_t optrxlos_lvl : 1; 609 uint16_t oprxflt_lvl : 1; 610 uint16_t optxon_lvl : 1; 611 uint16_t res1 : 7; 612 #else 613 uint16_t res1 : 7; 614 uint16_t optxon_lvl : 1; 615 uint16_t oprxflt_lvl : 1; 616 uint16_t optrxlos_lvl : 1; 617 uint16_t optxflt_lvl : 1; 618 uint16_t opprflt_lvl : 1; 619 uint16_t obtmpflt_lvl : 1; 620 uint16_t opbiasflt_lvl : 1; 621 uint16_t optxrst_lvl : 1; 622 uint16_t optxenb_lvl : 1; 623 #endif 624 } bits; 625 } control_t, *p_control_t; 626 627 typedef union _pmd_tx_control { 628 uint16_t value; 629 struct { 630 #ifdef _BIT_FIELDS_HTOL 631 uint16_t res1 : 7; 632 uint16_t xfp_clken : 1; 633 uint16_t tx_dac_txd : 2; 634 uint16_t tx_dac_txck : 2; 635 uint16_t tsd_lpwren : 1; 636 uint16_t tsck_lpwren : 1; 637 uint16_t cmu_lpwren : 1; 638 uint16_t sfiforst : 1; 639 #else 640 uint16_t sfiforst : 1; 641 uint16_t cmu_lpwren : 1; 642 uint16_t tsck_lpwren : 1; 643 uint16_t tsd_lpwren : 1; 644 uint16_t tx_dac_txck : 2; 645 uint16_t tx_dac_txd : 2; 646 uint16_t xfp_clken : 1; 647 uint16_t res1 : 7; 648 #endif 649 } bits; 650 } pmd_tx_control_t, *p_pmd_tx_control_t; 651 652 653 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 654 655 656 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 657 658 typedef union _optics_dcntr { 659 uint16_t value; 660 struct { 661 #ifdef _BIT_FIELDS_HTOL 662 uint16_t fault_mode : 1; 663 uint16_t tx_pwrdown : 1; 664 uint16_t rx_pwrdown : 1; 665 uint16_t ext_flt_en : 1; 666 uint16_t opt_rst : 1; 667 uint16_t pcs_tx_inv_b : 1; 668 uint16_t pcs_rx_inv : 1; 669 uint16_t res3 : 2; 670 uint16_t gpio_sel : 2; 671 uint16_t res2 : 1; 672 uint16_t lpbk_err_dis : 1; 673 uint16_t res1 : 2; 674 uint16_t txonoff_pwdwn_dis : 1; 675 #else 676 uint16_t txonoff_pwdwn_dis : 1; 677 uint16_t res1 : 2; 678 uint16_t lpbk_err_dis : 1; 679 uint16_t res2 : 1; 680 uint16_t gpio_sel : 2; 681 uint16_t res3 : 2; 682 uint16_t pcs_rx_inv : 1; 683 uint16_t pcs_tx_inv_b : 1; 684 uint16_t opt_rst : 1; 685 uint16_t ext_flt_en : 1; 686 uint16_t rx_pwrdown : 1; 687 uint16_t tx_pwrdown : 1; 688 uint16_t fault_mode : 1; 689 #endif 690 } bits; 691 } optics_dcntr_t, *p_optics_dcntr_t; 692 693 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 694 695 #define PMD_RX_SIG_DET3 0x10 696 #define PMD_RX_SIG_DET2 0x08 697 #define PMD_RX_SIG_DET1 0x04 698 #define PMD_RX_SIG_DET0 0x02 699 #define GLOB_PMD_RX_SIG_OK 0x01 700 701 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 702 703 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 704 #define PCS_PRBS31_ABLE 0x0004 705 #define PCS_10GBASE_R_HI_BER 0x0002 706 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 707 708 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 709 710 #define XGXS_LANE_ALIGN_STATUS 0x1000 711 #define XGXS_PATTERN_TEST_ABILITY 0x0800 712 #define XGXS_LANE3_SYNC 0x0008 713 #define XGXS_LANE2_SYNC 0x0004 714 #define XGXS_LANE1_SYNC 0x0002 715 #define XGXS_LANE0_SYNC 0x0001 716 #define XGXS_LANE_STAT_MAGIC 0x0400 717 718 #ifdef __cplusplus 719 } 720 #endif 721 722 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 723