1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_PHY_HW_H 27 #define _SYS_NXGE_NXGE_PHY_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 35 /* 36 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved 37 * for on-chip serdes. So here the starting port is 6. 38 */ 39 #define NXGE_MAX_PHY_PORTS 32 40 #define NXGE_EXT_PHY_PORT_ST 6 41 42 #define NXGE_PMA_PMD_DEV_ADDR 1 43 #define NXGE_PCS_DEV_ADDR 3 44 #define NXGE_DEV_ID_REG_1 2 45 #define NXGE_DEV_ID_REG_2 3 46 #define NXGE_PHY_ID_REG_1 2 47 #define NXGE_PHY_ID_REG_2 3 48 49 #define BCM8704_CHIP_ID 0x8704 50 #define BCM8706_CHIP_ID 0x8706 51 #define MRVL88X201X_CHIP_ID 0x5043 52 53 /* 54 * Description of BCM_PHY_ID_MASK: 55 * The first nibble (bits 0 through 3) is changed with every revision 56 * of the silicon. So these bits are masked out to support future revisions 57 * of the same chip. The third nibble (bits 8 through 11) is changed for 58 * different chips of the same family. So these bits are masked out to 59 * support chips of the same family. 60 */ 61 #define BCM_PHY_ID_MASK 0xfffff0f0 62 #define BCM8704_DEV_ID 0x206033 63 #define BCM5464R_PHY_ID 0x2060b1 64 #define BCM8706_DEV_ID 0x206035 65 #define BCM5482_PHY_ID 0x143bcb1 66 #define MARVELL_88X_201X_DEV_ID 0x1410d24 67 #define MARVELL_88X201X_PHY_ID (MARVELL_88X_201X_DEV_ID & BCM_PHY_ID_MASK) 68 #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 69 #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 70 #define PHY_BCM5482_FAMILY (BCM5482_PHY_ID & BCM_PHY_ID_MASK) 71 /* 72 * The default value is 0xa19410, after masking out model and revision 73 * (bits[9:0]) use 0xa19400 for any model or revision of the TN1010 74 */ 75 #define TN1010_DEV_ID 0xa19400 76 /* 77 * Description of TN1010_DEV_ID_MASK: 78 * The device ID assigned to Teranetics is stored in TN1010 register 79 * 1.2 and register 1.3 except bits[9:4] of register 1.3 for model number 80 * and bits[3:0] of register 1.3 for revision numbers. Use mask 0xfffffc00 81 * to mask off model number and revision number and keep TN1010's device 82 * identifier 83 */ 84 #define TN1010_DEV_ID_MASK 0xfffffc00 85 86 #define CLAUSE_45_TYPE 1 87 #define CLAUSE_22_TYPE 2 88 89 /* IEEE802.3 Clause45 and Clause22 MDIO port addresses */ 90 #define NEPTUNE_CLAUSE22_PORT_ADDR_BASE 10 91 #define NEPTUNE_CLAUSE45_PORT_ADDR_BASE 8 92 #define N2_CLAUSE45_PORT_ADDR_BASE 16 93 #define MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 8 94 95 /* 96 * Phy address for the second NIU port on Goa NEM card can be either 97 * 20 or 17 98 */ 99 #define GOA_CLAUSE45_PORT_ADDR_BASE 16 100 #define ALT_GOA_CLAUSE45_PORT1_ADDR 20 101 /* 102 * Phy addresses for Maramba support. Support for P0 will eventually 103 * be removed. 104 */ 105 #define MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE 10 106 #define MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE 26 107 #define MARAMBA_CLAUSE45_PORT_ADDR_BASE 16 108 109 #define BCM8704_PMA_PMD_DEV_ADDR 1 110 #define BCM8704_PCS_DEV_ADDR 3 111 #define BCM8704_USER_DEV3_ADDR 3 112 #define BCM8704_PHYXS_ADDR 4 113 #define BCM8704_USER_DEV4_ADDR 4 114 115 /* Definitions for BCM 5464R PHY chip */ 116 117 #define BCM5464R_PHY_ECR 16 118 #define BCM5464R_PHY_ESR 17 119 #define BCM5464R_RXERR_CNT 18 120 #define BCM5464R_FALSECS_CNT 19 121 #define BCM5464R_RX_NOTOK_CNT 20 122 #define BCM5464R_ER_DATA 21 123 #define BCM5464R_RES 22 124 #define BCM5464R_ER_ACC 23 125 #define BCM5464R_AUX_CTL 24 126 #define BCM5464R_AUX_S 25 127 #define BCM5464R_INTR_S 26 128 #define BCM5464R_INTR_M 27 129 #define BCM5464R_MISC 28 130 #define BCM5464R_MISC1 29 131 #define BCM5464R_TESTR1 30 132 133 #define PHY_BCM_5464R_OUI 0x001018 134 #define PHY_BCM_5464R_MODEL 0x0B 135 136 /* MARVELL PHY Definitions */ 137 /* REG Offsets */ 138 #define MRVL_88X2011_USER_DEV1_ADDR 1 139 #define MRVL_88X2011_USER_DEV2_ADDR 2 140 #define MRVL_88X2011_USER_DEV3_ADDR 3 141 #define MRVL_88X2011_USER_DEV4_ADDR 4 142 #define MRVL_88X2011_PMA_PMD_CTL_1 0x0000 143 #define MRVL_88X2011_PMA_PMD_STAT_1 0x0001 144 #define MRVL_88X2011_10G_PMD_STAT_2 0x0008 145 #define MRVL_88X2011_10G_PMD_TX_DIS 0x0009 146 #define MRVL_88X2011_10G_XGXS_LANE_STAT 0x0018 147 #define MRVL_88X2011_GEN_CTL 0x8300 148 #define MRVL_88X2011_LED_BLINK_CTL 0x8303 149 #define MRVL_88X2011_LED_8_TO_11_CTL 0x8306 150 151 /* MRVL88X2011 register control */ 152 #define MRVL_88X2011_ENA_PMDTX 0x0000 153 #define MRVL_88X2011_ENA_XFPREFCLK 0x0001 154 #define MRVL_88X2011_LOOPBACK 0x1 155 #define MRVL_88X2011_LED_ACT 0x1 156 #define MRVL_88X2011_LNK_STATUS_OK 0x4 157 #define MRVL_88X2011_LED_BLK_MASK 0x70 158 #define MRVL_88X2011_LED_BLK_SHIFT 4 159 #define MRVL_88X2011_LED_BLK34MS 0x0 160 #define MRVL_88X2011_LED_BLK67MS 0x1 161 #define MRVL_88X2011_LED_BLK134MS 0x2 162 #define MRVL_88X2011_LED_BLK269MS 0x3 163 #define MRVL_88X2011_LED_BLK538MS 0x4 164 #define MRVL_88X2011_LED_CTL_OFF 0x0 165 #define MRVL_88X2011_LED_CTL_PCS_ERR 0x2 166 #define MRVL_88X2011_LED_CTL_PCS_ACT 0x5 167 #define MRVL_88X2011_LED_CTL_MASK 0x7 168 #define MRVL_88X2011_LED(n, v) ((v)<<((n)*4)) 169 #define MRVL_88X2011_LED_STAT(n, v) ((v)>>((n)*4)) 170 171 /* 172 * MII Register 16: PHY Extended Control Register 173 */ 174 175 typedef union _mii_phy_ecr_t { 176 uint16_t value; 177 struct { 178 #ifdef _BIT_FIELDS_HTOL 179 uint16_t mac_phy_if_mode : 1; 180 uint16_t dis_automdicross : 1; 181 uint16_t tx_dis : 1; 182 uint16_t intr_dis : 1; 183 uint16_t force_intr : 1; 184 uint16_t bypass_encdec : 1; 185 uint16_t bypass_scrdes : 1; 186 uint16_t bypass_mlt3 : 1; 187 uint16_t bypass_rx_sym : 1; 188 uint16_t reset_scr : 1; 189 uint16_t en_led_traffic : 1; 190 uint16_t force_leds_on : 1; 191 uint16_t force_leds_off : 1; 192 uint16_t res : 2; 193 uint16_t gmii_fifo_elas : 1; 194 #else 195 uint16_t gmii_fifo_elas : 1; 196 uint16_t res : 2; 197 uint16_t force_leds_off : 1; 198 uint16_t force_leds_on : 1; 199 uint16_t en_led_traffic : 1; 200 uint16_t reset_scr : 1; 201 uint16_t bypass_rx_sym : 1; 202 uint16_t bypass_mlt3 : 1; 203 uint16_t bypass_scrdes : 1; 204 uint16_t bypass_encdec : 1; 205 uint16_t force_intr : 1; 206 uint16_t intr_dis : 1; 207 uint16_t tx_dis : 1; 208 uint16_t dis_automdicross : 1; 209 uint16_t mac_phy_if_mode : 1; 210 #endif 211 } bits; 212 } mii_phy_ecr_t, *p_mii_phy_ecr_t; 213 214 /* 215 * MII Register 17: PHY Extended Status Register 216 */ 217 typedef union _mii_phy_esr_t { 218 uint16_t value; 219 struct { 220 #ifdef _BIT_FIELDS_HTOL 221 uint16_t anbpsfm : 1; 222 uint16_t wsdwngr : 1; 223 uint16_t mdi_crst : 1; 224 uint16_t intr_s : 1; 225 uint16_t rmt_rx_s : 1; 226 uint16_t loc_rx_s : 1; 227 uint16_t locked : 1; 228 uint16_t link_s : 1; 229 uint16_t crc_err : 1; 230 uint16_t cext_err : 1; 231 uint16_t bad_ssd : 1; 232 uint16_t bad_esd : 1; 233 uint16_t rx_err : 1; 234 uint16_t tx_err : 1; 235 uint16_t lock_err : 1; 236 uint16_t mlt3_cerr : 1; 237 #else 238 uint16_t mlt3_cerr : 1; 239 uint16_t lock_err : 1; 240 uint16_t tx_err : 1; 241 uint16_t rx_err : 1; 242 uint16_t bad_esd : 1; 243 uint16_t bad_ssd : 1; 244 uint16_t cext_err : 1; 245 uint16_t crc_err : 1; 246 uint16_t link_s : 1; 247 uint16_t locked : 1; 248 uint16_t loc_rx_s : 1; 249 uint16_t rmt_rx_s : 1; 250 uint16_t intr_s : 1; 251 uint16_t mdi_crst : 1; 252 uint16_t wsdwngr : 1; 253 uint16_t anbpsfm : 1; 254 #endif 255 } bits; 256 } mii_phy_esr_t, *p_mii_phy_esr_t; 257 258 /* 259 * MII Register 18: Receive Error Counter Register 260 */ 261 typedef union _mii_rxerr_cnt_t { 262 uint16_t value; 263 struct { 264 uint16_t rx_err_cnt : 16; 265 } bits; 266 } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 267 268 /* 269 * MII Register 19: False Carrier Sense Counter Register 270 */ 271 typedef union _mii_falsecs_cnt_t { 272 uint16_t value; 273 struct { 274 #ifdef _BIT_FIELDS_HTOL 275 uint16_t res : 8; 276 uint16_t false_cs_cnt : 8; 277 #else 278 uint16_t false_cs_cnt : 8; 279 uint16_t res : 8; 280 #endif 281 } bits; 282 } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 283 284 /* 285 * MII Register 20: Receiver NOT_OK Counter Register 286 */ 287 typedef union _mii_rx_notok_cnt_t { 288 uint16_t value; 289 struct { 290 #ifdef _BIT_FIELDS_HTOL 291 uint16_t l_rx_notok_cnt : 8; 292 uint16_t r_rx_notok_cnt : 8; 293 #else 294 uint16_t r_rx_notok_cnt : 8; 295 uint16_t l_rx_notok_cnt : 8; 296 #endif 297 } bits; 298 } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 299 300 /* 301 * MII Register 21: Expansion Register Data Register 302 */ 303 typedef union _mii_er_data_t { 304 uint16_t value; 305 struct { 306 uint16_t reg_data; 307 } bits; 308 } mii_er_data_t, *p_mii_er_data_t; 309 310 /* 311 * MII Register 23: Expansion Register Access Register 312 */ 313 typedef union _mii_er_acc_t { 314 struct { 315 #ifdef _BIT_FIELDS_HTOL 316 uint16_t res : 4; 317 uint16_t er_sel : 4; 318 uint16_t er_acc : 8; 319 #else 320 uint16_t er_acc : 8; 321 uint16_t er_sel : 4; 322 uint16_t res : 4; 323 #endif 324 } bits; 325 } mii_er_acc_t, *p_mii_er_acc_t; 326 327 #define EXP_RXTX_PKT_CNT 0x0 328 #define EXP_INTR_STAT 0x1 329 #define MULTICOL_LED_SEL 0x4 330 #define MULTICOL_LED_FLASH_RATE_CTL 0x5 331 #define MULTICOL_LED_BLINK_CTL 0x6 332 #define CABLE_DIAG_CTL 0x10 333 #define CABLE_DIAG_RES 0x11 334 #define CABLE_DIAG_LEN_CH_2_1 0x12 335 #define CABLE_DIAG_LEN_CH_4_3 0x13 336 337 /* 338 * MII Register 24: Auxiliary Control Register 339 */ 340 typedef union _mii_aux_ctl_t { 341 uint16_t value; 342 struct { 343 #ifdef _BIT_FIELDS_HTOL 344 uint16_t ext_lb : 1; 345 uint16_t ext_pkt_len : 1; 346 uint16_t edge_rate_ctl_1000 : 2; 347 uint16_t res : 1; 348 uint16_t write_1 : 1; 349 uint16_t res1 : 2; 350 uint16_t dis_partial_resp : 1; 351 uint16_t res2 : 1; 352 uint16_t edge_rate_ctl_100 : 2; 353 uint16_t diag_mode : 1; 354 uint16_t shadow_reg_sel : 3; 355 #else 356 uint16_t shadow_reg_sel : 3; 357 uint16_t diag_mode : 1; 358 uint16_t edge_rate_ctl_100 : 2; 359 uint16_t res2 : 1; 360 uint16_t dis_partial_resp : 1; 361 uint16_t res1 : 2; 362 uint16_t write_1 : 1; 363 uint16_t res : 1; 364 uint16_t edge_rate_ctl_1000 : 2; 365 uint16_t ext_pkt_len : 1; 366 uint16_t ext_lb : 1; 367 #endif 368 } bits; 369 } mii_aux_ctl_t, *p_mii_aux_ctl_t; 370 371 #define AUX_REG 0x0 372 #define AUX_10BASET 0x1 373 #define AUX_PWR_CTL 0x2 374 #define AUX_MISC_TEST 0x4 375 #define AUX_MISC_CTL 0x7 376 377 /* 378 * MII Register 25: Auxiliary Status Summary Register 379 */ 380 typedef union _mii_aux_s_t { 381 uint16_t value; 382 struct { 383 #ifdef _BIT_FIELDS_HTOL 384 uint16_t an_complete : 1; 385 uint16_t an_complete_ack : 1; 386 uint16_t an_ack_detect : 1; 387 uint16_t an_ability_detect : 1; 388 uint16_t an_np_wait : 1; 389 uint16_t an_hcd : 3; 390 uint16_t pd_fault : 1; 391 uint16_t rmt_fault : 1; 392 uint16_t an_page_rx : 1; 393 uint16_t lp_an_ability : 1; 394 uint16_t lp_np_ability : 1; 395 uint16_t link_s : 1; 396 uint16_t pause_res_rx_dir : 1; 397 uint16_t pause_res_tx_dir : 1; 398 #else 399 uint16_t pause_res_tx_dir : 1; 400 uint16_t pause_res_rx_dir : 1; 401 uint16_t link_s : 1; 402 uint16_t lp_np_ability : 1; 403 uint16_t lp_an_ability : 1; 404 uint16_t an_page_rx : 1; 405 uint16_t rmt_fault : 1; 406 uint16_t pd_fault : 1; 407 uint16_t an_hcd : 3; 408 uint16_t an_np_wait : 1; 409 uint16_t an_ability_detect : 1; 410 uint16_t an_ack_detect : 1; 411 uint16_t an_complete_ack : 1; 412 uint16_t an_complete : 1; 413 #endif 414 } bits; 415 } mii_aux_s_t, *p_mii_aux_s_t; 416 417 /* 418 * MII Register 26, 27: Interrupt Status and Mask Registers 419 */ 420 typedef union _mii_intr_t { 421 uint16_t value; 422 struct { 423 #ifdef _BIT_FIELDS_HTOL 424 uint16_t res : 1; 425 uint16_t illegal_pair_swap : 1; 426 uint16_t mdix_status_change : 1; 427 uint16_t exceed_hicnt_thres : 1; 428 uint16_t exceed_locnt_thres : 1; 429 uint16_t an_page_rx : 1; 430 uint16_t hcd_nolink : 1; 431 uint16_t no_hcd : 1; 432 uint16_t neg_unsupported_hcd : 1; 433 uint16_t scr_sync_err : 1; 434 uint16_t rmt_rx_status_change : 1; 435 uint16_t loc_rx_status_change : 1; 436 uint16_t duplex_mode_change : 1; 437 uint16_t link_speed_change : 1; 438 uint16_t link_status_change : 1; 439 uint16_t crc_err : 1; 440 #else 441 uint16_t crc_err : 1; 442 uint16_t link_status_change : 1; 443 uint16_t link_speed_change : 1; 444 uint16_t duplex_mode_change : 1; 445 uint16_t loc_rx_status_change : 1; 446 uint16_t rmt_rx_status_change : 1; 447 uint16_t scr_sync_err : 1; 448 uint16_t neg_unsupported_hcd : 1; 449 uint16_t no_hcd : 1; 450 uint16_t hcd_nolink : 1; 451 uint16_t an_page_rx : 1; 452 uint16_t exceed_locnt_thres : 1; 453 uint16_t exceed_hicnt_thres : 1; 454 uint16_t mdix_status_change : 1; 455 uint16_t illegal_pair_swap : 1; 456 uint16_t res : 1; 457 #endif 458 } bits; 459 } mii_intr_t, *p_mii_intr_t; 460 461 /* 462 * MII Register 28: Register 1C Access Register 463 */ 464 typedef union _mii_misc_t { 465 uint16_t value; 466 struct { 467 #ifdef _BIT_FIELDS_HTOL 468 uint16_t w_en : 1; 469 uint16_t shadow_reg_sel : 5; 470 uint16_t data : 10; 471 #else 472 uint16_t data : 10; 473 uint16_t shadow_reg_sel : 5; 474 uint16_t w_en : 1; 475 #endif 476 } bits; 477 } mii_misc_t, *p_mii_misc_t; 478 479 #define LINK_LED_MODE 0x2 480 #define CLK_ALIGN_CTL 0x3 481 #define WIRE_SP_RETRY 0x4 482 #define CLK125 0x5 483 #define LED_STATUS 0x8 484 #define LED_CONTROL 0x9 485 #define AUTO_PWR_DOWN 0xA 486 #define LED_SEL1 0xD 487 #define LED_SEL2 0xE 488 489 /* 490 * MII Register 29: Master/Slave Seed / HCD Status Register 491 */ 492 493 typedef union _mii_misc1_t { 494 uint16_t value; 495 struct { 496 #ifdef _BIT_FIELDS_HTOL 497 uint16_t en_shadow_reg : 1; 498 uint16_t data : 15; 499 #else 500 uint16_t data : 15; 501 uint16_t en_shadow_reg : 1; 502 #endif 503 } bits; 504 } mii_misc1_t, *p_mii_misc1_t; 505 506 /* 507 * MII Register 30: Test Register 1 508 */ 509 510 typedef union _mii_test1_t { 511 uint16_t value; 512 struct { 513 #ifdef _BIT_FIELDS_HTOL 514 uint16_t crc_err_cnt_sel : 1; 515 uint16_t res : 7; 516 uint16_t manual_swap_mdi_st : 1; 517 uint16_t res1 : 7; 518 #else 519 uint16_t res1 : 7; 520 uint16_t manual_swap_mdi_st : 1; 521 uint16_t res : 7; 522 uint16_t crc_err_cnt_sel : 1; 523 #endif 524 } bits; 525 } mii_test1_t, *p_mii_test1_t; 526 527 528 /* Definitions of BCM8704 */ 529 530 #define BCM8704_PMD_CONTROL_REG 0 531 #define BCM8704_PMD_STATUS_REG 0x1 532 #define BCM8704_PMD_ID_0_REG 0x2 533 #define BCM8704_PMD_ID_1_REG 0x3 534 #define BCM8704_PMD_SPEED_ABIL_REG 0x4 535 #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 536 #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 537 #define BCM8704_PMD_CONTROL2_REG 0x7 538 #define BCM8704_PMD_STATUS2_REG 0x8 539 #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 540 #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 541 #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 542 #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 543 #define BCM8704_PCS_CONTROL_REG 0 544 #define BCM8704_PCS_STATUS1_REG 0x1 545 #define BCM8704_PCS_ID_0_REG 0x2 546 #define BCM8704_PCS_ID_1_REG 0x3 547 #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 548 #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 549 #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 550 #define BCM8704_PCS_CONTROL2_REG 0x7 551 #define BCM8704_PCS_STATUS2_REG 0x8 552 #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 553 #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 554 #define BCM8704_PCS_STATUS_REG 0x18 555 #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 556 #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 557 #define BCM8704_PHYXS_CONTROL_REG 0 558 #define BCM8704_PHYXS_STATUS_REG 0x1 559 #define BCM8704_PHY_ID_0_REG 0x2 560 #define BCM8704_PHY_ID_1_REG 0x3 561 #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 562 #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 563 #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 564 #define BCM8704_PHYXS_STATUS2_REG 0x8 565 #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 566 #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 567 #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 568 #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 569 #define BCM8704_USER_CONTROL_REG 0xC800 570 #define BCM8704_USER_ANALOG_CLK_REG 0xC801 571 #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 572 #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 573 #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 574 #define BCM8704_CHIP_ID_REG 0xC807 575 #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 576 #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 577 #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 578 #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 579 #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 580 581 /* Rx Channel Control1 Register bits */ 582 #define BCM8704_RXPOL_FLIP 0x20 583 584 typedef union _phyxs_control { 585 uint16_t value; 586 struct { 587 #ifdef _BIT_FIELDS_HTOL 588 uint16_t reset : 1; 589 uint16_t loopback : 1; 590 uint16_t speed_sel2 : 1; 591 uint16_t res2 : 1; 592 uint16_t low_power : 1; 593 uint16_t res1 : 4; 594 uint16_t speed_sel1 : 1; 595 uint16_t speed_sel0 : 4; 596 uint16_t res0 : 2; 597 #else 598 uint16_t res0 : 2; 599 uint16_t speed_sel0 : 4; 600 uint16_t speed_sel1 : 1; 601 uint16_t res1 : 4; 602 uint16_t low_power : 1; 603 uint16_t res2 : 1; 604 uint16_t speed_sel2 : 1; 605 uint16_t loopback : 1; 606 uint16_t reset : 1; 607 #endif 608 } bits; 609 } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 610 611 612 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 613 614 typedef union _control { 615 uint16_t value; 616 struct { 617 #ifdef _BIT_FIELDS_HTOL 618 uint16_t optxenb_lvl : 1; 619 uint16_t optxrst_lvl : 1; 620 uint16_t opbiasflt_lvl : 1; 621 uint16_t obtmpflt_lvl : 1; 622 uint16_t opprflt_lvl : 1; 623 uint16_t optxflt_lvl : 1; 624 uint16_t optrxlos_lvl : 1; 625 uint16_t oprxflt_lvl : 1; 626 uint16_t optxon_lvl : 1; 627 uint16_t res1 : 7; 628 #else 629 uint16_t res1 : 7; 630 uint16_t optxon_lvl : 1; 631 uint16_t oprxflt_lvl : 1; 632 uint16_t optrxlos_lvl : 1; 633 uint16_t optxflt_lvl : 1; 634 uint16_t opprflt_lvl : 1; 635 uint16_t obtmpflt_lvl : 1; 636 uint16_t opbiasflt_lvl : 1; 637 uint16_t optxrst_lvl : 1; 638 uint16_t optxenb_lvl : 1; 639 #endif 640 } bits; 641 } control_t, *p_control_t; 642 643 typedef union _pmd_tx_control { 644 uint16_t value; 645 struct { 646 #ifdef _BIT_FIELDS_HTOL 647 uint16_t res1 : 7; 648 uint16_t xfp_clken : 1; 649 uint16_t tx_dac_txd : 2; 650 uint16_t tx_dac_txck : 2; 651 uint16_t tsd_lpwren : 1; 652 uint16_t tsck_lpwren : 1; 653 uint16_t cmu_lpwren : 1; 654 uint16_t sfiforst : 1; 655 #else 656 uint16_t sfiforst : 1; 657 uint16_t cmu_lpwren : 1; 658 uint16_t tsck_lpwren : 1; 659 uint16_t tsd_lpwren : 1; 660 uint16_t tx_dac_txck : 2; 661 uint16_t tx_dac_txd : 2; 662 uint16_t xfp_clken : 1; 663 uint16_t res1 : 7; 664 #endif 665 } bits; 666 } pmd_tx_control_t, *p_pmd_tx_control_t; 667 668 669 /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 670 671 typedef union _optics_dcntr { 672 uint16_t value; 673 struct { 674 #ifdef _BIT_FIELDS_HTOL 675 uint16_t fault_mode : 1; 676 uint16_t tx_pwrdown : 1; 677 uint16_t rx_pwrdown : 1; 678 uint16_t ext_flt_en : 1; 679 uint16_t opt_rst : 1; 680 uint16_t pcs_tx_inv_b : 1; 681 uint16_t pcs_rx_inv : 1; 682 uint16_t res3 : 2; 683 uint16_t gpio_sel : 2; 684 uint16_t res2 : 1; 685 uint16_t lpbk_err_dis : 1; 686 uint16_t res1 : 2; 687 uint16_t txonoff_pwdwn_dis : 1; 688 #else 689 uint16_t txonoff_pwdwn_dis : 1; 690 uint16_t res1 : 2; 691 uint16_t lpbk_err_dis : 1; 692 uint16_t res2 : 1; 693 uint16_t gpio_sel : 2; 694 uint16_t res3 : 2; 695 uint16_t pcs_rx_inv : 1; 696 uint16_t pcs_tx_inv_b : 1; 697 uint16_t opt_rst : 1; 698 uint16_t ext_flt_en : 1; 699 uint16_t rx_pwrdown : 1; 700 uint16_t tx_pwrdown : 1; 701 uint16_t fault_mode : 1; 702 #endif 703 } bits; 704 } optics_dcntr_t, *p_optics_dcntr_t; 705 706 /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 707 708 #define PMD_RX_SIG_DET3 0x10 709 #define PMD_RX_SIG_DET2 0x08 710 #define PMD_RX_SIG_DET1 0x04 711 #define PMD_RX_SIG_DET0 0x02 712 #define GLOB_PMD_RX_SIG_OK 0x01 713 714 /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 715 716 #define PCS_10GBASE_RX_LINK_STATUS 0x1000 717 #define PCS_PRBS31_ABLE 0x0004 718 #define PCS_10GBASE_R_HI_BER 0x0002 719 #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 720 721 /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 722 723 #define XGXS_LANE_ALIGN_STATUS 0x1000 724 #define XGXS_PATTERN_TEST_ABILITY 0x0800 725 #define XGXS_LANE3_SYNC 0x0008 726 #define XGXS_LANE2_SYNC 0x0004 727 #define XGXS_LANE1_SYNC 0x0002 728 #define XGXS_LANE0_SYNC 0x0001 729 #define XGXS_LANE_STAT_MAGIC 0x0400 730 731 732 /* Teranetics TN1010 Definitions */ 733 734 /* Teranetics TN1010 PHY MMD Addresses */ 735 #define TN1010_PMA_PMD_DEV_ADDR 1 736 #define TN1010_PCS_DEV_ADDR 3 737 #define TN1010_PHYXS_DEV_ADDR 4 738 #define TN1010_AUTONEG_DEV_ADDR 7 739 #define TN1010_VENDOR_MMD1_DEV_ADDR 30 740 741 /* TN1010 PCS Control Register */ 742 typedef union _tn1010_pcs_ctrl { 743 uint16_t value; 744 struct { 745 #ifdef _BIT_FIELDS_HTOL 746 uint16_t reset : 1; /* bit 15 */ 747 uint16_t loopback : 1; /* bit 14 */ 748 uint16_t speed_sel2 : 1; 749 uint16_t res2 : 1; 750 uint16_t low_power : 1; 751 uint16_t res1 : 4; 752 uint16_t speed_sel1 : 1; /* bit 6 */ 753 uint16_t speed_sel0 : 4; /* bits[5:2] */ 754 uint16_t res0 : 2; 755 #else 756 uint16_t res0 : 2; 757 uint16_t speed_sel0 : 4; /* bits[5:2] */ 758 uint16_t speed_sel1 : 1; /* bit 6 */ 759 uint16_t res1 : 4; 760 uint16_t low_power : 1; 761 uint16_t res2 : 1; 762 uint16_t speed_sel2 : 1; 763 uint16_t loopback : 1; /* bit 14 */ 764 uint16_t reset : 1; /* bit 15 */ 765 #endif 766 } bits; 767 } tn1010_phyxs_ctrl_t, *p_tn1010_phyxs_ctrl_t; 768 769 /* TN1010 PHY XS Control Register */ 770 typedef union _tn1010_phyxs_ctrl { 771 uint16_t value; 772 struct { 773 #ifdef _BIT_FIELDS_HTOL 774 uint16_t reset : 1; /* bit 15 */ 775 uint16_t loopback : 1; /* bit 14 */ 776 uint16_t speed_sel2 : 1; 777 uint16_t res2 : 1; 778 uint16_t low_power : 1; 779 uint16_t res1 : 4; 780 uint16_t speed_sel1 : 1; /* bit 6 */ 781 uint16_t speed_sel0 : 4; /* bits[5:2] */ 782 uint16_t res0 : 2; 783 #else 784 uint16_t res0 : 2; 785 uint16_t speed_sel0 : 4; /* bits[5:2] */ 786 uint16_t speed_sel1 : 1; /* bit 6 */ 787 uint16_t res1 : 4; 788 uint16_t low_power : 1; 789 uint16_t res2 : 1; 790 uint16_t speed_sel2 : 1; 791 uint16_t loopback : 1; /* bit 14 */ 792 uint16_t reset : 1; /* bit 15 */ 793 #endif 794 } bits; 795 } tn1010_pcs_ctrl_t, *p_tn1010_pcs_ctrl_t; 796 797 /* TN1010 VENDOR MMD1 GPHY Control register 30.310 */ 798 #define TN1010_SGMII_LOOPBACK 1 799 #define TN1010_DEEP_LOOPBACK 2 800 801 #define TN1010_PMD_CONTROL_REG 0 802 #define TN1010_PMD_STATUS_REG 1 803 #define TN1010_PMD_ID_HIGH_REG 2 804 #define TN1010_PMD_ID_LOW_REG 3 805 #define TN1010_PMD_SPEED_ABIL_REG 4 806 #define TN1010_PMD_DEV_IN_PKG1_REG 5 807 #define TN1010_PMD_DEV_IN_PKG2_REG 6 808 #define TN1010_PMD_CONTROL2_REG 7 809 #define TN1010_PMD_STATUS2_REG 8 810 #define TN1010_PMD_TRANSMIT_DIS_REG 9 811 #define TN1010_PMD_RECEIVE_SIG_DETECT 10 812 #define TN1010_PMD_ORG_UNIQUE_ID_0_REG 14 813 #define TN1010_PMD_ORG_UNIQUE_ID_1_REG 15 814 #define TN1010_PCS_CONTROL_REG 0 815 #define TN1010_PCS_STATUS1_REG 1 816 #define TN1010_PCS_ID_HIGH_REG 2 817 #define TN1010_PCS_ID_LOW_REG 3 818 #define TN1010_PCS_SPEED_ABILITY_REG 4 819 #define TN1010_PCS_DEV_IN_PKG1_REG 5 820 #define TN1010_PCS_DEV_IN_PKG2_REG 6 821 #define TN1010_PCS_CONTROL2_REG 7 822 #define TN1010_PCS_STATUS2_REG 8 823 #define TN1010_PCS_ORG_UNIQUE_ID_0_REG 14 824 #define TN1010_PCS_ORG_UNIQUE_ID_1_REG 15 825 #define TN1010_PCS_10GBASE_R_T_STATUS1_REG 32 826 #define TN1010_PCS_10GBASE_R_T_STATUS2_REG 33 827 #define TN1010_PHYXS_CONTROL_REG 0 828 #define TN1010_PHYXS_STATUS_REG 1 829 #define TN1010_PHY_ID_HIGH_REG 2 830 #define TN1010_PHY_ID_LOW_REG 3 831 #define TN1010_PHYXS_SPEED_ABILITY_REG 4 832 #define TN1010_PHYXS_DEV_IN_PKG2_REG 5 833 #define TN1010_PHYXS_DEV_IN_PKG1_REG 6 834 #define TN1010_PHYXS_STATUS2_REG 8 835 #define TN1010_PHYXS_ORG_UNIQUE_ID_0_REG 14 836 #define TN1010_PHYXS_ORG_UNIQUE_ID_1_REG 15 837 #define TN1010_PHYXS_XGXS_LANE_STATUS_REG 24 838 #define TN1010_PHYXS_XGXS_TEST_CONTROL_REG 25 839 840 #define TN1010_AUTONEG_CONTROL_REG 0 841 #define TN1010_AUTONEG_STATUS_REG 1 842 #define TN1010_AUTONEG_ID_HIGH_REG 2 843 #define TN1010_AUTONEG_ID_LOW_REG 3 844 #define TN1010_AUTONEG_DEV_IN_PKG1_REG 5 845 #define TN1010_AUTUNEG_DEV_IN_PKG2_REG 6 846 #define TN1010_AUTONEG_ORG_UNIQUE_ID_0_REG 14 847 #define TN1010_AUTONEG_ORG_UNIQUE_ID_1_REG 15 848 #define TN1010_AUTONEG_ADVERTISE_REG 16 849 #define TN1010_AUTONEG_PARTNER_ABILITY_REG 19 850 851 #define TN1010_VENDOR_MMD1_CONTROL_REG 0 852 #define TN1010_VENDOR_MMD1_STATUS_REG 1 853 #define TN1010_VENDOR_MMD1_ID_HIGH 2 854 #define TN1010_VENDOR_MMD1_ID_LOW 3 855 #define TN1010_VENDOR_MMD1_DEV_STATUS_REG 8 856 #define TN1010_VENDOR_MMD1_FNS_CONTROL_RER 9 857 #define TN1010_VENDOR_MMD1_PKG_ID_0_REG 14 858 #define TN1010_VENDOR_MMD1_PKG_ID_1_REG 15 859 #define TN1010_VENDOR_MMD1_GPHY_CTRL 310 860 861 /* Bits definitions of TN1010_AUTONEG_CONTROL_REG */ 862 #define TN1010_AN_CTRL_RESET_BIT 0x8000 /* Reset */ 863 #define TN1010_AN_CTRL_EN_BIT 0x1000 /* Enable autoneg */ 864 #define TN1010_AN_CTRL_RESTART_BIT 0x200 /* Restart autoneg */ 865 #define TN1010_AN_LINK_STAT_BIT 0x4 /* Link status */ 866 867 /* Bits definitions of TN1010_PHYXS_CONTROL_REG */ 868 #define TN1010_VENDOR_MMD1_AN_STAT_BITS 0xC0 869 870 /* 871 * Shift right 6 bits so bits[7:6] becomes [1:0]. 872 * Bits[7:6] of TN1010_VENDOR_MND1_STATUS_REG are for autoneg status 873 * 00 in progress 874 * 01 completed 875 * 10 reserved 876 * 11 failed 877 */ 878 #define TN1010_VENDOR_MMD1_AN_STAT_SHIFT 6 879 880 /* Bit 4 of TN1010_VENDOR_MMD1_STATUS_REG is speed. 0: 10G, 1: 1G */ 881 #define TN1010_VENDOR_MMD1_AN_SPEED_BIT 0x10 882 883 /* Shift right 4 bits so bit4 becomes bit0 */ 884 #define TN1010_VENDOR_MMD1_AN_SPEED_SHIFT 4 885 886 887 #ifdef __cplusplus 888 } 889 #endif 890 891 #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 892