1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_MII_H_ 27 #define _SYS_NXGE_NXGE_MII_H_ 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/miiregs.h> 34 35 /* 36 * Configuration Register space. 37 */ 38 39 #define NXGE_MII_LPRXNPR 8 40 #define NXGE_MII_GCR 9 41 #define NXGE_MII_GSR 10 42 #define NXGE_MII_RES0 11 43 #define NXGE_MII_RES1 12 44 #define NXGE_MII_RES2 13 45 #define NXGE_MII_RES3 14 46 #define NXGE_MII_ESR 15 47 48 #define NXGE_MII_SHADOW MII_VENDOR(0xc) 49 /* Shadow register definition */ 50 #define NXGE_MII_MODE_CONTROL_REG MII_VENDOR(0xf) 51 52 #define NXGE_MAX_MII_REGS 32 53 54 /* 55 * Configuration Register space. 56 */ 57 typedef struct _mii_regs { 58 uchar_t bmcr; /* Basic mode control register */ 59 uchar_t bmsr; /* Basic mode status register */ 60 uchar_t idr1; /* Phy identifier register 1 */ 61 uchar_t idr2; /* Phy identifier register 2 */ 62 uchar_t anar; /* Auto-Negotiation advertisement register */ 63 uchar_t anlpar; /* Auto-Negotiation link Partner ability reg */ 64 uchar_t aner; /* Auto-Negotiation expansion register */ 65 uchar_t nptxr; /* Next page transmit register */ 66 uchar_t lprxnpr; /* Link partner received next page register */ 67 uchar_t gcr; /* Gigabit basic mode control register. */ 68 uchar_t gsr; /* Gigabit basic mode status register */ 69 uchar_t mii_res1[4]; /* For future use by MII working group */ 70 uchar_t esr; /* Extended status register. */ 71 uchar_t vendor_res[12]; /* For future use by Phy Vendors */ 72 uchar_t shadow; 73 uchar_t vendor_res2[3]; /* For future use by Phy Vendors */ 74 } mii_regs_t, *p_mii_regs_t; 75 76 /* 77 * MII Register 0: Basic mode control register. 78 */ 79 typedef union _mii_bmcr { 80 uint16_t value; 81 struct { 82 #if defined(_BIT_FIELDS_HTOL) 83 uint16_t reset:1; 84 uint16_t loopback:1; 85 uint16_t speed_sel:1; 86 uint16_t enable_autoneg:1; 87 uint16_t power_down:1; 88 uint16_t isolate:1; 89 uint16_t restart_autoneg:1; 90 uint16_t duplex_mode:1; 91 uint16_t col_test:1; 92 uint16_t speed_1000_sel:1; 93 uint16_t res1:6; 94 #elif defined(_BIT_FIELDS_LTOH) 95 uint16_t res1:6; 96 uint16_t speed_1000_sel:1; 97 uint16_t col_test:1; 98 uint16_t duplex_mode:1; 99 uint16_t restart_autoneg:1; 100 uint16_t isolate:1; 101 uint16_t power_down:1; 102 uint16_t enable_autoneg:1; 103 uint16_t speed_sel:1; 104 uint16_t loopback:1; 105 uint16_t reset:1; 106 #endif 107 } bits; 108 } mii_bmcr_t, *p_mii_bmcr_t; 109 110 /* 111 * MII Register 1: Basic mode status register. 112 */ 113 typedef union _mii_bmsr { 114 uint16_t value; 115 struct { 116 #if defined(_BIT_FIELDS_HTOL) 117 uint16_t link_100T4:1; 118 uint16_t link_100fdx:1; 119 uint16_t link_100hdx:1; 120 uint16_t link_10fdx:1; 121 uint16_t link_10hdx:1; 122 uint16_t res2:2; 123 uint16_t extend_status:1; 124 uint16_t res1:1; 125 uint16_t preamble_supress:1; 126 uint16_t auto_neg_complete:1; 127 uint16_t remote_fault:1; 128 uint16_t auto_neg_able:1; 129 uint16_t link_status:1; 130 uint16_t jabber_detect:1; 131 uint16_t ext_cap:1; 132 #elif defined(_BIT_FIELDS_LTOH) 133 int16_t ext_cap:1; 134 uint16_t jabber_detect:1; 135 uint16_t link_status:1; 136 uint16_t auto_neg_able:1; 137 uint16_t remote_fault:1; 138 uint16_t auto_neg_complete:1; 139 uint16_t preamble_supress:1; 140 uint16_t res1:1; 141 uint16_t extend_status:1; 142 uint16_t res2:2; 143 uint16_t link_10hdx:1; 144 uint16_t link_10fdx:1; 145 uint16_t link_100hdx:1; 146 uint16_t link_100fdx:1; 147 uint16_t link_100T4:1; 148 #endif 149 } bits; 150 } mii_bmsr_t, *p_mii_bmsr_t; 151 152 /* 153 * MII Register 2: Physical Identifier 1. 154 */ 155 /* contains BCM OUI bits [3:18] */ 156 typedef union _mii_idr1 { 157 uint16_t value; 158 struct { 159 uint16_t ieee_address:16; 160 } bits; 161 } mii_idr1_t, *p_mii_idr1_t; 162 163 /* 164 * MII Register 3: Physical Identifier 2. 165 */ 166 typedef union _mii_idr2 { 167 uint16_t value; 168 struct { 169 #if defined(_BIT_FIELDS_HTOL) 170 uint16_t ieee_address:6; 171 uint16_t model_no:6; 172 uint16_t rev_no:4; 173 #elif defined(_BIT_FIELDS_LTOH) 174 uint16_t rev_no:4; 175 uint16_t model_no:6; 176 uint16_t ieee_address:6; 177 #endif 178 } bits; 179 } mii_idr2_t, *p_mii_idr2_t; 180 181 /* 182 * MII Register 4: Auto-negotiation advertisement register. 183 */ 184 typedef union _mii_anar { 185 uint16_t value; 186 struct { 187 #if defined(_BIT_FIELDS_HTOL) 188 uint16_t np_indication:1; 189 uint16_t acknowledge:1; 190 uint16_t remote_fault:1; 191 uint16_t res1:1; 192 uint16_t cap_asmpause:1; 193 uint16_t cap_pause:1; 194 uint16_t cap_100T4:1; 195 uint16_t cap_100fdx:1; 196 uint16_t cap_100hdx:1; 197 uint16_t cap_10fdx:1; 198 uint16_t cap_10hdx:1; 199 uint16_t selector:5; 200 #elif defined(_BIT_FIELDS_LTOH) 201 uint16_t selector:5; 202 uint16_t cap_10hdx:1; 203 uint16_t cap_10fdx:1; 204 uint16_t cap_100hdx:1; 205 uint16_t cap_100fdx:1; 206 uint16_t cap_100T4:1; 207 uint16_t cap_pause:1; 208 uint16_t cap_asmpause:1; 209 uint16_t res1:1; 210 uint16_t remote_fault:1; 211 uint16_t acknowledge:1; 212 uint16_t np_indication:1; 213 #endif 214 } bits; 215 } mii_anar_t, *p_mii_anar_t; 216 217 /* 218 * MII Register 5: Auto-negotiation link partner ability register. 219 */ 220 typedef mii_anar_t mii_anlpar_t, *pmii_anlpar_t; 221 222 /* 223 * MII Register 6: Auto-negotiation expansion register. 224 */ 225 typedef union _mii_aner { 226 uint16_t value; 227 struct { 228 #if defined(_BIT_FIELDS_HTOL) 229 uint16_t res:11; 230 uint16_t mlf:1; 231 uint16_t lp_np_able:1; 232 uint16_t np_able:1; 233 uint16_t page_rx:1; 234 uint16_t lp_an_able:1; 235 #else 236 uint16_t lp_an_able:1; 237 uint16_t page_rx:1; 238 uint16_t np_able:1; 239 uint16_t lp_np_able:1; 240 uint16_t mlf:1; 241 uint16_t res:11; 242 #endif 243 } bits; 244 } mii_aner_t, *p_mii_aner_t; 245 246 /* 247 * MII Register 7: Next page transmit register. 248 */ 249 typedef union _mii_nptxr { 250 uint16_t value; 251 struct { 252 #if defined(_BIT_FIELDS_HTOL) 253 uint16_t np:1; 254 uint16_t res:1; 255 uint16_t msgp:1; 256 uint16_t ack2:1; 257 uint16_t toggle:1; 258 uint16_t res1:11; 259 #else 260 uint16_t res1:11; 261 uint16_t toggle:1; 262 uint16_t ack2:1; 263 uint16_t msgp:1; 264 uint16_t res:1; 265 uint16_t np:1; 266 #endif 267 } bits; 268 } mii_nptxr_t, *p_mii_nptxr_t; 269 270 /* 271 * MII Register 8: Link partner received next page register. 272 */ 273 typedef union _mii_lprxnpr { 274 uint16_t value; 275 struct { 276 #if defined(_BIT_FIELDS_HTOL) 277 uint16_t np:1; 278 uint16_t ack:1; 279 uint16_t msgp:1; 280 uint16_t ack2:1; 281 uint16_t toggle:1; 282 uint16_t mcf:11; 283 #else 284 uint16_t mcf:11; 285 uint16_t toggle:1; 286 uint16_t ack2:1; 287 uint16_t msgp:1; 288 uint16_t ack:1; 289 uint16_t np:1; 290 #endif 291 } bits; 292 } mii_lprxnpr_t, *p_mii_lprxnpr_t; 293 294 /* 295 * MII Register 9: 1000BaseT control register. 296 */ 297 typedef union _mii_gcr { 298 uint16_t value; 299 struct { 300 #if defined(_BIT_FIELDS_HTOL) 301 uint16_t test_mode:3; 302 uint16_t ms_mode_en:1; 303 uint16_t master:1; 304 uint16_t dte_or_repeater:1; 305 uint16_t link_1000fdx:1; 306 uint16_t link_1000hdx:1; 307 uint16_t res:8; 308 #else 309 uint16_t res:8; 310 uint16_t link_1000hdx:1; 311 uint16_t link_1000fdx:1; 312 uint16_t dte_or_repeater:1; 313 uint16_t master:1; 314 uint16_t ms_mode_en:1; 315 uint16_t test_mode:3; 316 #endif 317 } bits; 318 } mii_gcr_t, *p_mii_gcr_t; 319 320 /* 321 * MII Register 10: 1000BaseT status register. 322 */ 323 typedef union _mii_gsr { 324 uint16_t value; 325 struct { 326 #if defined(_BIT_FIELDS_HTOL) 327 uint16_t ms_config_fault:1; 328 uint16_t ms_resolve:1; 329 uint16_t local_rx_status:1; 330 uint16_t remote_rx_status:1; 331 uint16_t link_1000fdx:1; 332 uint16_t link_1000hdx:1; 333 uint16_t res:2; 334 uint16_t idle_err_cnt:8; 335 #else 336 uint16_t idle_err_cnt:8; 337 uint16_t res:2; 338 uint16_t link_1000hdx:1; 339 uint16_t link_1000fdx:1; 340 uint16_t remote_rx_status:1; 341 uint16_t local_rx_status:1; 342 uint16_t ms_resolve:1; 343 uint16_t ms_config_fault:1; 344 #endif 345 } bits; 346 } mii_gsr_t, *p_mii_gsr_t; 347 348 /* 349 * MII Register 15: Extended status register. 350 */ 351 typedef union _mii_esr { 352 uint16_t value; 353 struct { 354 #if defined(_BIT_FIELDS_HTOL) 355 uint16_t link_1000Xfdx:1; 356 uint16_t link_1000Xhdx:1; 357 uint16_t link_1000fdx:1; 358 uint16_t link_1000hdx:1; 359 uint16_t res:12; 360 #else 361 uint16_t res:12; 362 uint16_t link_1000hdx:1; 363 uint16_t link_1000fdx:1; 364 uint16_t link_1000Xhdx:1; 365 uint16_t link_1000Xfdx:1; 366 #endif 367 } bits; 368 } mii_esr_t, *p_mii_esr_t; 369 370 #define NXGE_MODE_SELECT_FIBER 0x01 371 /* Shadow regiser 0x11111 */ 372 typedef union _mii_mode_control_stat { 373 uint16_t value; 374 struct { 375 #if defined(_BIT_FIELDS_HTOL) 376 uint16_t write_enable:1; 377 uint16_t shadow:5; 378 uint16_t rsv:1; 379 uint16_t change:1; 380 uint16_t copper:1; 381 uint16_t fiber:1; 382 uint16_t copper_energy:1; 383 uint16_t fiber_signal:1; 384 uint16_t rsv1:1; 385 uint16_t mode:2; 386 uint16_t enable:1; 387 #elif defined(_BIT_FIELDS_LTOH) 388 uint16_t enable:1; 389 uint16_t mode:2; 390 uint16_t rsv1:1; 391 uint16_t fiber_signal:1; 392 uint16_t copper_energy:1; 393 uint16_t fiber:1; 394 uint16_t copper:1; 395 uint16_t change:1; 396 uint16_t rsv:1; 397 uint16_t shadow:5; 398 uint16_t write_enable:1; 399 #endif 400 } bits; 401 } mii_mode_control_stat_t, *p_mode_control_stat_t; 402 403 #ifdef __cplusplus 404 } 405 #endif 406 407 #endif /* _SYS_NXGE_NXGE_MII_H_ */ 408