1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MAC_NXGE_MAC_HW_H 27 #define _SYS_MAC_NXGE_MAC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* -------------------------- From May's template --------------------------- */ 38 39 #define NXGE_1GETHERMIN 255 40 #define NXGE_ETHERMIN 97 41 #define NXGE_MAX_HEADER 250 42 43 /* Hardware reset */ 44 typedef enum { 45 NXGE_TX_DISABLE, /* Disable Tx side */ 46 NXGE_RX_DISABLE, /* Disable Rx side */ 47 NXGE_CHIP_RESET /* Full chip reset */ 48 } nxge_reset_t; 49 50 #define NXGE_DELAY_AFTER_TXRX 10000 /* 10ms after idling rx/tx */ 51 #define NXGE_DELAY_AFTER_RESET 1000 /* 1ms after the reset */ 52 #define NXGE_DELAY_AFTER_EE_RESET 10000 /* 10ms after EEPROM reset */ 53 #define NXGE_DELAY_AFTER_LINK_RESET 13 /* 13 Us after link reset */ 54 #define NXGE_LINK_RESETS 8 /* Max PHY resets to wait for */ 55 /* linkup */ 56 57 #define FILTER_M_CTL 0xDCEF1 58 #define HASH_BITS 8 59 #define NMCFILTER_BITS (1 << HASH_BITS) 60 #define HASH_REG_WIDTH 16 61 #define BROADCAST_HASH_WORD 0x0f 62 #define BROADCAST_HASH_BIT 0x8000 63 #define NMCFILTER_REGS NMCFILTER_BITS / HASH_REG_WIDTH 64 /* Number of multicast filter regs */ 65 66 /* -------------------------------------------------------------------------- */ 67 68 #define XMAC_PORT_0 0 69 #define XMAC_PORT_1 1 70 #define BMAC_PORT_0 2 71 #define BMAC_PORT_1 3 72 73 #define MAC_RESET_WAIT 10 /* usecs */ 74 75 #define MAC_ADDR_REG_MASK 0xFFFF 76 77 /* 78 * Neptune port PHY type and Speed encoding. 79 * 80 * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits 81 * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0 82 * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed 83 * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the 84 * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy 85 * type encoding for the ports 0 thru 3. 86 * 87 * p3phy p2phy p1phy p0phy p3spd p2spd p1spd p0spd 88 * | | | | | | | | 89 * --- --- --- --- --- --- --- --- 90 * / \ / \ / \ / \ / \ / \ / \ / \ 91 * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0 92 */ 93 94 #define NXGE_PORT_SPD_NONE 0x0 95 #define NXGE_PORT_SPD_1G 0x1 96 #define NXGE_PORT_SPD_10G 0x2 97 #define NXGE_PORT_SPD_RSVD 0x7 98 99 #define NXGE_PHY_NONE 0x0 100 #define NXGE_PHY_COPPER 0x1 101 #define NXGE_PHY_FIBRE 0x2 102 #define NXGE_PHY_SERDES 0x3 103 #define NXGE_PHY_RGMII_FIBER 0x4 104 #define NXGE_PHY_RSVD 0x7 105 106 #define NXGE_PORT_SPD_SHIFT 0 107 #define NXGE_PORT_SPD_MASK 0x0f 108 109 #define NXGE_PHY_SHIFT 16 110 #define NXGE_PHY_MASK 0x0f0000 111 112 #define NXGE_PORT_1G_COPPER (NXGE_PORT_SPD_1G | \ 113 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 114 #define NXGE_PORT_10G_COPPER (NXGE_PORT_SPD_10G | \ 115 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 116 #define NXGE_PORT_1G_FIBRE (NXGE_PORT_SPD_1G | \ 117 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 118 #define NXGE_PORT_10G_FIBRE (NXGE_PORT_SPD_10G | \ 119 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 120 #define NXGE_PORT_1G_SERDES (NXGE_PORT_SPD_1G | \ 121 (NXGE_PHY_SERDES << NXGE_PHY_SHIFT)) 122 #define NXGE_PORT_10G_SERDES (NXGE_PORT_SPD_10G | \ 123 (NXGE_PHY_SERDES << NXGE_PHY_SHIFT)) 124 #define NXGE_PORT_1G_RGMII_FIBER (NXGE_PORT_SPD_1G | \ 125 (NXGE_PHY_RGMII_FIBER << NXGE_PHY_SHIFT)) 126 #define NXGE_PORT_NONE (NXGE_PORT_SPD_NONE | \ 127 (NXGE_PHY_NONE << NXGE_PHY_SHIFT)) 128 #define NXGE_PORT_RSVD (NXGE_PORT_SPD_RSVD | \ 129 (NXGE_PHY_RSVD << NXGE_PHY_SHIFT)) 130 131 #define NXGE_PORT_TYPE_MASK (NXGE_PORT_SPD_MASK | NXGE_PHY_MASK) 132 133 /* number of bits used for phy/spd encoding per port */ 134 #define NXGE_PORT_TYPE_SHIFT 4 135 136 /* Network Modes */ 137 138 typedef enum nxge_network_mode { 139 NET_2_10GE_FIBER = 1, 140 NET_2_10GE_COPPER, 141 NET_1_10GE_FIBER_3_1GE_COPPER, 142 NET_1_10GE_COPPER_3_1GE_COPPER, 143 NET_1_10GE_FIBER_3_1GE_FIBER, 144 NET_1_10GE_COPPER_3_1GE_FIBER, 145 NET_2_1GE_FIBER_2_1GE_COPPER, 146 NET_QGE_FIBER, 147 NET_QGE_COPPER 148 } nxge_network_mode_t; 149 150 typedef enum nxge_port { 151 PORT_TYPE_XMAC = 1, 152 PORT_TYPE_BMAC 153 } nxge_port_t; 154 155 typedef enum nxge_port_mode { 156 PORT_1G_COPPER = 1, 157 PORT_1G_FIBER, 158 PORT_10G_COPPER, 159 PORT_10G_FIBER, 160 PORT_10G_SERDES, 161 PORT_1G_SERDES, 162 PORT_1G_RGMII_FIBER, 163 PORT_HSP_MODE 164 } nxge_port_mode_t; 165 166 typedef enum nxge_linkchk_mode { 167 LINKCHK_INTR = 1, 168 LINKCHK_TIMER 169 } nxge_linkchk_mode_t; 170 171 typedef enum { 172 LINK_INTR_STOP, 173 LINK_INTR_START 174 } link_intr_enable_t, *link_intr_enable_pt; 175 176 typedef enum { 177 LINK_MONITOR_STOP, 178 LINK_MONITOR_START, 179 LINK_MONITOR_STOPPING 180 } link_mon_enable_t, *link_mon_enable_pt; 181 182 typedef enum { 183 NO_XCVR, 184 INT_MII_XCVR, 185 EXT_MII_XCVR, 186 PCS_XCVR, 187 XPCS_XCVR, 188 HSP_XCVR 189 } xcvr_inuse_t; 190 191 /* macros for port offset calculations */ 192 193 #define PORT_1_OFFSET 0x6000 194 #define PORT_GT_1_OFFSET 0x4000 195 196 /* XMAC address macros */ 197 198 #define XMAC_ADDR_OFFSET_0 0 199 #define XMAC_ADDR_OFFSET_1 0x6000 200 201 #define XMAC_ADDR_OFFSET(port_num)\ 202 (XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 203 204 #define XMAC_REG_ADDR(port_num, reg)\ 205 (FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg)) 206 207 #define XMAC_PORT_ADDR(port_num)\ 208 (FZC_MAC + XMAC_ADDR_OFFSET(port_num)) 209 210 /* BMAC address macros */ 211 212 #define BMAC_ADDR_OFFSET_2 0x0C000 213 #define BMAC_ADDR_OFFSET_3 0x10000 214 215 #define BMAC_ADDR_OFFSET(port_num)\ 216 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 217 218 #define BMAC_REG_ADDR(port_num, reg)\ 219 (FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg)) 220 221 #define BMAC_PORT_ADDR(port_num)\ 222 (FZC_MAC + BMAC_ADDR_OFFSET(port_num)) 223 224 /* PCS address macros */ 225 226 #define PCS_ADDR_OFFSET_0 0x04000 227 #define PCS_ADDR_OFFSET_1 0x0A000 228 #define PCS_ADDR_OFFSET_2 0x0E000 229 #define PCS_ADDR_OFFSET_3 0x12000 230 231 #define PCS_ADDR_OFFSET(port_num)\ 232 ((port_num <= 1) ? \ 233 (PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \ 234 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 235 236 #define PCS_REG_ADDR(port_num, reg)\ 237 (FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg))) 238 239 #define PCS_PORT_ADDR(port_num)\ 240 (FZC_MAC + (PCS_ADDR_OFFSET(port_num))) 241 242 /* XPCS address macros */ 243 244 #define XPCS_ADDR_OFFSET_0 0x02000 245 #define XPCS_ADDR_OFFSET_1 0x08000 246 #define XPCS_ADDR_OFFSET(port_num)\ 247 (XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 248 249 #define XPCS_ADDR(port_num, reg)\ 250 (FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg))) 251 252 #define XPCS_PORT_ADDR(port_num)\ 253 (FZC_MAC + (XPCS_ADDR_OFFSET(port_num))) 254 255 /* ESR address macro */ 256 #define ESR_ADDR_OFFSET 0x14000 257 #define ESR_ADDR(reg)\ 258 (FZC_MAC + (ESR_ADDR_OFFSET) + (reg)) 259 260 /* MIF address macros */ 261 #define MIF_ADDR_OFFSET 0x16000 262 #define MIF_ADDR(reg)\ 263 (FZC_MAC + (MIF_ADDR_OFFSET) + (reg)) 264 265 /* BMAC registers offset */ 266 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ 267 #define BRXMAC_SW_RST_REG 0x008 /* RX MAC software reset */ 268 #define MAC_SEND_PAUSE_REG 0x010 /* send pause command */ 269 #define BTXMAC_STATUS_REG 0x020 /* TX MAC status */ 270 #define BRXMAC_STATUS_REG 0x028 /* RX MAC status */ 271 #define BMAC_CTRL_STAT_REG 0x030 /* MAC control status */ 272 #define BTXMAC_STAT_MSK_REG 0x040 /* TX MAC mask */ 273 #define BRXMAC_STAT_MSK_REG 0x048 /* RX MAC mask */ 274 #define BMAC_C_S_MSK_REG 0x050 /* MAC control mask */ 275 #define TXMAC_CONFIG_REG 0x060 /* TX MAC config */ 276 /* cfg register bitmap */ 277 278 typedef union _btxmac_config_t { 279 uint64_t value; 280 281 struct { 282 #if defined(_BIG_ENDIAN) 283 uint32_t msw; /* Most significant word */ 284 uint32_t lsw; /* Least significant word */ 285 #elif defined(_LITTLE_ENDIAN) 286 uint32_t lsw; /* Least significant word */ 287 uint32_t msw; /* Most significant word */ 288 #endif 289 } val; 290 struct { 291 #if defined(_BIG_ENDIAN) 292 uint32_t w1; 293 #endif 294 struct { 295 #if defined(_BIT_FIELDS_HTOL) 296 uint32_t rsrvd : 22; 297 uint32_t hdx_ctrl2 : 1; 298 uint32_t no_fcs : 1; 299 uint32_t hdx_ctrl : 7; 300 uint32_t txmac_enable : 1; 301 #elif defined(_BIT_FIELDS_LTOH) 302 uint32_t txmac_enable : 1; 303 uint32_t hdx_ctrl : 7; 304 uint32_t no_fcs : 1; 305 uint32_t hdx_ctrl2 : 1; 306 uint32_t rsrvd : 22; 307 #endif 308 } w0; 309 310 #if defined(_LITTLE_ENDIAN) 311 uint32_t w1; 312 #endif 313 } bits; 314 } btxmac_config_t, *p_btxmac_config_t; 315 316 #define RXMAC_CONFIG_REG 0x068 /* RX MAC config */ 317 318 typedef union _brxmac_config_t { 319 uint64_t value; 320 321 struct { 322 #if defined(_BIG_ENDIAN) 323 uint32_t msw; /* Most significant word */ 324 uint32_t lsw; /* Least significant word */ 325 #elif defined(_LITTLE_ENDIAN) 326 uint32_t lsw; /* Least significant word */ 327 uint32_t msw; /* Most significant word */ 328 #endif 329 } val; 330 struct { 331 #if defined(_BIG_ENDIAN) 332 uint32_t w1; 333 #endif 334 struct { 335 #if defined(_BIT_FIELDS_HTOL) 336 uint32_t rsrvd : 20; 337 uint32_t mac_reg_sw_test : 2; 338 uint32_t mac2ipp_pkt_cnt_en : 1; 339 uint32_t rx_crs_extend_en : 1; 340 uint32_t error_chk_dis : 1; 341 uint32_t addr_filter_en : 1; 342 uint32_t hash_filter_en : 1; 343 uint32_t promiscuous_group : 1; 344 uint32_t promiscuous : 1; 345 uint32_t strip_fcs : 1; 346 uint32_t strip_pad : 1; 347 uint32_t rxmac_enable : 1; 348 #elif defined(_BIT_FIELDS_LTOH) 349 uint32_t rxmac_enable : 1; 350 uint32_t strip_pad : 1; 351 uint32_t strip_fcs : 1; 352 uint32_t promiscuous : 1; 353 uint32_t promiscuous_group : 1; 354 uint32_t hash_filter_en : 1; 355 uint32_t addr_filter_en : 1; 356 uint32_t error_chk_dis : 1; 357 uint32_t rx_crs_extend_en : 1; 358 uint32_t mac2ipp_pkt_cnt_en : 1; 359 uint32_t mac_reg_sw_test : 2; 360 uint32_t rsrvd : 20; 361 #endif 362 } w0; 363 364 #if defined(_LITTLE_ENDIAN) 365 uint32_t w1; 366 #endif 367 } bits; 368 } brxmac_config_t, *p_brxmac_config_t; 369 370 #define MAC_CTRL_CONFIG_REG 0x070 /* MAC control config */ 371 #define MAC_XIF_CONFIG_REG 0x078 /* XIF config */ 372 373 typedef union _bxif_config_t { 374 uint64_t value; 375 376 struct { 377 #if defined(_BIG_ENDIAN) 378 uint32_t msw; /* Most significant word */ 379 uint32_t lsw; /* Least significant word */ 380 #elif defined(_LITTLE_ENDIAN) 381 uint32_t lsw; /* Least significant word */ 382 uint32_t msw; /* Most significant word */ 383 #endif 384 } val; 385 struct { 386 #if defined(_BIG_ENDIAN) 387 uint32_t w1; 388 #endif 389 struct { 390 #if defined(_BIT_FIELDS_HTOL) 391 uint32_t rsrvd2 : 24; 392 uint32_t sel_clk_25mhz : 1; 393 uint32_t led_polarity : 1; 394 uint32_t force_led_on : 1; 395 uint32_t used : 1; 396 uint32_t gmii_mode : 1; 397 uint32_t rsrvd : 1; 398 uint32_t loopback : 1; 399 uint32_t tx_output_en : 1; 400 #elif defined(_BIT_FIELDS_LTOH) 401 uint32_t tx_output_en : 1; 402 uint32_t loopback : 1; 403 uint32_t rsrvd : 1; 404 uint32_t gmii_mode : 1; 405 uint32_t used : 1; 406 uint32_t force_led_on : 1; 407 uint32_t led_polarity : 1; 408 uint32_t sel_clk_25mhz : 1; 409 uint32_t rsrvd2 : 24; 410 #endif 411 } w0; 412 413 #if defined(_LITTLE_ENDIAN) 414 uint32_t w1; 415 #endif 416 } bits; 417 } bxif_config_t, *p_bxif_config_t; 418 419 #define BMAC_MIN_REG 0x0a0 /* min frame size */ 420 #define BMAC_MAX_REG 0x0a8 /* max frame size reg */ 421 #define MAC_PA_SIZE_REG 0x0b0 /* num of preamble bytes */ 422 #define MAC_CTRL_TYPE_REG 0x0c8 /* type field of MAC ctrl */ 423 #define BMAC_ADDR0_REG 0x100 /* MAC unique ad0 reg (HI 0) */ 424 #define BMAC_ADDR1_REG 0x108 /* MAC unique ad1 reg */ 425 #define BMAC_ADDR2_REG 0x110 /* MAC unique ad2 reg */ 426 #define BMAC_ADDR3_REG 0x118 /* MAC alt ad0 reg (HI 1) */ 427 #define BMAC_ADDR4_REG 0x120 /* MAC alt ad0 reg */ 428 #define BMAC_ADDR5_REG 0x128 /* MAC alt ad0 reg */ 429 #define BMAC_ADDR6_REG 0x130 /* MAC alt ad1 reg (HI 2) */ 430 #define BMAC_ADDR7_REG 0x138 /* MAC alt ad1 reg */ 431 #define BMAC_ADDR8_REG 0x140 /* MAC alt ad1 reg */ 432 #define BMAC_ADDR9_REG 0x148 /* MAC alt ad2 reg (HI 3) */ 433 #define BMAC_ADDR10_REG 0x150 /* MAC alt ad2 reg */ 434 #define BMAC_ADDR11_REG 0x158 /* MAC alt ad2 reg */ 435 #define BMAC_ADDR12_REG 0x160 /* MAC alt ad3 reg (HI 4) */ 436 #define BMAC_ADDR13_REG 0x168 /* MAC alt ad3 reg */ 437 #define BMAC_ADDR14_REG 0x170 /* MAC alt ad3 reg */ 438 #define BMAC_ADDR15_REG 0x178 /* MAC alt ad4 reg (HI 5) */ 439 #define BMAC_ADDR16_REG 0x180 /* MAC alt ad4 reg */ 440 #define BMAC_ADDR17_REG 0x188 /* MAC alt ad4 reg */ 441 #define BMAC_ADDR18_REG 0x190 /* MAC alt ad5 reg (HI 6) */ 442 #define BMAC_ADDR19_REG 0x198 /* MAC alt ad5 reg */ 443 #define BMAC_ADDR20_REG 0x1a0 /* MAC alt ad5 reg */ 444 #define BMAC_ADDR21_REG 0x1a8 /* MAC alt ad6 reg (HI 7) */ 445 #define BMAC_ADDR22_REG 0x1b0 /* MAC alt ad6 reg */ 446 #define BMAC_ADDR23_REG 0x1b8 /* MAC alt ad6 reg */ 447 #define MAC_FC_ADDR0_REG 0x268 /* FC frame addr0 (HI 0, p3) */ 448 #define MAC_FC_ADDR1_REG 0x270 /* FC frame addr1 */ 449 #define MAC_FC_ADDR2_REG 0x278 /* FC frame addr2 */ 450 #define MAC_ADDR_FILT0_REG 0x298 /* bits [47:32] (HI 0, p2) */ 451 #define MAC_ADDR_FILT1_REG 0x2a0 /* bits [31:16] */ 452 #define MAC_ADDR_FILT2_REG 0x2a8 /* bits [15:0] */ 453 #define MAC_ADDR_FILT12_MASK_REG 0x2b0 /* addr filter 2 & 1 mask */ 454 #define MAC_ADDR_FILT00_MASK_REG 0x2b8 /* addr filter 0 mask */ 455 #define MAC_HASH_TBL0_REG 0x2c0 /* hash table 0 reg */ 456 #define MAC_HASH_TBL1_REG 0x2c8 /* hash table 1 reg */ 457 #define MAC_HASH_TBL2_REG 0x2d0 /* hash table 2 reg */ 458 #define MAC_HASH_TBL3_REG 0x2d8 /* hash table 3 reg */ 459 #define MAC_HASH_TBL4_REG 0x2e0 /* hash table 4 reg */ 460 #define MAC_HASH_TBL5_REG 0x2e8 /* hash table 5 reg */ 461 #define MAC_HASH_TBL6_REG 0x2f0 /* hash table 6 reg */ 462 #define MAC_HASH_TBL7_REG 0x2f8 /* hash table 7 reg */ 463 #define MAC_HASH_TBL8_REG 0x300 /* hash table 8 reg */ 464 #define MAC_HASH_TBL9_REG 0x308 /* hash table 9 reg */ 465 #define MAC_HASH_TBL10_REG 0x310 /* hash table 10 reg */ 466 #define MAC_HASH_TBL11_REG 0x318 /* hash table 11 reg */ 467 #define MAC_HASH_TBL12_REG 0x320 /* hash table 12 reg */ 468 #define MAC_HASH_TBL13_REG 0x328 /* hash table 13 reg */ 469 #define MAC_HASH_TBL14_REG 0x330 /* hash table 14 reg */ 470 #define MAC_HASH_TBL15_REG 0x338 /* hash table 15 reg */ 471 #define RXMAC_FRM_CNT_REG 0x370 /* receive frame counter */ 472 #define MAC_LEN_ER_CNT_REG 0x378 /* length error counter */ 473 #define BMAC_AL_ER_CNT_REG 0x380 /* alignment error counter */ 474 #define BMAC_CRC_ER_CNT_REG 0x388 /* FCS error counter */ 475 #define BMAC_CD_VIO_CNT_REG 0x390 /* RX code violation err */ 476 #define BMAC_SM_REG 0x3a0 /* (ro) state machine reg */ 477 #define BMAC_ALTAD_CMPEN_REG 0x3f8 /* Alt addr compare enable */ 478 #define BMAC_HOST_INF0_REG 0x400 /* Host info */ 479 /* (own da, add filter, fc) */ 480 #define BMAC_HOST_INF1_REG 0x408 /* Host info (alt ad 0) */ 481 #define BMAC_HOST_INF2_REG 0x410 /* Host info (alt ad 1) */ 482 #define BMAC_HOST_INF3_REG 0x418 /* Host info (alt ad 2) */ 483 #define BMAC_HOST_INF4_REG 0x420 /* Host info (alt ad 3) */ 484 #define BMAC_HOST_INF5_REG 0x428 /* Host info (alt ad 4) */ 485 #define BMAC_HOST_INF6_REG 0x430 /* Host info (alt ad 5) */ 486 #define BMAC_HOST_INF7_REG 0x438 /* Host info (alt ad 6) */ 487 #define BMAC_HOST_INF8_REG 0x440 /* Host info (hash hit, miss) */ 488 #define BTXMAC_BYTE_CNT_REG 0x448 /* Tx byte count */ 489 #define BTXMAC_FRM_CNT_REG 0x450 /* frame count */ 490 #define BRXMAC_BYTE_CNT_REG 0x458 /* Rx byte count */ 491 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */ 492 #define BMAC_ALT_ADDR0N_REG_ADDR(x) (BMAC_ADDR3_REG + (x) * 24) 493 #define BMAC_ALT_ADDR1N_REG_ADDR(x) (BMAC_ADDR3_REG + 8 + (x) * 24) 494 #define BMAC_ALT_ADDR2N_REG_ADDR(x) (BMAC_ADDR3_REG + 0x10 + (x) * 24) 495 #define BMAC_HASH_TBLN_REG_ADDR(x) (MAC_HASH_TBL0_REG + (x) * 8) 496 #define BMAC_HOST_INFN_REG_ADDR(x) (BMAC_HOST_INF0_REG + (x) * 8) 497 498 /* XMAC registers offset */ 499 #define XTXMAC_SW_RST_REG 0x000 /* XTX MAC soft reset */ 500 #define XRXMAC_SW_RST_REG 0x008 /* XRX MAC soft reset */ 501 #define XTXMAC_STATUS_REG 0x020 /* XTX MAC status */ 502 #define XRXMAC_STATUS_REG 0x028 /* XRX MAC status */ 503 #define XMAC_CTRL_STAT_REG 0x030 /* Control / Status */ 504 #define XTXMAC_STAT_MSK_REG 0x040 /* XTX MAC Status mask */ 505 #define XRXMAC_STAT_MSK_REG 0x048 /* XRX MAC Status mask */ 506 #define XMAC_C_S_MSK_REG 0x050 /* Control / Status mask */ 507 #define XMAC_CONFIG_REG 0x060 /* Configuration */ 508 509 /* xmac config bit fields */ 510 typedef union _xmac_cfg_t { 511 uint64_t value; 512 513 struct { 514 #if defined(_BIG_ENDIAN) 515 uint32_t msw; /* Most significant word */ 516 uint32_t lsw; /* Least significant word */ 517 #elif defined(_LITTLE_ENDIAN) 518 uint32_t lsw; /* Least significant word */ 519 uint32_t msw; /* Most significant word */ 520 #endif 521 } val; 522 struct { 523 #if defined(_BIG_ENDIAN) 524 uint32_t w1; 525 #endif 526 struct { 527 #if defined(_BIT_FIELDS_HTOL) 528 uint32_t sel_clk_25mhz : 1; 529 uint32_t pcs_bypass : 1; 530 uint32_t xpcs_bypass : 1; 531 uint32_t mii_gmii_mode : 2; 532 uint32_t lfs_disable : 1; 533 uint32_t loopback : 1; 534 uint32_t tx_output_en : 1; 535 uint32_t sel_por_clk_src : 1; 536 uint32_t led_polarity : 1; 537 uint32_t force_led_on : 1; 538 uint32_t pass_fctl_frames : 1; 539 uint32_t recv_pause_en : 1; 540 uint32_t mac2ipp_pkt_cnt_en : 1; 541 uint32_t strip_crc : 1; 542 uint32_t addr_filter_en : 1; 543 uint32_t hash_filter_en : 1; 544 uint32_t code_viol_chk_dis : 1; 545 uint32_t reserved_mcast : 1; 546 uint32_t rx_crc_chk_dis : 1; 547 uint32_t error_chk_dis : 1; 548 uint32_t promisc_grp : 1; 549 uint32_t promiscuous : 1; 550 uint32_t rx_mac_enable : 1; 551 uint32_t warning_msg_en : 1; 552 uint32_t used : 3; 553 uint32_t always_no_crc : 1; 554 uint32_t var_min_ipg_en : 1; 555 uint32_t strech_mode : 1; 556 uint32_t tx_enable : 1; 557 #elif defined(_BIT_FIELDS_LTOH) 558 uint32_t tx_enable : 1; 559 uint32_t strech_mode : 1; 560 uint32_t var_min_ipg_en : 1; 561 uint32_t always_no_crc : 1; 562 uint32_t used : 3; 563 uint32_t warning_msg_en : 1; 564 uint32_t rx_mac_enable : 1; 565 uint32_t promiscuous : 1; 566 uint32_t promisc_grp : 1; 567 uint32_t error_chk_dis : 1; 568 uint32_t rx_crc_chk_dis : 1; 569 uint32_t reserved_mcast : 1; 570 uint32_t code_viol_chk_dis : 1; 571 uint32_t hash_filter_en : 1; 572 uint32_t addr_filter_en : 1; 573 uint32_t strip_crc : 1; 574 uint32_t mac2ipp_pkt_cnt_en : 1; 575 uint32_t recv_pause_en : 1; 576 uint32_t pass_fctl_frames : 1; 577 uint32_t force_led_on : 1; 578 uint32_t led_polarity : 1; 579 uint32_t sel_por_clk_src : 1; 580 uint32_t tx_output_en : 1; 581 uint32_t loopback : 1; 582 uint32_t lfs_disable : 1; 583 uint32_t mii_gmii_mode : 2; 584 uint32_t xpcs_bypass : 1; 585 uint32_t pcs_bypass : 1; 586 uint32_t sel_clk_25mhz : 1; 587 #endif 588 } w0; 589 590 #if defined(_LITTLE_ENDIAN) 591 uint32_t w1; 592 #endif 593 } bits; 594 } xmac_cfg_t, *p_xmac_cfg_t; 595 596 #define XMAC_IPG_REG 0x080 /* Inter-Packet-Gap */ 597 #define XMAC_MIN_REG 0x088 /* min frame size register */ 598 #define XMAC_MAX_REG 0x090 /* max frame/burst size */ 599 #define XMAC_ADDR0_REG 0x0a0 /* [47:32] of MAC addr (HI17) */ 600 #define XMAC_ADDR1_REG 0x0a8 /* [31:16] of MAC addr */ 601 #define XMAC_ADDR2_REG 0x0b0 /* [15:0] of MAC addr */ 602 #define XRXMAC_BT_CNT_REG 0x100 /* bytes received / 8 */ 603 #define XRXMAC_BC_FRM_CNT_REG 0x108 /* good BC frames received */ 604 #define XRXMAC_MC_FRM_CNT_REG 0x110 /* good MC frames received */ 605 #define XRXMAC_FRAG_CNT_REG 0x118 /* frag frames rejected */ 606 #define XRXMAC_HIST_CNT1_REG 0x120 /* 64 bytes frames */ 607 #define XRXMAC_HIST_CNT2_REG 0x128 /* 65-127 bytes frames */ 608 #define XRXMAC_HIST_CNT3_REG 0x130 /* 128-255 bytes frames */ 609 #define XRXMAC_HIST_CNT4_REG 0x138 /* 256-511 bytes frames */ 610 #define XRXMAC_HIST_CNT5_REG 0x140 /* 512-1023 bytes frames */ 611 #define XRXMAC_HIST_CNT6_REG 0x148 /* 1024-1522 bytes frames */ 612 #define XRXMAC_MPSZER_CNT_REG 0x150 /* frames > maxframesize */ 613 #define XRXMAC_CRC_ER_CNT_REG 0x158 /* frames failed CRC */ 614 #define XRXMAC_CD_VIO_CNT_REG 0x160 /* frames with code vio */ 615 #define XRXMAC_AL_ER_CNT_REG 0x168 /* frames with align error */ 616 #define XTXMAC_FRM_CNT_REG 0x170 /* tx frames */ 617 #define XTXMAC_BYTE_CNT_REG 0x178 /* tx bytes / 8 */ 618 #define XMAC_LINK_FLT_CNT_REG 0x180 /* link faults */ 619 #define XRXMAC_HIST_CNT7_REG 0x188 /* MAC2IPP/>1523 bytes frames */ 620 #define XMAC_SM_REG 0x1a8 /* State machine */ 621 #define XMAC_INTERN1_REG 0x1b0 /* internal signals for diag */ 622 #define XMAC_INTERN2_REG 0x1b8 /* internal signals for diag */ 623 #define XMAC_ADDR_CMPEN_REG 0x208 /* alt MAC addr check */ 624 #define XMAC_ADDR3_REG 0x218 /* alt MAC addr 0 (HI 0) */ 625 #define XMAC_ADDR4_REG 0x220 /* alt MAC addr 0 */ 626 #define XMAC_ADDR5_REG 0x228 /* alt MAC addr 0 */ 627 #define XMAC_ADDR6_REG 0x230 /* alt MAC addr 1 (HI 1) */ 628 #define XMAC_ADDR7_REG 0x238 /* alt MAC addr 1 */ 629 #define XMAC_ADDR8_REG 0x240 /* alt MAC addr 1 */ 630 #define XMAC_ADDR9_REG 0x248 /* alt MAC addr 2 (HI 2) */ 631 #define XMAC_ADDR10_REG 0x250 /* alt MAC addr 2 */ 632 #define XMAC_ADDR11_REG 0x258 /* alt MAC addr 2 */ 633 #define XMAC_ADDR12_REG 0x260 /* alt MAC addr 3 (HI 3) */ 634 #define XMAC_ADDR13_REG 0x268 /* alt MAC addr 3 */ 635 #define XMAC_ADDR14_REG 0x270 /* alt MAC addr 3 */ 636 #define XMAC_ADDR15_REG 0x278 /* alt MAC addr 4 (HI 4) */ 637 #define XMAC_ADDR16_REG 0x280 /* alt MAC addr 4 */ 638 #define XMAC_ADDR17_REG 0x288 /* alt MAC addr 4 */ 639 #define XMAC_ADDR18_REG 0x290 /* alt MAC addr 5 (HI 5) */ 640 #define XMAC_ADDR19_REG 0x298 /* alt MAC addr 5 */ 641 #define XMAC_ADDR20_REG 0x2a0 /* alt MAC addr 5 */ 642 #define XMAC_ADDR21_REG 0x2a8 /* alt MAC addr 6 (HI 6) */ 643 #define XMAC_ADDR22_REG 0x2b0 /* alt MAC addr 6 */ 644 #define XMAC_ADDR23_REG 0x2b8 /* alt MAC addr 6 */ 645 #define XMAC_ADDR24_REG 0x2c0 /* alt MAC addr 7 (HI 7) */ 646 #define XMAC_ADDR25_REG 0x2c8 /* alt MAC addr 7 */ 647 #define XMAC_ADDR26_REG 0x2d0 /* alt MAC addr 7 */ 648 #define XMAC_ADDR27_REG 0x2d8 /* alt MAC addr 8 (HI 8) */ 649 #define XMAC_ADDR28_REG 0x2e0 /* alt MAC addr 8 */ 650 #define XMAC_ADDR29_REG 0x2e8 /* alt MAC addr 8 */ 651 #define XMAC_ADDR30_REG 0x2f0 /* alt MAC addr 9 (HI 9) */ 652 #define XMAC_ADDR31_REG 0x2f8 /* alt MAC addr 9 */ 653 #define XMAC_ADDR32_REG 0x300 /* alt MAC addr 9 */ 654 #define XMAC_ADDR33_REG 0x308 /* alt MAC addr 10 (HI 10) */ 655 #define XMAC_ADDR34_REG 0x310 /* alt MAC addr 10 */ 656 #define XMAC_ADDR35_REG 0x318 /* alt MAC addr 10 */ 657 #define XMAC_ADDR36_REG 0x320 /* alt MAC addr 11 (HI 11) */ 658 #define XMAC_ADDR37_REG 0x328 /* alt MAC addr 11 */ 659 #define XMAC_ADDR38_REG 0x330 /* alt MAC addr 11 */ 660 #define XMAC_ADDR39_REG 0x338 /* alt MAC addr 12 (HI 12) */ 661 #define XMAC_ADDR40_REG 0x340 /* alt MAC addr 12 */ 662 #define XMAC_ADDR41_REG 0x348 /* alt MAC addr 12 */ 663 #define XMAC_ADDR42_REG 0x350 /* alt MAC addr 13 (HI 13) */ 664 #define XMAC_ADDR43_REG 0x358 /* alt MAC addr 13 */ 665 #define XMAC_ADDR44_REG 0x360 /* alt MAC addr 13 */ 666 #define XMAC_ADDR45_REG 0x368 /* alt MAC addr 14 (HI 14) */ 667 #define XMAC_ADDR46_REG 0x370 /* alt MAC addr 14 */ 668 #define XMAC_ADDR47_REG 0x378 /* alt MAC addr 14 */ 669 #define XMAC_ADDR48_REG 0x380 /* alt MAC addr 15 (HI 15) */ 670 #define XMAC_ADDR49_REG 0x388 /* alt MAC addr 15 */ 671 #define XMAC_ADDR50_REG 0x390 /* alt MAC addr 15 */ 672 #define XMAC_ADDR_FILT0_REG 0x818 /* [47:32] addr filter (HI18) */ 673 #define XMAC_ADDR_FILT1_REG 0x820 /* [31:16] of addr filter */ 674 #define XMAC_ADDR_FILT2_REG 0x828 /* [15:0] of addr filter */ 675 #define XMAC_ADDR_FILT12_MASK_REG 0x830 /* addr filter 2 & 1 mask */ 676 #define XMAC_ADDR_FILT0_MASK_REG 0x838 /* addr filter 0 mask */ 677 #define XMAC_HASH_TBL0_REG 0x840 /* hash table 0 reg */ 678 #define XMAC_HASH_TBL1_REG 0x848 /* hash table 1 reg */ 679 #define XMAC_HASH_TBL2_REG 0x850 /* hash table 2 reg */ 680 #define XMAC_HASH_TBL3_REG 0x858 /* hash table 3 reg */ 681 #define XMAC_HASH_TBL4_REG 0x860 /* hash table 4 reg */ 682 #define XMAC_HASH_TBL5_REG 0x868 /* hash table 5 reg */ 683 #define XMAC_HASH_TBL6_REG 0x870 /* hash table 6 reg */ 684 #define XMAC_HASH_TBL7_REG 0x878 /* hash table 7 reg */ 685 #define XMAC_HASH_TBL8_REG 0x880 /* hash table 8 reg */ 686 #define XMAC_HASH_TBL9_REG 0x888 /* hash table 9 reg */ 687 #define XMAC_HASH_TBL10_REG 0x890 /* hash table 10 reg */ 688 #define XMAC_HASH_TBL11_REG 0x898 /* hash table 11 reg */ 689 #define XMAC_HASH_TBL12_REG 0x8a0 /* hash table 12 reg */ 690 #define XMAC_HASH_TBL13_REG 0x8a8 /* hash table 13 reg */ 691 #define XMAC_HASH_TBL14_REG 0x8b0 /* hash table 14 reg */ 692 #define XMAC_HASH_TBL15_REG 0x8b8 /* hash table 15 reg */ 693 #define XMAC_HOST_INF0_REG 0x900 /* Host info 0 (alt ad 0) */ 694 #define XMAC_HOST_INF1_REG 0x908 /* Host info 1 (alt ad 1) */ 695 #define XMAC_HOST_INF2_REG 0x910 /* Host info 2 (alt ad 2) */ 696 #define XMAC_HOST_INF3_REG 0x918 /* Host info 3 (alt ad 3) */ 697 #define XMAC_HOST_INF4_REG 0x920 /* Host info 4 (alt ad 4) */ 698 #define XMAC_HOST_INF5_REG 0x928 /* Host info 5 (alt ad 5) */ 699 #define XMAC_HOST_INF6_REG 0x930 /* Host info 6 (alt ad 6) */ 700 #define XMAC_HOST_INF7_REG 0x938 /* Host info 7 (alt ad 7) */ 701 #define XMAC_HOST_INF8_REG 0x940 /* Host info 8 (alt ad 8) */ 702 #define XMAC_HOST_INF9_REG 0x948 /* Host info 9 (alt ad 9) */ 703 #define XMAC_HOST_INF10_REG 0x950 /* Host info 10 (alt ad 10) */ 704 #define XMAC_HOST_INF11_REG 0x958 /* Host info 11 (alt ad 11) */ 705 #define XMAC_HOST_INF12_REG 0x960 /* Host info 12 (alt ad 12) */ 706 #define XMAC_HOST_INF13_REG 0x968 /* Host info 13 (alt ad 13) */ 707 #define XMAC_HOST_INF14_REG 0x970 /* Host info 14 (alt ad 14) */ 708 #define XMAC_HOST_INF15_REG 0x978 /* Host info 15 (alt ad 15) */ 709 #define XMAC_HOST_INF16_REG 0x980 /* Host info 16 (hash hit) */ 710 #define XMAC_HOST_INF17_REG 0x988 /* Host info 17 (own da) */ 711 #define XMAC_HOST_INF18_REG 0x990 /* Host info 18 (filter hit) */ 712 #define XMAC_HOST_INF19_REG 0x998 /* Host info 19 (fc hit) */ 713 #define XMAC_PA_DATA0_REG 0xb80 /* preamble [31:0] */ 714 #define XMAC_PA_DATA1_REG 0xb88 /* preamble [63:32] */ 715 #define XMAC_DEBUG_SEL_REG 0xb90 /* debug select */ 716 #define XMAC_TRAINING_VECT_REG 0xb98 /* training vector */ 717 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */ 718 #define XMAC_ALT_ADDR0N_REG_ADDR(x) (XMAC_ADDR3_REG + (x) * 24) 719 #define XMAC_ALT_ADDR1N_REG_ADDR(x) (XMAC_ADDR3_REG + 8 + (x) * 24) 720 #define XMAC_ALT_ADDR2N_REG_ADDR(x) (XMAC_ADDR3_REG + 16 + (x) * 24) 721 #define XMAC_HASH_TBLN_REG_ADDR(x) (XMAC_HASH_TBL0_REG + (x) * 8) 722 #define XMAC_HOST_INFN_REG_ADDR(x) (XMAC_HOST_INF0_REG + (x) * 8) 723 724 /* MIF registers offset */ 725 #define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */ 726 #define MIF_BB_MDO_REG 0x008 /* MIF bit-bang data */ 727 #define MIF_BB_MDO_EN_REG 0x010 /* MIF bit-bang output en */ 728 #define MIF_OUTPUT_FRAME_REG 0x018 /* MIF frame/output reg */ 729 #define MIF_CONFIG_REG 0x020 /* MIF config reg */ 730 #define MIF_POLL_STATUS_REG 0x028 /* MIF poll status reg */ 731 #define MIF_POLL_MASK_REG 0x030 /* MIF poll mask reg */ 732 #define MIF_STATE_MACHINE_REG 0x038 /* MIF state machine reg */ 733 #define MIF_STATUS_REG 0x040 /* MIF status reg */ 734 #define MIF_MASK_REG 0x048 /* MIF mask reg */ 735 736 737 /* PCS registers offset */ 738 #define PCS_MII_CTRL_REG 0 /* PCS MII control reg */ 739 #define PCS_MII_STATUS_REG 0x008 /* PCS MII status reg */ 740 #define PCS_MII_ADVERT_REG 0x010 /* PCS MII advertisement */ 741 #define PCS_MII_LPA_REG 0x018 /* link partner ability */ 742 #define PCS_CONFIG_REG 0x020 /* PCS config reg */ 743 #define PCS_STATE_MACHINE_REG 0x028 /* PCS state machine */ 744 #define PCS_INTR_STATUS_REG 0x030 /* PCS interrupt status */ 745 #define PCS_DATAPATH_MODE_REG 0x0a0 /* datapath mode reg */ 746 #define PCS_PACKET_COUNT_REG 0x0c0 /* PCS packet counter */ 747 748 #define XPCS_CTRL_1_REG 0 /* Control */ 749 #define XPCS_STATUS_1_REG 0x008 750 #define XPCS_DEV_ID_REG 0x010 /* 32bits IEEE manufacture ID */ 751 #define XPCS_SPEED_ABILITY_REG 0x018 752 #define XPCS_DEV_IN_PKG_REG 0x020 753 #define XPCS_CTRL_2_REG 0x028 754 #define XPCS_STATUS_2_REG 0x030 755 #define XPCS_PKG_ID_REG 0x038 /* Package ID */ 756 #define XPCS_STATUS_REG 0x040 757 #define XPCS_TEST_CTRL_REG 0x048 758 #define XPCS_CFG_VENDOR_1_REG 0x050 759 #define XPCS_DIAG_VENDOR_2_REG 0x058 760 #define XPCS_MASK_1_REG 0x060 761 #define XPCS_PKT_CNTR_REG 0x068 762 #define XPCS_TX_STATE_MC_REG 0x070 763 #define XPCS_DESKEW_ERR_CNTR_REG 0x078 764 #define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080 765 #define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088 766 #define XPCS_TRAINING_VECTOR_REG 0x090 767 768 /* ESR registers offset */ 769 #define ESR_RESET_REG 0 770 #define ESR_CONFIG_REG 0x008 771 #define ESR_0_PLL_CONFIG_REG 0x010 772 #define ESR_0_CONTROL_REG 0x018 773 #define ESR_0_TEST_CONFIG_REG 0x020 774 #define ESR_1_PLL_CONFIG_REG 0x028 775 #define ESR_1_CONTROL_REG 0x030 776 #define ESR_1_TEST_CONFIG_REG 0x038 777 #define ESR_ENET_RGMII_CFG_REG 0x040 778 #define ESR_INTERNAL_SIGNALS_REG 0x800 779 #define ESR_DEBUG_SEL_REG 0x808 780 781 782 /* Reset Register */ 783 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time */ 784 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl */ 785 786 /* Tx MAC Status Register */ 787 #define MAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 788 #define MAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 789 #define MAC_TX_MAX_PACKET_ERR 0x00000004 /* TX frame exceeds max */ 790 #define MAC_TX_BYTE_CNT_EXP 0x00000400 /* TX byte cnt overflow */ 791 #define MAC_TX_FRAME_CNT_EXP 0x00000800 /* Tx frame cnt overflow */ 792 793 /* Rx MAC Status Register */ 794 #define MAC_RX_FRAME_RECV 0x00000001 /* successful rx frame */ 795 #define MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 796 #define MAC_RX_FRAME_COUNT 0x00000004 /* rx frame cnt rollover */ 797 #define MAC_RX_ALIGN_ERR 0x00000008 /* alignment err rollover */ 798 #define MAC_RX_CRC_ERR 0x00000010 /* crc error cnt rollover */ 799 #define MAC_RX_LEN_ERR 0x00000020 /* length err cnt rollover */ 800 #define MAC_RX_VIOL_ERR 0x00000040 /* code vio err rollover */ 801 #define MAC_RX_BYTE_CNT_EXP 0x00000080 /* RX MAC byte rollover */ 802 803 /* MAC Control Status Register */ 804 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful pause frame */ 805 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 806 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 807 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 808 #define MAC_CTRL_PAUSE_TIME_SHIFT 16 809 810 /* Tx MAC Configuration Register */ 811 #define MAC_TX_CFG_TXMAC_ENABLE 0x00000001 /* enable TX MAC. */ 812 #define MAC_TX_CFG_NO_FCS 0x00000100 /* TX not generate CRC */ 813 814 /* Rx MAC Configuration Register */ 815 #define MAC_RX_CFG_RXMAC_ENABLE 0x00000001 /* enable RX MAC */ 816 #define MAC_RX_CFG_STRIP_PAD 0x00000002 /* not supported, set to 0 */ 817 #define MAC_RX_CFG_STRIP_FCS 0x00000004 /* strip last 4bytes (CRC) */ 818 #define MAC_RX_CFG_PROMISC 0x00000008 /* promisc mode enable */ 819 #define MAC_RX_CFG_PROMISC_GROUP 0x00000010 /* accept all MC frames */ 820 #define MAC_RX_CFG_HASH_FILTER_EN 0x00000020 /* use hash table */ 821 #define MAC_RX_CFG_ADDR_FILTER_EN 0x00000040 /* use address filter */ 822 #define MAC_RX_CFG_DISABLE_DISCARD 0x00000080 /* do not set abort bit */ 823 #define MAC_RX_MAC2IPP_PKT_CNT_EN 0x00000200 /* rx pkt cnt -> BMAC-IPP */ 824 #define MAC_RX_MAC_REG_RW_TEST_MASK 0x00000c00 /* BMAC reg RW test */ 825 #define MAC_RX_MAC_REG_RW_TEST_SHIFT 10 826 827 /* MAC Control Configuration Register */ 828 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x00000001 /* send pause flow ctrl */ 829 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x00000002 /* receive pause flow ctrl */ 830 #define MAC_CTRL_CFG_PASS_CTRL 0x00000004 /* accept MAC ctrl pkts */ 831 832 /* MAC XIF Configuration Register */ 833 #define MAC_XIF_TX_OUTPUT_EN 0x00000001 /* enable Tx output driver */ 834 #define MAC_XIF_MII_INT_LOOPBACK 0x00000002 /* loopback GMII xmit data */ 835 #define MAC_XIF_GMII_MODE 0x00000008 /* operates with GMII clks */ 836 #define MAC_XIF_LINK_LED 0x00000020 /* LINKLED# active (low) */ 837 #define MAC_XIF_LED_POLARITY 0x00000040 /* LED polarity */ 838 #define MAC_XIF_SEL_CLK_25MHZ 0x00000080 /* Select 10/100Mbps */ 839 840 /* MAC IPG Registers */ 841 #define BMAC_MIN_FRAME_MASK 0x3FF /* 10-bit reg */ 842 843 /* MAC Max Frame Size Register */ 844 #define BMAC_MAX_BURST_MASK 0x3FFF0000 /* max burst size [30:16] */ 845 #define BMAC_MAX_BURST_SHIFT 16 846 #define BMAC_MAX_FRAME_MASK 0x00007FFF /* max frame size [14:0] */ 847 #define BMAC_MAX_FRAME_SHIFT 0 848 849 /* MAC Preamble size register */ 850 #define BMAC_PA_SIZE_MASK 0x000003FF 851 /* # of preable bytes TxMAC sends at the beginning of each frame */ 852 853 /* 854 * mac address registers: 855 * register contains comparison 856 * -------- -------- ---------- 857 * 0 16 MSB of primary MAC addr [47:32] of DA field 858 * 1 16 middle bits "" [31:16] of DA field 859 * 2 16 LSB "" [15:0] of DA field 860 * 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field 861 * 4*x 16 middle bits "" [31:16] 862 * 5*x 16 LSB "" [15:0] 863 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 864 * 43 16 middle bits "" [31:16] 865 * 44 16 LSB "" [15:0] 866 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 867 * if there is a match, MAC will set the bit for alternative address 868 * filter pass [15] 869 * 870 * here is the map of registers given MAC address notation: a:b:c:d:e:f 871 * ab cd ef 872 * primary addr reg 2 reg 1 reg 0 873 * alt addr 1 reg 5 reg 4 reg 3 874 * alt addr x reg 5*x reg 4*x reg 3*x 875 * | | | | 876 * | | | | 877 * alt addr 7 reg 23 reg 22 reg 21 878 * ctrl addr reg 44 reg 43 reg 42 879 */ 880 881 #define BMAC_ALT_ADDR_BASE 0x118 882 #define BMAC_MAX_ALT_ADDR_ENTRY 7 /* 7 alternate MAC addr */ 883 #define BMAC_MAX_ADDR_ENTRY (BMAC_MAX_ALT_ADDR_ENTRY + 1) 884 885 /* hash table registers */ 886 #define MAC_MAX_HASH_ENTRY 16 887 888 /* 27-bit register has the current state for key state machines in the MAC */ 889 #define MAC_SM_RLM_MASK 0x07800000 890 #define MAC_SM_RLM_SHIFT 23 891 #define MAC_SM_RX_FC_MASK 0x00700000 892 #define MAC_SM_RX_FC_SHIFT 20 893 #define MAC_SM_TLM_MASK 0x000F0000 894 #define MAC_SM_TLM_SHIFT 16 895 #define MAC_SM_ENCAP_SM_MASK 0x0000F000 896 #define MAC_SM_ENCAP_SM_SHIFT 12 897 #define MAC_SM_TX_REQ_MASK 0x00000C00 898 #define MAC_SM_TX_REQ_SHIFT 10 899 #define MAC_SM_TX_FC_MASK 0x000003C0 900 #define MAC_SM_TX_FC_SHIFT 6 901 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 902 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 903 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 904 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 905 906 #define BMAC_ADDR0_CMPEN 0x00000001 907 #define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x)) 908 909 /* MAC Host Info Table Registers */ 910 #define BMAC_MAX_HOST_INFO_ENTRY 9 /* 9 host entries */ 911 912 /* 913 * ********************* XMAC registers ********************************* 914 */ 915 916 /* Reset Register */ 917 #define XTXMAC_SOFT_RST 0x00000001 /* XTX MAC software reset */ 918 #define XTXMAC_REG_RST 0x00000002 /* XTX MAC registers reset */ 919 #define XRXMAC_SOFT_RST 0x00000001 /* XRX MAC software reset */ 920 #define XRXMAC_REG_RST 0x00000002 /* XRX MAC registers reset */ 921 922 /* XTX MAC Status Register */ 923 #define XMAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 924 #define XMAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 925 #define XMAC_TX_MAX_PACKET_ERR 0x00000004 /* XTX frame exceeds max */ 926 #define XMAC_TX_OVERFLOW 0x00000008 /* XTX byte cnt overflow */ 927 #define XMAC_TX_FIFO_XFR_ERR 0x00000010 /* xtlm state mach error */ 928 #define XMAC_TX_BYTE_CNT_EXP 0x00000400 /* XTX byte cnt overflow */ 929 #define XMAC_TX_FRAME_CNT_EXP 0x00000800 /* XTX frame cnt overflow */ 930 931 /* XRX MAC Status Register */ 932 #define XMAC_RX_FRAME_RCVD 0x00000001 /* successful rx frame */ 933 #define XMAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 934 #define XMAC_RX_UNDERFLOW 0x00000004 /* RX FIFO underrun */ 935 #define XMAC_RX_CRC_ERR_CNT_EXP 0x00000008 /* crc error cnt rollover */ 936 #define XMAC_RX_LEN_ERR_CNT_EXP 0x00000010 /* length err cnt rollover */ 937 #define XMAC_RX_VIOL_ERR_CNT_EXP 0x00000020 /* code vio err rollover */ 938 #define XMAC_RX_OCT_CNT_EXP 0x00000040 /* XRX MAC byte rollover */ 939 #define XMAC_RX_HST_CNT1_EXP 0x00000080 /* XRX MAC hist1 rollover */ 940 #define XMAC_RX_HST_CNT2_EXP 0x00000100 /* XRX MAC hist2 rollover */ 941 #define XMAC_RX_HST_CNT3_EXP 0x00000200 /* XRX MAC hist3 rollover */ 942 #define XMAC_RX_HST_CNT4_EXP 0x00000400 /* XRX MAC hist4 rollover */ 943 #define XMAC_RX_HST_CNT5_EXP 0x00000800 /* XRX MAC hist5 rollover */ 944 #define XMAC_RX_HST_CNT6_EXP 0x00001000 /* XRX MAC hist6 rollover */ 945 #define XMAC_RX_BCAST_CNT_EXP 0x00002000 /* XRX BC cnt rollover */ 946 #define XMAC_RX_MCAST_CNT_EXP 0x00004000 /* XRX MC cnt rollover */ 947 #define XMAC_RX_FRAG_CNT_EXP 0x00008000 /* fragment cnt rollover */ 948 #define XMAC_RX_ALIGNERR_CNT_EXP 0x00010000 /* framealign err rollover */ 949 #define XMAC_RX_LINK_FLT_CNT_EXP 0x00020000 /* link fault cnt rollover */ 950 #define XMAC_RX_REMOTE_FLT_DET 0x00040000 /* Remote Fault detected */ 951 #define XMAC_RX_LOCAL_FLT_DET 0x00080000 /* Local Fault detected */ 952 #define XMAC_RX_HST_CNT7_EXP 0x00100000 /* XRX MAC hist7 rollover */ 953 954 955 #define XMAC_CTRL_PAUSE_RCVD 0x00000001 /* successful pause frame */ 956 #define XMAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 957 #define XMAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 958 #define XMAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 959 #define XMAC_CTRL_PAUSE_TIME_SHIFT 16 960 961 /* XMAC Configuration Register */ 962 #define XMAC_CONFIG_TX_BIT_MASK 0x000000ff /* bits [7:0] */ 963 #define XMAC_CONFIG_RX_BIT_MASK 0x001fff00 /* bits [20:8] */ 964 #define XMAC_CONFIG_XIF_BIT_MASK 0xffe00000 /* bits [31:21] */ 965 966 /* XTX MAC config bits */ 967 #define XMAC_TX_CFG_TX_ENABLE 0x00000001 /* enable XTX MAC */ 968 #define XMAC_TX_CFG_STRETCH_MD 0x00000002 /* WAN application */ 969 #define XMAC_TX_CFG_VAR_MIN_IPG_EN 0x00000004 /* Transmit pkts < minpsz */ 970 #define XMAC_TX_CFG_ALWAYS_NO_CRC 0x00000008 /* No CRC generated */ 971 972 #define XMAC_WARNING_MSG_ENABLE 0x00000080 /* Sim warning msg enable */ 973 974 /* XRX MAC config bits */ 975 #define XMAC_RX_CFG_RX_ENABLE 0x00000100 /* enable XRX MAC */ 976 #define XMAC_RX_CFG_PROMISC 0x00000200 /* promisc mode enable */ 977 #define XMAC_RX_CFG_PROMISC_GROUP 0x00000400 /* accept all MC frames */ 978 #define XMAC_RX_CFG_ERR_CHK_DISABLE 0x00000800 /* do not set abort bit */ 979 #define XMAC_RX_CFG_CRC_CHK_DISABLE 0x00001000 /* disable CRC logic */ 980 #define XMAC_RX_CFG_RESERVED_MCAST 0x00002000 /* reserved MCaddr compare */ 981 #define XMAC_RX_CFG_CD_VIO_CHK 0x00004000 /* rx code violation chk */ 982 #define XMAC_RX_CFG_HASH_FILTER_EN 0x00008000 /* use hash table */ 983 #define XMAC_RX_CFG_ADDR_FILTER_EN 0x00010000 /* use alt addr filter */ 984 #define XMAC_RX_CFG_STRIP_CRC 0x00020000 /* strip last 4bytes (CRC) */ 985 #define XMAC_RX_MAC2IPP_PKT_CNT_EN 0x00040000 /* histo_cntr7 cnt mode */ 986 #define XMAC_RX_CFG_RX_PAUSE_EN 0x00080000 /* receive pause flow ctrl */ 987 #define XMAC_RX_CFG_PASS_FLOW_CTRL 0x00100000 /* accept MAC ctrl pkts */ 988 989 990 /* MAC transceiver (XIF) configuration registers */ 991 992 #define XMAC_XIF_FORCE_LED_ON 0x00200000 /* Force Link LED on */ 993 #define XMAC_XIF_LED_POLARITY 0x00400000 /* LED polarity */ 994 #define XMAC_XIF_SEL_POR_CLK_SRC 0x00800000 /* Select POR clk src */ 995 #define XMAC_XIF_TX_OUTPUT_EN 0x01000000 /* enable MII/GMII modes */ 996 #define XMAC_XIF_LOOPBACK 0x02000000 /* loopback xmac xgmii tx */ 997 #define XMAC_XIF_LFS_DISABLE 0x04000000 /* disable link fault sig */ 998 #define XMAC_XIF_MII_MODE_MASK 0x18000000 /* MII/GMII/XGMII mode */ 999 #define XMAC_XIF_MII_MODE_SHIFT 27 1000 #define XMAC_XIF_XGMII_MODE 0x00 1001 #define XMAC_XIF_GMII_MODE 0x01 1002 #define XMAC_XIF_MII_MODE 0x02 1003 #define XMAC_XIF_ILLEGAL_MODE 0x03 1004 #define XMAC_XIF_XPCS_BYPASS 0x20000000 /* use external xpcs */ 1005 #define XMAC_XIF_1G_PCS_BYPASS 0x40000000 /* use external pcs */ 1006 #define XMAC_XIF_SEL_CLK_25MHZ 0x80000000 /* 25Mhz clk for 100mbps */ 1007 1008 /* IPG register */ 1009 #define XMAC_IPG_VALUE_MASK 0x00000007 /* IPG in XGMII mode */ 1010 #define XMAC_IPG_VALUE_SHIFT 0 1011 #define XMAC_IPG_VALUE1_MASK 0x0000ff00 /* IPG in GMII/MII mode */ 1012 #define XMAC_IPG_VALUE1_SHIFT 8 1013 #define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000 1014 #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 1015 #define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000 1016 #define XMAC_IPG_STRETCH_CONST_SHIFT 21 1017 1018 #define IPG_12_15_BYTE 3 1019 #define IPG_16_19_BYTE 4 1020 #define IPG_20_23_BYTE 5 1021 #define IPG1_12_BYTES 10 1022 #define IPG1_13_BYTES 11 1023 #define IPG1_14_BYTES 12 1024 #define IPG1_15_BYTES 13 1025 #define IPG1_16_BYTES 14 1026 1027 1028 #define XMAC_MIN_TX_FRM_SZ_MASK 0x3ff /* Min tx frame size */ 1029 #define XMAC_MIN_TX_FRM_SZ_SHIFT 0 1030 #define XMAC_SLOT_TIME_MASK 0x0003fc00 /* slot time */ 1031 #define XMAC_SLOT_TIME_SHIFT 10 1032 #define XMAC_MIN_RX_FRM_SZ_MASK 0x3ff00000 /* Min rx frame size */ 1033 #define XMAC_MIN_RX_FRM_SZ_SHIFT 20 1034 #define XMAC_MAX_FRM_SZ_MASK 0x00003fff /* max tx frame size */ 1035 1036 /* State Machine Register */ 1037 #define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007 1038 #define XMAC_SM_TX_LNK_MGMT_SHIFT 0 1039 #define XMAC_SM_SOP_DETECT 0x00000008 1040 #define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030 1041 #define XMAC_SM_LNK_FLT_SIG_SHIFT 4 1042 #define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040 1043 #define XMAC_SM_XGMII_MD_RX_LNK 0x00000080 1044 #define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100 1045 #define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200 1046 #define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00 1047 #define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10 1048 #define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000 1049 #define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18 1050 #define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000 1051 #define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23 1052 #define XMAC_SM_TXFIFO_FULL_CLK 0x10000000 1053 #define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000 1054 #define XMAC_SM_RXFIFO_FULL_CLK 0x40000000 1055 #define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000 1056 1057 /* Internal Signals 1 Register */ 1058 #define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F 1059 #define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0 1060 #define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010 1061 #define XMAC_IS1_OPP_TXMAC_TAG 0x00000020 1062 #define XMAC_IS1_OPP_TXMAC_ACK 0x00000040 1063 #define XMAC_IS1_TXMAC_OPP_REQ 0x00000080 1064 #define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00 1065 #define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8 1066 #define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000 1067 #define XMAC_IS1_RXMAC_IPP_TAG 0x20000000 1068 #define XMAC_IS1_IPP_RXMAC_REQ 0x40000000 1069 #define XMAC_IS1_RXMAC_IPP_ACK 0x80000000 1070 1071 /* Internal Signals 2 Register */ 1072 #define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F 1073 #define XMAC_IS2_TX_HB_TIMER_SHIFT 0 1074 #define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0 1075 #define XMAC_IS2_RX_HB_TIMER_SHIFT 4 1076 #define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00 1077 #define XMAC_IS2_XPCS_RXC_SHIFT 8 1078 #define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000 1079 #define XMAC_IS2_XPCS_TXC_SHIFT 16 1080 #define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000 1081 #define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000 1082 1083 /* Register size masking */ 1084 1085 #define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF 1086 #define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF 1087 #define XRXMAC_CRC_ER_CNT_MASK 0x000000FF 1088 #define XRXMAC_MPSZER_CNT_MASK 0x000000FF 1089 #define XRXMAC_CD_VIO_CNT_MASK 0x000000FF 1090 #define XRXMAC_BT_CNT_MASK 0xFFFFFFFF 1091 #define XRXMAC_HIST_CNT1_MASK 0x001FFFFF 1092 #define XRXMAC_HIST_CNT2_MASK 0x001FFFFF 1093 #define XRXMAC_HIST_CNT3_MASK 0x000FFFFF 1094 #define XRXMAC_HIST_CNT4_MASK 0x0007FFFF 1095 #define XRXMAC_HIST_CNT5_MASK 0x0003FFFF 1096 #define XRXMAC_HIST_CNT6_MASK 0x0001FFFF 1097 #define XRXMAC_HIST_CNT7_MASK 0x07FFFFFF 1098 #define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF 1099 #define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF 1100 #define XRXMAC_FRAG_CNT_MASK 0x001FFFFF 1101 #define XRXMAC_AL_ER_CNT_MASK 0x000000FF 1102 #define XMAC_LINK_FLT_CNT_MASK 0x000000FF 1103 #define BTXMAC_FRM_CNT_MASK 0x001FFFFF 1104 #define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF 1105 #define RXMAC_FRM_CNT_MASK 0x0000FFFF 1106 #define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF 1107 #define BMAC_AL_ER_CNT_MASK 0x0000FFFF 1108 #define MAC_LEN_ER_CNT_MASK 0x0000FFFF 1109 #define BMAC_CRC_ER_CNT_MASK 0x0000FFFF 1110 #define BMAC_CD_VIO_CNT_MASK 0x0000FFFF 1111 #define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF 1112 #define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF 1113 #define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000 1114 #define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16 1115 #define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF 1116 #define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000 1117 #define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16 1118 1119 /* Alternate MAC address registers */ 1120 #define XMAC_MAX_ALT_ADDR_ENTRY 16 /* 16 alternate MAC addrs */ 1121 #define XMAC_MAX_ADDR_ENTRY (XMAC_MAX_ALT_ADDR_ENTRY + 1) 1122 1123 /* Max / Min parameters for Neptune MAC */ 1124 1125 #define MAC_MAX_ALT_ADDR_ENTRY XMAC_MAX_ALT_ADDR_ENTRY 1126 #define MAC_MAX_HOST_INFO_ENTRY XMAC_MAX_HOST_INFO_ENTRY 1127 1128 /* HostInfo entry for the unique MAC address */ 1129 #define XMAC_UNIQUE_HOST_INFO_ENTRY 17 1130 #define BMAC_UNIQUE_HOST_INFO_ENTRY 0 1131 1132 /* HostInfo entry for the multicat address */ 1133 #define XMAC_MULTI_HOST_INFO_ENTRY 16 1134 #define BMAC_MULTI_HOST_INFO_ENTRY 8 1135 1136 /* XMAC Host Info Register */ 1137 typedef union hostinfo { 1138 1139 uint64_t value; 1140 1141 struct { 1142 #if defined(_BIG_ENDIAN) 1143 uint32_t msw; /* Most significant word */ 1144 uint32_t lsw; /* Least significant word */ 1145 #elif defined(_LITTLE_ENDIAN) 1146 uint32_t lsw; /* Least significant word */ 1147 uint32_t msw; /* Most significant word */ 1148 #endif 1149 } val; 1150 struct { 1151 #if defined(_BIG_ENDIAN) 1152 uint32_t w1; 1153 #endif 1154 struct { 1155 #if defined(_BIT_FIELDS_HTOL) 1156 uint32_t reserved2 : 23; 1157 uint32_t mac_pref : 1; 1158 uint32_t reserved1 : 5; 1159 uint32_t rdc_tbl_num : 3; 1160 #elif defined(_BIT_FIELDS_LTOH) 1161 uint32_t rdc_tbl_num : 3; 1162 uint32_t reserved1 : 5; 1163 uint32_t mac_pref : 1; 1164 uint32_t reserved2 : 23; 1165 #endif 1166 } w0; 1167 1168 #if defined(_LITTLE_ENDIAN) 1169 uint32_t w1; 1170 #endif 1171 } bits; 1172 1173 } hostinfo_t; 1174 1175 typedef union hostinfo *hostinfo_pt; 1176 1177 #define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007 1178 #define XMAC_HI_MAC_PREF 0x00000100 1179 1180 #define XMAC_MAX_HOST_INFO_ENTRY 20 /* 20 host entries */ 1181 1182 /* 1183 * ******************** MIF registers ********************************* 1184 */ 1185 1186 /* 1187 * 32-bit register serves as an instruction register when the MIF is 1188 * programmed in frame mode. load this register w/ a valid instruction 1189 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1190 * execution completion. during a read operation, this register will also 1191 * contain the 16-bit data returned by the transceiver. unless specified 1192 * otherwise, fields are considered "don't care" when polling for 1193 * completion. 1194 */ 1195 1196 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame mask */ 1197 #define MIF_FRAME_ST_22 0x40000000 /* STart of frame, Cl 22 */ 1198 #define MIF_FRAME_ST_45 0x00000000 /* STart of frame, Cl 45 */ 1199 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode */ 1200 #define MIF_FRAME_OP_READ_22 0x20000000 /* read OPcode, Cl 22 */ 1201 #define MIF_FRAME_OP_WRITE_22 0x10000000 /* write OPcode, Cl 22 */ 1202 #define MIF_FRAME_OP_ADDR_45 0x00000000 /* addr of reg to access */ 1203 #define MIF_FRAME_OP_READ_45 0x30000000 /* read OPcode, Cl 45 */ 1204 #define MIF_FRAME_OP_WRITE_45 0x10000000 /* write OPcode, Cl 45 */ 1205 #define MIF_FRAME_OP_P_R_I_A_45 0x10000000 /* post-read-inc-addr */ 1206 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address mask */ 1207 #define MIF_FRAME_PHY_ADDR_SHIFT 23 1208 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* reg addr in Cl 22 */ 1209 /* dev addr in Cl 45 */ 1210 #define MIF_FRAME_REG_ADDR_SHIFT 18 1211 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. */ 1212 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. */ 1213 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload */ 1214 1215 /* Clause 45 frame field values */ 1216 #define FRAME45_ST 0 1217 #define FRAME45_OP_ADDR 0 1218 #define FRAME45_OP_WRITE 1 1219 #define FRAME45_OP_READ_INC 2 1220 #define FRAME45_OP_READ 3 1221 1222 typedef union _mif_frame_t { 1223 1224 uint64_t value; 1225 1226 struct { 1227 #if defined(_BIG_ENDIAN) 1228 uint32_t msw; /* Most significant word */ 1229 uint32_t lsw; /* Least significant word */ 1230 #elif defined(_LITTLE_ENDIAN) 1231 uint32_t lsw; /* Least significant word */ 1232 uint32_t msw; /* Most significant word */ 1233 #endif 1234 } val; 1235 struct { 1236 #if defined(_BIG_ENDIAN) 1237 uint32_t w1; 1238 #endif 1239 struct { 1240 #if defined(_BIT_FIELDS_HTOL) 1241 uint32_t st : 2; 1242 uint32_t op : 2; 1243 uint32_t phyad : 5; 1244 uint32_t regad : 5; 1245 uint32_t ta_msb : 1; 1246 uint32_t ta_lsb : 1; 1247 uint32_t data : 16; 1248 #elif defined(_BIT_FIELDS_LTOH) 1249 uint32_t data : 16; 1250 uint32_t ta_lsb : 1; 1251 uint32_t ta_msb : 1; 1252 uint32_t regad : 5; 1253 uint32_t phyad : 5; 1254 uint32_t op : 2; 1255 uint32_t st : 2; 1256 #endif 1257 } w0; 1258 1259 #if defined(_LITTLE_ENDIAN) 1260 uint32_t w1; 1261 #endif 1262 } bits; 1263 } mif_frame_t; 1264 1265 #define MIF_CFG_POLL_EN 0x00000008 /* enable polling */ 1266 #define MIF_CFG_BB_MODE 0x00000010 /* bit-bang mode */ 1267 #define MIF_CFG_POLL_REG_MASK 0x000003E0 /* reg addr to be polled */ 1268 #define MIF_CFG_POLL_REG_SHIFT 5 1269 #define MIF_CFG_POLL_PHY_MASK 0x00007C00 /* XCVR addr to be polled */ 1270 #define MIF_CFG_POLL_PHY_SHIFT 10 1271 #define MIF_CFG_INDIRECT_MODE 0x0000800 1272 /* used to decide if Cl 22 */ 1273 /* or Cl 45 frame is */ 1274 /* constructed. */ 1275 /* 1 = Clause 45,ST = '00' */ 1276 /* 0 = Clause 22,ST = '01' */ 1277 #define MIF_CFG_ATCE_GE_EN 0x00010000 /* Enable ATCA gigabit mode */ 1278 1279 typedef union _mif_cfg_t { 1280 1281 uint64_t value; 1282 1283 struct { 1284 #if defined(_BIG_ENDIAN) 1285 uint32_t msw; /* Most significant word */ 1286 uint32_t lsw; /* Least significant word */ 1287 1288 #elif defined(_LITTLE_ENDIAN) 1289 uint32_t lsw; /* Least significant word */ 1290 uint32_t msw; /* Most significant word */ 1291 #endif 1292 } val; 1293 struct { 1294 #if defined(_BIG_ENDIAN) 1295 uint32_t w1; 1296 #endif 1297 struct { 1298 #if defined(_BIT_FIELDS_HTOL) 1299 uint32_t res2 : 15; 1300 uint32_t atca_ge : 1; 1301 uint32_t indirect_md : 1; 1302 uint32_t phy_addr : 5; 1303 uint32_t reg_addr : 5; 1304 uint32_t bb_mode : 1; 1305 uint32_t poll_en : 1; 1306 uint32_t res1 : 2; 1307 uint32_t res : 1; 1308 #elif defined(_BIT_FIELDS_LTOH) 1309 uint32_t res : 1; 1310 uint32_t res1 : 2; 1311 uint32_t poll_en : 1; 1312 uint32_t bb_mode : 1; 1313 uint32_t reg_addr : 5; 1314 uint32_t phy_addr : 5; 1315 uint32_t indirect_md : 1; 1316 uint32_t atca_ge : 1; 1317 uint32_t res2 : 15; 1318 #endif 1319 } w0; 1320 1321 #if defined(_LITTLE_ENDIAN) 1322 uint32_t w1; 1323 #endif 1324 } bits; 1325 1326 } mif_cfg_t; 1327 1328 #define MIF_POLL_STATUS_DATA_MASK 0xffff0000 1329 #define MIF_POLL_STATUS_STAT_MASK 0x0000ffff 1330 1331 typedef union _mif_poll_stat_t { 1332 uint64_t value; 1333 1334 struct { 1335 #if defined(_BIG_ENDIAN) 1336 uint32_t msw; /* Most significant word */ 1337 uint32_t lsw; /* Least significant word */ 1338 #elif defined(_LITTLE_ENDIAN) 1339 uint32_t lsw; /* Least significant word */ 1340 uint32_t msw; /* Most significant word */ 1341 #endif 1342 } val; 1343 struct { 1344 #if defined(_BIG_ENDIAN) 1345 uint32_t w1; 1346 #endif 1347 struct { 1348 #if defined(_BIT_FIELDS_HTOL) 1349 uint16_t data; 1350 uint16_t status; 1351 #elif defined(_BIT_FIELDS_LTOH) 1352 uint16_t status; 1353 uint16_t data; 1354 #endif 1355 } w0; 1356 1357 #if defined(_LITTLE_ENDIAN) 1358 uint32_t w1; 1359 #endif 1360 } bits; 1361 } mif_poll_stat_t; 1362 1363 1364 #define MIF_POLL_MASK_MASK 0x0000ffff 1365 1366 typedef union _mif_poll_mask_t { 1367 uint64_t value; 1368 1369 struct { 1370 #if defined(_BIG_ENDIAN) 1371 uint32_t msw; /* Most significant word */ 1372 uint32_t lsw; /* Least significant word */ 1373 #elif defined(_LITTLE_ENDIAN) 1374 uint32_t lsw; /* Least significant word */ 1375 uint32_t msw; /* Most significant word */ 1376 #endif 1377 } val; 1378 struct { 1379 #if defined(_BIG_ENDIAN) 1380 uint32_t w1; 1381 #endif 1382 struct { 1383 #if defined(_BIT_FIELDS_HTOL) 1384 uint16_t rsvd; 1385 uint16_t mask; 1386 #elif defined(_BIT_FIELDS_LTOH) 1387 uint16_t mask; 1388 uint16_t rsvd; 1389 #endif 1390 } w0; 1391 1392 #if defined(_LITTLE_ENDIAN) 1393 uint32_t w1; 1394 #endif 1395 } bits; 1396 } mif_poll_mask_t; 1397 1398 #define MIF_STATUS_INIT_DONE_MASK 0x00000001 1399 #define MIF_STATUS_XGE_ERR0_MASK 0x00000002 1400 #define MIF_STATUS_XGE_ERR1_MASK 0x00000004 1401 #define MIF_STATUS_PEU_ERR_MASK 0x00000008 1402 #define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010 1403 #define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020 1404 1405 typedef union _mif_stat_t { 1406 uint64_t value; 1407 1408 struct { 1409 #if defined(_BIG_ENDIAN) 1410 uint32_t msw; /* Most significant word */ 1411 uint32_t lsw; /* Least significant word */ 1412 #elif defined(_LITTLE_ENDIAN) 1413 uint32_t lsw; /* Least significant word */ 1414 uint32_t msw; /* Most significant word */ 1415 #endif 1416 } val; 1417 struct { 1418 #if defined(_BIG_ENDIAN) 1419 uint32_t w1; 1420 #endif 1421 struct { 1422 #if defined(_BIT_FIELDS_HTOL) 1423 uint32_t rsvd:26; 1424 uint32_t ext_phy_intr_flag1:1; 1425 uint32_t ext_phy_intr_flag0:1; 1426 uint32_t peu_err:1; 1427 uint32_t xge_err1:1; 1428 uint32_t xge_err0:1; 1429 uint32_t mif_init_done_stat:1; 1430 1431 #elif defined(_BIT_FIELDS_LTOH) 1432 uint32_t mif_init_done_stat:1; 1433 uint32_t xge_err0:1; 1434 uint32_t xge_err1:1; 1435 uint32_t ext_phy_intr_flag0:1; 1436 uint32_t ext_phy_intr_flag1:1; 1437 uint32_t rsvd:26; 1438 #endif 1439 } w0; 1440 1441 #if defined(_LITTLE_ENDIAN) 1442 uint32_t w1; 1443 #endif 1444 } bits; 1445 } mif_stat_t; 1446 1447 /* MIF State Machine Register */ 1448 1449 #define MIF_SM_EXECUTION_MASK 0x0000003f /* execution state */ 1450 #define MIF_SM_EXECUTION_SHIFT 0 1451 #define MIF_SM_CONTROL_MASK 0x000001c0 /* control state */ 1452 #define MIF_SM_CONTROL_MASK_SHIFT 6 1453 #define MIF_SM_MDI 0x00000200 1454 #define MIF_SM_MDO 0x00000400 1455 #define MIF_SM_MDO_EN 0x00000800 1456 #define MIF_SM_MDC 0x00001000 1457 #define MIF_SM_MDI_0 0x00002000 1458 #define MIF_SM_MDI_1 0x00004000 1459 #define MIF_SM_MDI_2 0x00008000 1460 #define MIF_SM_PORT_ADDR_MASK 0x001f0000 1461 #define MIF_SM_PORT_ADDR_SHIFT 16 1462 #define MIF_SM_INT_SIG_MASK 0xffe00000 1463 #define MIF_SM_INT_SIG_SHIFT 21 1464 1465 1466 /* 1467 * ******************** PCS registers ********************************* 1468 */ 1469 1470 /* PCS Registers */ 1471 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on wr */ 1472 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal */ 1473 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. */ 1474 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. */ 1475 #define PCS_MII_ISOLATE 0x0400 /* read 0. ignored on wr */ 1476 #define PCS_MII_POWER_DOWN 0x0800 /* read 0. ignored on wr */ 1477 #define PCS_MII_AUTONEG_EN 0x1000 /* autonegotiation */ 1478 #define PCS_MII_10_100_SEL 0x2000 /* read 0. ignored on wr */ 1479 #define PCS_MII_RESET 0x8000 /* reset PCS. */ 1480 1481 typedef union _pcs_ctrl_t { 1482 uint64_t value; 1483 1484 struct { 1485 #if defined(_BIG_ENDIAN) 1486 uint32_t msw; /* Most significant word */ 1487 uint32_t lsw; /* Least significant word */ 1488 #elif defined(_LITTLE_ENDIAN) 1489 uint32_t lsw; /* Least significant word */ 1490 uint32_t msw; /* Most significant word */ 1491 #endif 1492 } val; 1493 struct { 1494 #if defined(_BIG_ENDIAN) 1495 uint32_t w1; 1496 #endif 1497 struct { 1498 #if defined(_BIT_FIELDS_HTOL) 1499 uint32_t res0 : 16; 1500 uint32_t reset : 1; 1501 uint32_t res1 : 1; 1502 uint32_t sel_10_100 : 1; 1503 uint32_t an_enable : 1; 1504 uint32_t pwr_down : 1; 1505 uint32_t isolate : 1; 1506 uint32_t restart_an : 1; 1507 uint32_t duplex : 1; 1508 uint32_t col_test : 1; 1509 uint32_t sel_1000 : 1; 1510 uint32_t res2 : 6; 1511 #elif defined(_BIT_FIELDS_LTOH) 1512 uint32_t res2 : 6; 1513 uint32_t sel_1000 : 1; 1514 uint32_t col_test : 1; 1515 uint32_t duplex : 1; 1516 uint32_t restart_an : 1; 1517 uint32_t isolate : 1; 1518 uint32_t pwr_down : 1; 1519 uint32_t an_enable : 1; 1520 uint32_t sel_10_100 : 1; 1521 uint32_t res1 : 1; 1522 uint32_t reset : 1; 1523 uint32_t res0 : 16; 1524 #endif 1525 } w0; 1526 1527 #if defined(_LITTLE_ENDIAN) 1528 uint32_t w1; 1529 #endif 1530 } bits; 1531 } pcs_ctrl_t; 1532 1533 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1534 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1535 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* link status */ 1536 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 */ 1537 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* remote fault detected */ 1538 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* auto-neg completed */ 1539 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* 1000 Base-X PHY */ 1540 1541 typedef union _pcs_stat_t { 1542 uint64_t value; 1543 1544 struct { 1545 #if defined(_BIG_ENDIAN) 1546 uint32_t msw; /* Most significant word */ 1547 uint32_t lsw; /* Least significant word */ 1548 #elif defined(_LITTLE_ENDIAN) 1549 uint32_t lsw; /* Least significant word */ 1550 uint32_t msw; /* Most significant word */ 1551 #endif 1552 } val; 1553 struct { 1554 #if defined(_BIG_ENDIAN) 1555 uint32_t w1; 1556 #endif 1557 struct { 1558 #if defined(_BIT_FIELDS_HTOL) 1559 uint32_t res0 : 23; 1560 uint32_t ext_stat : 1; 1561 uint32_t res1 : 2; 1562 uint32_t an_complete : 1; 1563 uint32_t remote_fault : 1; 1564 uint32_t an_able : 1; 1565 uint32_t link_stat : 1; 1566 uint32_t jabber_detect : 1; 1567 uint32_t ext_cap : 1; 1568 #elif defined(_BIT_FIELDS_LTOH) 1569 uint32_t ext_cap : 1; 1570 uint32_t jabber_detect : 1; 1571 uint32_t link_stat : 1; 1572 uint32_t an_able : 1; 1573 uint32_t remote_fault : 1; 1574 uint32_t an_complete : 1; 1575 uint32_t res1 : 2; 1576 uint32_t ext_stat : 1; 1577 uint32_t res0 : 23; 1578 #endif 1579 } w0; 1580 1581 #if defined(_LITTLE_ENDIAN) 1582 uint32_t w1; 1583 #endif 1584 } bits; 1585 } pcs_stat_t; 1586 1587 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex */ 1588 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex */ 1589 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE sym */ 1590 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE asym */ 1591 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault */ 1592 #define PCS_MII_ADVERT_RF_SHIFT 12 1593 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1594 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1595 1596 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1597 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1598 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1599 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1600 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1601 #define PCS_MII_LPA_RF_SHIFT PCS_MII_ADVERT_RF_SHIFT 1602 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1603 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1604 1605 typedef union _pcs_anar_t { 1606 uint64_t value; 1607 1608 struct { 1609 #if defined(_BIG_ENDIAN) 1610 uint32_t msw; /* Most significant word */ 1611 uint32_t lsw; /* Least significant word */ 1612 #elif defined(_LITTLE_ENDIAN) 1613 uint32_t lsw; /* Least significant word */ 1614 uint32_t msw; /* Most significant word */ 1615 #endif 1616 } val; 1617 struct { 1618 #if defined(_BIG_ENDIAN) 1619 uint32_t w1; 1620 #endif 1621 struct { 1622 #if defined(_BIT_FIELDS_HTOL) 1623 uint32_t res0 : 16; 1624 uint32_t next_page : 1; 1625 uint32_t ack : 1; 1626 uint32_t remote_fault : 2; 1627 uint32_t res1 : 3; 1628 uint32_t asm_pause : 1; 1629 uint32_t pause : 1; 1630 uint32_t half_duplex : 1; 1631 uint32_t full_duplex : 1; 1632 uint32_t res2 : 5; 1633 #elif defined(_BIT_FIELDS_LTOH) 1634 uint32_t res2 : 5; 1635 uint32_t full_duplex : 1; 1636 uint32_t half_duplex : 1; 1637 uint32_t pause : 1; 1638 uint32_t asm_pause : 1; 1639 uint32_t res1 : 3; 1640 uint32_t remore_fault : 2; 1641 uint32_t ack : 1; 1642 uint32_t next_page : 1; 1643 uint32_t res0 : 16; 1644 #endif 1645 } w0; 1646 1647 #if defined(_LITTLE_ENDIAN) 1648 uint32_t w1; 1649 #endif 1650 } bits; 1651 } pcs_anar_t, *p_pcs_anar_t; 1652 1653 #define PCS_CFG_EN 0x0001 /* enable PCS. */ 1654 #define PCS_CFG_SD_OVERRIDE 0x0002 1655 #define PCS_CFG_SD_ACTIVE_LOW 0x0004 /* sig detect active low */ 1656 #define PCS_CFG_JITTER_STUDY_MASK 0x0018 /* jitter measurements */ 1657 #define PCS_CFG_JITTER_STUDY_SHIFT 4 1658 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x0020 /* shortens autoneg timer */ 1659 #define PCS_CFG_MASK 0x0040 /* PCS global mask bit */ 1660 1661 typedef union _pcs_cfg_t { 1662 uint64_t value; 1663 1664 struct { 1665 #if defined(_BIG_ENDIAN) 1666 uint32_t msw; /* Most significant word */ 1667 uint32_t lsw; /* Least significant word */ 1668 #elif defined(_LITTLE_ENDIAN) 1669 uint32_t lsw; /* Least significant word */ 1670 uint32_t msw; /* Most significant word */ 1671 #endif 1672 } val; 1673 struct { 1674 #if defined(_BIG_ENDIAN) 1675 uint32_t w1; 1676 #endif 1677 struct { 1678 #if defined(_BIT_FIELDS_HTOL) 1679 uint32_t res0 : 25; 1680 uint32_t mask : 1; 1681 uint32_t override_10ms_timer : 1; 1682 uint32_t jitter_study : 2; 1683 uint32_t sig_det_a_low : 1; 1684 uint32_t sig_det_override : 1; 1685 uint32_t enable : 1; 1686 #elif defined(_BIT_FIELDS_LTOH) 1687 uint32_t enable : 1; 1688 uint32_t sig_det_override : 1; 1689 uint32_t sig_det_a_low : 1; 1690 uint32_t jitter_study : 2; 1691 uint32_t override_10ms_timer : 1; 1692 uint32_t mask : 1; 1693 uint32_t res0 : 25; 1694 #endif 1695 } w0; 1696 1697 #if defined(_LITTLE_ENDIAN) 1698 uint32_t w1; 1699 #endif 1700 } bits; 1701 } pcs_cfg_t, *p_pcs_cfg_t; 1702 1703 1704 /* used for diagnostic purposes. bits 20-22 autoclear on read */ 1705 #define PCS_SM_TX_STATE_MASK 0x0000000F /* Tx idle state mask */ 1706 #define PCS_SM_TX_STATE_SHIFT 0 1707 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* Rx idle state mask */ 1708 #define PCS_SM_RX_STATE_SHIFT 4 1709 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* loss of sync state mask */ 1710 #define PCS_SM_WORD_SYNC_STATE_SHIFT 8 1711 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* sequence detect */ 1712 #define PCS_SM_SEQ_DETECT_STATE_SHIFT 11 1713 #define PCS_SM_LINK_STATE_MASK 0x0001E000 /* link state */ 1714 #define PCS_SM_LINK_STATE_SHIFT 13 1715 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link */ 1716 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of sync */ 1717 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect fail */ 1718 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* receipt of breaklink */ 1719 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes initializing */ 1720 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable */ 1721 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not achieved */ 1722 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes */ 1723 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* linkpartner send C code */ 1724 1725 typedef union _pcs_stat_mc_t { 1726 uint64_t value; 1727 1728 struct { 1729 #if defined(_BIG_ENDIAN) 1730 uint32_t msw; /* Most significant word */ 1731 uint32_t lsw; /* Least significant word */ 1732 #elif defined(_LITTLE_ENDIAN) 1733 uint32_t lsw; /* Least significant word */ 1734 uint32_t msw; /* Most significant word */ 1735 #endif 1736 } val; 1737 struct { 1738 #if defined(_BIG_ENDIAN) 1739 uint32_t w1; 1740 #endif 1741 struct { 1742 #if defined(_BIT_FIELDS_HTOL) 1743 uint32_t res2 : 2; 1744 uint32_t lnk_dwn_ni : 1; 1745 uint32_t lnk_dwn_wc : 1; 1746 uint32_t lnk_dwn_ls : 1; 1747 uint32_t lnk_dwn_nc : 1; 1748 uint32_t lnk_dwn_ser : 1; 1749 uint32_t lnk_loss_bc : 1; 1750 uint32_t res1 : 1; 1751 uint32_t loss_sd : 1; 1752 uint32_t lnk_loss_sync : 1; 1753 uint32_t lnk_loss_c : 1; 1754 uint32_t res0 : 3; 1755 uint32_t link_cfg_stat : 4; 1756 uint32_t seq_detc_stat : 2; 1757 uint32_t word_sync : 3; 1758 uint32_t rx_ctrl : 4; 1759 uint32_t tx_ctrl : 4; 1760 #elif defined(_BIT_FIELDS_LTOH) 1761 uint32_t tx_ctrl : 4; 1762 uint32_t rx_ctrl : 4; 1763 uint32_t word_sync : 3; 1764 uint32_t seq_detc_stat : 2; 1765 uint32_t link_cfg_stat : 4; 1766 uint32_t res0 : 3; 1767 uint32_t lnk_loss_c : 1; 1768 uint32_t lnk_loss_sync : 1; 1769 uint32_t loss_sd : 1; 1770 uint32_t res1 : 1; 1771 uint32_t lnk_loss_bc : 1; 1772 uint32_t lnk_dwn_ser : 1; 1773 uint32_t lnk_dwn_nc : 1; 1774 uint32_t lnk_dwn_ls : 1; 1775 uint32_t lnk_dwn_wc : 1; 1776 uint32_t lnk_dwn_ni : 1; 1777 uint32_t res2 : 2; 1778 #endif 1779 } w0; 1780 1781 #if defined(_LITTLE_ENDIAN) 1782 uint32_t w1; 1783 #endif 1784 } bits; 1785 } pcs_stat_mc_t, *p_pcs_stat_mc_t; 1786 1787 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed */ 1788 1789 /* 1790 * control which network interface is used. no more than one bit should 1791 * be set. 1792 */ 1793 #define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */ 1794 #define PCS_DATAPATH_MODE_MII 0x00000002 /* GMII/RGMII is selected. */ 1795 1796 #define PCS_PACKET_COUNT_TX_MASK 0x000007FF /* pkts xmitted by PCS */ 1797 #define PCS_PACKET_COUNT_RX_MASK 0x07FF0000 /* pkts recvd by PCS */ 1798 #define PCS_PACKET_COUNT_RX_SHIFT 16 1799 1800 /* 1801 * ******************** XPCS registers ********************************* 1802 */ 1803 1804 /* XPCS Base 10G Control1 Register */ 1805 #define XPCS_CTRL1_RST 0x8000 /* Self clearing reset. */ 1806 #define XPCS_CTRL1_LOOPBK 0x4000 /* xpcs Loopback */ 1807 #define XPCS_CTRL1_SPEED_SEL_3 0x2000 /* 1 indicates 10G speed */ 1808 #define XPCS_CTRL1_LOW_PWR 0x0800 /* low power mode. */ 1809 #define XPCS_CTRL1_SPEED_SEL_1 0x0040 /* 1 indicates 10G speed */ 1810 #define XPCS_CTRL1_SPEED_SEL_0_MASK 0x003c /* 0 indicates 10G speed. */ 1811 #define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2 1812 1813 1814 1815 typedef union _xpcs_ctrl1_t { 1816 uint64_t value; 1817 1818 struct { 1819 #if defined(_BIG_ENDIAN) 1820 uint32_t msw; /* Most significant word */ 1821 uint32_t lsw; /* Least significant word */ 1822 #elif defined(_LITTLE_ENDIAN) 1823 uint32_t lsw; /* Least significant word */ 1824 uint32_t msw; /* Most significant word */ 1825 #endif 1826 } val; 1827 struct { 1828 #if defined(_BIG_ENDIAN) 1829 uint32_t w1; 1830 #endif 1831 struct { 1832 #if defined(_BIT_FIELDS_HTOL) 1833 uint32_t res3 : 16; 1834 uint32_t reset : 1; 1835 uint32_t csr_lb : 1; 1836 uint32_t csr_speed_sel3 : 1; 1837 uint32_t res2 : 1; 1838 uint32_t csr_low_pwr : 1; 1839 uint32_t res1 : 4; 1840 uint32_t csr_speed_sel1 : 1; 1841 uint32_t csr_speed_sel0 : 4; 1842 uint32_t res0 : 2; 1843 #elif defined(_BIT_FIELDS_LTOH) 1844 uint32_t res0 : 2; 1845 uint32_t csr_speed_sel0 : 4; 1846 uint32_t csr_speed_sel1 : 1; 1847 uint32_t res1 : 4; 1848 uint32_t csr_low_pwr : 1; 1849 uint32_t res2 : 1; 1850 uint32_t csr_speed_sel3 : 1; 1851 uint32_t csr_lb : 1; 1852 uint32_t reset : 1; 1853 uint32_t res3 : 16; 1854 #endif 1855 } w0; 1856 1857 #if defined(_LITTLE_ENDIAN) 1858 uint32_t w1; 1859 #endif 1860 } bits; 1861 } xpcs_ctrl1_t; 1862 1863 1864 /* XPCS Base 10G Status1 Register (Read Only) */ 1865 #define XPCS_STATUS1_FAULT 0x0080 1866 #define XPCS_STATUS1_RX_LINK_STATUS_UP 0x0004 /* Link status interrupt */ 1867 #define XPCS_STATUS1_LOW_POWER_ABILITY 0x0002 /* low power mode */ 1868 #define XPCS_STATUS_RX_LINK_STATUS_UP 0x1000 /* Link status interrupt */ 1869 1870 1871 typedef union _xpcs_stat1_t { 1872 uint64_t value; 1873 1874 struct { 1875 #if defined(_BIG_ENDIAN) 1876 uint32_t msw; /* Most significant word */ 1877 uint32_t lsw; /* Least significant word */ 1878 #elif defined(_LITTLE_ENDIAN) 1879 uint32_t lsw; /* Least significant word */ 1880 uint32_t msw; /* Most significant word */ 1881 #endif 1882 } val; 1883 struct { 1884 #if defined(_BIG_ENDIAN) 1885 uint32_t w1; 1886 #endif 1887 struct { 1888 #if defined(_BIT_FIELDS_HTOL) 1889 uint32_t res4 : 16; 1890 uint32_t res3 : 8; 1891 uint32_t csr_fault : 1; 1892 uint32_t res1 : 4; 1893 uint32_t csr_rx_link_stat : 1; 1894 uint32_t csr_low_pwr_ability : 1; 1895 uint32_t res0 : 1; 1896 #elif defined(_BIT_FIELDS_LTOH) 1897 uint32_t res0 : 1; 1898 uint32_t csr_low_pwr_ability : 1; 1899 uint32_t csr_rx_link_stat : 1; 1900 uint32_t res1 : 4; 1901 uint32_t csr_fault : 1; 1902 uint32_t res3 : 8; 1903 uint32_t res4 : 16; 1904 #endif 1905 } w0; 1906 1907 #if defined(_LITTLE_ENDIAN) 1908 uint32_t w1; 1909 #endif 1910 } bits; 1911 } xpcs_stat1_t; 1912 1913 1914 /* XPCS Base Speed Ability Register. Indicates 10G capability */ 1915 #define XPCS_SPEED_ABILITY_10_GIG 0x0001 1916 1917 1918 typedef union _xpcs_speed_ab_t { 1919 uint64_t value; 1920 1921 struct { 1922 #if defined(_BIG_ENDIAN) 1923 uint32_t msw; /* Most significant word */ 1924 uint32_t lsw; /* Least significant word */ 1925 #elif defined(_LITTLE_ENDIAN) 1926 uint32_t lsw; /* Least significant word */ 1927 uint32_t msw; /* Most significant word */ 1928 #endif 1929 } val; 1930 struct { 1931 #if defined(_BIG_ENDIAN) 1932 uint32_t w1; 1933 #endif 1934 struct { 1935 #if defined(_BIT_FIELDS_HTOL) 1936 uint32_t res1 : 16; 1937 uint32_t res0 : 15; 1938 uint32_t csr_10gig : 1; 1939 #elif defined(_BIT_FIELDS_LTOH) 1940 uint32_t csr_10gig : 1; 1941 uint32_t res0 : 15; 1942 uint32_t res1 : 16; 1943 #endif 1944 } w0; 1945 1946 #if defined(_LITTLE_ENDIAN) 1947 uint32_t w1; 1948 #endif 1949 } bits; 1950 } xpcs_speed_ab_t; 1951 1952 1953 /* XPCS Base 10G Devices in Package Register */ 1954 #define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000 1955 #define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000 1956 #define XPCS_DEV_IN_PKG_DTE_XS 0x00000020 1957 #define XPCS_DEV_IN_PKG_PHY_XS 0x00000010 1958 #define XPCS_DEV_IN_PKG_PCS 0x00000008 1959 #define XPCS_DEV_IN_PKG_WIS 0x00000004 1960 #define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002 1961 #define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000 1962 1963 1964 1965 typedef union _xpcs_dev_in_pkg_t { 1966 uint64_t value; 1967 1968 struct { 1969 #if defined(_BIG_ENDIAN) 1970 uint32_t msw; /* Most significant word */ 1971 uint32_t lsw; /* Least significant word */ 1972 #elif defined(_LITTLE_ENDIAN) 1973 uint32_t lsw; /* Least significant word */ 1974 uint32_t msw; /* Most significant word */ 1975 #endif 1976 } val; 1977 struct { 1978 #if defined(_BIG_ENDIAN) 1979 uint32_t w1; 1980 #endif 1981 struct { 1982 #if defined(_BIT_FIELDS_HTOL) 1983 uint32_t csr_vendor2 : 1; 1984 uint32_t csr_vendor1 : 1; 1985 uint32_t res1 : 14; 1986 uint32_t res0 : 10; 1987 uint32_t dte_xs : 1; 1988 uint32_t phy_xs : 1; 1989 uint32_t pcs : 1; 1990 uint32_t wis : 1; 1991 uint32_t pmd_pma : 1; 1992 uint32_t clause_22_reg : 1; 1993 #elif defined(_BIT_FIELDS_LTOH) 1994 uint32_t clause_22_reg : 1; 1995 uint32_t pmd_pma : 1; 1996 uint32_t wis : 1; 1997 uint32_t pcs : 1; 1998 uint32_t phy_xs : 1; 1999 uint32_t dte_xs : 1; 2000 uint32_t res0 : 10; 2001 uint32_t res1 : 14; 2002 uint32_t csr_vendor1 : 1; 2003 uint32_t csr_vendor2 : 1; 2004 #endif 2005 } w0; 2006 2007 #if defined(_LITTLE_ENDIAN) 2008 uint32_t w1; 2009 #endif 2010 } bits; 2011 } xpcs_dev_in_pkg_t; 2012 2013 2014 /* XPCS Base 10G Control2 Register */ 2015 #define XPCS_PSC_SEL_MASK 0x0003 2016 #define PSC_SEL_10G_BASE_X_PCS 0x0001 2017 2018 2019 typedef union _xpcs_ctrl2_t { 2020 uint64_t value; 2021 2022 struct { 2023 #if defined(_BIG_ENDIAN) 2024 uint32_t msw; /* Most significant word */ 2025 uint32_t lsw; /* Least significant word */ 2026 #elif defined(_LITTLE_ENDIAN) 2027 uint32_t lsw; /* Least significant word */ 2028 uint32_t msw; /* Most significant word */ 2029 #endif 2030 } val; 2031 struct { 2032 #if defined(_BIG_ENDIAN) 2033 uint32_t w1; 2034 #endif 2035 struct { 2036 #if defined(_BIT_FIELDS_HTOL) 2037 uint32_t res1 : 16; 2038 uint32_t res0 : 14; 2039 uint32_t csr_psc_sel : 2; 2040 #elif defined(_BIT_FIELDS_LTOH) 2041 uint32_t csr_psc_sel : 2; 2042 uint32_t res0 : 14; 2043 uint32_t res1 : 16; 2044 #endif 2045 } w0; 2046 2047 #if defined(_LITTLE_ENDIAN) 2048 uint32_t w1; 2049 #endif 2050 } bits; 2051 } xpcs_ctrl2_t; 2052 2053 2054 /* XPCS Base10G Status2 Register */ 2055 #define XPCS_STATUS2_DEV_PRESENT_MASK 0xc000 /* ?????? */ 2056 #define XPCS_STATUS2_TX_FAULT 0x0800 /* Fault on tx path */ 2057 #define XPCS_STATUS2_RX_FAULT 0x0400 /* Fault on rx path */ 2058 #define XPCS_STATUS2_TEN_GBASE_W 0x0004 /* 10G-Base-W */ 2059 #define XPCS_STATUS2_TEN_GBASE_X 0x0002 /* 10G-Base-X */ 2060 #define XPCS_STATUS2_TEN_GBASE_R 0x0001 /* 10G-Base-R */ 2061 2062 typedef union _xpcs_stat2_t { 2063 uint64_t value; 2064 2065 struct { 2066 #if defined(_BIG_ENDIAN) 2067 uint32_t msw; /* Most significant word */ 2068 uint32_t lsw; /* Least significant word */ 2069 #elif defined(_LITTLE_ENDIAN) 2070 uint32_t lsw; /* Least significant word */ 2071 uint32_t msw; /* Most significant word */ 2072 #endif 2073 } val; 2074 struct { 2075 #if defined(_BIG_ENDIAN) 2076 uint32_t w1; 2077 #endif 2078 struct { 2079 #if defined(_BIT_FIELDS_HTOL) 2080 uint32_t res2 : 16; 2081 uint32_t csr_dev_pres : 2; 2082 uint32_t res1 : 2; 2083 uint32_t csr_tx_fault : 1; 2084 uint32_t csr_rx_fault : 1; 2085 uint32_t res0 : 7; 2086 uint32_t ten_gbase_w : 1; 2087 uint32_t ten_gbase_x : 1; 2088 uint32_t ten_gbase_r : 1; 2089 #elif defined(_BIT_FIELDS_LTOH) 2090 uint32_t ten_gbase_r : 1; 2091 uint32_t ten_gbase_x : 1; 2092 uint32_t ten_gbase_w : 1; 2093 uint32_t res0 : 7; 2094 uint32_t csr_rx_fault : 1; 2095 uint32_t csr_tx_fault : 1; 2096 uint32_t res1 : 2; 2097 uint32_t csr_dev_pres : 2; 2098 uint32_t res2 : 16; 2099 #endif 2100 } w0; 2101 2102 #if defined(_LITTLE_ENDIAN) 2103 uint32_t w1; 2104 #endif 2105 } bits; 2106 } xpcs_stat2_t; 2107 2108 2109 2110 /* XPCS Base10G Status Register */ 2111 #define XPCS_STATUS_LANE_ALIGN 0x1000 /* 10GBaseX PCS rx lanes align */ 2112 #define XPCS_STATUS_PATTERN_TEST_ABLE 0x0800 /* able to generate patterns. */ 2113 #define XPCS_STATUS_LANE3_SYNC 0x0008 /* Lane 3 is synchronized */ 2114 #define XPCS_STATUS_LANE2_SYNC 0x0004 /* Lane 2 is synchronized */ 2115 #define XPCS_STATUS_LANE1_SYNC 0x0002 /* Lane 1 is synchronized */ 2116 #define XPCS_STATUS_LANE0_SYNC 0x0001 /* Lane 0 is synchronized */ 2117 2118 typedef union _xpcs_stat_t { 2119 uint64_t value; 2120 2121 struct { 2122 #if defined(_BIG_ENDIAN) 2123 uint32_t msw; /* Most significant word */ 2124 uint32_t lsw; /* Least significant word */ 2125 #elif defined(_LITTLE_ENDIAN) 2126 uint32_t lsw; /* Least significant word */ 2127 uint32_t msw; /* Most significant word */ 2128 #endif 2129 } val; 2130 struct { 2131 #if defined(_BIG_ENDIAN) 2132 uint32_t w1; 2133 #endif 2134 struct { 2135 #if defined(_BIT_FIELDS_HTOL) 2136 uint32_t res2 : 16; 2137 uint32_t res1 : 3; 2138 uint32_t csr_lane_align : 1; 2139 uint32_t csr_pattern_test_able : 1; 2140 uint32_t res0 : 7; 2141 uint32_t csr_lane3_sync : 1; 2142 uint32_t csr_lane2_sync : 1; 2143 uint32_t csr_lane1_sync : 1; 2144 uint32_t csr_lane0_sync : 1; 2145 #elif defined(_BIT_FIELDS_LTOH) 2146 uint32_t csr_lane0_sync : 1; 2147 uint32_t csr_lane1_sync : 1; 2148 uint32_t csr_lane2_sync : 1; 2149 uint32_t csr_lane3_sync : 1; 2150 uint32_t res0 : 7; 2151 uint32_t csr_pat_test_able : 1; 2152 uint32_t csr_lane_align : 1; 2153 uint32_t res1 : 3; 2154 uint32_t res2 : 16; 2155 #endif 2156 } w0; 2157 2158 #if defined(_LITTLE_ENDIAN) 2159 uint32_t w1; 2160 #endif 2161 } bits; 2162 } xpcs_stat_t; 2163 2164 /* XPCS Base10G Test Control Register */ 2165 #define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004 2166 #define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003 2167 #define TEST_PATTERN_HIGH_FREQ 0 2168 #define TEST_PATTERN_LOW_FREQ 1 2169 #define TEST_PATTERN_MIXED_FREQ 2 2170 2171 typedef union _xpcs_test_ctl_t { 2172 uint64_t value; 2173 2174 struct { 2175 #if defined(_BIG_ENDIAN) 2176 uint32_t msw; /* Most significant word */ 2177 uint32_t lsw; /* Least significant word */ 2178 #elif defined(_LITTLE_ENDIAN) 2179 uint32_t lsw; /* Least significant word */ 2180 uint32_t msw; /* Most significant word */ 2181 #endif 2182 } val; 2183 struct { 2184 #if defined(_BIG_ENDIAN) 2185 uint32_t w1; 2186 #endif 2187 struct { 2188 #if defined(_BIT_FIELDS_HTOL) 2189 uint32_t res1 : 16; 2190 uint32_t res0 : 13; 2191 uint32_t csr_tx_test_en : 1; 2192 uint32_t csr_test_pat_sel : 2; 2193 #elif defined(_BIT_FIELDS_LTOH) 2194 uint32_t csr_test_pat_sel : 2; 2195 uint32_t csr_tx_test_en : 1; 2196 uint32_t res0 : 13; 2197 uint32_t res1 : 16; 2198 #endif 2199 } w0; 2200 2201 #if defined(_LITTLE_ENDIAN) 2202 uint32_t w1; 2203 #endif 2204 } bits; 2205 } xpcs_test_ctl_t; 2206 2207 /* XPCS Base10G Diagnostic Register */ 2208 #define XPCS_DIAG_EB_ALIGN_ERR3 0x40 2209 #define XPCS_DIAG_EB_ALIGN_ERR2 0x20 2210 #define XPCS_DIAG_EB_ALIGN_ERR1 0x10 2211 #define XPCS_DIAG_EB_DESKEW_OK 0x08 2212 #define XPCS_DIAG_EB_ALIGN_DET3 0x04 2213 #define XPCS_DIAG_EB_ALIGN_DET2 0x02 2214 #define XPCS_DIAG_EB_ALIGN_DET1 0x01 2215 #define XPCS_DIAG_EB_DESKEW_LOSS 0 2216 2217 #define XPCS_DIAG_SYNC_3_INVALID 0x8 2218 #define XPCS_DIAG_SYNC_2_INVALID 0x4 2219 #define XPCS_DIAG_SYNC_1_INVALID 0x2 2220 #define XPCS_DIAG_SYNC_IN_SYNC 0x1 2221 #define XPCS_DIAG_SYNC_LOSS_SYNC 0 2222 2223 #define XPCS_RX_SM_RECEIVE_STATE 1 2224 #define XPCS_RX_SM_FAULT_STATE 0 2225 2226 typedef union _xpcs_diag_t { 2227 uint64_t value; 2228 2229 struct { 2230 #if defined(_BIG_ENDIAN) 2231 uint32_t msw; /* Most significant word */ 2232 uint32_t lsw; /* Least significant word */ 2233 #elif defined(_LITTLE_ENDIAN) 2234 uint32_t lsw; /* Least significant word */ 2235 uint32_t msw; /* Most significant word */ 2236 #endif 2237 } val; 2238 struct { 2239 #if defined(_BIG_ENDIAN) 2240 uint32_t w1; 2241 #endif 2242 struct { 2243 #if defined(_BIT_FIELDS_HTOL) 2244 uint32_t res1 : 7; 2245 uint32_t sync_sm_lane3 : 4; 2246 uint32_t sync_sm_lane2 : 4; 2247 uint32_t sync_sm_lane1 : 4; 2248 uint32_t sync_sm_lane0 : 4; 2249 uint32_t elastic_buffer_sm : 8; 2250 uint32_t receive_sm : 1; 2251 #elif defined(_BIT_FIELDS_LTOH) 2252 uint32_t receive_sm : 1; 2253 uint32_t elastic_buffer_sm : 8; 2254 uint32_t sync_sm_lane0 : 4; 2255 uint32_t sync_sm_lane1 : 4; 2256 uint32_t sync_sm_lane2 : 4; 2257 uint32_t sync_sm_lane3 : 4; 2258 uint32_t res1 : 7; 2259 #endif 2260 } w0; 2261 2262 #if defined(_LITTLE_ENDIAN) 2263 uint32_t w1; 2264 #endif 2265 } bits; 2266 } xpcs_diag_t; 2267 2268 /* XPCS Base10G Tx State Machine Register */ 2269 #define XPCS_TX_SM_SEND_UNDERRUN 0x9 2270 #define XPCS_TX_SM_SEND_RANDOM_Q 0x8 2271 #define XPCS_TX_SM_SEND_RANDOM_K 0x7 2272 #define XPCS_TX_SM_SEND_RANDOM_A 0x6 2273 #define XPCS_TX_SM_SEND_RANDOM_R 0x5 2274 #define XPCS_TX_SM_SEND_Q 0x4 2275 #define XPCS_TX_SM_SEND_K 0x3 2276 #define XPCS_TX_SM_SEND_A 0x2 2277 #define XPCS_TX_SM_SEND_SDP 0x1 2278 #define XPCS_TX_SM_SEND_DATA 0 2279 2280 /* XPCS Base10G Configuration Register */ 2281 #define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78 2282 #define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3 2283 #define XPCS_CFG_BYPASS_SIG_DETECT 0x0004 2284 #define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002 2285 #define XPCS_CFG_XPCS_ENABLE 0x0001 2286 2287 typedef union _xpcs_config_t { 2288 uint64_t value; 2289 2290 struct { 2291 #if defined(_BIG_ENDIAN) 2292 uint32_t msw; /* Most significant word */ 2293 uint32_t lsw; /* Least significant word */ 2294 #elif defined(_LITTLE_ENDIAN) 2295 uint32_t lsw; /* Least significant word */ 2296 uint32_t msw; /* Most significant word */ 2297 #endif 2298 } val; 2299 struct { 2300 #if defined(_BIG_ENDIAN) 2301 uint32_t w1; 2302 #endif 2303 struct { 2304 #if defined(_BIT_FIELDS_HTOL) 2305 uint32_t res1 : 16; 2306 uint32_t res0 : 9; 2307 uint32_t csr_vendor_dbg_sel : 4; 2308 uint32_t csr_bypass_sig_detect : 1; 2309 uint32_t csr_en_tx_buf : 1; 2310 uint32_t csr_xpcs_en : 1; 2311 #elif defined(_BIT_FIELDS_LTOH) 2312 uint32_t csr_xpcs_en : 1; 2313 uint32_t csr_en_tx_buf : 1; 2314 uint32_t csr_bypass_sig_detect : 1; 2315 uint32_t csr_vendor_dbg_sel : 4; 2316 uint32_t res0 : 9; 2317 uint32_t res1 : 16; 2318 #endif 2319 } w0; 2320 2321 #if defined(_LITTLE_ENDIAN) 2322 uint32_t w1; 2323 #endif 2324 } bits; 2325 } xpcs_config_t; 2326 2327 2328 2329 /* XPCS Base10G Mask1 Register */ 2330 #define XPCS_MASK1_FAULT_MASK 0x0080 /* mask fault interrupt. */ 2331 #define XPCS_MASK1_RX_LINK_STATUS_MASK 0x0040 /* mask linkstat interrupt */ 2332 2333 /* XPCS Base10G Packet Counter */ 2334 #define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000 2335 #define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16 2336 #define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff 2337 #define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0 2338 2339 /* XPCS Base10G TX State Machine status register */ 2340 #define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f 2341 #define XPCS_DESKEW_ERR_CNTR_MASK 0xff 2342 2343 /* XPCS Base10G Lane symbol error counters */ 2344 #define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000 2345 #define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff 2346 #define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000 2347 #define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff 2348 2349 #define XPCS_SYM_ERR_CNT_MULTIPLIER 16 2350 2351 /* ESR Reset Register */ 2352 #define ESR_RESET_1 2 2353 #define ESR_RESET_0 1 2354 2355 /* ESR Configuration Register */ 2356 #define ESR_BLUNT_END_LOOPBACK 2 2357 #define ESR_FORCE_SERDES_SERDES_RDY 1 2358 2359 /* ESR Neptune Serdes PLL Configuration */ 2360 #define ESR_PLL_CFG_FBDIV_0 0x1 2361 #define ESR_PLL_CFG_FBDIV_1 0x2 2362 #define ESR_PLL_CFG_FBDIV_2 0x4 2363 #define ESR_PLL_CFG_HALF_RATE_0 0x8 2364 #define ESR_PLL_CFG_HALF_RATE_1 0x10 2365 #define ESR_PLL_CFG_HALF_RATE_2 0x20 2366 #define ESR_PLL_CFG_HALF_RATE_3 0x40 2367 #define ESR_PLL_CFG_1G_SERDES (ESR_PLL_CFG_FBDIV_0 | \ 2368 ESR_PLL_CFG_HALF_RATE_0 | \ 2369 ESR_PLL_CFG_HALF_RATE_1 | \ 2370 ESR_PLL_CFG_HALF_RATE_2 | \ 2371 ESR_PLL_CFG_HALF_RATE_3) 2372 2373 #define ESR_PLL_CFG_10G_SERDES ESR_PLL_CFG_FBDIV_2 2374 2375 /* ESR Neptune Serdes Control Register */ 2376 #define ESR_CTL_EN_SYNCDET_0 0x00000001 2377 #define ESR_CTL_EN_SYNCDET_1 0x00000002 2378 #define ESR_CTL_EN_SYNCDET_2 0x00000004 2379 #define ESR_CTL_EN_SYNCDET_3 0x00000008 2380 #define ESR_CTL_OUT_EMPH_0_MASK 0x00000070 2381 #define ESR_CTL_OUT_EMPH_0_SHIFT 4 2382 #define ESR_CTL_OUT_EMPH_1_MASK 0x00000380 2383 #define ESR_CTL_OUT_EMPH_1_SHIFT 7 2384 #define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00 2385 #define ESR_CTL_OUT_EMPH_2_SHIFT 10 2386 #define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000 2387 #define ESR_CTL_OUT_EMPH_3_SHIFT 13 2388 #define ESR_CTL_LOSADJ_0_MASK 0x00070000 2389 #define ESR_CTL_LOSADJ_0_SHIFT 16 2390 #define ESR_CTL_LOSADJ_1_MASK 0x00380000 2391 #define ESR_CTL_LOSADJ_1_SHIFT 19 2392 #define ESR_CTL_LOSADJ_2_MASK 0x01c00000 2393 #define ESR_CTL_LOSADJ_2_SHIFT 22 2394 #define ESR_CTL_LOSADJ_3_MASK 0x0e000000 2395 #define ESR_CTL_LOSADJ_3_SHIFT 25 2396 #define ESR_CTL_RXITERM_0 0x10000000 2397 #define ESR_CTL_RXITERM_1 0x20000000 2398 #define ESR_CTL_RXITERM_2 0x40000000 2399 #define ESR_CTL_RXITERM_3 0x80000000 2400 #define ESR_CTL_1G_SERDES (ESR_CTL_EN_SYNCDET_0 | \ 2401 ESR_CTL_EN_SYNCDET_1 | \ 2402 ESR_CTL_EN_SYNCDET_2 | \ 2403 ESR_CTL_EN_SYNCDET_3 | \ 2404 (0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \ 2405 (0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \ 2406 (0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \ 2407 (0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \ 2408 (0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \ 2409 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \ 2410 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \ 2411 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \ 2412 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)) 2413 2414 /* ESR Neptune Serdes Test Configuration Register */ 2415 #define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003 2416 #define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0 2417 #define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c 2418 #define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2 2419 #define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030 2420 #define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4 2421 #define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0 2422 #define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6 2423 #define ESR_TSTCFG_LBTEST_PAD (ESR_PAD_LOOPBACK_CH3 | \ 2424 ESR_PAD_LOOPBACK_CH2 | \ 2425 ESR_PAD_LOOPBACK_CH1 | \ 2426 ESR_PAD_LOOPBACK_CH0) 2427 2428 /* ESR Neptune Ethernet RGMII Configuration Register */ 2429 #define ESR_RGMII_PT0_IN_USE 0x00000001 2430 #define ESR_RGMII_PT1_IN_USE 0x00000002 2431 #define ESR_RGMII_PT2_IN_USE 0x00000004 2432 #define ESR_RGMII_PT3_IN_USE 0x00000008 2433 #define ESR_RGMII_REG_RW_TEST 0x00000010 2434 2435 /* ESR Internal Signals Observation Register */ 2436 #define ESR_SIG_MASK 0xFFFFFFFF 2437 #define ESR_SIG_P0_BITS_MASK 0x33E0000F 2438 #define ESR_SIG_P1_BITS_MASK 0x0C1F00F0 2439 #define ESR_SIG_SERDES_RDY0_P0 0x20000000 2440 #define ESR_SIG_DETECT0_P0 0x10000000 2441 #define ESR_SIG_SERDES_RDY0_P1 0x08000000 2442 #define ESR_SIG_DETECT0_P1 0x04000000 2443 #define ESR_SIG_XSERDES_RDY_P0 0x02000000 2444 #define ESR_SIG_XDETECT_P0_CH3 0x01000000 2445 #define ESR_SIG_XDETECT_P0_CH2 0x00800000 2446 #define ESR_SIG_XDETECT_P0_CH1 0x00400000 2447 #define ESR_SIG_XDETECT_P0_CH0 0x00200000 2448 #define ESR_SIG_XSERDES_RDY_P1 0x00100000 2449 #define ESR_SIG_XDETECT_P1_CH3 0x00080000 2450 #define ESR_SIG_XDETECT_P1_CH2 0x00040000 2451 #define ESR_SIG_XDETECT_P1_CH1 0x00020000 2452 #define ESR_SIG_XDETECT_P1_CH0 0x00010000 2453 #define ESR_SIG_LOS_P1_CH3 0x00000080 2454 #define ESR_SIG_LOS_P1_CH2 0x00000040 2455 #define ESR_SIG_LOS_P1_CH1 0x00000020 2456 #define ESR_SIG_LOS_P1_CH0 0x00000010 2457 #define ESR_SIG_LOS_P0_CH3 0x00000008 2458 #define ESR_SIG_LOS_P0_CH2 0x00000004 2459 #define ESR_SIG_LOS_P0_CH1 0x00000002 2460 #define ESR_SIG_LOS_P0_CH0 0x00000001 2461 #define ESR_SIG_P0_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P0 | \ 2462 ESR_SIG_DETECT0_P0) 2463 #define ESR_SIG_P1_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P1 | \ 2464 ESR_SIG_DETECT0_P1) 2465 2466 /* ESR Debug Selection Register */ 2467 #define ESR_DEBUG_SEL_MASK 0x00000003f 2468 2469 /* ESR Test Configuration Register */ 2470 #define ESR_NO_LOOPBACK_CH3 (0x0 << 6) 2471 #define ESR_EWRAP_CH3 (0x1 << 6) 2472 #define ESR_PAD_LOOPBACK_CH3 (0x2 << 6) 2473 #define ESR_REVLOOPBACK_CH3 (0x3 << 6) 2474 #define ESR_NO_LOOPBACK_CH2 (0x0 << 4) 2475 #define ESR_EWRAP_CH2 (0x1 << 4) 2476 #define ESR_PAD_LOOPBACK_CH2 (0x2 << 4) 2477 #define ESR_REVLOOPBACK_CH2 (0x3 << 4) 2478 #define ESR_NO_LOOPBACK_CH1 (0x0 << 2) 2479 #define ESR_EWRAP_CH1 (0x1 << 2) 2480 #define ESR_PAD_LOOPBACK_CH1 (0x2 << 2) 2481 #define ESR_REVLOOPBACK_CH1 (0x3 << 2) 2482 #define ESR_NO_LOOPBACK_CH0 0x0 2483 #define ESR_EWRAP_CH0 0x1 2484 #define ESR_PAD_LOOPBACK_CH0 0x2 2485 #define ESR_REVLOOPBACK_CH0 0x3 2486 2487 /* convert values */ 2488 #define NXGE_BASE(x, y) \ 2489 (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2490 2491 #define NXGE_VAL_GET(fieldname, regval) \ 2492 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT)) 2493 2494 #define NXGE_VAL_SET(fieldname, regval, val) \ 2495 { \ 2496 (regval) &= ~((fieldname) ## _MASK); \ 2497 (regval) |= ((val) << (fieldname ## _SHIFT)); \ 2498 } 2499 2500 2501 #ifdef __cplusplus 2502 } 2503 #endif 2504 2505 #endif /* _SYS_MAC_NXGE_MAC_HW_H */ 2506