1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MAC_NXGE_MAC_HW_H 27 #define _SYS_MAC_NXGE_MAC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* -------------------------- From May's template --------------------------- */ 38 39 #define NXGE_1GETHERMIN 255 40 #define NXGE_ETHERMIN 97 41 #define NXGE_MAX_HEADER 250 42 43 /* Hardware reset */ 44 typedef enum { 45 NXGE_TX_DISABLE, /* Disable Tx side */ 46 NXGE_RX_DISABLE, /* Disable Rx side */ 47 NXGE_CHIP_RESET /* Full chip reset */ 48 } nxge_reset_t; 49 50 #define NXGE_DELAY_AFTER_TXRX 10000 /* 10ms after idling rx/tx */ 51 #define NXGE_DELAY_AFTER_RESET 1000 /* 1ms after the reset */ 52 #define NXGE_DELAY_AFTER_EE_RESET 10000 /* 10ms after EEPROM reset */ 53 #define NXGE_DELAY_AFTER_LINK_RESET 13 /* 13 Us after link reset */ 54 #define NXGE_LINK_RESETS 8 /* Max PHY resets to wait for */ 55 /* linkup */ 56 57 #define FILTER_M_CTL 0xDCEF1 58 #define HASH_BITS 8 59 #define NMCFILTER_BITS (1 << HASH_BITS) 60 #define HASH_REG_WIDTH 16 61 #define BROADCAST_HASH_WORD 0x0f 62 #define BROADCAST_HASH_BIT 0x8000 63 #define NMCFILTER_REGS NMCFILTER_BITS / HASH_REG_WIDTH 64 /* Number of multicast filter regs */ 65 66 /* -------------------------------------------------------------------------- */ 67 68 #define XMAC_PORT_0 0 69 #define XMAC_PORT_1 1 70 #define BMAC_PORT_0 2 71 #define BMAC_PORT_1 3 72 73 #define MAC_RESET_WAIT 10 /* usecs */ 74 75 #define MAC_ADDR_REG_MASK 0xFFFF 76 77 /* Network Modes */ 78 79 typedef enum nxge_network_mode { 80 NET_2_10GE_FIBER = 1, 81 NET_2_10GE_COPPER, 82 NET_1_10GE_FIBER_3_1GE_COPPER, 83 NET_1_10GE_COPPER_3_1GE_COPPER, 84 NET_1_10GE_FIBER_3_1GE_FIBER, 85 NET_1_10GE_COPPER_3_1GE_FIBER, 86 NET_2_1GE_FIBER_2_1GE_COPPER, 87 NET_QGE_FIBER, 88 NET_QGE_COPPER 89 } nxge_network_mode_t; 90 91 typedef enum nxge_port { 92 PORT_TYPE_XMAC = 1, 93 PORT_TYPE_BMAC 94 } nxge_port_t; 95 96 typedef enum nxge_port_mode { 97 PORT_1G_COPPER = 1, 98 PORT_1G_FIBER, 99 PORT_10G_COPPER, 100 PORT_10G_FIBER 101 } nxge_port_mode_t; 102 103 typedef enum nxge_linkchk_mode { 104 LINKCHK_INTR = 1, 105 LINKCHK_TIMER 106 } nxge_linkchk_mode_t; 107 108 typedef enum { 109 LINK_INTR_STOP, 110 LINK_INTR_START 111 } link_intr_enable_t, *link_intr_enable_pt; 112 113 typedef enum { 114 LINK_MONITOR_STOP, 115 LINK_MONITOR_START 116 } link_mon_enable_t, *link_mon_enable_pt; 117 118 typedef enum { 119 NO_XCVR, 120 INT_MII_XCVR, 121 EXT_MII_XCVR, 122 PCS_XCVR, 123 XPCS_XCVR 124 } xcvr_inuse_t; 125 126 /* macros for port offset calculations */ 127 128 #define PORT_1_OFFSET 0x6000 129 #define PORT_GT_1_OFFSET 0x4000 130 131 /* XMAC address macros */ 132 133 #define XMAC_ADDR_OFFSET_0 0 134 #define XMAC_ADDR_OFFSET_1 0x6000 135 136 #define XMAC_ADDR_OFFSET(port_num)\ 137 (XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 138 139 #define XMAC_REG_ADDR(port_num, reg)\ 140 (FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg)) 141 142 #define XMAC_PORT_ADDR(port_num)\ 143 (FZC_MAC + XMAC_ADDR_OFFSET(port_num)) 144 145 /* BMAC address macros */ 146 147 #define BMAC_ADDR_OFFSET_2 0x0C000 148 #define BMAC_ADDR_OFFSET_3 0x10000 149 150 #define BMAC_ADDR_OFFSET(port_num)\ 151 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 152 153 #define BMAC_REG_ADDR(port_num, reg)\ 154 (FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg)) 155 156 #define BMAC_PORT_ADDR(port_num)\ 157 (FZC_MAC + BMAC_ADDR_OFFSET(port_num)) 158 159 /* PCS address macros */ 160 161 #define PCS_ADDR_OFFSET_0 0x04000 162 #define PCS_ADDR_OFFSET_1 0x0A000 163 #define PCS_ADDR_OFFSET_2 0x0E000 164 #define PCS_ADDR_OFFSET_3 0x12000 165 166 #define PCS_ADDR_OFFSET(port_num)\ 167 ((port_num <= 1) ? \ 168 (PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \ 169 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 170 171 #define PCS_REG_ADDR(port_num, reg)\ 172 (FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg))) 173 174 #define PCS_PORT_ADDR(port_num)\ 175 (FZC_MAC + (PCS_ADDR_OFFSET(port_num))) 176 177 /* XPCS address macros */ 178 179 #define XPCS_ADDR_OFFSET_0 0x02000 180 #define XPCS_ADDR_OFFSET_1 0x08000 181 #define XPCS_ADDR_OFFSET(port_num)\ 182 (XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 183 184 #define XPCS_ADDR(port_num, reg)\ 185 (FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg))) 186 187 #define XPCS_PORT_ADDR(port_num)\ 188 (FZC_MAC + (XPCS_ADDR_OFFSET(port_num))) 189 190 /* ESR address macro */ 191 #define ESR_ADDR_OFFSET 0x14000 192 #define ESR_ADDR(reg)\ 193 (FZC_MAC + (ESR_ADDR_OFFSET) + (reg)) 194 195 /* MIF address macros */ 196 #define MIF_ADDR_OFFSET 0x16000 197 #define MIF_ADDR(reg)\ 198 (FZC_MAC + (MIF_ADDR_OFFSET) + (reg)) 199 200 /* BMAC registers offset */ 201 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ 202 #define BRXMAC_SW_RST_REG 0x008 /* RX MAC software reset */ 203 #define MAC_SEND_PAUSE_REG 0x010 /* send pause command */ 204 #define BTXMAC_STATUS_REG 0x020 /* TX MAC status */ 205 #define BRXMAC_STATUS_REG 0x028 /* RX MAC status */ 206 #define BMAC_CTRL_STAT_REG 0x030 /* MAC control status */ 207 #define BTXMAC_STAT_MSK_REG 0x040 /* TX MAC mask */ 208 #define BRXMAC_STAT_MSK_REG 0x048 /* RX MAC mask */ 209 #define BMAC_C_S_MSK_REG 0x050 /* MAC control mask */ 210 #define TXMAC_CONFIG_REG 0x060 /* TX MAC config */ 211 /* cfg register bitmap */ 212 213 typedef union _btxmac_config_t { 214 uint64_t value; 215 216 struct { 217 #if defined(_BIG_ENDIAN) 218 uint32_t msw; /* Most significant word */ 219 uint32_t lsw; /* Least significant word */ 220 #elif defined(_LITTLE_ENDIAN) 221 uint32_t lsw; /* Least significant word */ 222 uint32_t msw; /* Most significant word */ 223 #endif 224 } val; 225 struct { 226 #if defined(_BIG_ENDIAN) 227 uint32_t w1; 228 #endif 229 struct { 230 #if defined(_BIT_FIELDS_HTOL) 231 uint32_t rsrvd : 22; 232 uint32_t hdx_ctrl2 : 1; 233 uint32_t no_fcs : 1; 234 uint32_t hdx_ctrl : 7; 235 uint32_t txmac_enable : 1; 236 #elif defined(_BIT_FIELDS_LTOH) 237 uint32_t txmac_enable : 1; 238 uint32_t hdx_ctrl : 7; 239 uint32_t no_fcs : 1; 240 uint32_t hdx_ctrl2 : 1; 241 uint32_t rsrvd : 22; 242 #endif 243 } w0; 244 245 #if defined(_LITTLE_ENDIAN) 246 uint32_t w1; 247 #endif 248 } bits; 249 } btxmac_config_t, *p_btxmac_config_t; 250 251 #define RXMAC_CONFIG_REG 0x068 /* RX MAC config */ 252 253 typedef union _brxmac_config_t { 254 uint64_t value; 255 256 struct { 257 #if defined(_BIG_ENDIAN) 258 uint32_t msw; /* Most significant word */ 259 uint32_t lsw; /* Least significant word */ 260 #elif defined(_LITTLE_ENDIAN) 261 uint32_t lsw; /* Least significant word */ 262 uint32_t msw; /* Most significant word */ 263 #endif 264 } val; 265 struct { 266 #if defined(_BIG_ENDIAN) 267 uint32_t w1; 268 #endif 269 struct { 270 #if defined(_BIT_FIELDS_HTOL) 271 uint32_t rsrvd : 20; 272 uint32_t mac_reg_sw_test : 2; 273 uint32_t mac2ipp_pkt_cnt_en : 1; 274 uint32_t rx_crs_extend_en : 1; 275 uint32_t error_chk_dis : 1; 276 uint32_t addr_filter_en : 1; 277 uint32_t hash_filter_en : 1; 278 uint32_t promiscuous_group : 1; 279 uint32_t promiscuous : 1; 280 uint32_t strip_fcs : 1; 281 uint32_t strip_pad : 1; 282 uint32_t rxmac_enable : 1; 283 #elif defined(_BIT_FIELDS_LTOH) 284 uint32_t rxmac_enable : 1; 285 uint32_t strip_pad : 1; 286 uint32_t strip_fcs : 1; 287 uint32_t promiscuous : 1; 288 uint32_t promiscuous_group : 1; 289 uint32_t hash_filter_en : 1; 290 uint32_t addr_filter_en : 1; 291 uint32_t error_chk_dis : 1; 292 uint32_t rx_crs_extend_en : 1; 293 uint32_t mac2ipp_pkt_cnt_en : 1; 294 uint32_t mac_reg_sw_test : 2; 295 uint32_t rsrvd : 20; 296 #endif 297 } w0; 298 299 #if defined(_LITTLE_ENDIAN) 300 uint32_t w1; 301 #endif 302 } bits; 303 } brxmac_config_t, *p_brxmac_config_t; 304 305 #define MAC_CTRL_CONFIG_REG 0x070 /* MAC control config */ 306 #define MAC_XIF_CONFIG_REG 0x078 /* XIF config */ 307 308 typedef union _bxif_config_t { 309 uint64_t value; 310 311 struct { 312 #if defined(_BIG_ENDIAN) 313 uint32_t msw; /* Most significant word */ 314 uint32_t lsw; /* Least significant word */ 315 #elif defined(_LITTLE_ENDIAN) 316 uint32_t lsw; /* Least significant word */ 317 uint32_t msw; /* Most significant word */ 318 #endif 319 } val; 320 struct { 321 #if defined(_BIG_ENDIAN) 322 uint32_t w1; 323 #endif 324 struct { 325 #if defined(_BIT_FIELDS_HTOL) 326 uint32_t rsrvd2 : 24; 327 uint32_t sel_clk_25mhz : 1; 328 uint32_t led_polarity : 1; 329 uint32_t force_led_on : 1; 330 uint32_t used : 1; 331 uint32_t gmii_mode : 1; 332 uint32_t rsrvd : 1; 333 uint32_t loopback : 1; 334 uint32_t tx_output_en : 1; 335 #elif defined(_BIT_FIELDS_LTOH) 336 uint32_t tx_output_en : 1; 337 uint32_t loopback : 1; 338 uint32_t rsrvd : 1; 339 uint32_t gmii_mode : 1; 340 uint32_t used : 1; 341 uint32_t force_led_on : 1; 342 uint32_t led_polarity : 1; 343 uint32_t sel_clk_25mhz : 1; 344 uint32_t rsrvd2 : 24; 345 #endif 346 } w0; 347 348 #if defined(_LITTLE_ENDIAN) 349 uint32_t w1; 350 #endif 351 } bits; 352 } bxif_config_t, *p_bxif_config_t; 353 354 #define BMAC_MIN_REG 0x0a0 /* min frame size */ 355 #define BMAC_MAX_REG 0x0a8 /* max frame size reg */ 356 #define MAC_PA_SIZE_REG 0x0b0 /* num of preamble bytes */ 357 #define MAC_CTRL_TYPE_REG 0x0c8 /* type field of MAC ctrl */ 358 #define BMAC_ADDR0_REG 0x100 /* MAC unique ad0 reg (HI 0) */ 359 #define BMAC_ADDR1_REG 0x108 /* MAC unique ad1 reg */ 360 #define BMAC_ADDR2_REG 0x110 /* MAC unique ad2 reg */ 361 #define BMAC_ADDR3_REG 0x118 /* MAC alt ad0 reg (HI 1) */ 362 #define BMAC_ADDR4_REG 0x120 /* MAC alt ad0 reg */ 363 #define BMAC_ADDR5_REG 0x128 /* MAC alt ad0 reg */ 364 #define BMAC_ADDR6_REG 0x130 /* MAC alt ad1 reg (HI 2) */ 365 #define BMAC_ADDR7_REG 0x138 /* MAC alt ad1 reg */ 366 #define BMAC_ADDR8_REG 0x140 /* MAC alt ad1 reg */ 367 #define BMAC_ADDR9_REG 0x148 /* MAC alt ad2 reg (HI 3) */ 368 #define BMAC_ADDR10_REG 0x150 /* MAC alt ad2 reg */ 369 #define BMAC_ADDR11_REG 0x158 /* MAC alt ad2 reg */ 370 #define BMAC_ADDR12_REG 0x160 /* MAC alt ad3 reg (HI 4) */ 371 #define BMAC_ADDR13_REG 0x168 /* MAC alt ad3 reg */ 372 #define BMAC_ADDR14_REG 0x170 /* MAC alt ad3 reg */ 373 #define BMAC_ADDR15_REG 0x178 /* MAC alt ad4 reg (HI 5) */ 374 #define BMAC_ADDR16_REG 0x180 /* MAC alt ad4 reg */ 375 #define BMAC_ADDR17_REG 0x188 /* MAC alt ad4 reg */ 376 #define BMAC_ADDR18_REG 0x190 /* MAC alt ad5 reg (HI 6) */ 377 #define BMAC_ADDR19_REG 0x198 /* MAC alt ad5 reg */ 378 #define BMAC_ADDR20_REG 0x1a0 /* MAC alt ad5 reg */ 379 #define BMAC_ADDR21_REG 0x1a8 /* MAC alt ad6 reg (HI 7) */ 380 #define BMAC_ADDR22_REG 0x1b0 /* MAC alt ad6 reg */ 381 #define BMAC_ADDR23_REG 0x1b8 /* MAC alt ad6 reg */ 382 #define MAC_FC_ADDR0_REG 0x268 /* FC frame addr0 (HI 0, p3) */ 383 #define MAC_FC_ADDR1_REG 0x270 /* FC frame addr1 */ 384 #define MAC_FC_ADDR2_REG 0x278 /* FC frame addr2 */ 385 #define MAC_ADDR_FILT0_REG 0x298 /* bits [47:32] (HI 0, p2) */ 386 #define MAC_ADDR_FILT1_REG 0x2a0 /* bits [31:16] */ 387 #define MAC_ADDR_FILT2_REG 0x2a8 /* bits [15:0] */ 388 #define MAC_ADDR_FILT12_MASK_REG 0x2b0 /* addr filter 2 & 1 mask */ 389 #define MAC_ADDR_FILT00_MASK_REG 0x2b8 /* addr filter 0 mask */ 390 #define MAC_HASH_TBL0_REG 0x2c0 /* hash table 0 reg */ 391 #define MAC_HASH_TBL1_REG 0x2c8 /* hash table 1 reg */ 392 #define MAC_HASH_TBL2_REG 0x2d0 /* hash table 2 reg */ 393 #define MAC_HASH_TBL3_REG 0x2d8 /* hash table 3 reg */ 394 #define MAC_HASH_TBL4_REG 0x2e0 /* hash table 4 reg */ 395 #define MAC_HASH_TBL5_REG 0x2e8 /* hash table 5 reg */ 396 #define MAC_HASH_TBL6_REG 0x2f0 /* hash table 6 reg */ 397 #define MAC_HASH_TBL7_REG 0x2f8 /* hash table 7 reg */ 398 #define MAC_HASH_TBL8_REG 0x300 /* hash table 8 reg */ 399 #define MAC_HASH_TBL9_REG 0x308 /* hash table 9 reg */ 400 #define MAC_HASH_TBL10_REG 0x310 /* hash table 10 reg */ 401 #define MAC_HASH_TBL11_REG 0x318 /* hash table 11 reg */ 402 #define MAC_HASH_TBL12_REG 0x320 /* hash table 12 reg */ 403 #define MAC_HASH_TBL13_REG 0x328 /* hash table 13 reg */ 404 #define MAC_HASH_TBL14_REG 0x330 /* hash table 14 reg */ 405 #define MAC_HASH_TBL15_REG 0x338 /* hash table 15 reg */ 406 #define RXMAC_FRM_CNT_REG 0x370 /* receive frame counter */ 407 #define MAC_LEN_ER_CNT_REG 0x378 /* length error counter */ 408 #define BMAC_AL_ER_CNT_REG 0x380 /* alignment error counter */ 409 #define BMAC_CRC_ER_CNT_REG 0x388 /* FCS error counter */ 410 #define BMAC_CD_VIO_CNT_REG 0x390 /* RX code violation err */ 411 #define BMAC_SM_REG 0x3a0 /* (ro) state machine reg */ 412 #define BMAC_ALTAD_CMPEN_REG 0x3f8 /* Alt addr compare enable */ 413 #define BMAC_HOST_INF0_REG 0x400 /* Host info */ 414 /* (own da, add filter, fc) */ 415 #define BMAC_HOST_INF1_REG 0x408 /* Host info (alt ad 0) */ 416 #define BMAC_HOST_INF2_REG 0x410 /* Host info (alt ad 1) */ 417 #define BMAC_HOST_INF3_REG 0x418 /* Host info (alt ad 2) */ 418 #define BMAC_HOST_INF4_REG 0x420 /* Host info (alt ad 3) */ 419 #define BMAC_HOST_INF5_REG 0x428 /* Host info (alt ad 4) */ 420 #define BMAC_HOST_INF6_REG 0x430 /* Host info (alt ad 5) */ 421 #define BMAC_HOST_INF7_REG 0x438 /* Host info (alt ad 6) */ 422 #define BMAC_HOST_INF8_REG 0x440 /* Host info (hash hit, miss) */ 423 #define BTXMAC_BYTE_CNT_REG 0x448 /* Tx byte count */ 424 #define BTXMAC_FRM_CNT_REG 0x450 /* frame count */ 425 #define BRXMAC_BYTE_CNT_REG 0x458 /* Rx byte count */ 426 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */ 427 #define BMAC_ALT_ADDR0N_REG_ADDR(x) (BMAC_ADDR3_REG + (x) * 24) 428 #define BMAC_ALT_ADDR1N_REG_ADDR(x) (BMAC_ADDR3_REG + 8 + (x) * 24) 429 #define BMAC_ALT_ADDR2N_REG_ADDR(x) (BMAC_ADDR3_REG + 0x10 + (x) * 24) 430 #define BMAC_HASH_TBLN_REG_ADDR(x) (MAC_HASH_TBL0_REG + (x) * 8) 431 #define BMAC_HOST_INFN_REG_ADDR(x) (BMAC_HOST_INF0_REG + (x) * 8) 432 433 /* XMAC registers offset */ 434 #define XTXMAC_SW_RST_REG 0x000 /* XTX MAC soft reset */ 435 #define XRXMAC_SW_RST_REG 0x008 /* XRX MAC soft reset */ 436 #define XTXMAC_STATUS_REG 0x020 /* XTX MAC status */ 437 #define XRXMAC_STATUS_REG 0x028 /* XRX MAC status */ 438 #define XMAC_CTRL_STAT_REG 0x030 /* Control / Status */ 439 #define XTXMAC_STAT_MSK_REG 0x040 /* XTX MAC Status mask */ 440 #define XRXMAC_STAT_MSK_REG 0x048 /* XRX MAC Status mask */ 441 #define XMAC_C_S_MSK_REG 0x050 /* Control / Status mask */ 442 #define XMAC_CONFIG_REG 0x060 /* Configuration */ 443 444 /* xmac config bit fields */ 445 typedef union _xmac_cfg_t { 446 uint64_t value; 447 448 struct { 449 #if defined(_BIG_ENDIAN) 450 uint32_t msw; /* Most significant word */ 451 uint32_t lsw; /* Least significant word */ 452 #elif defined(_LITTLE_ENDIAN) 453 uint32_t lsw; /* Least significant word */ 454 uint32_t msw; /* Most significant word */ 455 #endif 456 } val; 457 struct { 458 #if defined(_BIG_ENDIAN) 459 uint32_t w1; 460 #endif 461 struct { 462 #if defined(_BIT_FIELDS_HTOL) 463 uint32_t sel_clk_25mhz : 1; 464 uint32_t pcs_bypass : 1; 465 uint32_t xpcs_bypass : 1; 466 uint32_t mii_gmii_mode : 2; 467 uint32_t lfs_disable : 1; 468 uint32_t loopback : 1; 469 uint32_t tx_output_en : 1; 470 uint32_t sel_por_clk_src : 1; 471 uint32_t led_polarity : 1; 472 uint32_t force_led_on : 1; 473 uint32_t pass_fctl_frames : 1; 474 uint32_t recv_pause_en : 1; 475 uint32_t mac2ipp_pkt_cnt_en : 1; 476 uint32_t strip_crc : 1; 477 uint32_t addr_filter_en : 1; 478 uint32_t hash_filter_en : 1; 479 uint32_t code_viol_chk_dis : 1; 480 uint32_t reserved_mcast : 1; 481 uint32_t rx_crc_chk_dis : 1; 482 uint32_t error_chk_dis : 1; 483 uint32_t promisc_grp : 1; 484 uint32_t promiscuous : 1; 485 uint32_t rx_mac_enable : 1; 486 uint32_t warning_msg_en : 1; 487 uint32_t used : 3; 488 uint32_t always_no_crc : 1; 489 uint32_t var_min_ipg_en : 1; 490 uint32_t strech_mode : 1; 491 uint32_t tx_enable : 1; 492 #elif defined(_BIT_FIELDS_LTOH) 493 uint32_t tx_enable : 1; 494 uint32_t strech_mode : 1; 495 uint32_t var_min_ipg_en : 1; 496 uint32_t always_no_crc : 1; 497 uint32_t used : 3; 498 uint32_t warning_msg_en : 1; 499 uint32_t rx_mac_enable : 1; 500 uint32_t promiscuous : 1; 501 uint32_t promisc_grp : 1; 502 uint32_t error_chk_dis : 1; 503 uint32_t rx_crc_chk_dis : 1; 504 uint32_t reserved_mcast : 1; 505 uint32_t code_viol_chk_dis : 1; 506 uint32_t hash_filter_en : 1; 507 uint32_t addr_filter_en : 1; 508 uint32_t strip_crc : 1; 509 uint32_t mac2ipp_pkt_cnt_en : 1; 510 uint32_t recv_pause_en : 1; 511 uint32_t pass_fctl_frames : 1; 512 uint32_t force_led_on : 1; 513 uint32_t led_polarity : 1; 514 uint32_t sel_por_clk_src : 1; 515 uint32_t tx_output_en : 1; 516 uint32_t loopback : 1; 517 uint32_t lfs_disable : 1; 518 uint32_t mii_gmii_mode : 2; 519 uint32_t xpcs_bypass : 1; 520 uint32_t pcs_bypass : 1; 521 uint32_t sel_clk_25mhz : 1; 522 #endif 523 } w0; 524 525 #if defined(_LITTLE_ENDIAN) 526 uint32_t w1; 527 #endif 528 } bits; 529 } xmac_cfg_t, *p_xmac_cfg_t; 530 531 #define XMAC_IPG_REG 0x080 /* Inter-Packet-Gap */ 532 #define XMAC_MIN_REG 0x088 /* min frame size register */ 533 #define XMAC_MAX_REG 0x090 /* max frame/burst size */ 534 #define XMAC_ADDR0_REG 0x0a0 /* [47:32] of MAC addr (HI17) */ 535 #define XMAC_ADDR1_REG 0x0a8 /* [31:16] of MAC addr */ 536 #define XMAC_ADDR2_REG 0x0b0 /* [15:0] of MAC addr */ 537 #define XRXMAC_BT_CNT_REG 0x100 /* bytes received / 8 */ 538 #define XRXMAC_BC_FRM_CNT_REG 0x108 /* good BC frames received */ 539 #define XRXMAC_MC_FRM_CNT_REG 0x110 /* good MC frames received */ 540 #define XRXMAC_FRAG_CNT_REG 0x118 /* frag frames rejected */ 541 #define XRXMAC_HIST_CNT1_REG 0x120 /* 64 bytes frames */ 542 #define XRXMAC_HIST_CNT2_REG 0x128 /* 65-127 bytes frames */ 543 #define XRXMAC_HIST_CNT3_REG 0x130 /* 128-255 bytes frames */ 544 #define XRXMAC_HIST_CNT4_REG 0x138 /* 256-511 bytes frames */ 545 #define XRXMAC_HIST_CNT5_REG 0x140 /* 512-1023 bytes frames */ 546 #define XRXMAC_HIST_CNT6_REG 0x148 /* 1024-1522 bytes frames */ 547 #define XRXMAC_MPSZER_CNT_REG 0x150 /* frames > maxframesize */ 548 #define XRXMAC_CRC_ER_CNT_REG 0x158 /* frames failed CRC */ 549 #define XRXMAC_CD_VIO_CNT_REG 0x160 /* frames with code vio */ 550 #define XRXMAC_AL_ER_CNT_REG 0x168 /* frames with align error */ 551 #define XTXMAC_FRM_CNT_REG 0x170 /* tx frames */ 552 #define XTXMAC_BYTE_CNT_REG 0x178 /* tx bytes / 8 */ 553 #define XMAC_LINK_FLT_CNT_REG 0x180 /* link faults */ 554 #define XRXMAC_HIST_CNT7_REG 0x188 /* MAC2IPP/>1523 bytes frames */ 555 #define XMAC_SM_REG 0x1a8 /* State machine */ 556 #define XMAC_INTERN1_REG 0x1b0 /* internal signals for diag */ 557 #define XMAC_INTERN2_REG 0x1b8 /* internal signals for diag */ 558 #define XMAC_ADDR_CMPEN_REG 0x208 /* alt MAC addr check */ 559 #define XMAC_ADDR3_REG 0x218 /* alt MAC addr 0 (HI 0) */ 560 #define XMAC_ADDR4_REG 0x220 /* alt MAC addr 0 */ 561 #define XMAC_ADDR5_REG 0x228 /* alt MAC addr 0 */ 562 #define XMAC_ADDR6_REG 0x230 /* alt MAC addr 1 (HI 1) */ 563 #define XMAC_ADDR7_REG 0x238 /* alt MAC addr 1 */ 564 #define XMAC_ADDR8_REG 0x240 /* alt MAC addr 1 */ 565 #define XMAC_ADDR9_REG 0x248 /* alt MAC addr 2 (HI 2) */ 566 #define XMAC_ADDR10_REG 0x250 /* alt MAC addr 2 */ 567 #define XMAC_ADDR11_REG 0x258 /* alt MAC addr 2 */ 568 #define XMAC_ADDR12_REG 0x260 /* alt MAC addr 3 (HI 3) */ 569 #define XMAC_ADDR13_REG 0x268 /* alt MAC addr 3 */ 570 #define XMAC_ADDR14_REG 0x270 /* alt MAC addr 3 */ 571 #define XMAC_ADDR15_REG 0x278 /* alt MAC addr 4 (HI 4) */ 572 #define XMAC_ADDR16_REG 0x280 /* alt MAC addr 4 */ 573 #define XMAC_ADDR17_REG 0x288 /* alt MAC addr 4 */ 574 #define XMAC_ADDR18_REG 0x290 /* alt MAC addr 5 (HI 5) */ 575 #define XMAC_ADDR19_REG 0x298 /* alt MAC addr 5 */ 576 #define XMAC_ADDR20_REG 0x2a0 /* alt MAC addr 5 */ 577 #define XMAC_ADDR21_REG 0x2a8 /* alt MAC addr 6 (HI 6) */ 578 #define XMAC_ADDR22_REG 0x2b0 /* alt MAC addr 6 */ 579 #define XMAC_ADDR23_REG 0x2b8 /* alt MAC addr 6 */ 580 #define XMAC_ADDR24_REG 0x2c0 /* alt MAC addr 7 (HI 7) */ 581 #define XMAC_ADDR25_REG 0x2c8 /* alt MAC addr 7 */ 582 #define XMAC_ADDR26_REG 0x2d0 /* alt MAC addr 7 */ 583 #define XMAC_ADDR27_REG 0x2d8 /* alt MAC addr 8 (HI 8) */ 584 #define XMAC_ADDR28_REG 0x2e0 /* alt MAC addr 8 */ 585 #define XMAC_ADDR29_REG 0x2e8 /* alt MAC addr 8 */ 586 #define XMAC_ADDR30_REG 0x2f0 /* alt MAC addr 9 (HI 9) */ 587 #define XMAC_ADDR31_REG 0x2f8 /* alt MAC addr 9 */ 588 #define XMAC_ADDR32_REG 0x300 /* alt MAC addr 9 */ 589 #define XMAC_ADDR33_REG 0x308 /* alt MAC addr 10 (HI 10) */ 590 #define XMAC_ADDR34_REG 0x310 /* alt MAC addr 10 */ 591 #define XMAC_ADDR35_REG 0x318 /* alt MAC addr 10 */ 592 #define XMAC_ADDR36_REG 0x320 /* alt MAC addr 11 (HI 11) */ 593 #define XMAC_ADDR37_REG 0x328 /* alt MAC addr 11 */ 594 #define XMAC_ADDR38_REG 0x330 /* alt MAC addr 11 */ 595 #define XMAC_ADDR39_REG 0x338 /* alt MAC addr 12 (HI 12) */ 596 #define XMAC_ADDR40_REG 0x340 /* alt MAC addr 12 */ 597 #define XMAC_ADDR41_REG 0x348 /* alt MAC addr 12 */ 598 #define XMAC_ADDR42_REG 0x350 /* alt MAC addr 13 (HI 13) */ 599 #define XMAC_ADDR43_REG 0x358 /* alt MAC addr 13 */ 600 #define XMAC_ADDR44_REG 0x360 /* alt MAC addr 13 */ 601 #define XMAC_ADDR45_REG 0x368 /* alt MAC addr 14 (HI 14) */ 602 #define XMAC_ADDR46_REG 0x370 /* alt MAC addr 14 */ 603 #define XMAC_ADDR47_REG 0x378 /* alt MAC addr 14 */ 604 #define XMAC_ADDR48_REG 0x380 /* alt MAC addr 15 (HI 15) */ 605 #define XMAC_ADDR49_REG 0x388 /* alt MAC addr 15 */ 606 #define XMAC_ADDR50_REG 0x390 /* alt MAC addr 15 */ 607 #define XMAC_ADDR_FILT0_REG 0x818 /* [47:32] addr filter (HI18) */ 608 #define XMAC_ADDR_FILT1_REG 0x820 /* [31:16] of addr filter */ 609 #define XMAC_ADDR_FILT2_REG 0x828 /* [15:0] of addr filter */ 610 #define XMAC_ADDR_FILT12_MASK_REG 0x830 /* addr filter 2 & 1 mask */ 611 #define XMAC_ADDR_FILT0_MASK_REG 0x838 /* addr filter 0 mask */ 612 #define XMAC_HASH_TBL0_REG 0x840 /* hash table 0 reg */ 613 #define XMAC_HASH_TBL1_REG 0x848 /* hash table 1 reg */ 614 #define XMAC_HASH_TBL2_REG 0x850 /* hash table 2 reg */ 615 #define XMAC_HASH_TBL3_REG 0x858 /* hash table 3 reg */ 616 #define XMAC_HASH_TBL4_REG 0x860 /* hash table 4 reg */ 617 #define XMAC_HASH_TBL5_REG 0x868 /* hash table 5 reg */ 618 #define XMAC_HASH_TBL6_REG 0x870 /* hash table 6 reg */ 619 #define XMAC_HASH_TBL7_REG 0x878 /* hash table 7 reg */ 620 #define XMAC_HASH_TBL8_REG 0x880 /* hash table 8 reg */ 621 #define XMAC_HASH_TBL9_REG 0x888 /* hash table 9 reg */ 622 #define XMAC_HASH_TBL10_REG 0x890 /* hash table 10 reg */ 623 #define XMAC_HASH_TBL11_REG 0x898 /* hash table 11 reg */ 624 #define XMAC_HASH_TBL12_REG 0x8a0 /* hash table 12 reg */ 625 #define XMAC_HASH_TBL13_REG 0x8a8 /* hash table 13 reg */ 626 #define XMAC_HASH_TBL14_REG 0x8b0 /* hash table 14 reg */ 627 #define XMAC_HASH_TBL15_REG 0x8b8 /* hash table 15 reg */ 628 #define XMAC_HOST_INF0_REG 0x900 /* Host info 0 (alt ad 0) */ 629 #define XMAC_HOST_INF1_REG 0x908 /* Host info 1 (alt ad 1) */ 630 #define XMAC_HOST_INF2_REG 0x910 /* Host info 2 (alt ad 2) */ 631 #define XMAC_HOST_INF3_REG 0x918 /* Host info 3 (alt ad 3) */ 632 #define XMAC_HOST_INF4_REG 0x920 /* Host info 4 (alt ad 4) */ 633 #define XMAC_HOST_INF5_REG 0x928 /* Host info 5 (alt ad 5) */ 634 #define XMAC_HOST_INF6_REG 0x930 /* Host info 6 (alt ad 6) */ 635 #define XMAC_HOST_INF7_REG 0x938 /* Host info 7 (alt ad 7) */ 636 #define XMAC_HOST_INF8_REG 0x940 /* Host info 8 (alt ad 8) */ 637 #define XMAC_HOST_INF9_REG 0x948 /* Host info 9 (alt ad 9) */ 638 #define XMAC_HOST_INF10_REG 0x950 /* Host info 10 (alt ad 10) */ 639 #define XMAC_HOST_INF11_REG 0x958 /* Host info 11 (alt ad 11) */ 640 #define XMAC_HOST_INF12_REG 0x960 /* Host info 12 (alt ad 12) */ 641 #define XMAC_HOST_INF13_REG 0x968 /* Host info 13 (alt ad 13) */ 642 #define XMAC_HOST_INF14_REG 0x970 /* Host info 14 (alt ad 14) */ 643 #define XMAC_HOST_INF15_REG 0x978 /* Host info 15 (alt ad 15) */ 644 #define XMAC_HOST_INF16_REG 0x980 /* Host info 16 (hash hit) */ 645 #define XMAC_HOST_INF17_REG 0x988 /* Host info 17 (own da) */ 646 #define XMAC_HOST_INF18_REG 0x990 /* Host info 18 (filter hit) */ 647 #define XMAC_HOST_INF19_REG 0x998 /* Host info 19 (fc hit) */ 648 #define XMAC_PA_DATA0_REG 0xb80 /* preamble [31:0] */ 649 #define XMAC_PA_DATA1_REG 0xb88 /* preamble [63:32] */ 650 #define XMAC_DEBUG_SEL_REG 0xb90 /* debug select */ 651 #define XMAC_TRAINING_VECT_REG 0xb98 /* training vector */ 652 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */ 653 #define XMAC_ALT_ADDR0N_REG_ADDR(x) (XMAC_ADDR3_REG + (x) * 24) 654 #define XMAC_ALT_ADDR1N_REG_ADDR(x) (XMAC_ADDR3_REG + 8 + (x) * 24) 655 #define XMAC_ALT_ADDR2N_REG_ADDR(x) (XMAC_ADDR3_REG + 16 + (x) * 24) 656 #define XMAC_HASH_TBLN_REG_ADDR(x) (XMAC_HASH_TBL0_REG + (x) * 8) 657 #define XMAC_HOST_INFN_REG_ADDR(x) (XMAC_HOST_INF0_REG + (x) * 8) 658 659 /* MIF registers offset */ 660 #define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */ 661 #define MIF_BB_MDO_REG 0x008 /* MIF bit-bang data */ 662 #define MIF_BB_MDO_EN_REG 0x010 /* MIF bit-bang output en */ 663 #define MIF_OUTPUT_FRAME_REG 0x018 /* MIF frame/output reg */ 664 #define MIF_CONFIG_REG 0x020 /* MIF config reg */ 665 #define MIF_POLL_STATUS_REG 0x028 /* MIF poll status reg */ 666 #define MIF_POLL_MASK_REG 0x030 /* MIF poll mask reg */ 667 #define MIF_STATE_MACHINE_REG 0x038 /* MIF state machine reg */ 668 #define MIF_STATUS_REG 0x040 /* MIF status reg */ 669 #define MIF_MASK_REG 0x048 /* MIF mask reg */ 670 671 672 /* PCS registers offset */ 673 #define PCS_MII_CTRL_REG 0 /* PCS MII control reg */ 674 #define PCS_MII_STATUS_REG 0x008 /* PCS MII status reg */ 675 #define PCS_MII_ADVERT_REG 0x010 /* PCS MII advertisement */ 676 #define PCS_MII_LPA_REG 0x018 /* link partner ability */ 677 #define PCS_CONFIG_REG 0x020 /* PCS config reg */ 678 #define PCS_STATE_MACHINE_REG 0x028 /* PCS state machine */ 679 #define PCS_INTR_STATUS_REG 0x030 /* PCS interrupt status */ 680 #define PCS_DATAPATH_MODE_REG 0x0a0 /* datapath mode reg */ 681 #define PCS_PACKET_COUNT_REG 0x0c0 /* PCS packet counter */ 682 683 #define XPCS_CTRL_1_REG 0 /* Control */ 684 #define XPCS_STATUS_1_REG 0x008 685 #define XPCS_DEV_ID_REG 0x010 /* 32bits IEEE manufacture ID */ 686 #define XPCS_SPEED_ABILITY_REG 0x018 687 #define XPCS_DEV_IN_PKG_REG 0x020 688 #define XPCS_CTRL_2_REG 0x028 689 #define XPCS_STATUS_2_REG 0x030 690 #define XPCS_PKG_ID_REG 0x038 /* Package ID */ 691 #define XPCS_STATUS_REG 0x040 692 #define XPCS_TEST_CTRL_REG 0x048 693 #define XPCS_CFG_VENDOR_1_REG 0x050 694 #define XPCS_DIAG_VENDOR_2_REG 0x058 695 #define XPCS_MASK_1_REG 0x060 696 #define XPCS_PKT_CNTR_REG 0x068 697 #define XPCS_TX_STATE_MC_REG 0x070 698 #define XPCS_DESKEW_ERR_CNTR_REG 0x078 699 #define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080 700 #define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088 701 #define XPCS_TRAINING_VECTOR_REG 0x090 702 703 /* ESR registers offset */ 704 #define ESR_RESET_REG 0 705 #define ESR_CONFIG_REG 0x008 706 #define ESR_0_PLL_CONFIG_REG 0x010 707 #define ESR_0_CONTROL_REG 0x018 708 #define ESR_0_TEST_CONFIG_REG 0x020 709 #define ESR_1_PLL_CONFIG_REG 0x028 710 #define ESR_1_CONTROL_REG 0x030 711 #define ESR_1_TEST_CONFIG_REG 0x038 712 #define ESR_ENET_RGMII_CFG_REG 0x040 713 #define ESR_INTERNAL_SIGNALS_REG 0x800 714 #define ESR_DEBUG_SEL_REG 0x808 715 716 717 /* Reset Register */ 718 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time */ 719 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl */ 720 721 /* Tx MAC Status Register */ 722 #define MAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 723 #define MAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 724 #define MAC_TX_MAX_PACKET_ERR 0x00000004 /* TX frame exceeds max */ 725 #define MAC_TX_BYTE_CNT_EXP 0x00000400 /* TX byte cnt overflow */ 726 #define MAC_TX_FRAME_CNT_EXP 0x00000800 /* Tx frame cnt overflow */ 727 728 /* Rx MAC Status Register */ 729 #define MAC_RX_FRAME_RECV 0x00000001 /* successful rx frame */ 730 #define MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 731 #define MAC_RX_FRAME_COUNT 0x00000004 /* rx frame cnt rollover */ 732 #define MAC_RX_ALIGN_ERR 0x00000008 /* alignment err rollover */ 733 #define MAC_RX_CRC_ERR 0x00000010 /* crc error cnt rollover */ 734 #define MAC_RX_LEN_ERR 0x00000020 /* length err cnt rollover */ 735 #define MAC_RX_VIOL_ERR 0x00000040 /* code vio err rollover */ 736 #define MAC_RX_BYTE_CNT_EXP 0x00000080 /* RX MAC byte rollover */ 737 738 /* MAC Control Status Register */ 739 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful pause frame */ 740 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 741 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 742 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 743 #define MAC_CTRL_PAUSE_TIME_SHIFT 16 744 745 /* Tx MAC Configuration Register */ 746 #define MAC_TX_CFG_TXMAC_ENABLE 0x00000001 /* enable TX MAC. */ 747 #define MAC_TX_CFG_NO_FCS 0x00000100 /* TX not generate CRC */ 748 749 /* Rx MAC Configuration Register */ 750 #define MAC_RX_CFG_RXMAC_ENABLE 0x00000001 /* enable RX MAC */ 751 #define MAC_RX_CFG_STRIP_PAD 0x00000002 /* not supported, set to 0 */ 752 #define MAC_RX_CFG_STRIP_FCS 0x00000004 /* strip last 4bytes (CRC) */ 753 #define MAC_RX_CFG_PROMISC 0x00000008 /* promisc mode enable */ 754 #define MAC_RX_CFG_PROMISC_GROUP 0x00000010 /* accept all MC frames */ 755 #define MAC_RX_CFG_HASH_FILTER_EN 0x00000020 /* use hash table */ 756 #define MAC_RX_CFG_ADDR_FILTER_EN 0x00000040 /* use address filter */ 757 #define MAC_RX_CFG_DISABLE_DISCARD 0x00000080 /* do not set abort bit */ 758 #define MAC_RX_MAC2IPP_PKT_CNT_EN 0x00000200 /* rx pkt cnt -> BMAC-IPP */ 759 #define MAC_RX_MAC_REG_RW_TEST_MASK 0x00000c00 /* BMAC reg RW test */ 760 #define MAC_RX_MAC_REG_RW_TEST_SHIFT 10 761 762 /* MAC Control Configuration Register */ 763 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x00000001 /* send pause flow ctrl */ 764 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x00000002 /* receive pause flow ctrl */ 765 #define MAC_CTRL_CFG_PASS_CTRL 0x00000004 /* accept MAC ctrl pkts */ 766 767 /* MAC XIF Configuration Register */ 768 #define MAC_XIF_TX_OUTPUT_EN 0x00000001 /* enable Tx output driver */ 769 #define MAC_XIF_MII_INT_LOOPBACK 0x00000002 /* loopback GMII xmit data */ 770 #define MAC_XIF_GMII_MODE 0x00000008 /* operates with GMII clks */ 771 #define MAC_XIF_LINK_LED 0x00000020 /* LINKLED# active (low) */ 772 #define MAC_XIF_LED_POLARITY 0x00000040 /* LED polarity */ 773 #define MAC_XIF_SEL_CLK_25MHZ 0x00000080 /* Select 10/100Mbps */ 774 775 /* MAC IPG Registers */ 776 #define BMAC_MIN_FRAME_MASK 0x3FF /* 10-bit reg */ 777 778 /* MAC Max Frame Size Register */ 779 #define BMAC_MAX_BURST_MASK 0x3FFF0000 /* max burst size [30:16] */ 780 #define BMAC_MAX_BURST_SHIFT 16 781 #define BMAC_MAX_FRAME_MASK 0x00007FFF /* max frame size [14:0] */ 782 #define BMAC_MAX_FRAME_SHIFT 0 783 784 /* MAC Preamble size register */ 785 #define BMAC_PA_SIZE_MASK 0x000003FF 786 /* # of preable bytes TxMAC sends at the beginning of each frame */ 787 788 /* 789 * mac address registers: 790 * register contains comparison 791 * -------- -------- ---------- 792 * 0 16 MSB of primary MAC addr [47:32] of DA field 793 * 1 16 middle bits "" [31:16] of DA field 794 * 2 16 LSB "" [15:0] of DA field 795 * 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field 796 * 4*x 16 middle bits "" [31:16] 797 * 5*x 16 LSB "" [15:0] 798 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 799 * 43 16 middle bits "" [31:16] 800 * 44 16 LSB "" [15:0] 801 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 802 * if there is a match, MAC will set the bit for alternative address 803 * filter pass [15] 804 * 805 * here is the map of registers given MAC address notation: a:b:c:d:e:f 806 * ab cd ef 807 * primary addr reg 2 reg 1 reg 0 808 * alt addr 1 reg 5 reg 4 reg 3 809 * alt addr x reg 5*x reg 4*x reg 3*x 810 * | | | | 811 * | | | | 812 * alt addr 7 reg 23 reg 22 reg 21 813 * ctrl addr reg 44 reg 43 reg 42 814 */ 815 816 #define BMAC_ALT_ADDR_BASE 0x118 817 #define BMAC_MAX_ALT_ADDR_ENTRY 7 /* 7 alternate MAC addr */ 818 #define BMAC_MAX_ADDR_ENTRY (BMAC_MAX_ALT_ADDR_ENTRY + 1) 819 820 /* hash table registers */ 821 #define MAC_MAX_HASH_ENTRY 16 822 823 /* 27-bit register has the current state for key state machines in the MAC */ 824 #define MAC_SM_RLM_MASK 0x07800000 825 #define MAC_SM_RLM_SHIFT 23 826 #define MAC_SM_RX_FC_MASK 0x00700000 827 #define MAC_SM_RX_FC_SHIFT 20 828 #define MAC_SM_TLM_MASK 0x000F0000 829 #define MAC_SM_TLM_SHIFT 16 830 #define MAC_SM_ENCAP_SM_MASK 0x0000F000 831 #define MAC_SM_ENCAP_SM_SHIFT 12 832 #define MAC_SM_TX_REQ_MASK 0x00000C00 833 #define MAC_SM_TX_REQ_SHIFT 10 834 #define MAC_SM_TX_FC_MASK 0x000003C0 835 #define MAC_SM_TX_FC_SHIFT 6 836 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 837 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 838 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 839 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 840 841 #define BMAC_ADDR0_CMPEN 0x00000001 842 #define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x)) 843 844 /* MAC Host Info Table Registers */ 845 #define BMAC_MAX_HOST_INFO_ENTRY 9 /* 9 host entries */ 846 847 /* 848 * ********************* XMAC registers ********************************* 849 */ 850 851 /* Reset Register */ 852 #define XTXMAC_SOFT_RST 0x00000001 /* XTX MAC software reset */ 853 #define XTXMAC_REG_RST 0x00000002 /* XTX MAC registers reset */ 854 #define XRXMAC_SOFT_RST 0x00000001 /* XRX MAC software reset */ 855 #define XRXMAC_REG_RST 0x00000002 /* XRX MAC registers reset */ 856 857 /* XTX MAC Status Register */ 858 #define XMAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 859 #define XMAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 860 #define XMAC_TX_MAX_PACKET_ERR 0x00000004 /* XTX frame exceeds max */ 861 #define XMAC_TX_OVERFLOW 0x00000008 /* XTX byte cnt overflow */ 862 #define XMAC_TX_FIFO_XFR_ERR 0x00000010 /* xtlm state mach error */ 863 #define XMAC_TX_BYTE_CNT_EXP 0x00000400 /* XTX byte cnt overflow */ 864 #define XMAC_TX_FRAME_CNT_EXP 0x00000800 /* XTX frame cnt overflow */ 865 866 /* XRX MAC Status Register */ 867 #define XMAC_RX_FRAME_RCVD 0x00000001 /* successful rx frame */ 868 #define XMAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 869 #define XMAC_RX_UNDERFLOW 0x00000004 /* RX FIFO underrun */ 870 #define XMAC_RX_CRC_ERR_CNT_EXP 0x00000008 /* crc error cnt rollover */ 871 #define XMAC_RX_LEN_ERR_CNT_EXP 0x00000010 /* length err cnt rollover */ 872 #define XMAC_RX_VIOL_ERR_CNT_EXP 0x00000020 /* code vio err rollover */ 873 #define XMAC_RX_OCT_CNT_EXP 0x00000040 /* XRX MAC byte rollover */ 874 #define XMAC_RX_HST_CNT1_EXP 0x00000080 /* XRX MAC hist1 rollover */ 875 #define XMAC_RX_HST_CNT2_EXP 0x00000100 /* XRX MAC hist2 rollover */ 876 #define XMAC_RX_HST_CNT3_EXP 0x00000200 /* XRX MAC hist3 rollover */ 877 #define XMAC_RX_HST_CNT4_EXP 0x00000400 /* XRX MAC hist4 rollover */ 878 #define XMAC_RX_HST_CNT5_EXP 0x00000800 /* XRX MAC hist5 rollover */ 879 #define XMAC_RX_HST_CNT6_EXP 0x00001000 /* XRX MAC hist6 rollover */ 880 #define XMAC_RX_BCAST_CNT_EXP 0x00002000 /* XRX BC cnt rollover */ 881 #define XMAC_RX_MCAST_CNT_EXP 0x00004000 /* XRX MC cnt rollover */ 882 #define XMAC_RX_FRAG_CNT_EXP 0x00008000 /* fragment cnt rollover */ 883 #define XMAC_RX_ALIGNERR_CNT_EXP 0x00010000 /* framealign err rollover */ 884 #define XMAC_RX_LINK_FLT_CNT_EXP 0x00020000 /* link fault cnt rollover */ 885 #define XMAC_RX_REMOTE_FLT_DET 0x00040000 /* Remote Fault detected */ 886 #define XMAC_RX_LOCAL_FLT_DET 0x00080000 /* Local Fault detected */ 887 #define XMAC_RX_HST_CNT7_EXP 0x00100000 /* XRX MAC hist7 rollover */ 888 889 890 #define XMAC_CTRL_PAUSE_RCVD 0x00000001 /* successful pause frame */ 891 #define XMAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 892 #define XMAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 893 #define XMAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 894 #define XMAC_CTRL_PAUSE_TIME_SHIFT 16 895 896 /* XMAC Configuration Register */ 897 #define XMAC_CONFIG_TX_BIT_MASK 0x000000ff /* bits [7:0] */ 898 #define XMAC_CONFIG_RX_BIT_MASK 0x001fff00 /* bits [20:8] */ 899 #define XMAC_CONFIG_XIF_BIT_MASK 0xffe00000 /* bits [31:21] */ 900 901 /* XTX MAC config bits */ 902 #define XMAC_TX_CFG_TX_ENABLE 0x00000001 /* enable XTX MAC */ 903 #define XMAC_TX_CFG_STRETCH_MD 0x00000002 /* WAN application */ 904 #define XMAC_TX_CFG_VAR_MIN_IPG_EN 0x00000004 /* Transmit pkts < minpsz */ 905 #define XMAC_TX_CFG_ALWAYS_NO_CRC 0x00000008 /* No CRC generated */ 906 907 #define XMAC_WARNING_MSG_ENABLE 0x00000080 /* Sim warning msg enable */ 908 909 /* XRX MAC config bits */ 910 #define XMAC_RX_CFG_RX_ENABLE 0x00000100 /* enable XRX MAC */ 911 #define XMAC_RX_CFG_PROMISC 0x00000200 /* promisc mode enable */ 912 #define XMAC_RX_CFG_PROMISC_GROUP 0x00000400 /* accept all MC frames */ 913 #define XMAC_RX_CFG_ERR_CHK_DISABLE 0x00000800 /* do not set abort bit */ 914 #define XMAC_RX_CFG_CRC_CHK_DISABLE 0x00001000 /* disable CRC logic */ 915 #define XMAC_RX_CFG_RESERVED_MCAST 0x00002000 /* reserved MCaddr compare */ 916 #define XMAC_RX_CFG_CD_VIO_CHK 0x00004000 /* rx code violation chk */ 917 #define XMAC_RX_CFG_HASH_FILTER_EN 0x00008000 /* use hash table */ 918 #define XMAC_RX_CFG_ADDR_FILTER_EN 0x00010000 /* use alt addr filter */ 919 #define XMAC_RX_CFG_STRIP_CRC 0x00020000 /* strip last 4bytes (CRC) */ 920 #define XMAC_RX_MAC2IPP_PKT_CNT_EN 0x00040000 /* histo_cntr7 cnt mode */ 921 #define XMAC_RX_CFG_RX_PAUSE_EN 0x00080000 /* receive pause flow ctrl */ 922 #define XMAC_RX_CFG_PASS_FLOW_CTRL 0x00100000 /* accept MAC ctrl pkts */ 923 924 925 /* MAC transceiver (XIF) configuration registers */ 926 927 #define XMAC_XIF_FORCE_LED_ON 0x00200000 /* Force Link LED on */ 928 #define XMAC_XIF_LED_POLARITY 0x00400000 /* LED polarity */ 929 #define XMAC_XIF_SEL_POR_CLK_SRC 0x00800000 /* Select POR clk src */ 930 #define XMAC_XIF_TX_OUTPUT_EN 0x01000000 /* enable MII/GMII modes */ 931 #define XMAC_XIF_LOOPBACK 0x02000000 /* loopback xmac xgmii tx */ 932 #define XMAC_XIF_LFS_DISABLE 0x04000000 /* disable link fault sig */ 933 #define XMAC_XIF_MII_MODE_MASK 0x18000000 /* MII/GMII/XGMII mode */ 934 #define XMAC_XIF_MII_MODE_SHIFT 27 935 #define XMAC_XIF_XGMII_MODE 0x00 936 #define XMAC_XIF_GMII_MODE 0x01 937 #define XMAC_XIF_MII_MODE 0x02 938 #define XMAC_XIF_ILLEGAL_MODE 0x03 939 #define XMAC_XIF_XPCS_BYPASS 0x20000000 /* use external xpcs */ 940 #define XMAC_XIF_1G_PCS_BYPASS 0x40000000 /* use external pcs */ 941 #define XMAC_XIF_SEL_CLK_25MHZ 0x80000000 /* 25Mhz clk for 100mbps */ 942 943 /* IPG register */ 944 #define XMAC_IPG_VALUE_MASK 0x00000007 /* IPG in XGMII mode */ 945 #define XMAC_IPG_VALUE_SHIFT 0 946 #define XMAC_IPG_VALUE1_MASK 0x0000ff00 /* IPG in GMII/MII mode */ 947 #define XMAC_IPG_VALUE1_SHIFT 8 948 #define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000 949 #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 950 #define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000 951 #define XMAC_IPG_STRETCH_CONST_SHIFT 21 952 953 #define IPG_12_15_BYTE 3 954 #define IPG_16_19_BYTE 4 955 #define IPG_20_23_BYTE 5 956 #define IPG1_12_BYTES 10 957 #define IPG1_13_BYTES 11 958 #define IPG1_14_BYTES 12 959 #define IPG1_15_BYTES 13 960 #define IPG1_16_BYTES 14 961 962 963 #define XMAC_MIN_TX_FRM_SZ_MASK 0x3ff /* Min tx frame size */ 964 #define XMAC_MIN_TX_FRM_SZ_SHIFT 0 965 #define XMAC_SLOT_TIME_MASK 0x0003fc00 /* slot time */ 966 #define XMAC_SLOT_TIME_SHIFT 10 967 #define XMAC_MIN_RX_FRM_SZ_MASK 0x3ff00000 /* Min rx frame size */ 968 #define XMAC_MIN_RX_FRM_SZ_SHIFT 20 969 #define XMAC_MAX_FRM_SZ_MASK 0x00003fff /* max tx frame size */ 970 971 /* State Machine Register */ 972 #define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007 973 #define XMAC_SM_TX_LNK_MGMT_SHIFT 0 974 #define XMAC_SM_SOP_DETECT 0x00000008 975 #define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030 976 #define XMAC_SM_LNK_FLT_SIG_SHIFT 4 977 #define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040 978 #define XMAC_SM_XGMII_MD_RX_LNK 0x00000080 979 #define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100 980 #define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200 981 #define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00 982 #define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10 983 #define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000 984 #define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18 985 #define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000 986 #define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23 987 #define XMAC_SM_TXFIFO_FULL_CLK 0x10000000 988 #define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000 989 #define XMAC_SM_RXFIFO_FULL_CLK 0x40000000 990 #define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000 991 992 /* Internal Signals 1 Register */ 993 #define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F 994 #define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0 995 #define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010 996 #define XMAC_IS1_OPP_TXMAC_TAG 0x00000020 997 #define XMAC_IS1_OPP_TXMAC_ACK 0x00000040 998 #define XMAC_IS1_TXMAC_OPP_REQ 0x00000080 999 #define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00 1000 #define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8 1001 #define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000 1002 #define XMAC_IS1_RXMAC_IPP_TAG 0x20000000 1003 #define XMAC_IS1_IPP_RXMAC_REQ 0x40000000 1004 #define XMAC_IS1_RXMAC_IPP_ACK 0x80000000 1005 1006 /* Internal Signals 2 Register */ 1007 #define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F 1008 #define XMAC_IS2_TX_HB_TIMER_SHIFT 0 1009 #define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0 1010 #define XMAC_IS2_RX_HB_TIMER_SHIFT 4 1011 #define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00 1012 #define XMAC_IS2_XPCS_RXC_SHIFT 8 1013 #define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000 1014 #define XMAC_IS2_XPCS_TXC_SHIFT 16 1015 #define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000 1016 #define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000 1017 1018 /* Register size masking */ 1019 1020 #define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF 1021 #define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF 1022 #define XRXMAC_CRC_ER_CNT_MASK 0x000000FF 1023 #define XRXMAC_MPSZER_CNT_MASK 0x000000FF 1024 #define XRXMAC_CD_VIO_CNT_MASK 0x000000FF 1025 #define XRXMAC_BT_CNT_MASK 0xFFFFFFFF 1026 #define XRXMAC_HIST_CNT1_MASK 0x001FFFFF 1027 #define XRXMAC_HIST_CNT2_MASK 0x001FFFFF 1028 #define XRXMAC_HIST_CNT3_MASK 0x000FFFFF 1029 #define XRXMAC_HIST_CNT4_MASK 0x0007FFFF 1030 #define XRXMAC_HIST_CNT5_MASK 0x0003FFFF 1031 #define XRXMAC_HIST_CNT6_MASK 0x0001FFFF 1032 #define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF 1033 #define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF 1034 #define XRXMAC_FRAG_CNT_MASK 0x001FFFFF 1035 #define XRXMAC_AL_ER_CNT_MASK 0x000000FF 1036 #define XMAC_LINK_FLT_CNT_MASK 0x000000FF 1037 #define BTXMAC_FRM_CNT_MASK 0x001FFFFF 1038 #define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF 1039 #define RXMAC_FRM_CNT_MASK 0x0000FFFF 1040 #define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF 1041 #define BMAC_AL_ER_CNT_MASK 0x0000FFFF 1042 #define MAC_LEN_ER_CNT_MASK 0x0000FFFF 1043 #define BMAC_CRC_ER_CNT_MASK 0x0000FFFF 1044 #define BMAC_CD_VIO_CNT_MASK 0x0000FFFF 1045 #define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF 1046 #define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF 1047 #define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000 1048 #define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16 1049 #define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF 1050 #define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000 1051 #define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16 1052 1053 /* Alternate MAC address registers */ 1054 #define XMAC_MAX_ALT_ADDR_ENTRY 16 /* 16 alternate MAC addrs */ 1055 #define XMAC_MAX_ADDR_ENTRY (XMAC_MAX_ALT_ADDR_ENTRY + 1) 1056 1057 /* Max / Min parameters for Neptune MAC */ 1058 1059 #define MAC_MAX_ALT_ADDR_ENTRY XMAC_MAX_ALT_ADDR_ENTRY 1060 #define MAC_MAX_HOST_INFO_ENTRY XMAC_MAX_HOST_INFO_ENTRY 1061 1062 /* HostInfo entry for the unique MAC address */ 1063 #define XMAC_UNIQUE_HOST_INFO_ENTRY 17 1064 #define BMAC_UNIQUE_HOST_INFO_ENTRY 0 1065 1066 /* HostInfo entry for the multicat address */ 1067 #define XMAC_MULTI_HOST_INFO_ENTRY 16 1068 #define BMAC_MULTI_HOST_INFO_ENTRY 8 1069 1070 /* XMAC Host Info Register */ 1071 typedef union hostinfo { 1072 1073 uint64_t value; 1074 1075 struct { 1076 #if defined(_BIG_ENDIAN) 1077 uint32_t msw; /* Most significant word */ 1078 uint32_t lsw; /* Least significant word */ 1079 #elif defined(_LITTLE_ENDIAN) 1080 uint32_t lsw; /* Least significant word */ 1081 uint32_t msw; /* Most significant word */ 1082 #endif 1083 } val; 1084 struct { 1085 #if defined(_BIG_ENDIAN) 1086 uint32_t w1; 1087 #endif 1088 struct { 1089 #if defined(_BIT_FIELDS_HTOL) 1090 uint32_t reserved2 : 23; 1091 uint32_t mac_pref : 1; 1092 uint32_t reserved1 : 5; 1093 uint32_t rdc_tbl_num : 3; 1094 #elif defined(_BIT_FIELDS_LTOH) 1095 uint32_t rdc_tbl_num : 3; 1096 uint32_t reserved1 : 5; 1097 uint32_t mac_pref : 1; 1098 uint32_t reserved2 : 23; 1099 #endif 1100 } w0; 1101 1102 #if defined(_LITTLE_ENDIAN) 1103 uint32_t w1; 1104 #endif 1105 } bits; 1106 1107 } hostinfo_t; 1108 1109 typedef union hostinfo *hostinfo_pt; 1110 1111 #define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007 1112 #define XMAC_HI_MAC_PREF 0x00000100 1113 1114 #define XMAC_MAX_HOST_INFO_ENTRY 20 /* 20 host entries */ 1115 1116 /* 1117 * ******************** MIF registers ********************************* 1118 */ 1119 1120 /* 1121 * 32-bit register serves as an instruction register when the MIF is 1122 * programmed in frame mode. load this register w/ a valid instruction 1123 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1124 * execution completion. during a read operation, this register will also 1125 * contain the 16-bit data returned by the transceiver. unless specified 1126 * otherwise, fields are considered "don't care" when polling for 1127 * completion. 1128 */ 1129 1130 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame mask */ 1131 #define MIF_FRAME_ST_22 0x40000000 /* STart of frame, Cl 22 */ 1132 #define MIF_FRAME_ST_45 0x00000000 /* STart of frame, Cl 45 */ 1133 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode */ 1134 #define MIF_FRAME_OP_READ_22 0x20000000 /* read OPcode, Cl 22 */ 1135 #define MIF_FRAME_OP_WRITE_22 0x10000000 /* write OPcode, Cl 22 */ 1136 #define MIF_FRAME_OP_ADDR_45 0x00000000 /* addr of reg to access */ 1137 #define MIF_FRAME_OP_READ_45 0x30000000 /* read OPcode, Cl 45 */ 1138 #define MIF_FRAME_OP_WRITE_45 0x10000000 /* write OPcode, Cl 45 */ 1139 #define MIF_FRAME_OP_P_R_I_A_45 0x10000000 /* post-read-inc-addr */ 1140 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address mask */ 1141 #define MIF_FRAME_PHY_ADDR_SHIFT 23 1142 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* reg addr in Cl 22 */ 1143 /* dev addr in Cl 45 */ 1144 #define MIF_FRAME_REG_ADDR_SHIFT 18 1145 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. */ 1146 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. */ 1147 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload */ 1148 1149 /* Clause 45 frame field values */ 1150 #define FRAME45_ST 0 1151 #define FRAME45_OP_ADDR 0 1152 #define FRAME45_OP_WRITE 1 1153 #define FRAME45_OP_READ_INC 2 1154 #define FRAME45_OP_READ 3 1155 1156 typedef union _mif_frame_t { 1157 1158 uint64_t value; 1159 1160 struct { 1161 #if defined(_BIG_ENDIAN) 1162 uint32_t msw; /* Most significant word */ 1163 uint32_t lsw; /* Least significant word */ 1164 #elif defined(_LITTLE_ENDIAN) 1165 uint32_t lsw; /* Least significant word */ 1166 uint32_t msw; /* Most significant word */ 1167 #endif 1168 } val; 1169 struct { 1170 #if defined(_BIG_ENDIAN) 1171 uint32_t w1; 1172 #endif 1173 struct { 1174 #if defined(_BIT_FIELDS_HTOL) 1175 uint32_t st : 2; 1176 uint32_t op : 2; 1177 uint32_t phyad : 5; 1178 uint32_t regad : 5; 1179 uint32_t ta_msb : 1; 1180 uint32_t ta_lsb : 1; 1181 uint32_t data : 16; 1182 #elif defined(_BIT_FIELDS_LTOH) 1183 uint32_t data : 16; 1184 uint32_t ta_lsb : 1; 1185 uint32_t ta_msb : 1; 1186 uint32_t regad : 5; 1187 uint32_t phyad : 5; 1188 uint32_t op : 2; 1189 uint32_t st : 2; 1190 #endif 1191 } w0; 1192 1193 #if defined(_LITTLE_ENDIAN) 1194 uint32_t w1; 1195 #endif 1196 } bits; 1197 } mif_frame_t; 1198 1199 #define MIF_CFG_POLL_EN 0x00000008 /* enable polling */ 1200 #define MIF_CFG_BB_MODE 0x00000010 /* bit-bang mode */ 1201 #define MIF_CFG_POLL_REG_MASK 0x000003E0 /* reg addr to be polled */ 1202 #define MIF_CFG_POLL_REG_SHIFT 5 1203 #define MIF_CFG_POLL_PHY_MASK 0x00007C00 /* XCVR addr to be polled */ 1204 #define MIF_CFG_POLL_PHY_SHIFT 10 1205 #define MIF_CFG_INDIRECT_MODE 0x0000800 1206 /* used to decide if Cl 22 */ 1207 /* or Cl 45 frame is */ 1208 /* constructed. */ 1209 /* 1 = Clause 45,ST = '00' */ 1210 /* 0 = Clause 22,ST = '01' */ 1211 #define MIF_CFG_ATCE_GE_EN 0x00010000 /* Enable ATCA gigabit mode */ 1212 1213 typedef union _mif_cfg_t { 1214 1215 uint64_t value; 1216 1217 struct { 1218 #if defined(_BIG_ENDIAN) 1219 uint32_t msw; /* Most significant word */ 1220 uint32_t lsw; /* Least significant word */ 1221 1222 #elif defined(_LITTLE_ENDIAN) 1223 uint32_t lsw; /* Least significant word */ 1224 uint32_t msw; /* Most significant word */ 1225 #endif 1226 } val; 1227 struct { 1228 #if defined(_BIG_ENDIAN) 1229 uint32_t w1; 1230 #endif 1231 struct { 1232 #if defined(_BIT_FIELDS_HTOL) 1233 uint32_t res2 : 15; 1234 uint32_t atca_ge : 1; 1235 uint32_t indirect_md : 1; 1236 uint32_t phy_addr : 5; 1237 uint32_t reg_addr : 5; 1238 uint32_t bb_mode : 1; 1239 uint32_t poll_en : 1; 1240 uint32_t res1 : 2; 1241 uint32_t res : 1; 1242 #elif defined(_BIT_FIELDS_LTOH) 1243 uint32_t res : 1; 1244 uint32_t res1 : 2; 1245 uint32_t poll_en : 1; 1246 uint32_t bb_mode : 1; 1247 uint32_t reg_addr : 5; 1248 uint32_t phy_addr : 5; 1249 uint32_t indirect_md : 1; 1250 uint32_t atca_ge : 1; 1251 uint32_t res2 : 15; 1252 #endif 1253 } w0; 1254 1255 #if defined(_LITTLE_ENDIAN) 1256 uint32_t w1; 1257 #endif 1258 } bits; 1259 1260 } mif_cfg_t; 1261 1262 #define MIF_POLL_STATUS_DATA_MASK 0xffff0000 1263 #define MIF_POLL_STATUS_STAT_MASK 0x0000ffff 1264 1265 typedef union _mif_poll_stat_t { 1266 uint64_t value; 1267 1268 struct { 1269 #if defined(_BIG_ENDIAN) 1270 uint32_t msw; /* Most significant word */ 1271 uint32_t lsw; /* Least significant word */ 1272 #elif defined(_LITTLE_ENDIAN) 1273 uint32_t lsw; /* Least significant word */ 1274 uint32_t msw; /* Most significant word */ 1275 #endif 1276 } val; 1277 struct { 1278 #if defined(_BIG_ENDIAN) 1279 uint32_t w1; 1280 #endif 1281 struct { 1282 #if defined(_BIT_FIELDS_HTOL) 1283 uint16_t data; 1284 uint16_t status; 1285 #elif defined(_BIT_FIELDS_LTOH) 1286 uint16_t status; 1287 uint16_t data; 1288 #endif 1289 } w0; 1290 1291 #if defined(_LITTLE_ENDIAN) 1292 uint32_t w1; 1293 #endif 1294 } bits; 1295 } mif_poll_stat_t; 1296 1297 1298 #define MIF_POLL_MASK_MASK 0x0000ffff 1299 1300 typedef union _mif_poll_mask_t { 1301 uint64_t value; 1302 1303 struct { 1304 #if defined(_BIG_ENDIAN) 1305 uint32_t msw; /* Most significant word */ 1306 uint32_t lsw; /* Least significant word */ 1307 #elif defined(_LITTLE_ENDIAN) 1308 uint32_t lsw; /* Least significant word */ 1309 uint32_t msw; /* Most significant word */ 1310 #endif 1311 } val; 1312 struct { 1313 #if defined(_BIG_ENDIAN) 1314 uint32_t w1; 1315 #endif 1316 struct { 1317 #if defined(_BIT_FIELDS_HTOL) 1318 uint16_t rsvd; 1319 uint16_t mask; 1320 #elif defined(_BIT_FIELDS_LTOH) 1321 uint16_t mask; 1322 uint16_t rsvd; 1323 #endif 1324 } w0; 1325 1326 #if defined(_LITTLE_ENDIAN) 1327 uint32_t w1; 1328 #endif 1329 } bits; 1330 } mif_poll_mask_t; 1331 1332 #define MIF_STATUS_INIT_DONE_MASK 0x00000001 1333 #define MIF_STATUS_XGE_ERR0_MASK 0x00000002 1334 #define MIF_STATUS_XGE_ERR1_MASK 0x00000004 1335 #define MIF_STATUS_PEU_ERR_MASK 0x00000008 1336 #define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010 1337 #define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020 1338 1339 typedef union _mif_stat_t { 1340 uint64_t value; 1341 1342 struct { 1343 #if defined(_BIG_ENDIAN) 1344 uint32_t msw; /* Most significant word */ 1345 uint32_t lsw; /* Least significant word */ 1346 #elif defined(_LITTLE_ENDIAN) 1347 uint32_t lsw; /* Least significant word */ 1348 uint32_t msw; /* Most significant word */ 1349 #endif 1350 } val; 1351 struct { 1352 #if defined(_BIG_ENDIAN) 1353 uint32_t w1; 1354 #endif 1355 struct { 1356 #if defined(_BIT_FIELDS_HTOL) 1357 uint32_t rsvd:26; 1358 uint32_t ext_phy_intr_flag1:1; 1359 uint32_t ext_phy_intr_flag0:1; 1360 uint32_t peu_err:1; 1361 uint32_t xge_err1:1; 1362 uint32_t xge_err0:1; 1363 uint32_t mif_init_done_stat:1; 1364 1365 #elif defined(_BIT_FIELDS_LTOH) 1366 uint32_t mif_init_done_stat:1; 1367 uint32_t xge_err0:1; 1368 uint32_t xge_err1:1; 1369 uint32_t ext_phy_intr_flag0:1; 1370 uint32_t ext_phy_intr_flag1:1; 1371 uint32_t rsvd:26; 1372 #endif 1373 } w0; 1374 1375 #if defined(_LITTLE_ENDIAN) 1376 uint32_t w1; 1377 #endif 1378 } bits; 1379 } mif_stat_t; 1380 1381 /* MIF State Machine Register */ 1382 1383 #define MIF_SM_EXECUTION_MASK 0x0000003f /* execution state */ 1384 #define MIF_SM_EXECUTION_SHIFT 0 1385 #define MIF_SM_CONTROL_MASK 0x000001c0 /* control state */ 1386 #define MIF_SM_CONTROL_MASK_SHIFT 6 1387 #define MIF_SM_MDI 0x00000200 1388 #define MIF_SM_MDO 0x00000400 1389 #define MIF_SM_MDO_EN 0x00000800 1390 #define MIF_SM_MDC 0x00001000 1391 #define MIF_SM_MDI_0 0x00002000 1392 #define MIF_SM_MDI_1 0x00004000 1393 #define MIF_SM_MDI_2 0x00008000 1394 #define MIF_SM_PORT_ADDR_MASK 0x001f0000 1395 #define MIF_SM_PORT_ADDR_SHIFT 16 1396 #define MIF_SM_INT_SIG_MASK 0xffe00000 1397 #define MIF_SM_INT_SIG_SHIFT 21 1398 1399 1400 /* 1401 * ******************** PCS registers ********************************* 1402 */ 1403 1404 /* PCS Registers */ 1405 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on wr */ 1406 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal */ 1407 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. */ 1408 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. */ 1409 #define PCS_MII_ISOLATE 0x0400 /* read 0. ignored on wr */ 1410 #define PCS_MII_POWER_DOWN 0x0800 /* read 0. ignored on wr */ 1411 #define PCS_MII_AUTONEG_EN 0x1000 /* autonegotiation */ 1412 #define PCS_MII_10_100_SEL 0x2000 /* read 0. ignored on wr */ 1413 #define PCS_MII_RESET 0x8000 /* reset PCS. */ 1414 1415 typedef union _pcs_ctrl_t { 1416 uint64_t value; 1417 1418 struct { 1419 #if defined(_BIG_ENDIAN) 1420 uint32_t msw; /* Most significant word */ 1421 uint32_t lsw; /* Least significant word */ 1422 #elif defined(_LITTLE_ENDIAN) 1423 uint32_t lsw; /* Least significant word */ 1424 uint32_t msw; /* Most significant word */ 1425 #endif 1426 } val; 1427 struct { 1428 #if defined(_BIG_ENDIAN) 1429 uint32_t w1; 1430 #endif 1431 struct { 1432 #if defined(_BIT_FIELDS_HTOL) 1433 uint32_t res0 : 16; 1434 uint32_t reset : 1; 1435 uint32_t res1 : 1; 1436 uint32_t sel_10_100 : 1; 1437 uint32_t an_enable : 1; 1438 uint32_t pwr_down : 1; 1439 uint32_t isolate : 1; 1440 uint32_t restart_an : 1; 1441 uint32_t duplex : 1; 1442 uint32_t col_test : 1; 1443 uint32_t sel_1000 : 1; 1444 uint32_t res2 : 6; 1445 #elif defined(_BIT_FIELDS_LTOH) 1446 uint32_t res2 : 6; 1447 uint32_t sel_1000 : 1; 1448 uint32_t col_test : 1; 1449 uint32_t duplex : 1; 1450 uint32_t restart_an : 1; 1451 uint32_t isolate : 1; 1452 uint32_t pwr_down : 1; 1453 uint32_t an_enable : 1; 1454 uint32_t sel_10_100 : 1; 1455 uint32_t res1 : 1; 1456 uint32_t reset : 1; 1457 uint32_t res0 : 16; 1458 #endif 1459 } w0; 1460 1461 #if defined(_LITTLE_ENDIAN) 1462 uint32_t w1; 1463 #endif 1464 } bits; 1465 } pcs_ctrl_t; 1466 1467 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1468 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1469 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* link status */ 1470 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 */ 1471 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* remote fault detected */ 1472 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* auto-neg completed */ 1473 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* 1000 Base-X PHY */ 1474 1475 typedef union _pcs_stat_t { 1476 uint64_t value; 1477 1478 struct { 1479 #if defined(_BIG_ENDIAN) 1480 uint32_t msw; /* Most significant word */ 1481 uint32_t lsw; /* Least significant word */ 1482 #elif defined(_LITTLE_ENDIAN) 1483 uint32_t lsw; /* Least significant word */ 1484 uint32_t msw; /* Most significant word */ 1485 #endif 1486 } val; 1487 struct { 1488 #if defined(_BIG_ENDIAN) 1489 uint32_t w1; 1490 #endif 1491 struct { 1492 #if defined(_BIT_FIELDS_HTOL) 1493 uint32_t res0 : 23; 1494 uint32_t ext_stat : 1; 1495 uint32_t res1 : 2; 1496 uint32_t an_complete : 1; 1497 uint32_t remote_fault : 1; 1498 uint32_t an_able : 1; 1499 uint32_t link_stat : 1; 1500 uint32_t jabber_detect : 1; 1501 uint32_t ext_cap : 1; 1502 #elif defined(_BIT_FIELDS_LTOH) 1503 uint32_t ext_cap : 1; 1504 uint32_t jabber_detect : 1; 1505 uint32_t link_stat : 1; 1506 uint32_t an_able : 1; 1507 uint32_t remote_fault : 1; 1508 uint32_t an_complete : 1; 1509 uint32_t res1 : 2; 1510 uint32_t ext_stat : 1; 1511 uint32_t res0 : 23; 1512 #endif 1513 } w0; 1514 1515 #if defined(_LITTLE_ENDIAN) 1516 uint32_t w1; 1517 #endif 1518 } bits; 1519 } pcs_stat_t; 1520 1521 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex */ 1522 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex */ 1523 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE sym */ 1524 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE asym */ 1525 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault */ 1526 #define PCS_MII_ADVERT_RF_SHIFT 12 1527 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1528 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1529 1530 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1531 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1532 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1533 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1534 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1535 #define PCS_MII_LPA_RF_SHIFT PCS_MII_ADVERT_RF_SHIFT 1536 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1537 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1538 1539 typedef union _pcs_anar_t { 1540 uint64_t value; 1541 1542 struct { 1543 #if defined(_BIG_ENDIAN) 1544 uint32_t msw; /* Most significant word */ 1545 uint32_t lsw; /* Least significant word */ 1546 #elif defined(_LITTLE_ENDIAN) 1547 uint32_t lsw; /* Least significant word */ 1548 uint32_t msw; /* Most significant word */ 1549 #endif 1550 } val; 1551 struct { 1552 #if defined(_BIG_ENDIAN) 1553 uint32_t w1; 1554 #endif 1555 struct { 1556 #if defined(_BIT_FIELDS_HTOL) 1557 uint32_t res0 : 16; 1558 uint32_t next_page : 1; 1559 uint32_t ack : 1; 1560 uint32_t remote_fault : 2; 1561 uint32_t res1 : 3; 1562 uint32_t asm_pause : 1; 1563 uint32_t pause : 1; 1564 uint32_t half_duplex : 1; 1565 uint32_t full_duplex : 1; 1566 uint32_t res2 : 5; 1567 #elif defined(_BIT_FIELDS_LTOH) 1568 uint32_t res2 : 5; 1569 uint32_t full_duplex : 1; 1570 uint32_t half_duplex : 1; 1571 uint32_t pause : 1; 1572 uint32_t asm_pause : 1; 1573 uint32_t res1 : 3; 1574 uint32_t remore_fault : 2; 1575 uint32_t ack : 1; 1576 uint32_t next_page : 1; 1577 uint32_t res0 : 16; 1578 #endif 1579 } w0; 1580 1581 #if defined(_LITTLE_ENDIAN) 1582 uint32_t w1; 1583 #endif 1584 } bits; 1585 } pcs_anar_t, *p_pcs_anar_t; 1586 1587 #define PCS_CFG_EN 0x0001 /* enable PCS. */ 1588 #define PCS_CFG_SD_OVERRIDE 0x0002 1589 #define PCS_CFG_SD_ACTIVE_LOW 0x0004 /* sig detect active low */ 1590 #define PCS_CFG_JITTER_STUDY_MASK 0x0018 /* jitter measurements */ 1591 #define PCS_CFG_JITTER_STUDY_SHIFT 4 1592 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x0020 /* shortens autoneg timer */ 1593 #define PCS_CFG_MASK 0x0040 /* PCS global mask bit */ 1594 1595 typedef union _pcs_cfg_t { 1596 uint64_t value; 1597 1598 struct { 1599 #if defined(_BIG_ENDIAN) 1600 uint32_t msw; /* Most significant word */ 1601 uint32_t lsw; /* Least significant word */ 1602 #elif defined(_LITTLE_ENDIAN) 1603 uint32_t lsw; /* Least significant word */ 1604 uint32_t msw; /* Most significant word */ 1605 #endif 1606 } val; 1607 struct { 1608 #if defined(_BIG_ENDIAN) 1609 uint32_t w1; 1610 #endif 1611 struct { 1612 #if defined(_BIT_FIELDS_HTOL) 1613 uint32_t res0 : 25; 1614 uint32_t mask : 1; 1615 uint32_t override_10ms_timer : 1; 1616 uint32_t jitter_study : 2; 1617 uint32_t sig_det_a_low : 1; 1618 uint32_t sig_det_override : 1; 1619 uint32_t enable : 1; 1620 #elif defined(_BIT_FIELDS_LTOH) 1621 uint32_t enable : 1; 1622 uint32_t sig_det_override : 1; 1623 uint32_t sig_det_a_low : 1; 1624 uint32_t jitter_study : 2; 1625 uint32_t override_10ms_timer : 1; 1626 uint32_t mask : 1; 1627 uint32_t res0 : 25; 1628 #endif 1629 } w0; 1630 1631 #if defined(_LITTLE_ENDIAN) 1632 uint32_t w1; 1633 #endif 1634 } bits; 1635 } pcs_cfg_t, *p_pcs_cfg_t; 1636 1637 1638 /* used for diagnostic purposes. bits 20-22 autoclear on read */ 1639 #define PCS_SM_TX_STATE_MASK 0x0000000F /* Tx idle state mask */ 1640 #define PCS_SM_TX_STATE_SHIFT 0 1641 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* Rx idle state mask */ 1642 #define PCS_SM_RX_STATE_SHIFT 4 1643 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* loss of sync state mask */ 1644 #define PCS_SM_WORD_SYNC_STATE_SHIFT 8 1645 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* sequence detect */ 1646 #define PCS_SM_SEQ_DETECT_STATE_SHIFT 11 1647 #define PCS_SM_LINK_STATE_MASK 0x0001E000 /* link state */ 1648 #define PCS_SM_LINK_STATE_SHIFT 13 1649 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link */ 1650 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of sync */ 1651 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect fail */ 1652 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* receipt of breaklink */ 1653 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes initializing */ 1654 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable */ 1655 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not achieved */ 1656 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes */ 1657 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* linkpartner send C code */ 1658 1659 typedef union _pcs_stat_mc_t { 1660 uint64_t value; 1661 1662 struct { 1663 #if defined(_BIG_ENDIAN) 1664 uint32_t msw; /* Most significant word */ 1665 uint32_t lsw; /* Least significant word */ 1666 #elif defined(_LITTLE_ENDIAN) 1667 uint32_t lsw; /* Least significant word */ 1668 uint32_t msw; /* Most significant word */ 1669 #endif 1670 } val; 1671 struct { 1672 #if defined(_BIG_ENDIAN) 1673 uint32_t w1; 1674 #endif 1675 struct { 1676 #if defined(_BIT_FIELDS_HTOL) 1677 uint32_t res2 : 2; 1678 uint32_t lnk_dwn_ni : 1; 1679 uint32_t lnk_dwn_wc : 1; 1680 uint32_t lnk_dwn_ls : 1; 1681 uint32_t lnk_dwn_nc : 1; 1682 uint32_t lnk_dwn_ser : 1; 1683 uint32_t lnk_loss_bc : 1; 1684 uint32_t res1 : 1; 1685 uint32_t loss_sd : 1; 1686 uint32_t lnk_loss_sync : 1; 1687 uint32_t lnk_loss_c : 1; 1688 uint32_t res0 : 3; 1689 uint32_t link_cfg_stat : 4; 1690 uint32_t seq_detc_stat : 2; 1691 uint32_t word_sync : 3; 1692 uint32_t rx_ctrl : 4; 1693 uint32_t tx_ctrl : 4; 1694 #elif defined(_BIT_FIELDS_LTOH) 1695 uint32_t tx_ctrl : 4; 1696 uint32_t rx_ctrl : 4; 1697 uint32_t word_sync : 3; 1698 uint32_t seq_detc_stat : 2; 1699 uint32_t link_cfg_stat : 4; 1700 uint32_t res0 : 3; 1701 uint32_t lnk_loss_c : 1; 1702 uint32_t lnk_loss_sync : 1; 1703 uint32_t loss_sd : 1; 1704 uint32_t res1 : 1; 1705 uint32_t lnk_loss_bc : 1; 1706 uint32_t lnk_dwn_ser : 1; 1707 uint32_t lnk_dwn_nc : 1; 1708 uint32_t lnk_dwn_ls : 1; 1709 uint32_t lnk_dwn_wc : 1; 1710 uint32_t lnk_dwn_ni : 1; 1711 uint32_t res2 : 2; 1712 #endif 1713 } w0; 1714 1715 #if defined(_LITTLE_ENDIAN) 1716 uint32_t w1; 1717 #endif 1718 } bits; 1719 } pcs_stat_mc_t, *p_pcs_stat_mc_t; 1720 1721 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed */ 1722 1723 /* 1724 * control which network interface is used. no more than one bit should 1725 * be set. 1726 */ 1727 #define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */ 1728 #define PCS_DATAPATH_MODE_MII 0x00000002 /* GMII/RGMII is selected. */ 1729 1730 #define PCS_PACKET_COUNT_TX_MASK 0x000007FF /* pkts xmitted by PCS */ 1731 #define PCS_PACKET_COUNT_RX_MASK 0x07FF0000 /* pkts recvd by PCS */ 1732 #define PCS_PACKET_COUNT_RX_SHIFT 16 1733 1734 /* 1735 * ******************** XPCS registers ********************************* 1736 */ 1737 1738 /* XPCS Base 10G Control1 Register */ 1739 #define XPCS_CTRL1_RST 0x8000 /* Self clearing reset. */ 1740 #define XPCS_CTRL1_LOOPBK 0x4000 /* xpcs Loopback */ 1741 #define XPCS_CTRL1_SPEED_SEL_3 0x2000 /* 1 indicates 10G speed */ 1742 #define XPCS_CTRL1_LOW_PWR 0x0800 /* low power mode. */ 1743 #define XPCS_CTRL1_SPEED_SEL_1 0x0040 /* 1 indicates 10G speed */ 1744 #define XPCS_CTRL1_SPEED_SEL_0_MASK 0x003c /* 0 indicates 10G speed. */ 1745 #define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2 1746 1747 1748 1749 typedef union _xpcs_ctrl1_t { 1750 uint64_t value; 1751 1752 struct { 1753 #if defined(_BIG_ENDIAN) 1754 uint32_t msw; /* Most significant word */ 1755 uint32_t lsw; /* Least significant word */ 1756 #elif defined(_LITTLE_ENDIAN) 1757 uint32_t lsw; /* Least significant word */ 1758 uint32_t msw; /* Most significant word */ 1759 #endif 1760 } val; 1761 struct { 1762 #if defined(_BIG_ENDIAN) 1763 uint32_t w1; 1764 #endif 1765 struct { 1766 #if defined(_BIT_FIELDS_HTOL) 1767 uint32_t res3 : 16; 1768 uint32_t reset : 1; 1769 uint32_t csr_lb : 1; 1770 uint32_t csr_speed_sel3 : 1; 1771 uint32_t res2 : 1; 1772 uint32_t csr_low_pwr : 1; 1773 uint32_t res1 : 4; 1774 uint32_t csr_speed_sel1 : 1; 1775 uint32_t csr_speed_sel0 : 4; 1776 uint32_t res0 : 2; 1777 #elif defined(_BIT_FIELDS_LTOH) 1778 uint32_t res0 : 2; 1779 uint32_t csr_speed_sel0 : 4; 1780 uint32_t csr_speed_sel1 : 1; 1781 uint32_t res1 : 4; 1782 uint32_t csr_low_pwr : 1; 1783 uint32_t res2 : 1; 1784 uint32_t csr_speed_sel3 : 1; 1785 uint32_t csr_lb : 1; 1786 uint32_t reset : 1; 1787 uint32_t res3 : 16; 1788 #endif 1789 } w0; 1790 1791 #if defined(_LITTLE_ENDIAN) 1792 uint32_t w1; 1793 #endif 1794 } bits; 1795 } xpcs_ctrl1_t; 1796 1797 1798 /* XPCS Base 10G Status1 Register (Read Only) */ 1799 #define XPCS_STATUS1_FAULT 0x0080 1800 #define XPCS_STATUS1_RX_LINK_STATUS_UP 0x0004 /* Link status interrupt */ 1801 #define XPCS_STATUS1_LOW_POWER_ABILITY 0x0002 /* low power mode */ 1802 1803 1804 typedef union _xpcs_stat1_t { 1805 uint64_t value; 1806 1807 struct { 1808 #if defined(_BIG_ENDIAN) 1809 uint32_t msw; /* Most significant word */ 1810 uint32_t lsw; /* Least significant word */ 1811 #elif defined(_LITTLE_ENDIAN) 1812 uint32_t lsw; /* Least significant word */ 1813 uint32_t msw; /* Most significant word */ 1814 #endif 1815 } val; 1816 struct { 1817 #if defined(_BIG_ENDIAN) 1818 uint32_t w1; 1819 #endif 1820 struct { 1821 #if defined(_BIT_FIELDS_HTOL) 1822 uint32_t res4 : 16; 1823 uint32_t res3 : 8; 1824 uint32_t csr_fault : 1; 1825 uint32_t res1 : 4; 1826 uint32_t csr_rx_link_stat : 1; 1827 uint32_t csr_low_pwr_ability : 1; 1828 uint32_t res0 : 1; 1829 #elif defined(_BIT_FIELDS_LTOH) 1830 uint32_t res0 : 1; 1831 uint32_t csr_low_pwr_ability : 1; 1832 uint32_t csr_rx_link_stat : 1; 1833 uint32_t res1 : 4; 1834 uint32_t csr_fault : 1; 1835 uint32_t res3 : 8; 1836 uint32_t res4 : 16; 1837 #endif 1838 } w0; 1839 1840 #if defined(_LITTLE_ENDIAN) 1841 uint32_t w1; 1842 #endif 1843 } bits; 1844 } xpcs_stat1_t; 1845 1846 1847 /* XPCS Base Speed Ability Register. Indicates 10G capability */ 1848 #define XPCS_SPEED_ABILITY_10_GIG 0x0001 1849 1850 1851 typedef union _xpcs_speed_ab_t { 1852 uint64_t value; 1853 1854 struct { 1855 #if defined(_BIG_ENDIAN) 1856 uint32_t msw; /* Most significant word */ 1857 uint32_t lsw; /* Least significant word */ 1858 #elif defined(_LITTLE_ENDIAN) 1859 uint32_t lsw; /* Least significant word */ 1860 uint32_t msw; /* Most significant word */ 1861 #endif 1862 } val; 1863 struct { 1864 #if defined(_BIG_ENDIAN) 1865 uint32_t w1; 1866 #endif 1867 struct { 1868 #if defined(_BIT_FIELDS_HTOL) 1869 uint32_t res1 : 16; 1870 uint32_t res0 : 15; 1871 uint32_t csr_10gig : 1; 1872 #elif defined(_BIT_FIELDS_LTOH) 1873 uint32_t csr_10gig : 1; 1874 uint32_t res0 : 15; 1875 uint32_t res1 : 16; 1876 #endif 1877 } w0; 1878 1879 #if defined(_LITTLE_ENDIAN) 1880 uint32_t w1; 1881 #endif 1882 } bits; 1883 } xpcs_speed_ab_t; 1884 1885 1886 /* XPCS Base 10G Devices in Package Register */ 1887 #define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000 1888 #define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000 1889 #define XPCS_DEV_IN_PKG_DTE_XS 0x00000020 1890 #define XPCS_DEV_IN_PKG_PHY_XS 0x00000010 1891 #define XPCS_DEV_IN_PKG_PCS 0x00000008 1892 #define XPCS_DEV_IN_PKG_WIS 0x00000004 1893 #define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002 1894 #define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000 1895 1896 1897 1898 typedef union _xpcs_dev_in_pkg_t { 1899 uint64_t value; 1900 1901 struct { 1902 #if defined(_BIG_ENDIAN) 1903 uint32_t msw; /* Most significant word */ 1904 uint32_t lsw; /* Least significant word */ 1905 #elif defined(_LITTLE_ENDIAN) 1906 uint32_t lsw; /* Least significant word */ 1907 uint32_t msw; /* Most significant word */ 1908 #endif 1909 } val; 1910 struct { 1911 #if defined(_BIG_ENDIAN) 1912 uint32_t w1; 1913 #endif 1914 struct { 1915 #if defined(_BIT_FIELDS_HTOL) 1916 uint32_t csr_vendor2 : 1; 1917 uint32_t csr_vendor1 : 1; 1918 uint32_t res1 : 14; 1919 uint32_t res0 : 10; 1920 uint32_t dte_xs : 1; 1921 uint32_t phy_xs : 1; 1922 uint32_t pcs : 1; 1923 uint32_t wis : 1; 1924 uint32_t pmd_pma : 1; 1925 uint32_t clause_22_reg : 1; 1926 #elif defined(_BIT_FIELDS_LTOH) 1927 uint32_t clause_22_reg : 1; 1928 uint32_t pmd_pma : 1; 1929 uint32_t wis : 1; 1930 uint32_t pcs : 1; 1931 uint32_t phy_xs : 1; 1932 uint32_t dte_xs : 1; 1933 uint32_t res0 : 10; 1934 uint32_t res1 : 14; 1935 uint32_t csr_vendor1 : 1; 1936 uint32_t csr_vendor2 : 1; 1937 #endif 1938 } w0; 1939 1940 #if defined(_LITTLE_ENDIAN) 1941 uint32_t w1; 1942 #endif 1943 } bits; 1944 } xpcs_dev_in_pkg_t; 1945 1946 1947 /* XPCS Base 10G Control2 Register */ 1948 #define XPCS_PSC_SEL_MASK 0x0003 1949 #define PSC_SEL_10G_BASE_X_PCS 0x0001 1950 1951 1952 typedef union _xpcs_ctrl2_t { 1953 uint64_t value; 1954 1955 struct { 1956 #if defined(_BIG_ENDIAN) 1957 uint32_t msw; /* Most significant word */ 1958 uint32_t lsw; /* Least significant word */ 1959 #elif defined(_LITTLE_ENDIAN) 1960 uint32_t lsw; /* Least significant word */ 1961 uint32_t msw; /* Most significant word */ 1962 #endif 1963 } val; 1964 struct { 1965 #if defined(_BIG_ENDIAN) 1966 uint32_t w1; 1967 #endif 1968 struct { 1969 #if defined(_BIT_FIELDS_HTOL) 1970 uint32_t res1 : 16; 1971 uint32_t res0 : 14; 1972 uint32_t csr_psc_sel : 2; 1973 #elif defined(_BIT_FIELDS_LTOH) 1974 uint32_t csr_psc_sel : 2; 1975 uint32_t res0 : 14; 1976 uint32_t res1 : 16; 1977 #endif 1978 } w0; 1979 1980 #if defined(_LITTLE_ENDIAN) 1981 uint32_t w1; 1982 #endif 1983 } bits; 1984 } xpcs_ctrl2_t; 1985 1986 1987 /* XPCS Base10G Status2 Register */ 1988 #define XPCS_STATUS2_DEV_PRESENT_MASK 0xc000 /* ?????? */ 1989 #define XPCS_STATUS2_TX_FAULT 0x0800 /* Fault on tx path */ 1990 #define XPCS_STATUS2_RX_FAULT 0x0400 /* Fault on rx path */ 1991 #define XPCS_STATUS2_TEN_GBASE_W 0x0004 /* 10G-Base-W */ 1992 #define XPCS_STATUS2_TEN_GBASE_X 0x0002 /* 10G-Base-X */ 1993 #define XPCS_STATUS2_TEN_GBASE_R 0x0001 /* 10G-Base-R */ 1994 1995 typedef union _xpcs_stat2_t { 1996 uint64_t value; 1997 1998 struct { 1999 #if defined(_BIG_ENDIAN) 2000 uint32_t msw; /* Most significant word */ 2001 uint32_t lsw; /* Least significant word */ 2002 #elif defined(_LITTLE_ENDIAN) 2003 uint32_t lsw; /* Least significant word */ 2004 uint32_t msw; /* Most significant word */ 2005 #endif 2006 } val; 2007 struct { 2008 #if defined(_BIG_ENDIAN) 2009 uint32_t w1; 2010 #endif 2011 struct { 2012 #if defined(_BIT_FIELDS_HTOL) 2013 uint32_t res2 : 16; 2014 uint32_t csr_dev_pres : 2; 2015 uint32_t res1 : 2; 2016 uint32_t csr_tx_fault : 1; 2017 uint32_t csr_rx_fault : 1; 2018 uint32_t res0 : 7; 2019 uint32_t ten_gbase_w : 1; 2020 uint32_t ten_gbase_x : 1; 2021 uint32_t ten_gbase_r : 1; 2022 #elif defined(_BIT_FIELDS_LTOH) 2023 uint32_t ten_gbase_r : 1; 2024 uint32_t ten_gbase_x : 1; 2025 uint32_t ten_gbase_w : 1; 2026 uint32_t res0 : 7; 2027 uint32_t csr_rx_fault : 1; 2028 uint32_t csr_tx_fault : 1; 2029 uint32_t res1 : 2; 2030 uint32_t csr_dev_pres : 2; 2031 uint32_t res2 : 16; 2032 #endif 2033 } w0; 2034 2035 #if defined(_LITTLE_ENDIAN) 2036 uint32_t w1; 2037 #endif 2038 } bits; 2039 } xpcs_stat2_t; 2040 2041 2042 2043 /* XPCS Base10G Status Register */ 2044 #define XPCS_STATUS_LANE_ALIGN 0x1000 /* 10GBaseX PCS rx lanes align */ 2045 #define XPCS_STATUS_PATTERN_TEST_ABLE 0x0800 /* able to generate patterns. */ 2046 #define XPCS_STATUS_LANE3_SYNC 0x0008 /* Lane 3 is synchronized */ 2047 #define XPCS_STATUS_LANE2_SYNC 0x0004 /* Lane 2 is synchronized */ 2048 #define XPCS_STATUS_LANE1_SYNC 0x0002 /* Lane 1 is synchronized */ 2049 #define XPCS_STATUS_LANE0_SYNC 0x0001 /* Lane 0 is synchronized */ 2050 2051 typedef union _xpcs_stat_t { 2052 uint64_t value; 2053 2054 struct { 2055 #if defined(_BIG_ENDIAN) 2056 uint32_t msw; /* Most significant word */ 2057 uint32_t lsw; /* Least significant word */ 2058 #elif defined(_LITTLE_ENDIAN) 2059 uint32_t lsw; /* Least significant word */ 2060 uint32_t msw; /* Most significant word */ 2061 #endif 2062 } val; 2063 struct { 2064 #if defined(_BIG_ENDIAN) 2065 uint32_t w1; 2066 #endif 2067 struct { 2068 #if defined(_BIT_FIELDS_HTOL) 2069 uint32_t res2 : 16; 2070 uint32_t res1 : 3; 2071 uint32_t csr_lane_align : 1; 2072 uint32_t csr_pattern_test_able : 1; 2073 uint32_t res0 : 7; 2074 uint32_t csr_lane3_sync : 1; 2075 uint32_t csr_lane2_sync : 1; 2076 uint32_t csr_lane1_sync : 1; 2077 uint32_t csr_lane0_sync : 1; 2078 #elif defined(_BIT_FIELDS_LTOH) 2079 uint32_t csr_lane0_sync : 1; 2080 uint32_t csr_lane1_sync : 1; 2081 uint32_t csr_lane2_sync : 1; 2082 uint32_t csr_lane3_sync : 1; 2083 uint32_t res0 : 7; 2084 uint32_t csr_pat_test_able : 1; 2085 uint32_t csr_lane_align : 1; 2086 uint32_t res1 : 3; 2087 uint32_t res2 : 16; 2088 #endif 2089 } w0; 2090 2091 #if defined(_LITTLE_ENDIAN) 2092 uint32_t w1; 2093 #endif 2094 } bits; 2095 } xpcs_stat_t; 2096 2097 /* XPCS Base10G Test Control Register */ 2098 #define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004 2099 #define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003 2100 #define TEST_PATTERN_HIGH_FREQ 0 2101 #define TEST_PATTERN_LOW_FREQ 1 2102 #define TEST_PATTERN_MIXED_FREQ 2 2103 2104 typedef union _xpcs_test_ctl_t { 2105 uint64_t value; 2106 2107 struct { 2108 #if defined(_BIG_ENDIAN) 2109 uint32_t msw; /* Most significant word */ 2110 uint32_t lsw; /* Least significant word */ 2111 #elif defined(_LITTLE_ENDIAN) 2112 uint32_t lsw; /* Least significant word */ 2113 uint32_t msw; /* Most significant word */ 2114 #endif 2115 } val; 2116 struct { 2117 #if defined(_BIG_ENDIAN) 2118 uint32_t w1; 2119 #endif 2120 struct { 2121 #if defined(_BIT_FIELDS_HTOL) 2122 uint32_t res1 : 16; 2123 uint32_t res0 : 13; 2124 uint32_t csr_tx_test_en : 1; 2125 uint32_t csr_test_pat_sel : 2; 2126 #elif defined(_BIT_FIELDS_LTOH) 2127 uint32_t csr_test_pat_sel : 2; 2128 uint32_t csr_tx_test_en : 1; 2129 uint32_t res0 : 13; 2130 uint32_t res1 : 16; 2131 #endif 2132 } w0; 2133 2134 #if defined(_LITTLE_ENDIAN) 2135 uint32_t w1; 2136 #endif 2137 } bits; 2138 } xpcs_test_ctl_t; 2139 2140 /* XPCS Base10G Diagnostic Register */ 2141 #define XPCS_DIAG_EB_ALIGN_ERR3 0x40 2142 #define XPCS_DIAG_EB_ALIGN_ERR2 0x20 2143 #define XPCS_DIAG_EB_ALIGN_ERR1 0x10 2144 #define XPCS_DIAG_EB_DESKEW_OK 0x08 2145 #define XPCS_DIAG_EB_ALIGN_DET3 0x04 2146 #define XPCS_DIAG_EB_ALIGN_DET2 0x02 2147 #define XPCS_DIAG_EB_ALIGN_DET1 0x01 2148 #define XPCS_DIAG_EB_DESKEW_LOSS 0 2149 2150 #define XPCS_DIAG_SYNC_3_INVALID 0x8 2151 #define XPCS_DIAG_SYNC_2_INVALID 0x4 2152 #define XPCS_DIAG_SYNC_1_INVALID 0x2 2153 #define XPCS_DIAG_SYNC_IN_SYNC 0x1 2154 #define XPCS_DIAG_SYNC_LOSS_SYNC 0 2155 2156 #define XPCS_RX_SM_RECEIVE_STATE 1 2157 #define XPCS_RX_SM_FAULT_STATE 0 2158 2159 typedef union _xpcs_diag_t { 2160 uint64_t value; 2161 2162 struct { 2163 #if defined(_BIG_ENDIAN) 2164 uint32_t msw; /* Most significant word */ 2165 uint32_t lsw; /* Least significant word */ 2166 #elif defined(_LITTLE_ENDIAN) 2167 uint32_t lsw; /* Least significant word */ 2168 uint32_t msw; /* Most significant word */ 2169 #endif 2170 } val; 2171 struct { 2172 #if defined(_BIG_ENDIAN) 2173 uint32_t w1; 2174 #endif 2175 struct { 2176 #if defined(_BIT_FIELDS_HTOL) 2177 uint32_t res1 : 7; 2178 uint32_t sync_sm_lane3 : 4; 2179 uint32_t sync_sm_lane2 : 4; 2180 uint32_t sync_sm_lane1 : 4; 2181 uint32_t sync_sm_lane0 : 4; 2182 uint32_t elastic_buffer_sm : 8; 2183 uint32_t receive_sm : 1; 2184 #elif defined(_BIT_FIELDS_LTOH) 2185 uint32_t receive_sm : 1; 2186 uint32_t elastic_buffer_sm : 8; 2187 uint32_t sync_sm_lane0 : 4; 2188 uint32_t sync_sm_lane1 : 4; 2189 uint32_t sync_sm_lane2 : 4; 2190 uint32_t sync_sm_lane3 : 4; 2191 uint32_t res1 : 7; 2192 #endif 2193 } w0; 2194 2195 #if defined(_LITTLE_ENDIAN) 2196 uint32_t w1; 2197 #endif 2198 } bits; 2199 } xpcs_diag_t; 2200 2201 /* XPCS Base10G Tx State Machine Register */ 2202 #define XPCS_TX_SM_SEND_UNDERRUN 0x9 2203 #define XPCS_TX_SM_SEND_RANDOM_Q 0x8 2204 #define XPCS_TX_SM_SEND_RANDOM_K 0x7 2205 #define XPCS_TX_SM_SEND_RANDOM_A 0x6 2206 #define XPCS_TX_SM_SEND_RANDOM_R 0x5 2207 #define XPCS_TX_SM_SEND_Q 0x4 2208 #define XPCS_TX_SM_SEND_K 0x3 2209 #define XPCS_TX_SM_SEND_A 0x2 2210 #define XPCS_TX_SM_SEND_SDP 0x1 2211 #define XPCS_TX_SM_SEND_DATA 0 2212 2213 /* XPCS Base10G Configuration Register */ 2214 #define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78 2215 #define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3 2216 #define XPCS_CFG_BYPASS_SIG_DETECT 0x0004 2217 #define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002 2218 #define XPCS_CFG_XPCS_ENABLE 0x0001 2219 2220 typedef union _xpcs_config_t { 2221 uint64_t value; 2222 2223 struct { 2224 #if defined(_BIG_ENDIAN) 2225 uint32_t msw; /* Most significant word */ 2226 uint32_t lsw; /* Least significant word */ 2227 #elif defined(_LITTLE_ENDIAN) 2228 uint32_t lsw; /* Least significant word */ 2229 uint32_t msw; /* Most significant word */ 2230 #endif 2231 } val; 2232 struct { 2233 #if defined(_BIG_ENDIAN) 2234 uint32_t w1; 2235 #endif 2236 struct { 2237 #if defined(_BIT_FIELDS_HTOL) 2238 uint32_t res1 : 16; 2239 uint32_t res0 : 9; 2240 uint32_t csr_vendor_dbg_sel : 4; 2241 uint32_t csr_bypass_sig_detect : 1; 2242 uint32_t csr_en_tx_buf : 1; 2243 uint32_t csr_xpcs_en : 1; 2244 #elif defined(_BIT_FIELDS_LTOH) 2245 uint32_t csr_xpcs_en : 1; 2246 uint32_t csr_en_tx_buf : 1; 2247 uint32_t csr_bypass_sig_detect : 1; 2248 uint32_t csr_vendor_dbg_sel : 4; 2249 uint32_t res0 : 9; 2250 uint32_t res1 : 16; 2251 #endif 2252 } w0; 2253 2254 #if defined(_LITTLE_ENDIAN) 2255 uint32_t w1; 2256 #endif 2257 } bits; 2258 } xpcs_config_t; 2259 2260 2261 2262 /* XPCS Base10G Mask1 Register */ 2263 #define XPCS_MASK1_FAULT_MASK 0x0080 /* mask fault interrupt. */ 2264 #define XPCS_MASK1_RX_LINK_STATUS_MASK 0x0040 /* mask linkstat interrupt */ 2265 2266 /* XPCS Base10G Packet Counter */ 2267 #define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000 2268 #define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16 2269 #define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff 2270 #define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0 2271 2272 /* XPCS Base10G TX State Machine status register */ 2273 #define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f 2274 #define XPCS_DESKEW_ERR_CNTR_MASK 0xff 2275 2276 /* XPCS Base10G Lane symbol error counters */ 2277 #define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000 2278 #define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff 2279 #define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000 2280 #define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff 2281 2282 #define XPCS_SYM_ERR_CNT_MULTIPLIER 16 2283 2284 /* ESR Reset Register */ 2285 #define ESR_RESET_1 2 2286 #define ESR_RESET_0 1 2287 2288 /* ESR Configuration Register */ 2289 #define ESR_BLUNT_END_LOOPBACK 2 2290 #define ESR_FORCE_SERDES_SERDES_RDY 1 2291 2292 /* ESR Neptune Serdes PLL Configuration */ 2293 #define ESR_PLL_CFG_FBDIV_0 0x1 2294 #define ESR_PLL_CFG_FBDIV_1 0x2 2295 #define ESR_PLL_CFG_FBDIV_2 0x4 2296 #define ESR_PLL_CFG_HALF_RATE_0 0x8 2297 #define ESR_PLL_CFG_HALF_RATE_1 0x10 2298 #define ESR_PLL_CFG_HALF_RATE_2 0x20 2299 #define ESR_PLL_CFG_HALF_RATE_3 0x40 2300 2301 /* ESR Neptune Serdes Control Register */ 2302 #define ESR_CTL_EN_SYNCDET_0 0x00000001 2303 #define ESR_CTL_EN_SYNCDET_1 0x00000002 2304 #define ESR_CTL_EN_SYNCDET_2 0x00000004 2305 #define ESR_CTL_EN_SYNCDET_3 0x00000008 2306 #define ESR_CTL_OUT_EMPH_0_MASK 0x00000070 2307 #define ESR_CTL_OUT_EMPH_0_SHIFT 4 2308 #define ESR_CTL_OUT_EMPH_1_MASK 0x00000380 2309 #define ESR_CTL_OUT_EMPH_1_SHIFT 7 2310 #define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00 2311 #define ESR_CTL_OUT_EMPH_2_SHIFT 10 2312 #define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000 2313 #define ESR_CTL_OUT_EMPH_3_SHIFT 13 2314 #define ESR_CTL_LOSADJ_0_MASK 0x00070000 2315 #define ESR_CTL_LOSADJ_0_SHIFT 16 2316 #define ESR_CTL_LOSADJ_1_MASK 0x00380000 2317 #define ESR_CTL_LOSADJ_1_SHIFT 19 2318 #define ESR_CTL_LOSADJ_2_MASK 0x01c00000 2319 #define ESR_CTL_LOSADJ_2_SHIFT 22 2320 #define ESR_CTL_LOSADJ_3_MASK 0x0e000000 2321 #define ESR_CTL_LOSADJ_3_SHIFT 25 2322 #define ESR_CTL_RXITERM_0 0x10000000 2323 #define ESR_CTL_RXITERM_1 0x20000000 2324 #define ESR_CTL_RXITERM_2 0x40000000 2325 #define ESR_CTL_RXITERM_3 0x80000000 2326 2327 /* ESR Neptune Serdes Test Configuration Register */ 2328 #define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003 2329 #define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0 2330 #define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c 2331 #define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2 2332 #define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030 2333 #define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4 2334 #define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0 2335 #define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6 2336 2337 /* ESR Neptune Ethernet RGMII Configuration Register */ 2338 #define ESR_RGMII_PT0_IN_USE 0x00000001 2339 #define ESR_RGMII_PT1_IN_USE 0x00000002 2340 #define ESR_RGMII_PT2_IN_USE 0x00000004 2341 #define ESR_RGMII_PT3_IN_USE 0x00000008 2342 #define ESR_RGMII_REG_RW_TEST 0x00000010 2343 2344 /* ESR Internal Signals Observation Register */ 2345 #define ESR_SIG_MASK 0xFFFFFFFF 2346 #define ESR_SIG_P0_BITS_MASK 0x33E0000F 2347 #define ESR_SIG_P1_BITS_MASK 0x0C1F00F0 2348 #define ESR_SIG_SERDES_RDY0_P0 0x20000000 2349 #define ESR_SIG_DETECT0_P0 0x10000000 2350 #define ESR_SIG_SERDES_RDY0_P1 0x08000000 2351 #define ESR_SIG_DETECT0_P1 0x04000000 2352 #define ESR_SIG_XSERDES_RDY_P0 0x02000000 2353 #define ESR_SIG_XDETECT_P0_CH3 0x01000000 2354 #define ESR_SIG_XDETECT_P0_CH2 0x00800000 2355 #define ESR_SIG_XDETECT_P0_CH1 0x00400000 2356 #define ESR_SIG_XDETECT_P0_CH0 0x00200000 2357 #define ESR_SIG_XSERDES_RDY_P1 0x00100000 2358 #define ESR_SIG_XDETECT_P1_CH3 0x00080000 2359 #define ESR_SIG_XDETECT_P1_CH2 0x00040000 2360 #define ESR_SIG_XDETECT_P1_CH1 0x00020000 2361 #define ESR_SIG_XDETECT_P1_CH0 0x00010000 2362 #define ESR_SIG_LOS_P1_CH3 0x00000080 2363 #define ESR_SIG_LOS_P1_CH2 0x00000040 2364 #define ESR_SIG_LOS_P1_CH1 0x00000020 2365 #define ESR_SIG_LOS_P1_CH0 0x00000010 2366 #define ESR_SIG_LOS_P0_CH3 0x00000008 2367 #define ESR_SIG_LOS_P0_CH2 0x00000004 2368 #define ESR_SIG_LOS_P0_CH1 0x00000002 2369 #define ESR_SIG_LOS_P0_CH0 0x00000001 2370 2371 /* ESR Debug Selection Register */ 2372 #define ESR_DEBUG_SEL_MASK 0x00000003f 2373 2374 /* ESR Test Configuration Register */ 2375 #define ESR_NO_LOOPBACK_CH3 (0x0 << 6) 2376 #define ESR_EWRAP_CH3 (0x1 << 6) 2377 #define ESR_PAD_LOOPBACK_CH3 (0x2 << 6) 2378 #define ESR_REVLOOPBACK_CH3 (0x3 << 6) 2379 #define ESR_NO_LOOPBACK_CH2 (0x0 << 4) 2380 #define ESR_EWRAP_CH2 (0x1 << 4) 2381 #define ESR_PAD_LOOPBACK_CH2 (0x2 << 4) 2382 #define ESR_REVLOOPBACK_CH2 (0x3 << 4) 2383 #define ESR_NO_LOOPBACK_CH1 (0x0 << 2) 2384 #define ESR_EWRAP_CH1 (0x1 << 2) 2385 #define ESR_PAD_LOOPBACK_CH1 (0x2 << 2) 2386 #define ESR_REVLOOPBACK_CH1 (0x3 << 2) 2387 #define ESR_NO_LOOPBACK_CH0 0x0 2388 #define ESR_EWRAP_CH0 0x1 2389 #define ESR_PAD_LOOPBACK_CH0 0x2 2390 #define ESR_REVLOOPBACK_CH0 0x3 2391 2392 /* convert values */ 2393 #define NXGE_BASE(x, y) \ 2394 (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2395 2396 #define NXGE_VAL_GET(fieldname, regval) \ 2397 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT)) 2398 2399 #define NXGE_VAL_SET(fieldname, regval, val) \ 2400 { \ 2401 (regval) &= ~((fieldname) ## _MASK); \ 2402 (regval) |= ((val) << (fieldname ## _SHIFT)); \ 2403 } 2404 2405 2406 #ifdef __cplusplus 2407 } 2408 #endif 2409 2410 #endif /* _SYS_MAC_NXGE_MAC_HW_H */ 2411