1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MAC_NXGE_MAC_HW_H 27 #define _SYS_MAC_NXGE_MAC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* -------------------------- From May's template --------------------------- */ 38 39 #define NXGE_1GETHERMIN 255 40 #define NXGE_ETHERMIN 97 41 #define NXGE_MAX_HEADER 250 42 43 /* Hardware reset */ 44 typedef enum { 45 NXGE_TX_DISABLE, /* Disable Tx side */ 46 NXGE_RX_DISABLE, /* Disable Rx side */ 47 NXGE_CHIP_RESET /* Full chip reset */ 48 } nxge_reset_t; 49 50 #define NXGE_DELAY_AFTER_TXRX 10000 /* 10ms after idling rx/tx */ 51 #define NXGE_DELAY_AFTER_RESET 1000 /* 1ms after the reset */ 52 #define NXGE_DELAY_AFTER_EE_RESET 10000 /* 10ms after EEPROM reset */ 53 #define NXGE_DELAY_AFTER_LINK_RESET 13 /* 13 Us after link reset */ 54 #define NXGE_LINK_RESETS 8 /* Max PHY resets to wait for */ 55 /* linkup */ 56 57 #define FILTER_M_CTL 0xDCEF1 58 #define HASH_BITS 8 59 #define NMCFILTER_BITS (1 << HASH_BITS) 60 #define HASH_REG_WIDTH 16 61 #define BROADCAST_HASH_WORD 0x0f 62 #define BROADCAST_HASH_BIT 0x8000 63 #define NMCFILTER_REGS NMCFILTER_BITS / HASH_REG_WIDTH 64 /* Number of multicast filter regs */ 65 66 /* -------------------------------------------------------------------------- */ 67 68 #define XMAC_PORT_0 0 69 #define XMAC_PORT_1 1 70 #define BMAC_PORT_0 2 71 #define BMAC_PORT_1 3 72 73 #define MAC_RESET_WAIT 10 /* usecs */ 74 75 #define MAC_ADDR_REG_MASK 0xFFFF 76 77 /* 78 * Neptune port PHY type and Speed encoding. 79 * 80 * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits 81 * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0 82 * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed 83 * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the 84 * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy 85 * type encoding for the ports 0 thru 3. 86 * 87 * p3phy p2phy p1phy p0phy p3spd p2spd p1spd p0spd 88 * | | | | | | | | 89 * --- --- --- --- --- --- --- --- 90 * / \ / \ / \ / \ / \ / \ / \ / \ 91 * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0 92 */ 93 94 #define NXGE_PORT_SPD_NONE 0x0 95 #define NXGE_PORT_SPD_1G 0x1 96 #define NXGE_PORT_SPD_10G 0x2 97 #define NXGE_PORT_SPD_RSVD 0x7 98 99 #define NXGE_PHY_NONE 0x0 100 #define NXGE_PHY_COPPER 0x1 101 #define NXGE_PHY_FIBRE 0x2 102 #define NXGE_PHY_SERDES 0x3 103 #define NXGE_PHY_RGMII_FIBER 0x4 104 #define NXGE_PHY_RSVD 0x7 105 106 #define NXGE_PORT_SPD_SHIFT 0 107 #define NXGE_PORT_SPD_MASK 0x0f 108 109 #define NXGE_PHY_SHIFT 16 110 #define NXGE_PHY_MASK 0x0f0000 111 112 #define NXGE_PORT_1G_COPPER (NXGE_PORT_SPD_1G | \ 113 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 114 #define NXGE_PORT_10G_COPPER (NXGE_PORT_SPD_10G | \ 115 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 116 #define NXGE_PORT_1G_FIBRE (NXGE_PORT_SPD_1G | \ 117 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 118 #define NXGE_PORT_10G_FIBRE (NXGE_PORT_SPD_10G | \ 119 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 120 #define NXGE_PORT_1G_SERDES (NXGE_PORT_SPD_1G | \ 121 (NXGE_PHY_SERDES << NXGE_PHY_SHIFT)) 122 #define NXGE_PORT_10G_SERDES (NXGE_PORT_SPD_10G | \ 123 (NXGE_PHY_SERDES << NXGE_PHY_SHIFT)) 124 #define NXGE_PORT_1G_RGMII_FIBER (NXGE_PORT_SPD_1G | \ 125 (NXGE_PHY_RGMII_FIBER << NXGE_PHY_SHIFT)) 126 #define NXGE_PORT_NONE (NXGE_PORT_SPD_NONE | \ 127 (NXGE_PHY_NONE << NXGE_PHY_SHIFT)) 128 #define NXGE_PORT_RSVD (NXGE_PORT_SPD_RSVD | \ 129 (NXGE_PHY_RSVD << NXGE_PHY_SHIFT)) 130 131 #define NXGE_PORT_TYPE_MASK (NXGE_PORT_SPD_MASK | NXGE_PHY_MASK) 132 133 /* number of bits used for phy/spd encoding per port */ 134 #define NXGE_PORT_TYPE_SHIFT 4 135 136 /* Network Modes */ 137 138 typedef enum nxge_network_mode { 139 NET_2_10GE_FIBER = 1, 140 NET_2_10GE_COPPER, 141 NET_1_10GE_FIBER_3_1GE_COPPER, 142 NET_1_10GE_COPPER_3_1GE_COPPER, 143 NET_1_10GE_FIBER_3_1GE_FIBER, 144 NET_1_10GE_COPPER_3_1GE_FIBER, 145 NET_2_1GE_FIBER_2_1GE_COPPER, 146 NET_QGE_FIBER, 147 NET_QGE_COPPER 148 } nxge_network_mode_t; 149 150 typedef enum nxge_port { 151 PORT_TYPE_XMAC = 1, 152 PORT_TYPE_BMAC, 153 PORT_TYPE_LOGICAL 154 } nxge_port_t; 155 156 typedef enum nxge_port_mode { 157 PORT_1G_COPPER = 1, 158 PORT_1G_FIBER, 159 PORT_10G_COPPER, 160 PORT_10G_FIBER, 161 PORT_10G_SERDES, 162 PORT_1G_SERDES, 163 PORT_1G_RGMII_FIBER, 164 PORT_HSP_MODE, 165 PORT_LOGICAL 166 } nxge_port_mode_t; 167 168 typedef enum nxge_linkchk_mode { 169 LINKCHK_INTR = 1, 170 LINKCHK_TIMER 171 } nxge_linkchk_mode_t; 172 173 typedef enum { 174 LINK_INTR_STOP, 175 LINK_INTR_START 176 } link_intr_enable_t, *link_intr_enable_pt; 177 178 typedef enum { 179 LINK_MONITOR_STOP, 180 LINK_MONITOR_START, 181 LINK_MONITOR_STOPPING 182 } link_mon_enable_t, *link_mon_enable_pt; 183 184 typedef enum { 185 NO_XCVR, 186 INT_MII_XCVR, 187 EXT_MII_XCVR, 188 PCS_XCVR, 189 XPCS_XCVR, 190 HSP_XCVR, 191 LOGICAL_XCVR 192 } xcvr_inuse_t; 193 194 /* macros for port offset calculations */ 195 196 #define PORT_1_OFFSET 0x6000 197 #define PORT_GT_1_OFFSET 0x4000 198 199 /* XMAC address macros */ 200 201 #define XMAC_ADDR_OFFSET_0 0 202 #define XMAC_ADDR_OFFSET_1 0x6000 203 204 #define XMAC_ADDR_OFFSET(port_num)\ 205 (XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 206 207 #define XMAC_REG_ADDR(port_num, reg)\ 208 (FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg)) 209 210 #define XMAC_PORT_ADDR(port_num)\ 211 (FZC_MAC + XMAC_ADDR_OFFSET(port_num)) 212 213 /* BMAC address macros */ 214 215 #define BMAC_ADDR_OFFSET_2 0x0C000 216 #define BMAC_ADDR_OFFSET_3 0x10000 217 218 #define BMAC_ADDR_OFFSET(port_num)\ 219 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 220 221 #define BMAC_REG_ADDR(port_num, reg)\ 222 (FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg)) 223 224 #define BMAC_PORT_ADDR(port_num)\ 225 (FZC_MAC + BMAC_ADDR_OFFSET(port_num)) 226 227 /* PCS address macros */ 228 229 #define PCS_ADDR_OFFSET_0 0x04000 230 #define PCS_ADDR_OFFSET_1 0x0A000 231 #define PCS_ADDR_OFFSET_2 0x0E000 232 #define PCS_ADDR_OFFSET_3 0x12000 233 234 #define PCS_ADDR_OFFSET(port_num)\ 235 ((port_num <= 1) ? \ 236 (PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \ 237 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 238 239 #define PCS_REG_ADDR(port_num, reg)\ 240 (FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg))) 241 242 #define PCS_PORT_ADDR(port_num)\ 243 (FZC_MAC + (PCS_ADDR_OFFSET(port_num))) 244 245 /* XPCS address macros */ 246 247 #define XPCS_ADDR_OFFSET_0 0x02000 248 #define XPCS_ADDR_OFFSET_1 0x08000 249 #define XPCS_ADDR_OFFSET(port_num)\ 250 (XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 251 252 #define XPCS_ADDR(port_num, reg)\ 253 (FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg))) 254 255 #define XPCS_PORT_ADDR(port_num)\ 256 (FZC_MAC + (XPCS_ADDR_OFFSET(port_num))) 257 258 /* ESR address macro */ 259 #define ESR_ADDR_OFFSET 0x14000 260 #define ESR_ADDR(reg)\ 261 (FZC_MAC + (ESR_ADDR_OFFSET) + (reg)) 262 263 /* MIF address macros */ 264 #define MIF_ADDR_OFFSET 0x16000 265 #define MIF_ADDR(reg)\ 266 (FZC_MAC + (MIF_ADDR_OFFSET) + (reg)) 267 268 /* BMAC registers offset */ 269 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ 270 #define BRXMAC_SW_RST_REG 0x008 /* RX MAC software reset */ 271 #define MAC_SEND_PAUSE_REG 0x010 /* send pause command */ 272 #define BTXMAC_STATUS_REG 0x020 /* TX MAC status */ 273 #define BRXMAC_STATUS_REG 0x028 /* RX MAC status */ 274 #define BMAC_CTRL_STAT_REG 0x030 /* MAC control status */ 275 #define BTXMAC_STAT_MSK_REG 0x040 /* TX MAC mask */ 276 #define BRXMAC_STAT_MSK_REG 0x048 /* RX MAC mask */ 277 #define BMAC_C_S_MSK_REG 0x050 /* MAC control mask */ 278 #define TXMAC_CONFIG_REG 0x060 /* TX MAC config */ 279 /* cfg register bitmap */ 280 281 typedef union _btxmac_config_t { 282 uint64_t value; 283 284 struct { 285 #if defined(_BIG_ENDIAN) 286 uint32_t msw; /* Most significant word */ 287 uint32_t lsw; /* Least significant word */ 288 #elif defined(_LITTLE_ENDIAN) 289 uint32_t lsw; /* Least significant word */ 290 uint32_t msw; /* Most significant word */ 291 #endif 292 } val; 293 struct { 294 #if defined(_BIG_ENDIAN) 295 uint32_t w1; 296 #endif 297 struct { 298 #if defined(_BIT_FIELDS_HTOL) 299 uint32_t rsrvd : 22; 300 uint32_t hdx_ctrl2 : 1; 301 uint32_t no_fcs : 1; 302 uint32_t hdx_ctrl : 7; 303 uint32_t txmac_enable : 1; 304 #elif defined(_BIT_FIELDS_LTOH) 305 uint32_t txmac_enable : 1; 306 uint32_t hdx_ctrl : 7; 307 uint32_t no_fcs : 1; 308 uint32_t hdx_ctrl2 : 1; 309 uint32_t rsrvd : 22; 310 #endif 311 } w0; 312 313 #if defined(_LITTLE_ENDIAN) 314 uint32_t w1; 315 #endif 316 } bits; 317 } btxmac_config_t, *p_btxmac_config_t; 318 319 #define RXMAC_CONFIG_REG 0x068 /* RX MAC config */ 320 321 typedef union _brxmac_config_t { 322 uint64_t value; 323 324 struct { 325 #if defined(_BIG_ENDIAN) 326 uint32_t msw; /* Most significant word */ 327 uint32_t lsw; /* Least significant word */ 328 #elif defined(_LITTLE_ENDIAN) 329 uint32_t lsw; /* Least significant word */ 330 uint32_t msw; /* Most significant word */ 331 #endif 332 } val; 333 struct { 334 #if defined(_BIG_ENDIAN) 335 uint32_t w1; 336 #endif 337 struct { 338 #if defined(_BIT_FIELDS_HTOL) 339 uint32_t rsrvd : 20; 340 uint32_t mac_reg_sw_test : 2; 341 uint32_t mac2ipp_pkt_cnt_en : 1; 342 uint32_t rx_crs_extend_en : 1; 343 uint32_t error_chk_dis : 1; 344 uint32_t addr_filter_en : 1; 345 uint32_t hash_filter_en : 1; 346 uint32_t promiscuous_group : 1; 347 uint32_t promiscuous : 1; 348 uint32_t strip_fcs : 1; 349 uint32_t strip_pad : 1; 350 uint32_t rxmac_enable : 1; 351 #elif defined(_BIT_FIELDS_LTOH) 352 uint32_t rxmac_enable : 1; 353 uint32_t strip_pad : 1; 354 uint32_t strip_fcs : 1; 355 uint32_t promiscuous : 1; 356 uint32_t promiscuous_group : 1; 357 uint32_t hash_filter_en : 1; 358 uint32_t addr_filter_en : 1; 359 uint32_t error_chk_dis : 1; 360 uint32_t rx_crs_extend_en : 1; 361 uint32_t mac2ipp_pkt_cnt_en : 1; 362 uint32_t mac_reg_sw_test : 2; 363 uint32_t rsrvd : 20; 364 #endif 365 } w0; 366 367 #if defined(_LITTLE_ENDIAN) 368 uint32_t w1; 369 #endif 370 } bits; 371 } brxmac_config_t, *p_brxmac_config_t; 372 373 #define MAC_CTRL_CONFIG_REG 0x070 /* MAC control config */ 374 #define MAC_XIF_CONFIG_REG 0x078 /* XIF config */ 375 376 typedef union _bxif_config_t { 377 uint64_t value; 378 379 struct { 380 #if defined(_BIG_ENDIAN) 381 uint32_t msw; /* Most significant word */ 382 uint32_t lsw; /* Least significant word */ 383 #elif defined(_LITTLE_ENDIAN) 384 uint32_t lsw; /* Least significant word */ 385 uint32_t msw; /* Most significant word */ 386 #endif 387 } val; 388 struct { 389 #if defined(_BIG_ENDIAN) 390 uint32_t w1; 391 #endif 392 struct { 393 #if defined(_BIT_FIELDS_HTOL) 394 uint32_t rsrvd2 : 24; 395 uint32_t sel_clk_25mhz : 1; 396 uint32_t led_polarity : 1; 397 uint32_t force_led_on : 1; 398 uint32_t used : 1; 399 uint32_t gmii_mode : 1; 400 uint32_t rsrvd : 1; 401 uint32_t loopback : 1; 402 uint32_t tx_output_en : 1; 403 #elif defined(_BIT_FIELDS_LTOH) 404 uint32_t tx_output_en : 1; 405 uint32_t loopback : 1; 406 uint32_t rsrvd : 1; 407 uint32_t gmii_mode : 1; 408 uint32_t used : 1; 409 uint32_t force_led_on : 1; 410 uint32_t led_polarity : 1; 411 uint32_t sel_clk_25mhz : 1; 412 uint32_t rsrvd2 : 24; 413 #endif 414 } w0; 415 416 #if defined(_LITTLE_ENDIAN) 417 uint32_t w1; 418 #endif 419 } bits; 420 } bxif_config_t, *p_bxif_config_t; 421 422 #define BMAC_MIN_REG 0x0a0 /* min frame size */ 423 #define BMAC_MAX_REG 0x0a8 /* max frame size reg */ 424 #define MAC_PA_SIZE_REG 0x0b0 /* num of preamble bytes */ 425 #define MAC_CTRL_TYPE_REG 0x0c8 /* type field of MAC ctrl */ 426 #define BMAC_ADDR0_REG 0x100 /* MAC unique ad0 reg (HI 0) */ 427 #define BMAC_ADDR1_REG 0x108 /* MAC unique ad1 reg */ 428 #define BMAC_ADDR2_REG 0x110 /* MAC unique ad2 reg */ 429 #define BMAC_ADDR3_REG 0x118 /* MAC alt ad0 reg (HI 1) */ 430 #define BMAC_ADDR4_REG 0x120 /* MAC alt ad0 reg */ 431 #define BMAC_ADDR5_REG 0x128 /* MAC alt ad0 reg */ 432 #define BMAC_ADDR6_REG 0x130 /* MAC alt ad1 reg (HI 2) */ 433 #define BMAC_ADDR7_REG 0x138 /* MAC alt ad1 reg */ 434 #define BMAC_ADDR8_REG 0x140 /* MAC alt ad1 reg */ 435 #define BMAC_ADDR9_REG 0x148 /* MAC alt ad2 reg (HI 3) */ 436 #define BMAC_ADDR10_REG 0x150 /* MAC alt ad2 reg */ 437 #define BMAC_ADDR11_REG 0x158 /* MAC alt ad2 reg */ 438 #define BMAC_ADDR12_REG 0x160 /* MAC alt ad3 reg (HI 4) */ 439 #define BMAC_ADDR13_REG 0x168 /* MAC alt ad3 reg */ 440 #define BMAC_ADDR14_REG 0x170 /* MAC alt ad3 reg */ 441 #define BMAC_ADDR15_REG 0x178 /* MAC alt ad4 reg (HI 5) */ 442 #define BMAC_ADDR16_REG 0x180 /* MAC alt ad4 reg */ 443 #define BMAC_ADDR17_REG 0x188 /* MAC alt ad4 reg */ 444 #define BMAC_ADDR18_REG 0x190 /* MAC alt ad5 reg (HI 6) */ 445 #define BMAC_ADDR19_REG 0x198 /* MAC alt ad5 reg */ 446 #define BMAC_ADDR20_REG 0x1a0 /* MAC alt ad5 reg */ 447 #define BMAC_ADDR21_REG 0x1a8 /* MAC alt ad6 reg (HI 7) */ 448 #define BMAC_ADDR22_REG 0x1b0 /* MAC alt ad6 reg */ 449 #define BMAC_ADDR23_REG 0x1b8 /* MAC alt ad6 reg */ 450 #define MAC_FC_ADDR0_REG 0x268 /* FC frame addr0 (HI 0, p3) */ 451 #define MAC_FC_ADDR1_REG 0x270 /* FC frame addr1 */ 452 #define MAC_FC_ADDR2_REG 0x278 /* FC frame addr2 */ 453 #define MAC_ADDR_FILT0_REG 0x298 /* bits [47:32] (HI 0, p2) */ 454 #define MAC_ADDR_FILT1_REG 0x2a0 /* bits [31:16] */ 455 #define MAC_ADDR_FILT2_REG 0x2a8 /* bits [15:0] */ 456 #define MAC_ADDR_FILT12_MASK_REG 0x2b0 /* addr filter 2 & 1 mask */ 457 #define MAC_ADDR_FILT00_MASK_REG 0x2b8 /* addr filter 0 mask */ 458 #define MAC_HASH_TBL0_REG 0x2c0 /* hash table 0 reg */ 459 #define MAC_HASH_TBL1_REG 0x2c8 /* hash table 1 reg */ 460 #define MAC_HASH_TBL2_REG 0x2d0 /* hash table 2 reg */ 461 #define MAC_HASH_TBL3_REG 0x2d8 /* hash table 3 reg */ 462 #define MAC_HASH_TBL4_REG 0x2e0 /* hash table 4 reg */ 463 #define MAC_HASH_TBL5_REG 0x2e8 /* hash table 5 reg */ 464 #define MAC_HASH_TBL6_REG 0x2f0 /* hash table 6 reg */ 465 #define MAC_HASH_TBL7_REG 0x2f8 /* hash table 7 reg */ 466 #define MAC_HASH_TBL8_REG 0x300 /* hash table 8 reg */ 467 #define MAC_HASH_TBL9_REG 0x308 /* hash table 9 reg */ 468 #define MAC_HASH_TBL10_REG 0x310 /* hash table 10 reg */ 469 #define MAC_HASH_TBL11_REG 0x318 /* hash table 11 reg */ 470 #define MAC_HASH_TBL12_REG 0x320 /* hash table 12 reg */ 471 #define MAC_HASH_TBL13_REG 0x328 /* hash table 13 reg */ 472 #define MAC_HASH_TBL14_REG 0x330 /* hash table 14 reg */ 473 #define MAC_HASH_TBL15_REG 0x338 /* hash table 15 reg */ 474 #define RXMAC_FRM_CNT_REG 0x370 /* receive frame counter */ 475 #define MAC_LEN_ER_CNT_REG 0x378 /* length error counter */ 476 #define BMAC_AL_ER_CNT_REG 0x380 /* alignment error counter */ 477 #define BMAC_CRC_ER_CNT_REG 0x388 /* FCS error counter */ 478 #define BMAC_CD_VIO_CNT_REG 0x390 /* RX code violation err */ 479 #define BMAC_SM_REG 0x3a0 /* (ro) state machine reg */ 480 #define BMAC_ALTAD_CMPEN_REG 0x3f8 /* Alt addr compare enable */ 481 #define BMAC_HOST_INF0_REG 0x400 /* Host info */ 482 /* (own da, add filter, fc) */ 483 #define BMAC_HOST_INF1_REG 0x408 /* Host info (alt ad 0) */ 484 #define BMAC_HOST_INF2_REG 0x410 /* Host info (alt ad 1) */ 485 #define BMAC_HOST_INF3_REG 0x418 /* Host info (alt ad 2) */ 486 #define BMAC_HOST_INF4_REG 0x420 /* Host info (alt ad 3) */ 487 #define BMAC_HOST_INF5_REG 0x428 /* Host info (alt ad 4) */ 488 #define BMAC_HOST_INF6_REG 0x430 /* Host info (alt ad 5) */ 489 #define BMAC_HOST_INF7_REG 0x438 /* Host info (alt ad 6) */ 490 #define BMAC_HOST_INF8_REG 0x440 /* Host info (hash hit, miss) */ 491 #define BTXMAC_BYTE_CNT_REG 0x448 /* Tx byte count */ 492 #define BTXMAC_FRM_CNT_REG 0x450 /* frame count */ 493 #define BRXMAC_BYTE_CNT_REG 0x458 /* Rx byte count */ 494 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */ 495 #define BMAC_ALT_ADDR0N_REG_ADDR(x) (BMAC_ADDR3_REG + (x) * 24) 496 #define BMAC_ALT_ADDR1N_REG_ADDR(x) (BMAC_ADDR3_REG + 8 + (x) * 24) 497 #define BMAC_ALT_ADDR2N_REG_ADDR(x) (BMAC_ADDR3_REG + 0x10 + (x) * 24) 498 #define BMAC_HASH_TBLN_REG_ADDR(x) (MAC_HASH_TBL0_REG + (x) * 8) 499 #define BMAC_HOST_INFN_REG_ADDR(x) (BMAC_HOST_INF0_REG + (x) * 8) 500 501 /* XMAC registers offset */ 502 #define XTXMAC_SW_RST_REG 0x000 /* XTX MAC soft reset */ 503 #define XRXMAC_SW_RST_REG 0x008 /* XRX MAC soft reset */ 504 #define XTXMAC_STATUS_REG 0x020 /* XTX MAC status */ 505 #define XRXMAC_STATUS_REG 0x028 /* XRX MAC status */ 506 #define XMAC_CTRL_STAT_REG 0x030 /* Control / Status */ 507 #define XTXMAC_STAT_MSK_REG 0x040 /* XTX MAC Status mask */ 508 #define XRXMAC_STAT_MSK_REG 0x048 /* XRX MAC Status mask */ 509 #define XMAC_C_S_MSK_REG 0x050 /* Control / Status mask */ 510 #define XMAC_CONFIG_REG 0x060 /* Configuration */ 511 512 /* xmac config bit fields */ 513 typedef union _xmac_cfg_t { 514 uint64_t value; 515 516 struct { 517 #if defined(_BIG_ENDIAN) 518 uint32_t msw; /* Most significant word */ 519 uint32_t lsw; /* Least significant word */ 520 #elif defined(_LITTLE_ENDIAN) 521 uint32_t lsw; /* Least significant word */ 522 uint32_t msw; /* Most significant word */ 523 #endif 524 } val; 525 struct { 526 #if defined(_BIG_ENDIAN) 527 uint32_t w1; 528 #endif 529 struct { 530 #if defined(_BIT_FIELDS_HTOL) 531 uint32_t sel_clk_25mhz : 1; 532 uint32_t pcs_bypass : 1; 533 uint32_t xpcs_bypass : 1; 534 uint32_t mii_gmii_mode : 2; 535 uint32_t lfs_disable : 1; 536 uint32_t loopback : 1; 537 uint32_t tx_output_en : 1; 538 uint32_t sel_por_clk_src : 1; 539 uint32_t led_polarity : 1; 540 uint32_t force_led_on : 1; 541 uint32_t pass_fctl_frames : 1; 542 uint32_t recv_pause_en : 1; 543 uint32_t mac2ipp_pkt_cnt_en : 1; 544 uint32_t strip_crc : 1; 545 uint32_t addr_filter_en : 1; 546 uint32_t hash_filter_en : 1; 547 uint32_t code_viol_chk_dis : 1; 548 uint32_t reserved_mcast : 1; 549 uint32_t rx_crc_chk_dis : 1; 550 uint32_t error_chk_dis : 1; 551 uint32_t promisc_grp : 1; 552 uint32_t promiscuous : 1; 553 uint32_t rx_mac_enable : 1; 554 uint32_t warning_msg_en : 1; 555 uint32_t used : 3; 556 uint32_t always_no_crc : 1; 557 uint32_t var_min_ipg_en : 1; 558 uint32_t strech_mode : 1; 559 uint32_t tx_enable : 1; 560 #elif defined(_BIT_FIELDS_LTOH) 561 uint32_t tx_enable : 1; 562 uint32_t strech_mode : 1; 563 uint32_t var_min_ipg_en : 1; 564 uint32_t always_no_crc : 1; 565 uint32_t used : 3; 566 uint32_t warning_msg_en : 1; 567 uint32_t rx_mac_enable : 1; 568 uint32_t promiscuous : 1; 569 uint32_t promisc_grp : 1; 570 uint32_t error_chk_dis : 1; 571 uint32_t rx_crc_chk_dis : 1; 572 uint32_t reserved_mcast : 1; 573 uint32_t code_viol_chk_dis : 1; 574 uint32_t hash_filter_en : 1; 575 uint32_t addr_filter_en : 1; 576 uint32_t strip_crc : 1; 577 uint32_t mac2ipp_pkt_cnt_en : 1; 578 uint32_t recv_pause_en : 1; 579 uint32_t pass_fctl_frames : 1; 580 uint32_t force_led_on : 1; 581 uint32_t led_polarity : 1; 582 uint32_t sel_por_clk_src : 1; 583 uint32_t tx_output_en : 1; 584 uint32_t loopback : 1; 585 uint32_t lfs_disable : 1; 586 uint32_t mii_gmii_mode : 2; 587 uint32_t xpcs_bypass : 1; 588 uint32_t pcs_bypass : 1; 589 uint32_t sel_clk_25mhz : 1; 590 #endif 591 } w0; 592 593 #if defined(_LITTLE_ENDIAN) 594 uint32_t w1; 595 #endif 596 } bits; 597 } xmac_cfg_t, *p_xmac_cfg_t; 598 599 #define XMAC_IPG_REG 0x080 /* Inter-Packet-Gap */ 600 #define XMAC_MIN_REG 0x088 /* min frame size register */ 601 #define XMAC_MAX_REG 0x090 /* max frame/burst size */ 602 #define XMAC_ADDR0_REG 0x0a0 /* [47:32] of MAC addr (HI17) */ 603 #define XMAC_ADDR1_REG 0x0a8 /* [31:16] of MAC addr */ 604 #define XMAC_ADDR2_REG 0x0b0 /* [15:0] of MAC addr */ 605 #define XRXMAC_BT_CNT_REG 0x100 /* bytes received / 8 */ 606 #define XRXMAC_BC_FRM_CNT_REG 0x108 /* good BC frames received */ 607 #define XRXMAC_MC_FRM_CNT_REG 0x110 /* good MC frames received */ 608 #define XRXMAC_FRAG_CNT_REG 0x118 /* frag frames rejected */ 609 #define XRXMAC_HIST_CNT1_REG 0x120 /* 64 bytes frames */ 610 #define XRXMAC_HIST_CNT2_REG 0x128 /* 65-127 bytes frames */ 611 #define XRXMAC_HIST_CNT3_REG 0x130 /* 128-255 bytes frames */ 612 #define XRXMAC_HIST_CNT4_REG 0x138 /* 256-511 bytes frames */ 613 #define XRXMAC_HIST_CNT5_REG 0x140 /* 512-1023 bytes frames */ 614 #define XRXMAC_HIST_CNT6_REG 0x148 /* 1024-1522 bytes frames */ 615 #define XRXMAC_MPSZER_CNT_REG 0x150 /* frames > maxframesize */ 616 #define XRXMAC_CRC_ER_CNT_REG 0x158 /* frames failed CRC */ 617 #define XRXMAC_CD_VIO_CNT_REG 0x160 /* frames with code vio */ 618 #define XRXMAC_AL_ER_CNT_REG 0x168 /* frames with align error */ 619 #define XTXMAC_FRM_CNT_REG 0x170 /* tx frames */ 620 #define XTXMAC_BYTE_CNT_REG 0x178 /* tx bytes / 8 */ 621 #define XMAC_LINK_FLT_CNT_REG 0x180 /* link faults */ 622 #define XRXMAC_HIST_CNT7_REG 0x188 /* MAC2IPP/>1523 bytes frames */ 623 #define XMAC_SM_REG 0x1a8 /* State machine */ 624 #define XMAC_INTERN1_REG 0x1b0 /* internal signals for diag */ 625 #define XMAC_INTERN2_REG 0x1b8 /* internal signals for diag */ 626 #define XMAC_ADDR_CMPEN_REG 0x208 /* alt MAC addr check */ 627 #define XMAC_ADDR3_REG 0x218 /* alt MAC addr 0 (HI 0) */ 628 #define XMAC_ADDR4_REG 0x220 /* alt MAC addr 0 */ 629 #define XMAC_ADDR5_REG 0x228 /* alt MAC addr 0 */ 630 #define XMAC_ADDR6_REG 0x230 /* alt MAC addr 1 (HI 1) */ 631 #define XMAC_ADDR7_REG 0x238 /* alt MAC addr 1 */ 632 #define XMAC_ADDR8_REG 0x240 /* alt MAC addr 1 */ 633 #define XMAC_ADDR9_REG 0x248 /* alt MAC addr 2 (HI 2) */ 634 #define XMAC_ADDR10_REG 0x250 /* alt MAC addr 2 */ 635 #define XMAC_ADDR11_REG 0x258 /* alt MAC addr 2 */ 636 #define XMAC_ADDR12_REG 0x260 /* alt MAC addr 3 (HI 3) */ 637 #define XMAC_ADDR13_REG 0x268 /* alt MAC addr 3 */ 638 #define XMAC_ADDR14_REG 0x270 /* alt MAC addr 3 */ 639 #define XMAC_ADDR15_REG 0x278 /* alt MAC addr 4 (HI 4) */ 640 #define XMAC_ADDR16_REG 0x280 /* alt MAC addr 4 */ 641 #define XMAC_ADDR17_REG 0x288 /* alt MAC addr 4 */ 642 #define XMAC_ADDR18_REG 0x290 /* alt MAC addr 5 (HI 5) */ 643 #define XMAC_ADDR19_REG 0x298 /* alt MAC addr 5 */ 644 #define XMAC_ADDR20_REG 0x2a0 /* alt MAC addr 5 */ 645 #define XMAC_ADDR21_REG 0x2a8 /* alt MAC addr 6 (HI 6) */ 646 #define XMAC_ADDR22_REG 0x2b0 /* alt MAC addr 6 */ 647 #define XMAC_ADDR23_REG 0x2b8 /* alt MAC addr 6 */ 648 #define XMAC_ADDR24_REG 0x2c0 /* alt MAC addr 7 (HI 7) */ 649 #define XMAC_ADDR25_REG 0x2c8 /* alt MAC addr 7 */ 650 #define XMAC_ADDR26_REG 0x2d0 /* alt MAC addr 7 */ 651 #define XMAC_ADDR27_REG 0x2d8 /* alt MAC addr 8 (HI 8) */ 652 #define XMAC_ADDR28_REG 0x2e0 /* alt MAC addr 8 */ 653 #define XMAC_ADDR29_REG 0x2e8 /* alt MAC addr 8 */ 654 #define XMAC_ADDR30_REG 0x2f0 /* alt MAC addr 9 (HI 9) */ 655 #define XMAC_ADDR31_REG 0x2f8 /* alt MAC addr 9 */ 656 #define XMAC_ADDR32_REG 0x300 /* alt MAC addr 9 */ 657 #define XMAC_ADDR33_REG 0x308 /* alt MAC addr 10 (HI 10) */ 658 #define XMAC_ADDR34_REG 0x310 /* alt MAC addr 10 */ 659 #define XMAC_ADDR35_REG 0x318 /* alt MAC addr 10 */ 660 #define XMAC_ADDR36_REG 0x320 /* alt MAC addr 11 (HI 11) */ 661 #define XMAC_ADDR37_REG 0x328 /* alt MAC addr 11 */ 662 #define XMAC_ADDR38_REG 0x330 /* alt MAC addr 11 */ 663 #define XMAC_ADDR39_REG 0x338 /* alt MAC addr 12 (HI 12) */ 664 #define XMAC_ADDR40_REG 0x340 /* alt MAC addr 12 */ 665 #define XMAC_ADDR41_REG 0x348 /* alt MAC addr 12 */ 666 #define XMAC_ADDR42_REG 0x350 /* alt MAC addr 13 (HI 13) */ 667 #define XMAC_ADDR43_REG 0x358 /* alt MAC addr 13 */ 668 #define XMAC_ADDR44_REG 0x360 /* alt MAC addr 13 */ 669 #define XMAC_ADDR45_REG 0x368 /* alt MAC addr 14 (HI 14) */ 670 #define XMAC_ADDR46_REG 0x370 /* alt MAC addr 14 */ 671 #define XMAC_ADDR47_REG 0x378 /* alt MAC addr 14 */ 672 #define XMAC_ADDR48_REG 0x380 /* alt MAC addr 15 (HI 15) */ 673 #define XMAC_ADDR49_REG 0x388 /* alt MAC addr 15 */ 674 #define XMAC_ADDR50_REG 0x390 /* alt MAC addr 15 */ 675 #define XMAC_ADDR_FILT0_REG 0x818 /* [47:32] addr filter (HI18) */ 676 #define XMAC_ADDR_FILT1_REG 0x820 /* [31:16] of addr filter */ 677 #define XMAC_ADDR_FILT2_REG 0x828 /* [15:0] of addr filter */ 678 #define XMAC_ADDR_FILT12_MASK_REG 0x830 /* addr filter 2 & 1 mask */ 679 #define XMAC_ADDR_FILT0_MASK_REG 0x838 /* addr filter 0 mask */ 680 #define XMAC_HASH_TBL0_REG 0x840 /* hash table 0 reg */ 681 #define XMAC_HASH_TBL1_REG 0x848 /* hash table 1 reg */ 682 #define XMAC_HASH_TBL2_REG 0x850 /* hash table 2 reg */ 683 #define XMAC_HASH_TBL3_REG 0x858 /* hash table 3 reg */ 684 #define XMAC_HASH_TBL4_REG 0x860 /* hash table 4 reg */ 685 #define XMAC_HASH_TBL5_REG 0x868 /* hash table 5 reg */ 686 #define XMAC_HASH_TBL6_REG 0x870 /* hash table 6 reg */ 687 #define XMAC_HASH_TBL7_REG 0x878 /* hash table 7 reg */ 688 #define XMAC_HASH_TBL8_REG 0x880 /* hash table 8 reg */ 689 #define XMAC_HASH_TBL9_REG 0x888 /* hash table 9 reg */ 690 #define XMAC_HASH_TBL10_REG 0x890 /* hash table 10 reg */ 691 #define XMAC_HASH_TBL11_REG 0x898 /* hash table 11 reg */ 692 #define XMAC_HASH_TBL12_REG 0x8a0 /* hash table 12 reg */ 693 #define XMAC_HASH_TBL13_REG 0x8a8 /* hash table 13 reg */ 694 #define XMAC_HASH_TBL14_REG 0x8b0 /* hash table 14 reg */ 695 #define XMAC_HASH_TBL15_REG 0x8b8 /* hash table 15 reg */ 696 #define XMAC_HOST_INF0_REG 0x900 /* Host info 0 (alt ad 0) */ 697 #define XMAC_HOST_INF1_REG 0x908 /* Host info 1 (alt ad 1) */ 698 #define XMAC_HOST_INF2_REG 0x910 /* Host info 2 (alt ad 2) */ 699 #define XMAC_HOST_INF3_REG 0x918 /* Host info 3 (alt ad 3) */ 700 #define XMAC_HOST_INF4_REG 0x920 /* Host info 4 (alt ad 4) */ 701 #define XMAC_HOST_INF5_REG 0x928 /* Host info 5 (alt ad 5) */ 702 #define XMAC_HOST_INF6_REG 0x930 /* Host info 6 (alt ad 6) */ 703 #define XMAC_HOST_INF7_REG 0x938 /* Host info 7 (alt ad 7) */ 704 #define XMAC_HOST_INF8_REG 0x940 /* Host info 8 (alt ad 8) */ 705 #define XMAC_HOST_INF9_REG 0x948 /* Host info 9 (alt ad 9) */ 706 #define XMAC_HOST_INF10_REG 0x950 /* Host info 10 (alt ad 10) */ 707 #define XMAC_HOST_INF11_REG 0x958 /* Host info 11 (alt ad 11) */ 708 #define XMAC_HOST_INF12_REG 0x960 /* Host info 12 (alt ad 12) */ 709 #define XMAC_HOST_INF13_REG 0x968 /* Host info 13 (alt ad 13) */ 710 #define XMAC_HOST_INF14_REG 0x970 /* Host info 14 (alt ad 14) */ 711 #define XMAC_HOST_INF15_REG 0x978 /* Host info 15 (alt ad 15) */ 712 #define XMAC_HOST_INF16_REG 0x980 /* Host info 16 (hash hit) */ 713 #define XMAC_HOST_INF17_REG 0x988 /* Host info 17 (own da) */ 714 #define XMAC_HOST_INF18_REG 0x990 /* Host info 18 (filter hit) */ 715 #define XMAC_HOST_INF19_REG 0x998 /* Host info 19 (fc hit) */ 716 #define XMAC_PA_DATA0_REG 0xb80 /* preamble [31:0] */ 717 #define XMAC_PA_DATA1_REG 0xb88 /* preamble [63:32] */ 718 #define XMAC_DEBUG_SEL_REG 0xb90 /* debug select */ 719 #define XMAC_TRAINING_VECT_REG 0xb98 /* training vector */ 720 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */ 721 #define XMAC_ALT_ADDR0N_REG_ADDR(x) (XMAC_ADDR3_REG + (x) * 24) 722 #define XMAC_ALT_ADDR1N_REG_ADDR(x) (XMAC_ADDR3_REG + 8 + (x) * 24) 723 #define XMAC_ALT_ADDR2N_REG_ADDR(x) (XMAC_ADDR3_REG + 16 + (x) * 24) 724 #define XMAC_HASH_TBLN_REG_ADDR(x) (XMAC_HASH_TBL0_REG + (x) * 8) 725 #define XMAC_HOST_INFN_REG_ADDR(x) (XMAC_HOST_INF0_REG + (x) * 8) 726 727 /* MIF registers offset */ 728 #define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */ 729 #define MIF_BB_MDO_REG 0x008 /* MIF bit-bang data */ 730 #define MIF_BB_MDO_EN_REG 0x010 /* MIF bit-bang output en */ 731 #define MIF_OUTPUT_FRAME_REG 0x018 /* MIF frame/output reg */ 732 #define MIF_CONFIG_REG 0x020 /* MIF config reg */ 733 #define MIF_POLL_STATUS_REG 0x028 /* MIF poll status reg */ 734 #define MIF_POLL_MASK_REG 0x030 /* MIF poll mask reg */ 735 #define MIF_STATE_MACHINE_REG 0x038 /* MIF state machine reg */ 736 #define MIF_STATUS_REG 0x040 /* MIF status reg */ 737 #define MIF_MASK_REG 0x048 /* MIF mask reg */ 738 739 740 /* PCS registers offset */ 741 #define PCS_MII_CTRL_REG 0 /* PCS MII control reg */ 742 #define PCS_MII_STATUS_REG 0x008 /* PCS MII status reg */ 743 #define PCS_MII_ADVERT_REG 0x010 /* PCS MII advertisement */ 744 #define PCS_MII_LPA_REG 0x018 /* link partner ability */ 745 #define PCS_CONFIG_REG 0x020 /* PCS config reg */ 746 #define PCS_STATE_MACHINE_REG 0x028 /* PCS state machine */ 747 #define PCS_INTR_STATUS_REG 0x030 /* PCS interrupt status */ 748 #define PCS_DATAPATH_MODE_REG 0x0a0 /* datapath mode reg */ 749 #define PCS_PACKET_COUNT_REG 0x0c0 /* PCS packet counter */ 750 751 #define XPCS_CTRL_1_REG 0 /* Control */ 752 #define XPCS_STATUS_1_REG 0x008 753 #define XPCS_DEV_ID_REG 0x010 /* 32bits IEEE manufacture ID */ 754 #define XPCS_SPEED_ABILITY_REG 0x018 755 #define XPCS_DEV_IN_PKG_REG 0x020 756 #define XPCS_CTRL_2_REG 0x028 757 #define XPCS_STATUS_2_REG 0x030 758 #define XPCS_PKG_ID_REG 0x038 /* Package ID */ 759 #define XPCS_STATUS_REG 0x040 760 #define XPCS_TEST_CTRL_REG 0x048 761 #define XPCS_CFG_VENDOR_1_REG 0x050 762 #define XPCS_DIAG_VENDOR_2_REG 0x058 763 #define XPCS_MASK_1_REG 0x060 764 #define XPCS_PKT_CNTR_REG 0x068 765 #define XPCS_TX_STATE_MC_REG 0x070 766 #define XPCS_DESKEW_ERR_CNTR_REG 0x078 767 #define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080 768 #define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088 769 #define XPCS_TRAINING_VECTOR_REG 0x090 770 771 /* ESR registers offset */ 772 #define ESR_RESET_REG 0 773 #define ESR_CONFIG_REG 0x008 774 #define ESR_0_PLL_CONFIG_REG 0x010 775 #define ESR_0_CONTROL_REG 0x018 776 #define ESR_0_TEST_CONFIG_REG 0x020 777 #define ESR_1_PLL_CONFIG_REG 0x028 778 #define ESR_1_CONTROL_REG 0x030 779 #define ESR_1_TEST_CONFIG_REG 0x038 780 #define ESR_ENET_RGMII_CFG_REG 0x040 781 #define ESR_INTERNAL_SIGNALS_REG 0x800 782 #define ESR_DEBUG_SEL_REG 0x808 783 784 785 /* Reset Register */ 786 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time */ 787 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl */ 788 789 /* Tx MAC Status Register */ 790 #define MAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 791 #define MAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 792 #define MAC_TX_MAX_PACKET_ERR 0x00000004 /* TX frame exceeds max */ 793 #define MAC_TX_BYTE_CNT_EXP 0x00000400 /* TX byte cnt overflow */ 794 #define MAC_TX_FRAME_CNT_EXP 0x00000800 /* Tx frame cnt overflow */ 795 796 /* Rx MAC Status Register */ 797 #define MAC_RX_FRAME_RECV 0x00000001 /* successful rx frame */ 798 #define MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 799 #define MAC_RX_FRAME_COUNT 0x00000004 /* rx frame cnt rollover */ 800 #define MAC_RX_ALIGN_ERR 0x00000008 /* alignment err rollover */ 801 #define MAC_RX_CRC_ERR 0x00000010 /* crc error cnt rollover */ 802 #define MAC_RX_LEN_ERR 0x00000020 /* length err cnt rollover */ 803 #define MAC_RX_VIOL_ERR 0x00000040 /* code vio err rollover */ 804 #define MAC_RX_BYTE_CNT_EXP 0x00000080 /* RX MAC byte rollover */ 805 806 /* MAC Control Status Register */ 807 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful pause frame */ 808 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 809 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 810 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 811 #define MAC_CTRL_PAUSE_TIME_SHIFT 16 812 813 /* Tx MAC Configuration Register */ 814 #define MAC_TX_CFG_TXMAC_ENABLE 0x00000001 /* enable TX MAC. */ 815 #define MAC_TX_CFG_NO_FCS 0x00000100 /* TX not generate CRC */ 816 817 /* Rx MAC Configuration Register */ 818 #define MAC_RX_CFG_RXMAC_ENABLE 0x00000001 /* enable RX MAC */ 819 #define MAC_RX_CFG_STRIP_PAD 0x00000002 /* not supported, set to 0 */ 820 #define MAC_RX_CFG_STRIP_FCS 0x00000004 /* strip last 4bytes (CRC) */ 821 #define MAC_RX_CFG_PROMISC 0x00000008 /* promisc mode enable */ 822 #define MAC_RX_CFG_PROMISC_GROUP 0x00000010 /* accept all MC frames */ 823 #define MAC_RX_CFG_HASH_FILTER_EN 0x00000020 /* use hash table */ 824 #define MAC_RX_CFG_ADDR_FILTER_EN 0x00000040 /* use address filter */ 825 #define MAC_RX_CFG_DISABLE_DISCARD 0x00000080 /* do not set abort bit */ 826 #define MAC_RX_MAC2IPP_PKT_CNT_EN 0x00000200 /* rx pkt cnt -> BMAC-IPP */ 827 #define MAC_RX_MAC_REG_RW_TEST_MASK 0x00000c00 /* BMAC reg RW test */ 828 #define MAC_RX_MAC_REG_RW_TEST_SHIFT 10 829 830 /* MAC Control Configuration Register */ 831 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x00000001 /* send pause flow ctrl */ 832 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x00000002 /* receive pause flow ctrl */ 833 #define MAC_CTRL_CFG_PASS_CTRL 0x00000004 /* accept MAC ctrl pkts */ 834 835 /* MAC XIF Configuration Register */ 836 #define MAC_XIF_TX_OUTPUT_EN 0x00000001 /* enable Tx output driver */ 837 #define MAC_XIF_MII_INT_LOOPBACK 0x00000002 /* loopback GMII xmit data */ 838 #define MAC_XIF_GMII_MODE 0x00000008 /* operates with GMII clks */ 839 #define MAC_XIF_LINK_LED 0x00000020 /* LINKLED# active (low) */ 840 #define MAC_XIF_LED_POLARITY 0x00000040 /* LED polarity */ 841 #define MAC_XIF_SEL_CLK_25MHZ 0x00000080 /* Select 10/100Mbps */ 842 843 /* MAC IPG Registers */ 844 #define BMAC_MIN_FRAME_MASK 0x3FF /* 10-bit reg */ 845 846 /* MAC Max Frame Size Register */ 847 #define BMAC_MAX_BURST_MASK 0x3FFF0000 /* max burst size [30:16] */ 848 #define BMAC_MAX_BURST_SHIFT 16 849 #define BMAC_MAX_FRAME_MASK 0x00007FFF /* max frame size [14:0] */ 850 #define BMAC_MAX_FRAME_SHIFT 0 851 852 /* MAC Preamble size register */ 853 #define BMAC_PA_SIZE_MASK 0x000003FF 854 /* # of preable bytes TxMAC sends at the beginning of each frame */ 855 856 /* 857 * mac address registers: 858 * register contains comparison 859 * -------- -------- ---------- 860 * 0 16 MSB of primary MAC addr [47:32] of DA field 861 * 1 16 middle bits "" [31:16] of DA field 862 * 2 16 LSB "" [15:0] of DA field 863 * 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field 864 * 4*x 16 middle bits "" [31:16] 865 * 5*x 16 LSB "" [15:0] 866 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 867 * 43 16 middle bits "" [31:16] 868 * 44 16 LSB "" [15:0] 869 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 870 * if there is a match, MAC will set the bit for alternative address 871 * filter pass [15] 872 * 873 * here is the map of registers given MAC address notation: a:b:c:d:e:f 874 * ab cd ef 875 * primary addr reg 2 reg 1 reg 0 876 * alt addr 1 reg 5 reg 4 reg 3 877 * alt addr x reg 5*x reg 4*x reg 3*x 878 * | | | | 879 * | | | | 880 * alt addr 7 reg 23 reg 22 reg 21 881 * ctrl addr reg 44 reg 43 reg 42 882 */ 883 884 #define BMAC_ALT_ADDR_BASE 0x118 885 #define BMAC_MAX_ALT_ADDR_ENTRY 7 /* 7 alternate MAC addr */ 886 #define BMAC_MAX_ADDR_ENTRY (BMAC_MAX_ALT_ADDR_ENTRY + 1) 887 888 /* hash table registers */ 889 #define MAC_MAX_HASH_ENTRY 16 890 891 /* 27-bit register has the current state for key state machines in the MAC */ 892 #define MAC_SM_RLM_MASK 0x07800000 893 #define MAC_SM_RLM_SHIFT 23 894 #define MAC_SM_RX_FC_MASK 0x00700000 895 #define MAC_SM_RX_FC_SHIFT 20 896 #define MAC_SM_TLM_MASK 0x000F0000 897 #define MAC_SM_TLM_SHIFT 16 898 #define MAC_SM_ENCAP_SM_MASK 0x0000F000 899 #define MAC_SM_ENCAP_SM_SHIFT 12 900 #define MAC_SM_TX_REQ_MASK 0x00000C00 901 #define MAC_SM_TX_REQ_SHIFT 10 902 #define MAC_SM_TX_FC_MASK 0x000003C0 903 #define MAC_SM_TX_FC_SHIFT 6 904 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 905 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 906 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 907 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 908 909 #define BMAC_ADDR0_CMPEN 0x00000001 910 #define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x)) 911 912 /* MAC Host Info Table Registers */ 913 #define BMAC_MAX_HOST_INFO_ENTRY 9 /* 9 host entries */ 914 915 /* 916 * ********************* XMAC registers ********************************* 917 */ 918 919 /* Reset Register */ 920 #define XTXMAC_SOFT_RST 0x00000001 /* XTX MAC software reset */ 921 #define XTXMAC_REG_RST 0x00000002 /* XTX MAC registers reset */ 922 #define XRXMAC_SOFT_RST 0x00000001 /* XRX MAC software reset */ 923 #define XRXMAC_REG_RST 0x00000002 /* XRX MAC registers reset */ 924 925 /* XTX MAC Status Register */ 926 #define XMAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 927 #define XMAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 928 #define XMAC_TX_MAX_PACKET_ERR 0x00000004 /* XTX frame exceeds max */ 929 #define XMAC_TX_OVERFLOW 0x00000008 /* XTX byte cnt overflow */ 930 #define XMAC_TX_FIFO_XFR_ERR 0x00000010 /* xtlm state mach error */ 931 #define XMAC_TX_BYTE_CNT_EXP 0x00000400 /* XTX byte cnt overflow */ 932 #define XMAC_TX_FRAME_CNT_EXP 0x00000800 /* XTX frame cnt overflow */ 933 934 /* XRX MAC Status Register */ 935 #define XMAC_RX_FRAME_RCVD 0x00000001 /* successful rx frame */ 936 #define XMAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 937 #define XMAC_RX_UNDERFLOW 0x00000004 /* RX FIFO underrun */ 938 #define XMAC_RX_CRC_ERR_CNT_EXP 0x00000008 /* crc error cnt rollover */ 939 #define XMAC_RX_LEN_ERR_CNT_EXP 0x00000010 /* length err cnt rollover */ 940 #define XMAC_RX_VIOL_ERR_CNT_EXP 0x00000020 /* code vio err rollover */ 941 #define XMAC_RX_OCT_CNT_EXP 0x00000040 /* XRX MAC byte rollover */ 942 #define XMAC_RX_HST_CNT1_EXP 0x00000080 /* XRX MAC hist1 rollover */ 943 #define XMAC_RX_HST_CNT2_EXP 0x00000100 /* XRX MAC hist2 rollover */ 944 #define XMAC_RX_HST_CNT3_EXP 0x00000200 /* XRX MAC hist3 rollover */ 945 #define XMAC_RX_HST_CNT4_EXP 0x00000400 /* XRX MAC hist4 rollover */ 946 #define XMAC_RX_HST_CNT5_EXP 0x00000800 /* XRX MAC hist5 rollover */ 947 #define XMAC_RX_HST_CNT6_EXP 0x00001000 /* XRX MAC hist6 rollover */ 948 #define XMAC_RX_BCAST_CNT_EXP 0x00002000 /* XRX BC cnt rollover */ 949 #define XMAC_RX_MCAST_CNT_EXP 0x00004000 /* XRX MC cnt rollover */ 950 #define XMAC_RX_FRAG_CNT_EXP 0x00008000 /* fragment cnt rollover */ 951 #define XMAC_RX_ALIGNERR_CNT_EXP 0x00010000 /* framealign err rollover */ 952 #define XMAC_RX_LINK_FLT_CNT_EXP 0x00020000 /* link fault cnt rollover */ 953 #define XMAC_RX_REMOTE_FLT_DET 0x00040000 /* Remote Fault detected */ 954 #define XMAC_RX_LOCAL_FLT_DET 0x00080000 /* Local Fault detected */ 955 #define XMAC_RX_HST_CNT7_EXP 0x00100000 /* XRX MAC hist7 rollover */ 956 957 958 #define XMAC_CTRL_PAUSE_RCVD 0x00000001 /* successful pause frame */ 959 #define XMAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 960 #define XMAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 961 #define XMAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 962 #define XMAC_CTRL_PAUSE_TIME_SHIFT 16 963 964 /* XMAC Configuration Register */ 965 #define XMAC_CONFIG_TX_BIT_MASK 0x000000ff /* bits [7:0] */ 966 #define XMAC_CONFIG_RX_BIT_MASK 0x001fff00 /* bits [20:8] */ 967 #define XMAC_CONFIG_XIF_BIT_MASK 0xffe00000 /* bits [31:21] */ 968 969 /* XTX MAC config bits */ 970 #define XMAC_TX_CFG_TX_ENABLE 0x00000001 /* enable XTX MAC */ 971 #define XMAC_TX_CFG_STRETCH_MD 0x00000002 /* WAN application */ 972 #define XMAC_TX_CFG_VAR_MIN_IPG_EN 0x00000004 /* Transmit pkts < minpsz */ 973 #define XMAC_TX_CFG_ALWAYS_NO_CRC 0x00000008 /* No CRC generated */ 974 975 #define XMAC_WARNING_MSG_ENABLE 0x00000080 /* Sim warning msg enable */ 976 977 /* XRX MAC config bits */ 978 #define XMAC_RX_CFG_RX_ENABLE 0x00000100 /* enable XRX MAC */ 979 #define XMAC_RX_CFG_PROMISC 0x00000200 /* promisc mode enable */ 980 #define XMAC_RX_CFG_PROMISC_GROUP 0x00000400 /* accept all MC frames */ 981 #define XMAC_RX_CFG_ERR_CHK_DISABLE 0x00000800 /* do not set abort bit */ 982 #define XMAC_RX_CFG_CRC_CHK_DISABLE 0x00001000 /* disable CRC logic */ 983 #define XMAC_RX_CFG_RESERVED_MCAST 0x00002000 /* reserved MCaddr compare */ 984 #define XMAC_RX_CFG_CD_VIO_CHK 0x00004000 /* rx code violation chk */ 985 #define XMAC_RX_CFG_HASH_FILTER_EN 0x00008000 /* use hash table */ 986 #define XMAC_RX_CFG_ADDR_FILTER_EN 0x00010000 /* use alt addr filter */ 987 #define XMAC_RX_CFG_STRIP_CRC 0x00020000 /* strip last 4bytes (CRC) */ 988 #define XMAC_RX_MAC2IPP_PKT_CNT_EN 0x00040000 /* histo_cntr7 cnt mode */ 989 #define XMAC_RX_CFG_RX_PAUSE_EN 0x00080000 /* receive pause flow ctrl */ 990 #define XMAC_RX_CFG_PASS_FLOW_CTRL 0x00100000 /* accept MAC ctrl pkts */ 991 992 993 /* MAC transceiver (XIF) configuration registers */ 994 995 #define XMAC_XIF_FORCE_LED_ON 0x00200000 /* Force Link LED on */ 996 #define XMAC_XIF_LED_POLARITY 0x00400000 /* LED polarity */ 997 #define XMAC_XIF_SEL_POR_CLK_SRC 0x00800000 /* Select POR clk src */ 998 #define XMAC_XIF_TX_OUTPUT_EN 0x01000000 /* enable MII/GMII modes */ 999 #define XMAC_XIF_LOOPBACK 0x02000000 /* loopback xmac xgmii tx */ 1000 #define XMAC_XIF_LFS_DISABLE 0x04000000 /* disable link fault sig */ 1001 #define XMAC_XIF_MII_MODE_MASK 0x18000000 /* MII/GMII/XGMII mode */ 1002 #define XMAC_XIF_MII_MODE_SHIFT 27 1003 #define XMAC_XIF_XGMII_MODE 0x00 1004 #define XMAC_XIF_GMII_MODE 0x01 1005 #define XMAC_XIF_MII_MODE 0x02 1006 #define XMAC_XIF_ILLEGAL_MODE 0x03 1007 #define XMAC_XIF_XPCS_BYPASS 0x20000000 /* use external xpcs */ 1008 #define XMAC_XIF_1G_PCS_BYPASS 0x40000000 /* use external pcs */ 1009 #define XMAC_XIF_SEL_CLK_25MHZ 0x80000000 /* 25Mhz clk for 100mbps */ 1010 1011 /* IPG register */ 1012 #define XMAC_IPG_VALUE_MASK 0x00000007 /* IPG in XGMII mode */ 1013 #define XMAC_IPG_VALUE_SHIFT 0 1014 #define XMAC_IPG_VALUE1_MASK 0x0000ff00 /* IPG in GMII/MII mode */ 1015 #define XMAC_IPG_VALUE1_SHIFT 8 1016 #define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000 1017 #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 1018 #define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000 1019 #define XMAC_IPG_STRETCH_CONST_SHIFT 21 1020 1021 #define IPG_12_15_BYTE 3 1022 #define IPG_16_19_BYTE 4 1023 #define IPG_20_23_BYTE 5 1024 #define IPG1_12_BYTES 10 1025 #define IPG1_13_BYTES 11 1026 #define IPG1_14_BYTES 12 1027 #define IPG1_15_BYTES 13 1028 #define IPG1_16_BYTES 14 1029 1030 1031 #define XMAC_MIN_TX_FRM_SZ_MASK 0x3ff /* Min tx frame size */ 1032 #define XMAC_MIN_TX_FRM_SZ_SHIFT 0 1033 #define XMAC_SLOT_TIME_MASK 0x0003fc00 /* slot time */ 1034 #define XMAC_SLOT_TIME_SHIFT 10 1035 #define XMAC_MIN_RX_FRM_SZ_MASK 0x3ff00000 /* Min rx frame size */ 1036 #define XMAC_MIN_RX_FRM_SZ_SHIFT 20 1037 #define XMAC_MAX_FRM_SZ_MASK 0x00003fff /* max tx frame size */ 1038 1039 /* State Machine Register */ 1040 #define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007 1041 #define XMAC_SM_TX_LNK_MGMT_SHIFT 0 1042 #define XMAC_SM_SOP_DETECT 0x00000008 1043 #define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030 1044 #define XMAC_SM_LNK_FLT_SIG_SHIFT 4 1045 #define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040 1046 #define XMAC_SM_XGMII_MD_RX_LNK 0x00000080 1047 #define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100 1048 #define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200 1049 #define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00 1050 #define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10 1051 #define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000 1052 #define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18 1053 #define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000 1054 #define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23 1055 #define XMAC_SM_TXFIFO_FULL_CLK 0x10000000 1056 #define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000 1057 #define XMAC_SM_RXFIFO_FULL_CLK 0x40000000 1058 #define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000 1059 1060 /* Internal Signals 1 Register */ 1061 #define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F 1062 #define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0 1063 #define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010 1064 #define XMAC_IS1_OPP_TXMAC_TAG 0x00000020 1065 #define XMAC_IS1_OPP_TXMAC_ACK 0x00000040 1066 #define XMAC_IS1_TXMAC_OPP_REQ 0x00000080 1067 #define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00 1068 #define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8 1069 #define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000 1070 #define XMAC_IS1_RXMAC_IPP_TAG 0x20000000 1071 #define XMAC_IS1_IPP_RXMAC_REQ 0x40000000 1072 #define XMAC_IS1_RXMAC_IPP_ACK 0x80000000 1073 1074 /* Internal Signals 2 Register */ 1075 #define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F 1076 #define XMAC_IS2_TX_HB_TIMER_SHIFT 0 1077 #define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0 1078 #define XMAC_IS2_RX_HB_TIMER_SHIFT 4 1079 #define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00 1080 #define XMAC_IS2_XPCS_RXC_SHIFT 8 1081 #define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000 1082 #define XMAC_IS2_XPCS_TXC_SHIFT 16 1083 #define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000 1084 #define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000 1085 1086 /* Register size masking */ 1087 1088 #define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF 1089 #define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF 1090 #define XRXMAC_CRC_ER_CNT_MASK 0x000000FF 1091 #define XRXMAC_MPSZER_CNT_MASK 0x000000FF 1092 #define XRXMAC_CD_VIO_CNT_MASK 0x000000FF 1093 #define XRXMAC_BT_CNT_MASK 0xFFFFFFFF 1094 #define XRXMAC_HIST_CNT1_MASK 0x001FFFFF 1095 #define XRXMAC_HIST_CNT2_MASK 0x001FFFFF 1096 #define XRXMAC_HIST_CNT3_MASK 0x000FFFFF 1097 #define XRXMAC_HIST_CNT4_MASK 0x0007FFFF 1098 #define XRXMAC_HIST_CNT5_MASK 0x0003FFFF 1099 #define XRXMAC_HIST_CNT6_MASK 0x0001FFFF 1100 #define XRXMAC_HIST_CNT7_MASK 0x07FFFFFF 1101 #define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF 1102 #define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF 1103 #define XRXMAC_FRAG_CNT_MASK 0x001FFFFF 1104 #define XRXMAC_AL_ER_CNT_MASK 0x000000FF 1105 #define XMAC_LINK_FLT_CNT_MASK 0x000000FF 1106 #define BTXMAC_FRM_CNT_MASK 0x001FFFFF 1107 #define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF 1108 #define RXMAC_FRM_CNT_MASK 0x0000FFFF 1109 #define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF 1110 #define BMAC_AL_ER_CNT_MASK 0x0000FFFF 1111 #define MAC_LEN_ER_CNT_MASK 0x0000FFFF 1112 #define BMAC_CRC_ER_CNT_MASK 0x0000FFFF 1113 #define BMAC_CD_VIO_CNT_MASK 0x0000FFFF 1114 #define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF 1115 #define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF 1116 #define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000 1117 #define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16 1118 #define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF 1119 #define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000 1120 #define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16 1121 1122 /* Alternate MAC address registers */ 1123 #define XMAC_MAX_ALT_ADDR_ENTRY 16 /* 16 alternate MAC addrs */ 1124 #define XMAC_MAX_ADDR_ENTRY (XMAC_MAX_ALT_ADDR_ENTRY + 1) 1125 1126 /* Max / Min parameters for Neptune MAC */ 1127 1128 #define MAC_MAX_ALT_ADDR_ENTRY XMAC_MAX_ALT_ADDR_ENTRY 1129 #define MAC_MAX_HOST_INFO_ENTRY XMAC_MAX_HOST_INFO_ENTRY 1130 1131 /* HostInfo entry for the unique MAC address */ 1132 #define XMAC_UNIQUE_HOST_INFO_ENTRY 17 1133 #define BMAC_UNIQUE_HOST_INFO_ENTRY 0 1134 1135 /* HostInfo entry for the multicat address */ 1136 #define XMAC_MULTI_HOST_INFO_ENTRY 16 1137 #define BMAC_MULTI_HOST_INFO_ENTRY 8 1138 1139 /* XMAC Host Info Register */ 1140 typedef union hostinfo { 1141 1142 uint64_t value; 1143 1144 struct { 1145 #if defined(_BIG_ENDIAN) 1146 uint32_t msw; /* Most significant word */ 1147 uint32_t lsw; /* Least significant word */ 1148 #elif defined(_LITTLE_ENDIAN) 1149 uint32_t lsw; /* Least significant word */ 1150 uint32_t msw; /* Most significant word */ 1151 #endif 1152 } val; 1153 struct { 1154 #if defined(_BIG_ENDIAN) 1155 uint32_t w1; 1156 #endif 1157 struct { 1158 #if defined(_BIT_FIELDS_HTOL) 1159 uint32_t reserved2 : 23; 1160 uint32_t mac_pref : 1; 1161 uint32_t reserved1 : 5; 1162 uint32_t rdc_tbl_num : 3; 1163 #elif defined(_BIT_FIELDS_LTOH) 1164 uint32_t rdc_tbl_num : 3; 1165 uint32_t reserved1 : 5; 1166 uint32_t mac_pref : 1; 1167 uint32_t reserved2 : 23; 1168 #endif 1169 } w0; 1170 1171 #if defined(_LITTLE_ENDIAN) 1172 uint32_t w1; 1173 #endif 1174 } bits; 1175 1176 } hostinfo_t; 1177 1178 typedef union hostinfo *hostinfo_pt; 1179 1180 #define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007 1181 #define XMAC_HI_MAC_PREF 0x00000100 1182 1183 #define XMAC_MAX_HOST_INFO_ENTRY 20 /* 20 host entries */ 1184 1185 /* 1186 * ******************** MIF registers ********************************* 1187 */ 1188 1189 /* 1190 * 32-bit register serves as an instruction register when the MIF is 1191 * programmed in frame mode. load this register w/ a valid instruction 1192 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1193 * execution completion. during a read operation, this register will also 1194 * contain the 16-bit data returned by the transceiver. unless specified 1195 * otherwise, fields are considered "don't care" when polling for 1196 * completion. 1197 */ 1198 1199 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame mask */ 1200 #define MIF_FRAME_ST_22 0x40000000 /* STart of frame, Cl 22 */ 1201 #define MIF_FRAME_ST_45 0x00000000 /* STart of frame, Cl 45 */ 1202 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode */ 1203 #define MIF_FRAME_OP_READ_22 0x20000000 /* read OPcode, Cl 22 */ 1204 #define MIF_FRAME_OP_WRITE_22 0x10000000 /* write OPcode, Cl 22 */ 1205 #define MIF_FRAME_OP_ADDR_45 0x00000000 /* addr of reg to access */ 1206 #define MIF_FRAME_OP_READ_45 0x30000000 /* read OPcode, Cl 45 */ 1207 #define MIF_FRAME_OP_WRITE_45 0x10000000 /* write OPcode, Cl 45 */ 1208 #define MIF_FRAME_OP_P_R_I_A_45 0x10000000 /* post-read-inc-addr */ 1209 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address mask */ 1210 #define MIF_FRAME_PHY_ADDR_SHIFT 23 1211 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* reg addr in Cl 22 */ 1212 /* dev addr in Cl 45 */ 1213 #define MIF_FRAME_REG_ADDR_SHIFT 18 1214 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. */ 1215 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. */ 1216 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload */ 1217 1218 /* Clause 45 frame field values */ 1219 #define FRAME45_ST 0 1220 #define FRAME45_OP_ADDR 0 1221 #define FRAME45_OP_WRITE 1 1222 #define FRAME45_OP_READ_INC 2 1223 #define FRAME45_OP_READ 3 1224 1225 typedef union _mif_frame_t { 1226 1227 uint64_t value; 1228 1229 struct { 1230 #if defined(_BIG_ENDIAN) 1231 uint32_t msw; /* Most significant word */ 1232 uint32_t lsw; /* Least significant word */ 1233 #elif defined(_LITTLE_ENDIAN) 1234 uint32_t lsw; /* Least significant word */ 1235 uint32_t msw; /* Most significant word */ 1236 #endif 1237 } val; 1238 struct { 1239 #if defined(_BIG_ENDIAN) 1240 uint32_t w1; 1241 #endif 1242 struct { 1243 #if defined(_BIT_FIELDS_HTOL) 1244 uint32_t st : 2; 1245 uint32_t op : 2; 1246 uint32_t phyad : 5; 1247 uint32_t regad : 5; 1248 uint32_t ta_msb : 1; 1249 uint32_t ta_lsb : 1; 1250 uint32_t data : 16; 1251 #elif defined(_BIT_FIELDS_LTOH) 1252 uint32_t data : 16; 1253 uint32_t ta_lsb : 1; 1254 uint32_t ta_msb : 1; 1255 uint32_t regad : 5; 1256 uint32_t phyad : 5; 1257 uint32_t op : 2; 1258 uint32_t st : 2; 1259 #endif 1260 } w0; 1261 1262 #if defined(_LITTLE_ENDIAN) 1263 uint32_t w1; 1264 #endif 1265 } bits; 1266 } mif_frame_t; 1267 1268 #define MIF_CFG_POLL_EN 0x00000008 /* enable polling */ 1269 #define MIF_CFG_BB_MODE 0x00000010 /* bit-bang mode */ 1270 #define MIF_CFG_POLL_REG_MASK 0x000003E0 /* reg addr to be polled */ 1271 #define MIF_CFG_POLL_REG_SHIFT 5 1272 #define MIF_CFG_POLL_PHY_MASK 0x00007C00 /* XCVR addr to be polled */ 1273 #define MIF_CFG_POLL_PHY_SHIFT 10 1274 #define MIF_CFG_INDIRECT_MODE 0x0000800 1275 /* used to decide if Cl 22 */ 1276 /* or Cl 45 frame is */ 1277 /* constructed. */ 1278 /* 1 = Clause 45,ST = '00' */ 1279 /* 0 = Clause 22,ST = '01' */ 1280 #define MIF_CFG_ATCE_GE_EN 0x00010000 /* Enable ATCA gigabit mode */ 1281 1282 typedef union _mif_cfg_t { 1283 1284 uint64_t value; 1285 1286 struct { 1287 #if defined(_BIG_ENDIAN) 1288 uint32_t msw; /* Most significant word */ 1289 uint32_t lsw; /* Least significant word */ 1290 1291 #elif defined(_LITTLE_ENDIAN) 1292 uint32_t lsw; /* Least significant word */ 1293 uint32_t msw; /* Most significant word */ 1294 #endif 1295 } val; 1296 struct { 1297 #if defined(_BIG_ENDIAN) 1298 uint32_t w1; 1299 #endif 1300 struct { 1301 #if defined(_BIT_FIELDS_HTOL) 1302 uint32_t res2 : 15; 1303 uint32_t atca_ge : 1; 1304 uint32_t indirect_md : 1; 1305 uint32_t phy_addr : 5; 1306 uint32_t reg_addr : 5; 1307 uint32_t bb_mode : 1; 1308 uint32_t poll_en : 1; 1309 uint32_t res1 : 2; 1310 uint32_t res : 1; 1311 #elif defined(_BIT_FIELDS_LTOH) 1312 uint32_t res : 1; 1313 uint32_t res1 : 2; 1314 uint32_t poll_en : 1; 1315 uint32_t bb_mode : 1; 1316 uint32_t reg_addr : 5; 1317 uint32_t phy_addr : 5; 1318 uint32_t indirect_md : 1; 1319 uint32_t atca_ge : 1; 1320 uint32_t res2 : 15; 1321 #endif 1322 } w0; 1323 1324 #if defined(_LITTLE_ENDIAN) 1325 uint32_t w1; 1326 #endif 1327 } bits; 1328 1329 } mif_cfg_t; 1330 1331 #define MIF_POLL_STATUS_DATA_MASK 0xffff0000 1332 #define MIF_POLL_STATUS_STAT_MASK 0x0000ffff 1333 1334 typedef union _mif_poll_stat_t { 1335 uint64_t value; 1336 1337 struct { 1338 #if defined(_BIG_ENDIAN) 1339 uint32_t msw; /* Most significant word */ 1340 uint32_t lsw; /* Least significant word */ 1341 #elif defined(_LITTLE_ENDIAN) 1342 uint32_t lsw; /* Least significant word */ 1343 uint32_t msw; /* Most significant word */ 1344 #endif 1345 } val; 1346 struct { 1347 #if defined(_BIG_ENDIAN) 1348 uint32_t w1; 1349 #endif 1350 struct { 1351 #if defined(_BIT_FIELDS_HTOL) 1352 uint16_t data; 1353 uint16_t status; 1354 #elif defined(_BIT_FIELDS_LTOH) 1355 uint16_t status; 1356 uint16_t data; 1357 #endif 1358 } w0; 1359 1360 #if defined(_LITTLE_ENDIAN) 1361 uint32_t w1; 1362 #endif 1363 } bits; 1364 } mif_poll_stat_t; 1365 1366 1367 #define MIF_POLL_MASK_MASK 0x0000ffff 1368 1369 typedef union _mif_poll_mask_t { 1370 uint64_t value; 1371 1372 struct { 1373 #if defined(_BIG_ENDIAN) 1374 uint32_t msw; /* Most significant word */ 1375 uint32_t lsw; /* Least significant word */ 1376 #elif defined(_LITTLE_ENDIAN) 1377 uint32_t lsw; /* Least significant word */ 1378 uint32_t msw; /* Most significant word */ 1379 #endif 1380 } val; 1381 struct { 1382 #if defined(_BIG_ENDIAN) 1383 uint32_t w1; 1384 #endif 1385 struct { 1386 #if defined(_BIT_FIELDS_HTOL) 1387 uint16_t rsvd; 1388 uint16_t mask; 1389 #elif defined(_BIT_FIELDS_LTOH) 1390 uint16_t mask; 1391 uint16_t rsvd; 1392 #endif 1393 } w0; 1394 1395 #if defined(_LITTLE_ENDIAN) 1396 uint32_t w1; 1397 #endif 1398 } bits; 1399 } mif_poll_mask_t; 1400 1401 #define MIF_STATUS_INIT_DONE_MASK 0x00000001 1402 #define MIF_STATUS_XGE_ERR0_MASK 0x00000002 1403 #define MIF_STATUS_XGE_ERR1_MASK 0x00000004 1404 #define MIF_STATUS_PEU_ERR_MASK 0x00000008 1405 #define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010 1406 #define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020 1407 1408 typedef union _mif_stat_t { 1409 uint64_t value; 1410 1411 struct { 1412 #if defined(_BIG_ENDIAN) 1413 uint32_t msw; /* Most significant word */ 1414 uint32_t lsw; /* Least significant word */ 1415 #elif defined(_LITTLE_ENDIAN) 1416 uint32_t lsw; /* Least significant word */ 1417 uint32_t msw; /* Most significant word */ 1418 #endif 1419 } val; 1420 struct { 1421 #if defined(_BIG_ENDIAN) 1422 uint32_t w1; 1423 #endif 1424 struct { 1425 #if defined(_BIT_FIELDS_HTOL) 1426 uint32_t rsvd:26; 1427 uint32_t ext_phy_intr_flag1:1; 1428 uint32_t ext_phy_intr_flag0:1; 1429 uint32_t peu_err:1; 1430 uint32_t xge_err1:1; 1431 uint32_t xge_err0:1; 1432 uint32_t mif_init_done_stat:1; 1433 1434 #elif defined(_BIT_FIELDS_LTOH) 1435 uint32_t mif_init_done_stat:1; 1436 uint32_t xge_err0:1; 1437 uint32_t xge_err1:1; 1438 uint32_t ext_phy_intr_flag0:1; 1439 uint32_t ext_phy_intr_flag1:1; 1440 uint32_t rsvd:26; 1441 #endif 1442 } w0; 1443 1444 #if defined(_LITTLE_ENDIAN) 1445 uint32_t w1; 1446 #endif 1447 } bits; 1448 } mif_stat_t; 1449 1450 /* MIF State Machine Register */ 1451 1452 #define MIF_SM_EXECUTION_MASK 0x0000003f /* execution state */ 1453 #define MIF_SM_EXECUTION_SHIFT 0 1454 #define MIF_SM_CONTROL_MASK 0x000001c0 /* control state */ 1455 #define MIF_SM_CONTROL_MASK_SHIFT 6 1456 #define MIF_SM_MDI 0x00000200 1457 #define MIF_SM_MDO 0x00000400 1458 #define MIF_SM_MDO_EN 0x00000800 1459 #define MIF_SM_MDC 0x00001000 1460 #define MIF_SM_MDI_0 0x00002000 1461 #define MIF_SM_MDI_1 0x00004000 1462 #define MIF_SM_MDI_2 0x00008000 1463 #define MIF_SM_PORT_ADDR_MASK 0x001f0000 1464 #define MIF_SM_PORT_ADDR_SHIFT 16 1465 #define MIF_SM_INT_SIG_MASK 0xffe00000 1466 #define MIF_SM_INT_SIG_SHIFT 21 1467 1468 1469 /* 1470 * ******************** PCS registers ********************************* 1471 */ 1472 1473 /* PCS Registers */ 1474 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on wr */ 1475 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal */ 1476 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. */ 1477 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. */ 1478 #define PCS_MII_ISOLATE 0x0400 /* read 0. ignored on wr */ 1479 #define PCS_MII_POWER_DOWN 0x0800 /* read 0. ignored on wr */ 1480 #define PCS_MII_AUTONEG_EN 0x1000 /* autonegotiation */ 1481 #define PCS_MII_10_100_SEL 0x2000 /* read 0. ignored on wr */ 1482 #define PCS_MII_RESET 0x8000 /* reset PCS. */ 1483 1484 typedef union _pcs_ctrl_t { 1485 uint64_t value; 1486 1487 struct { 1488 #if defined(_BIG_ENDIAN) 1489 uint32_t msw; /* Most significant word */ 1490 uint32_t lsw; /* Least significant word */ 1491 #elif defined(_LITTLE_ENDIAN) 1492 uint32_t lsw; /* Least significant word */ 1493 uint32_t msw; /* Most significant word */ 1494 #endif 1495 } val; 1496 struct { 1497 #if defined(_BIG_ENDIAN) 1498 uint32_t w1; 1499 #endif 1500 struct { 1501 #if defined(_BIT_FIELDS_HTOL) 1502 uint32_t res0 : 16; 1503 uint32_t reset : 1; 1504 uint32_t res1 : 1; 1505 uint32_t sel_10_100 : 1; 1506 uint32_t an_enable : 1; 1507 uint32_t pwr_down : 1; 1508 uint32_t isolate : 1; 1509 uint32_t restart_an : 1; 1510 uint32_t duplex : 1; 1511 uint32_t col_test : 1; 1512 uint32_t sel_1000 : 1; 1513 uint32_t res2 : 6; 1514 #elif defined(_BIT_FIELDS_LTOH) 1515 uint32_t res2 : 6; 1516 uint32_t sel_1000 : 1; 1517 uint32_t col_test : 1; 1518 uint32_t duplex : 1; 1519 uint32_t restart_an : 1; 1520 uint32_t isolate : 1; 1521 uint32_t pwr_down : 1; 1522 uint32_t an_enable : 1; 1523 uint32_t sel_10_100 : 1; 1524 uint32_t res1 : 1; 1525 uint32_t reset : 1; 1526 uint32_t res0 : 16; 1527 #endif 1528 } w0; 1529 1530 #if defined(_LITTLE_ENDIAN) 1531 uint32_t w1; 1532 #endif 1533 } bits; 1534 } pcs_ctrl_t; 1535 1536 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1537 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1538 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* link status */ 1539 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 */ 1540 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* remote fault detected */ 1541 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* auto-neg completed */ 1542 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* 1000 Base-X PHY */ 1543 1544 typedef union _pcs_stat_t { 1545 uint64_t value; 1546 1547 struct { 1548 #if defined(_BIG_ENDIAN) 1549 uint32_t msw; /* Most significant word */ 1550 uint32_t lsw; /* Least significant word */ 1551 #elif defined(_LITTLE_ENDIAN) 1552 uint32_t lsw; /* Least significant word */ 1553 uint32_t msw; /* Most significant word */ 1554 #endif 1555 } val; 1556 struct { 1557 #if defined(_BIG_ENDIAN) 1558 uint32_t w1; 1559 #endif 1560 struct { 1561 #if defined(_BIT_FIELDS_HTOL) 1562 uint32_t res0 : 23; 1563 uint32_t ext_stat : 1; 1564 uint32_t res1 : 2; 1565 uint32_t an_complete : 1; 1566 uint32_t remote_fault : 1; 1567 uint32_t an_able : 1; 1568 uint32_t link_stat : 1; 1569 uint32_t jabber_detect : 1; 1570 uint32_t ext_cap : 1; 1571 #elif defined(_BIT_FIELDS_LTOH) 1572 uint32_t ext_cap : 1; 1573 uint32_t jabber_detect : 1; 1574 uint32_t link_stat : 1; 1575 uint32_t an_able : 1; 1576 uint32_t remote_fault : 1; 1577 uint32_t an_complete : 1; 1578 uint32_t res1 : 2; 1579 uint32_t ext_stat : 1; 1580 uint32_t res0 : 23; 1581 #endif 1582 } w0; 1583 1584 #if defined(_LITTLE_ENDIAN) 1585 uint32_t w1; 1586 #endif 1587 } bits; 1588 } pcs_stat_t; 1589 1590 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex */ 1591 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex */ 1592 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE sym */ 1593 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE asym */ 1594 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault */ 1595 #define PCS_MII_ADVERT_RF_SHIFT 12 1596 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1597 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1598 1599 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1600 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1601 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1602 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1603 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1604 #define PCS_MII_LPA_RF_SHIFT PCS_MII_ADVERT_RF_SHIFT 1605 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1606 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1607 1608 typedef union _pcs_anar_t { 1609 uint64_t value; 1610 1611 struct { 1612 #if defined(_BIG_ENDIAN) 1613 uint32_t msw; /* Most significant word */ 1614 uint32_t lsw; /* Least significant word */ 1615 #elif defined(_LITTLE_ENDIAN) 1616 uint32_t lsw; /* Least significant word */ 1617 uint32_t msw; /* Most significant word */ 1618 #endif 1619 } val; 1620 struct { 1621 #if defined(_BIG_ENDIAN) 1622 uint32_t w1; 1623 #endif 1624 struct { 1625 #if defined(_BIT_FIELDS_HTOL) 1626 uint32_t res0 : 16; 1627 uint32_t next_page : 1; 1628 uint32_t ack : 1; 1629 uint32_t remote_fault : 2; 1630 uint32_t res1 : 3; 1631 uint32_t asm_pause : 1; 1632 uint32_t pause : 1; 1633 uint32_t half_duplex : 1; 1634 uint32_t full_duplex : 1; 1635 uint32_t res2 : 5; 1636 #elif defined(_BIT_FIELDS_LTOH) 1637 uint32_t res2 : 5; 1638 uint32_t full_duplex : 1; 1639 uint32_t half_duplex : 1; 1640 uint32_t pause : 1; 1641 uint32_t asm_pause : 1; 1642 uint32_t res1 : 3; 1643 uint32_t remore_fault : 2; 1644 uint32_t ack : 1; 1645 uint32_t next_page : 1; 1646 uint32_t res0 : 16; 1647 #endif 1648 } w0; 1649 1650 #if defined(_LITTLE_ENDIAN) 1651 uint32_t w1; 1652 #endif 1653 } bits; 1654 } pcs_anar_t, *p_pcs_anar_t; 1655 1656 #define PCS_CFG_EN 0x0001 /* enable PCS. */ 1657 #define PCS_CFG_SD_OVERRIDE 0x0002 1658 #define PCS_CFG_SD_ACTIVE_LOW 0x0004 /* sig detect active low */ 1659 #define PCS_CFG_JITTER_STUDY_MASK 0x0018 /* jitter measurements */ 1660 #define PCS_CFG_JITTER_STUDY_SHIFT 4 1661 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x0020 /* shortens autoneg timer */ 1662 #define PCS_CFG_MASK 0x0040 /* PCS global mask bit */ 1663 1664 typedef union _pcs_cfg_t { 1665 uint64_t value; 1666 1667 struct { 1668 #if defined(_BIG_ENDIAN) 1669 uint32_t msw; /* Most significant word */ 1670 uint32_t lsw; /* Least significant word */ 1671 #elif defined(_LITTLE_ENDIAN) 1672 uint32_t lsw; /* Least significant word */ 1673 uint32_t msw; /* Most significant word */ 1674 #endif 1675 } val; 1676 struct { 1677 #if defined(_BIG_ENDIAN) 1678 uint32_t w1; 1679 #endif 1680 struct { 1681 #if defined(_BIT_FIELDS_HTOL) 1682 uint32_t res0 : 25; 1683 uint32_t mask : 1; 1684 uint32_t override_10ms_timer : 1; 1685 uint32_t jitter_study : 2; 1686 uint32_t sig_det_a_low : 1; 1687 uint32_t sig_det_override : 1; 1688 uint32_t enable : 1; 1689 #elif defined(_BIT_FIELDS_LTOH) 1690 uint32_t enable : 1; 1691 uint32_t sig_det_override : 1; 1692 uint32_t sig_det_a_low : 1; 1693 uint32_t jitter_study : 2; 1694 uint32_t override_10ms_timer : 1; 1695 uint32_t mask : 1; 1696 uint32_t res0 : 25; 1697 #endif 1698 } w0; 1699 1700 #if defined(_LITTLE_ENDIAN) 1701 uint32_t w1; 1702 #endif 1703 } bits; 1704 } pcs_cfg_t, *p_pcs_cfg_t; 1705 1706 1707 /* used for diagnostic purposes. bits 20-22 autoclear on read */ 1708 #define PCS_SM_TX_STATE_MASK 0x0000000F /* Tx idle state mask */ 1709 #define PCS_SM_TX_STATE_SHIFT 0 1710 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* Rx idle state mask */ 1711 #define PCS_SM_RX_STATE_SHIFT 4 1712 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* loss of sync state mask */ 1713 #define PCS_SM_WORD_SYNC_STATE_SHIFT 8 1714 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* sequence detect */ 1715 #define PCS_SM_SEQ_DETECT_STATE_SHIFT 11 1716 #define PCS_SM_LINK_STATE_MASK 0x0001E000 /* link state */ 1717 #define PCS_SM_LINK_STATE_SHIFT 13 1718 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link */ 1719 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of sync */ 1720 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect fail */ 1721 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* receipt of breaklink */ 1722 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes initializing */ 1723 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable */ 1724 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not achieved */ 1725 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes */ 1726 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* linkpartner send C code */ 1727 1728 typedef union _pcs_stat_mc_t { 1729 uint64_t value; 1730 1731 struct { 1732 #if defined(_BIG_ENDIAN) 1733 uint32_t msw; /* Most significant word */ 1734 uint32_t lsw; /* Least significant word */ 1735 #elif defined(_LITTLE_ENDIAN) 1736 uint32_t lsw; /* Least significant word */ 1737 uint32_t msw; /* Most significant word */ 1738 #endif 1739 } val; 1740 struct { 1741 #if defined(_BIG_ENDIAN) 1742 uint32_t w1; 1743 #endif 1744 struct { 1745 #if defined(_BIT_FIELDS_HTOL) 1746 uint32_t res2 : 2; 1747 uint32_t lnk_dwn_ni : 1; 1748 uint32_t lnk_dwn_wc : 1; 1749 uint32_t lnk_dwn_ls : 1; 1750 uint32_t lnk_dwn_nc : 1; 1751 uint32_t lnk_dwn_ser : 1; 1752 uint32_t lnk_loss_bc : 1; 1753 uint32_t res1 : 1; 1754 uint32_t loss_sd : 1; 1755 uint32_t lnk_loss_sync : 1; 1756 uint32_t lnk_loss_c : 1; 1757 uint32_t res0 : 3; 1758 uint32_t link_cfg_stat : 4; 1759 uint32_t seq_detc_stat : 2; 1760 uint32_t word_sync : 3; 1761 uint32_t rx_ctrl : 4; 1762 uint32_t tx_ctrl : 4; 1763 #elif defined(_BIT_FIELDS_LTOH) 1764 uint32_t tx_ctrl : 4; 1765 uint32_t rx_ctrl : 4; 1766 uint32_t word_sync : 3; 1767 uint32_t seq_detc_stat : 2; 1768 uint32_t link_cfg_stat : 4; 1769 uint32_t res0 : 3; 1770 uint32_t lnk_loss_c : 1; 1771 uint32_t lnk_loss_sync : 1; 1772 uint32_t loss_sd : 1; 1773 uint32_t res1 : 1; 1774 uint32_t lnk_loss_bc : 1; 1775 uint32_t lnk_dwn_ser : 1; 1776 uint32_t lnk_dwn_nc : 1; 1777 uint32_t lnk_dwn_ls : 1; 1778 uint32_t lnk_dwn_wc : 1; 1779 uint32_t lnk_dwn_ni : 1; 1780 uint32_t res2 : 2; 1781 #endif 1782 } w0; 1783 1784 #if defined(_LITTLE_ENDIAN) 1785 uint32_t w1; 1786 #endif 1787 } bits; 1788 } pcs_stat_mc_t, *p_pcs_stat_mc_t; 1789 1790 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed */ 1791 1792 /* 1793 * control which network interface is used. no more than one bit should 1794 * be set. 1795 */ 1796 #define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */ 1797 #define PCS_DATAPATH_MODE_MII 0x00000002 /* GMII/RGMII is selected. */ 1798 1799 #define PCS_PACKET_COUNT_TX_MASK 0x000007FF /* pkts xmitted by PCS */ 1800 #define PCS_PACKET_COUNT_RX_MASK 0x07FF0000 /* pkts recvd by PCS */ 1801 #define PCS_PACKET_COUNT_RX_SHIFT 16 1802 1803 /* 1804 * ******************** XPCS registers ********************************* 1805 */ 1806 1807 /* XPCS Base 10G Control1 Register */ 1808 #define XPCS_CTRL1_RST 0x8000 /* Self clearing reset. */ 1809 #define XPCS_CTRL1_LOOPBK 0x4000 /* xpcs Loopback */ 1810 #define XPCS_CTRL1_SPEED_SEL_3 0x2000 /* 1 indicates 10G speed */ 1811 #define XPCS_CTRL1_LOW_PWR 0x0800 /* low power mode. */ 1812 #define XPCS_CTRL1_SPEED_SEL_1 0x0040 /* 1 indicates 10G speed */ 1813 #define XPCS_CTRL1_SPEED_SEL_0_MASK 0x003c /* 0 indicates 10G speed. */ 1814 #define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2 1815 1816 1817 1818 typedef union _xpcs_ctrl1_t { 1819 uint64_t value; 1820 1821 struct { 1822 #if defined(_BIG_ENDIAN) 1823 uint32_t msw; /* Most significant word */ 1824 uint32_t lsw; /* Least significant word */ 1825 #elif defined(_LITTLE_ENDIAN) 1826 uint32_t lsw; /* Least significant word */ 1827 uint32_t msw; /* Most significant word */ 1828 #endif 1829 } val; 1830 struct { 1831 #if defined(_BIG_ENDIAN) 1832 uint32_t w1; 1833 #endif 1834 struct { 1835 #if defined(_BIT_FIELDS_HTOL) 1836 uint32_t res3 : 16; 1837 uint32_t reset : 1; 1838 uint32_t csr_lb : 1; 1839 uint32_t csr_speed_sel3 : 1; 1840 uint32_t res2 : 1; 1841 uint32_t csr_low_pwr : 1; 1842 uint32_t res1 : 4; 1843 uint32_t csr_speed_sel1 : 1; 1844 uint32_t csr_speed_sel0 : 4; 1845 uint32_t res0 : 2; 1846 #elif defined(_BIT_FIELDS_LTOH) 1847 uint32_t res0 : 2; 1848 uint32_t csr_speed_sel0 : 4; 1849 uint32_t csr_speed_sel1 : 1; 1850 uint32_t res1 : 4; 1851 uint32_t csr_low_pwr : 1; 1852 uint32_t res2 : 1; 1853 uint32_t csr_speed_sel3 : 1; 1854 uint32_t csr_lb : 1; 1855 uint32_t reset : 1; 1856 uint32_t res3 : 16; 1857 #endif 1858 } w0; 1859 1860 #if defined(_LITTLE_ENDIAN) 1861 uint32_t w1; 1862 #endif 1863 } bits; 1864 } xpcs_ctrl1_t; 1865 1866 1867 /* XPCS Base 10G Status1 Register (Read Only) */ 1868 #define XPCS_STATUS1_FAULT 0x0080 1869 #define XPCS_STATUS1_RX_LINK_STATUS_UP 0x0004 /* Link status interrupt */ 1870 #define XPCS_STATUS1_LOW_POWER_ABILITY 0x0002 /* low power mode */ 1871 #define XPCS_STATUS_RX_LINK_STATUS_UP 0x1000 /* Link status interrupt */ 1872 1873 1874 typedef union _xpcs_stat1_t { 1875 uint64_t value; 1876 1877 struct { 1878 #if defined(_BIG_ENDIAN) 1879 uint32_t msw; /* Most significant word */ 1880 uint32_t lsw; /* Least significant word */ 1881 #elif defined(_LITTLE_ENDIAN) 1882 uint32_t lsw; /* Least significant word */ 1883 uint32_t msw; /* Most significant word */ 1884 #endif 1885 } val; 1886 struct { 1887 #if defined(_BIG_ENDIAN) 1888 uint32_t w1; 1889 #endif 1890 struct { 1891 #if defined(_BIT_FIELDS_HTOL) 1892 uint32_t res4 : 16; 1893 uint32_t res3 : 8; 1894 uint32_t csr_fault : 1; 1895 uint32_t res1 : 4; 1896 uint32_t csr_rx_link_stat : 1; 1897 uint32_t csr_low_pwr_ability : 1; 1898 uint32_t res0 : 1; 1899 #elif defined(_BIT_FIELDS_LTOH) 1900 uint32_t res0 : 1; 1901 uint32_t csr_low_pwr_ability : 1; 1902 uint32_t csr_rx_link_stat : 1; 1903 uint32_t res1 : 4; 1904 uint32_t csr_fault : 1; 1905 uint32_t res3 : 8; 1906 uint32_t res4 : 16; 1907 #endif 1908 } w0; 1909 1910 #if defined(_LITTLE_ENDIAN) 1911 uint32_t w1; 1912 #endif 1913 } bits; 1914 } xpcs_stat1_t; 1915 1916 1917 /* XPCS Base Speed Ability Register. Indicates 10G capability */ 1918 #define XPCS_SPEED_ABILITY_10_GIG 0x0001 1919 1920 1921 typedef union _xpcs_speed_ab_t { 1922 uint64_t value; 1923 1924 struct { 1925 #if defined(_BIG_ENDIAN) 1926 uint32_t msw; /* Most significant word */ 1927 uint32_t lsw; /* Least significant word */ 1928 #elif defined(_LITTLE_ENDIAN) 1929 uint32_t lsw; /* Least significant word */ 1930 uint32_t msw; /* Most significant word */ 1931 #endif 1932 } val; 1933 struct { 1934 #if defined(_BIG_ENDIAN) 1935 uint32_t w1; 1936 #endif 1937 struct { 1938 #if defined(_BIT_FIELDS_HTOL) 1939 uint32_t res1 : 16; 1940 uint32_t res0 : 15; 1941 uint32_t csr_10gig : 1; 1942 #elif defined(_BIT_FIELDS_LTOH) 1943 uint32_t csr_10gig : 1; 1944 uint32_t res0 : 15; 1945 uint32_t res1 : 16; 1946 #endif 1947 } w0; 1948 1949 #if defined(_LITTLE_ENDIAN) 1950 uint32_t w1; 1951 #endif 1952 } bits; 1953 } xpcs_speed_ab_t; 1954 1955 1956 /* XPCS Base 10G Devices in Package Register */ 1957 #define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000 1958 #define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000 1959 #define XPCS_DEV_IN_PKG_DTE_XS 0x00000020 1960 #define XPCS_DEV_IN_PKG_PHY_XS 0x00000010 1961 #define XPCS_DEV_IN_PKG_PCS 0x00000008 1962 #define XPCS_DEV_IN_PKG_WIS 0x00000004 1963 #define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002 1964 #define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000 1965 1966 1967 1968 typedef union _xpcs_dev_in_pkg_t { 1969 uint64_t value; 1970 1971 struct { 1972 #if defined(_BIG_ENDIAN) 1973 uint32_t msw; /* Most significant word */ 1974 uint32_t lsw; /* Least significant word */ 1975 #elif defined(_LITTLE_ENDIAN) 1976 uint32_t lsw; /* Least significant word */ 1977 uint32_t msw; /* Most significant word */ 1978 #endif 1979 } val; 1980 struct { 1981 #if defined(_BIG_ENDIAN) 1982 uint32_t w1; 1983 #endif 1984 struct { 1985 #if defined(_BIT_FIELDS_HTOL) 1986 uint32_t csr_vendor2 : 1; 1987 uint32_t csr_vendor1 : 1; 1988 uint32_t res1 : 14; 1989 uint32_t res0 : 10; 1990 uint32_t dte_xs : 1; 1991 uint32_t phy_xs : 1; 1992 uint32_t pcs : 1; 1993 uint32_t wis : 1; 1994 uint32_t pmd_pma : 1; 1995 uint32_t clause_22_reg : 1; 1996 #elif defined(_BIT_FIELDS_LTOH) 1997 uint32_t clause_22_reg : 1; 1998 uint32_t pmd_pma : 1; 1999 uint32_t wis : 1; 2000 uint32_t pcs : 1; 2001 uint32_t phy_xs : 1; 2002 uint32_t dte_xs : 1; 2003 uint32_t res0 : 10; 2004 uint32_t res1 : 14; 2005 uint32_t csr_vendor1 : 1; 2006 uint32_t csr_vendor2 : 1; 2007 #endif 2008 } w0; 2009 2010 #if defined(_LITTLE_ENDIAN) 2011 uint32_t w1; 2012 #endif 2013 } bits; 2014 } xpcs_dev_in_pkg_t; 2015 2016 2017 /* XPCS Base 10G Control2 Register */ 2018 #define XPCS_PSC_SEL_MASK 0x0003 2019 #define PSC_SEL_10G_BASE_X_PCS 0x0001 2020 2021 2022 typedef union _xpcs_ctrl2_t { 2023 uint64_t value; 2024 2025 struct { 2026 #if defined(_BIG_ENDIAN) 2027 uint32_t msw; /* Most significant word */ 2028 uint32_t lsw; /* Least significant word */ 2029 #elif defined(_LITTLE_ENDIAN) 2030 uint32_t lsw; /* Least significant word */ 2031 uint32_t msw; /* Most significant word */ 2032 #endif 2033 } val; 2034 struct { 2035 #if defined(_BIG_ENDIAN) 2036 uint32_t w1; 2037 #endif 2038 struct { 2039 #if defined(_BIT_FIELDS_HTOL) 2040 uint32_t res1 : 16; 2041 uint32_t res0 : 14; 2042 uint32_t csr_psc_sel : 2; 2043 #elif defined(_BIT_FIELDS_LTOH) 2044 uint32_t csr_psc_sel : 2; 2045 uint32_t res0 : 14; 2046 uint32_t res1 : 16; 2047 #endif 2048 } w0; 2049 2050 #if defined(_LITTLE_ENDIAN) 2051 uint32_t w1; 2052 #endif 2053 } bits; 2054 } xpcs_ctrl2_t; 2055 2056 2057 /* XPCS Base10G Status2 Register */ 2058 #define XPCS_STATUS2_DEV_PRESENT_MASK 0xc000 /* ?????? */ 2059 #define XPCS_STATUS2_TX_FAULT 0x0800 /* Fault on tx path */ 2060 #define XPCS_STATUS2_RX_FAULT 0x0400 /* Fault on rx path */ 2061 #define XPCS_STATUS2_TEN_GBASE_W 0x0004 /* 10G-Base-W */ 2062 #define XPCS_STATUS2_TEN_GBASE_X 0x0002 /* 10G-Base-X */ 2063 #define XPCS_STATUS2_TEN_GBASE_R 0x0001 /* 10G-Base-R */ 2064 2065 typedef union _xpcs_stat2_t { 2066 uint64_t value; 2067 2068 struct { 2069 #if defined(_BIG_ENDIAN) 2070 uint32_t msw; /* Most significant word */ 2071 uint32_t lsw; /* Least significant word */ 2072 #elif defined(_LITTLE_ENDIAN) 2073 uint32_t lsw; /* Least significant word */ 2074 uint32_t msw; /* Most significant word */ 2075 #endif 2076 } val; 2077 struct { 2078 #if defined(_BIG_ENDIAN) 2079 uint32_t w1; 2080 #endif 2081 struct { 2082 #if defined(_BIT_FIELDS_HTOL) 2083 uint32_t res2 : 16; 2084 uint32_t csr_dev_pres : 2; 2085 uint32_t res1 : 2; 2086 uint32_t csr_tx_fault : 1; 2087 uint32_t csr_rx_fault : 1; 2088 uint32_t res0 : 7; 2089 uint32_t ten_gbase_w : 1; 2090 uint32_t ten_gbase_x : 1; 2091 uint32_t ten_gbase_r : 1; 2092 #elif defined(_BIT_FIELDS_LTOH) 2093 uint32_t ten_gbase_r : 1; 2094 uint32_t ten_gbase_x : 1; 2095 uint32_t ten_gbase_w : 1; 2096 uint32_t res0 : 7; 2097 uint32_t csr_rx_fault : 1; 2098 uint32_t csr_tx_fault : 1; 2099 uint32_t res1 : 2; 2100 uint32_t csr_dev_pres : 2; 2101 uint32_t res2 : 16; 2102 #endif 2103 } w0; 2104 2105 #if defined(_LITTLE_ENDIAN) 2106 uint32_t w1; 2107 #endif 2108 } bits; 2109 } xpcs_stat2_t; 2110 2111 2112 2113 /* XPCS Base10G Status Register */ 2114 #define XPCS_STATUS_LANE_ALIGN 0x1000 /* 10GBaseX PCS rx lanes align */ 2115 #define XPCS_STATUS_PATTERN_TEST_ABLE 0x0800 /* able to generate patterns. */ 2116 #define XPCS_STATUS_LANE3_SYNC 0x0008 /* Lane 3 is synchronized */ 2117 #define XPCS_STATUS_LANE2_SYNC 0x0004 /* Lane 2 is synchronized */ 2118 #define XPCS_STATUS_LANE1_SYNC 0x0002 /* Lane 1 is synchronized */ 2119 #define XPCS_STATUS_LANE0_SYNC 0x0001 /* Lane 0 is synchronized */ 2120 2121 typedef union _xpcs_stat_t { 2122 uint64_t value; 2123 2124 struct { 2125 #if defined(_BIG_ENDIAN) 2126 uint32_t msw; /* Most significant word */ 2127 uint32_t lsw; /* Least significant word */ 2128 #elif defined(_LITTLE_ENDIAN) 2129 uint32_t lsw; /* Least significant word */ 2130 uint32_t msw; /* Most significant word */ 2131 #endif 2132 } val; 2133 struct { 2134 #if defined(_BIG_ENDIAN) 2135 uint32_t w1; 2136 #endif 2137 struct { 2138 #if defined(_BIT_FIELDS_HTOL) 2139 uint32_t res2 : 16; 2140 uint32_t res1 : 3; 2141 uint32_t csr_lane_align : 1; 2142 uint32_t csr_pattern_test_able : 1; 2143 uint32_t res0 : 7; 2144 uint32_t csr_lane3_sync : 1; 2145 uint32_t csr_lane2_sync : 1; 2146 uint32_t csr_lane1_sync : 1; 2147 uint32_t csr_lane0_sync : 1; 2148 #elif defined(_BIT_FIELDS_LTOH) 2149 uint32_t csr_lane0_sync : 1; 2150 uint32_t csr_lane1_sync : 1; 2151 uint32_t csr_lane2_sync : 1; 2152 uint32_t csr_lane3_sync : 1; 2153 uint32_t res0 : 7; 2154 uint32_t csr_pat_test_able : 1; 2155 uint32_t csr_lane_align : 1; 2156 uint32_t res1 : 3; 2157 uint32_t res2 : 16; 2158 #endif 2159 } w0; 2160 2161 #if defined(_LITTLE_ENDIAN) 2162 uint32_t w1; 2163 #endif 2164 } bits; 2165 } xpcs_stat_t; 2166 2167 /* XPCS Base10G Test Control Register */ 2168 #define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004 2169 #define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003 2170 #define TEST_PATTERN_HIGH_FREQ 0 2171 #define TEST_PATTERN_LOW_FREQ 1 2172 #define TEST_PATTERN_MIXED_FREQ 2 2173 2174 typedef union _xpcs_test_ctl_t { 2175 uint64_t value; 2176 2177 struct { 2178 #if defined(_BIG_ENDIAN) 2179 uint32_t msw; /* Most significant word */ 2180 uint32_t lsw; /* Least significant word */ 2181 #elif defined(_LITTLE_ENDIAN) 2182 uint32_t lsw; /* Least significant word */ 2183 uint32_t msw; /* Most significant word */ 2184 #endif 2185 } val; 2186 struct { 2187 #if defined(_BIG_ENDIAN) 2188 uint32_t w1; 2189 #endif 2190 struct { 2191 #if defined(_BIT_FIELDS_HTOL) 2192 uint32_t res1 : 16; 2193 uint32_t res0 : 13; 2194 uint32_t csr_tx_test_en : 1; 2195 uint32_t csr_test_pat_sel : 2; 2196 #elif defined(_BIT_FIELDS_LTOH) 2197 uint32_t csr_test_pat_sel : 2; 2198 uint32_t csr_tx_test_en : 1; 2199 uint32_t res0 : 13; 2200 uint32_t res1 : 16; 2201 #endif 2202 } w0; 2203 2204 #if defined(_LITTLE_ENDIAN) 2205 uint32_t w1; 2206 #endif 2207 } bits; 2208 } xpcs_test_ctl_t; 2209 2210 /* XPCS Base10G Diagnostic Register */ 2211 #define XPCS_DIAG_EB_ALIGN_ERR3 0x40 2212 #define XPCS_DIAG_EB_ALIGN_ERR2 0x20 2213 #define XPCS_DIAG_EB_ALIGN_ERR1 0x10 2214 #define XPCS_DIAG_EB_DESKEW_OK 0x08 2215 #define XPCS_DIAG_EB_ALIGN_DET3 0x04 2216 #define XPCS_DIAG_EB_ALIGN_DET2 0x02 2217 #define XPCS_DIAG_EB_ALIGN_DET1 0x01 2218 #define XPCS_DIAG_EB_DESKEW_LOSS 0 2219 2220 #define XPCS_DIAG_SYNC_3_INVALID 0x8 2221 #define XPCS_DIAG_SYNC_2_INVALID 0x4 2222 #define XPCS_DIAG_SYNC_1_INVALID 0x2 2223 #define XPCS_DIAG_SYNC_IN_SYNC 0x1 2224 #define XPCS_DIAG_SYNC_LOSS_SYNC 0 2225 2226 #define XPCS_RX_SM_RECEIVE_STATE 1 2227 #define XPCS_RX_SM_FAULT_STATE 0 2228 2229 typedef union _xpcs_diag_t { 2230 uint64_t value; 2231 2232 struct { 2233 #if defined(_BIG_ENDIAN) 2234 uint32_t msw; /* Most significant word */ 2235 uint32_t lsw; /* Least significant word */ 2236 #elif defined(_LITTLE_ENDIAN) 2237 uint32_t lsw; /* Least significant word */ 2238 uint32_t msw; /* Most significant word */ 2239 #endif 2240 } val; 2241 struct { 2242 #if defined(_BIG_ENDIAN) 2243 uint32_t w1; 2244 #endif 2245 struct { 2246 #if defined(_BIT_FIELDS_HTOL) 2247 uint32_t res1 : 7; 2248 uint32_t sync_sm_lane3 : 4; 2249 uint32_t sync_sm_lane2 : 4; 2250 uint32_t sync_sm_lane1 : 4; 2251 uint32_t sync_sm_lane0 : 4; 2252 uint32_t elastic_buffer_sm : 8; 2253 uint32_t receive_sm : 1; 2254 #elif defined(_BIT_FIELDS_LTOH) 2255 uint32_t receive_sm : 1; 2256 uint32_t elastic_buffer_sm : 8; 2257 uint32_t sync_sm_lane0 : 4; 2258 uint32_t sync_sm_lane1 : 4; 2259 uint32_t sync_sm_lane2 : 4; 2260 uint32_t sync_sm_lane3 : 4; 2261 uint32_t res1 : 7; 2262 #endif 2263 } w0; 2264 2265 #if defined(_LITTLE_ENDIAN) 2266 uint32_t w1; 2267 #endif 2268 } bits; 2269 } xpcs_diag_t; 2270 2271 /* XPCS Base10G Tx State Machine Register */ 2272 #define XPCS_TX_SM_SEND_UNDERRUN 0x9 2273 #define XPCS_TX_SM_SEND_RANDOM_Q 0x8 2274 #define XPCS_TX_SM_SEND_RANDOM_K 0x7 2275 #define XPCS_TX_SM_SEND_RANDOM_A 0x6 2276 #define XPCS_TX_SM_SEND_RANDOM_R 0x5 2277 #define XPCS_TX_SM_SEND_Q 0x4 2278 #define XPCS_TX_SM_SEND_K 0x3 2279 #define XPCS_TX_SM_SEND_A 0x2 2280 #define XPCS_TX_SM_SEND_SDP 0x1 2281 #define XPCS_TX_SM_SEND_DATA 0 2282 2283 /* XPCS Base10G Configuration Register */ 2284 #define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78 2285 #define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3 2286 #define XPCS_CFG_BYPASS_SIG_DETECT 0x0004 2287 #define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002 2288 #define XPCS_CFG_XPCS_ENABLE 0x0001 2289 2290 typedef union _xpcs_config_t { 2291 uint64_t value; 2292 2293 struct { 2294 #if defined(_BIG_ENDIAN) 2295 uint32_t msw; /* Most significant word */ 2296 uint32_t lsw; /* Least significant word */ 2297 #elif defined(_LITTLE_ENDIAN) 2298 uint32_t lsw; /* Least significant word */ 2299 uint32_t msw; /* Most significant word */ 2300 #endif 2301 } val; 2302 struct { 2303 #if defined(_BIG_ENDIAN) 2304 uint32_t w1; 2305 #endif 2306 struct { 2307 #if defined(_BIT_FIELDS_HTOL) 2308 uint32_t res1 : 16; 2309 uint32_t res0 : 9; 2310 uint32_t csr_vendor_dbg_sel : 4; 2311 uint32_t csr_bypass_sig_detect : 1; 2312 uint32_t csr_en_tx_buf : 1; 2313 uint32_t csr_xpcs_en : 1; 2314 #elif defined(_BIT_FIELDS_LTOH) 2315 uint32_t csr_xpcs_en : 1; 2316 uint32_t csr_en_tx_buf : 1; 2317 uint32_t csr_bypass_sig_detect : 1; 2318 uint32_t csr_vendor_dbg_sel : 4; 2319 uint32_t res0 : 9; 2320 uint32_t res1 : 16; 2321 #endif 2322 } w0; 2323 2324 #if defined(_LITTLE_ENDIAN) 2325 uint32_t w1; 2326 #endif 2327 } bits; 2328 } xpcs_config_t; 2329 2330 2331 2332 /* XPCS Base10G Mask1 Register */ 2333 #define XPCS_MASK1_FAULT_MASK 0x0080 /* mask fault interrupt. */ 2334 #define XPCS_MASK1_RX_LINK_STATUS_MASK 0x0040 /* mask linkstat interrupt */ 2335 2336 /* XPCS Base10G Packet Counter */ 2337 #define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000 2338 #define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16 2339 #define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff 2340 #define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0 2341 2342 /* XPCS Base10G TX State Machine status register */ 2343 #define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f 2344 #define XPCS_DESKEW_ERR_CNTR_MASK 0xff 2345 2346 /* XPCS Base10G Lane symbol error counters */ 2347 #define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000 2348 #define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff 2349 #define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000 2350 #define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff 2351 2352 #define XPCS_SYM_ERR_CNT_MULTIPLIER 16 2353 2354 /* ESR Reset Register */ 2355 #define ESR_RESET_1 2 2356 #define ESR_RESET_0 1 2357 2358 /* ESR Configuration Register */ 2359 #define ESR_BLUNT_END_LOOPBACK 2 2360 #define ESR_FORCE_SERDES_SERDES_RDY 1 2361 2362 /* ESR Neptune Serdes PLL Configuration */ 2363 #define ESR_PLL_CFG_FBDIV_0 0x1 2364 #define ESR_PLL_CFG_FBDIV_1 0x2 2365 #define ESR_PLL_CFG_FBDIV_2 0x4 2366 #define ESR_PLL_CFG_HALF_RATE_0 0x8 2367 #define ESR_PLL_CFG_HALF_RATE_1 0x10 2368 #define ESR_PLL_CFG_HALF_RATE_2 0x20 2369 #define ESR_PLL_CFG_HALF_RATE_3 0x40 2370 #define ESR_PLL_CFG_1G_SERDES (ESR_PLL_CFG_FBDIV_0 | \ 2371 ESR_PLL_CFG_HALF_RATE_0 | \ 2372 ESR_PLL_CFG_HALF_RATE_1 | \ 2373 ESR_PLL_CFG_HALF_RATE_2 | \ 2374 ESR_PLL_CFG_HALF_RATE_3) 2375 2376 #define ESR_PLL_CFG_10G_SERDES ESR_PLL_CFG_FBDIV_2 2377 2378 /* ESR Neptune Serdes Control Register */ 2379 #define ESR_CTL_EN_SYNCDET_0 0x00000001 2380 #define ESR_CTL_EN_SYNCDET_1 0x00000002 2381 #define ESR_CTL_EN_SYNCDET_2 0x00000004 2382 #define ESR_CTL_EN_SYNCDET_3 0x00000008 2383 #define ESR_CTL_OUT_EMPH_0_MASK 0x00000070 2384 #define ESR_CTL_OUT_EMPH_0_SHIFT 4 2385 #define ESR_CTL_OUT_EMPH_1_MASK 0x00000380 2386 #define ESR_CTL_OUT_EMPH_1_SHIFT 7 2387 #define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00 2388 #define ESR_CTL_OUT_EMPH_2_SHIFT 10 2389 #define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000 2390 #define ESR_CTL_OUT_EMPH_3_SHIFT 13 2391 #define ESR_CTL_LOSADJ_0_MASK 0x00070000 2392 #define ESR_CTL_LOSADJ_0_SHIFT 16 2393 #define ESR_CTL_LOSADJ_1_MASK 0x00380000 2394 #define ESR_CTL_LOSADJ_1_SHIFT 19 2395 #define ESR_CTL_LOSADJ_2_MASK 0x01c00000 2396 #define ESR_CTL_LOSADJ_2_SHIFT 22 2397 #define ESR_CTL_LOSADJ_3_MASK 0x0e000000 2398 #define ESR_CTL_LOSADJ_3_SHIFT 25 2399 #define ESR_CTL_RXITERM_0 0x10000000 2400 #define ESR_CTL_RXITERM_1 0x20000000 2401 #define ESR_CTL_RXITERM_2 0x40000000 2402 #define ESR_CTL_RXITERM_3 0x80000000 2403 #define ESR_CTL_1G_SERDES (ESR_CTL_EN_SYNCDET_0 | \ 2404 ESR_CTL_EN_SYNCDET_1 | \ 2405 ESR_CTL_EN_SYNCDET_2 | \ 2406 ESR_CTL_EN_SYNCDET_3 | \ 2407 (0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \ 2408 (0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \ 2409 (0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \ 2410 (0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \ 2411 (0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \ 2412 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \ 2413 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \ 2414 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \ 2415 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)) 2416 2417 /* ESR Neptune Serdes Test Configuration Register */ 2418 #define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003 2419 #define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0 2420 #define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c 2421 #define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2 2422 #define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030 2423 #define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4 2424 #define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0 2425 #define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6 2426 #define ESR_TSTCFG_LBTEST_PAD (ESR_PAD_LOOPBACK_CH3 | \ 2427 ESR_PAD_LOOPBACK_CH2 | \ 2428 ESR_PAD_LOOPBACK_CH1 | \ 2429 ESR_PAD_LOOPBACK_CH0) 2430 2431 /* ESR Neptune Ethernet RGMII Configuration Register */ 2432 #define ESR_RGMII_PT0_IN_USE 0x00000001 2433 #define ESR_RGMII_PT1_IN_USE 0x00000002 2434 #define ESR_RGMII_PT2_IN_USE 0x00000004 2435 #define ESR_RGMII_PT3_IN_USE 0x00000008 2436 #define ESR_RGMII_REG_RW_TEST 0x00000010 2437 2438 /* ESR Internal Signals Observation Register */ 2439 #define ESR_SIG_MASK 0xFFFFFFFF 2440 #define ESR_SIG_P0_BITS_MASK 0x33E0000F 2441 #define ESR_SIG_P1_BITS_MASK 0x0C1F00F0 2442 #define ESR_SIG_SERDES_RDY0_P0 0x20000000 2443 #define ESR_SIG_DETECT0_P0 0x10000000 2444 #define ESR_SIG_SERDES_RDY0_P1 0x08000000 2445 #define ESR_SIG_DETECT0_P1 0x04000000 2446 #define ESR_SIG_XSERDES_RDY_P0 0x02000000 2447 #define ESR_SIG_XDETECT_P0_CH3 0x01000000 2448 #define ESR_SIG_XDETECT_P0_CH2 0x00800000 2449 #define ESR_SIG_XDETECT_P0_CH1 0x00400000 2450 #define ESR_SIG_XDETECT_P0_CH0 0x00200000 2451 #define ESR_SIG_XSERDES_RDY_P1 0x00100000 2452 #define ESR_SIG_XDETECT_P1_CH3 0x00080000 2453 #define ESR_SIG_XDETECT_P1_CH2 0x00040000 2454 #define ESR_SIG_XDETECT_P1_CH1 0x00020000 2455 #define ESR_SIG_XDETECT_P1_CH0 0x00010000 2456 #define ESR_SIG_LOS_P1_CH3 0x00000080 2457 #define ESR_SIG_LOS_P1_CH2 0x00000040 2458 #define ESR_SIG_LOS_P1_CH1 0x00000020 2459 #define ESR_SIG_LOS_P1_CH0 0x00000010 2460 #define ESR_SIG_LOS_P0_CH3 0x00000008 2461 #define ESR_SIG_LOS_P0_CH2 0x00000004 2462 #define ESR_SIG_LOS_P0_CH1 0x00000002 2463 #define ESR_SIG_LOS_P0_CH0 0x00000001 2464 #define ESR_SIG_P0_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P0 | \ 2465 ESR_SIG_DETECT0_P0) 2466 #define ESR_SIG_P1_BITS_MASK_1G (ESR_SIG_SERDES_RDY0_P1 | \ 2467 ESR_SIG_DETECT0_P1) 2468 2469 /* ESR Debug Selection Register */ 2470 #define ESR_DEBUG_SEL_MASK 0x00000003f 2471 2472 /* ESR Test Configuration Register */ 2473 #define ESR_NO_LOOPBACK_CH3 (0x0 << 6) 2474 #define ESR_EWRAP_CH3 (0x1 << 6) 2475 #define ESR_PAD_LOOPBACK_CH3 (0x2 << 6) 2476 #define ESR_REVLOOPBACK_CH3 (0x3 << 6) 2477 #define ESR_NO_LOOPBACK_CH2 (0x0 << 4) 2478 #define ESR_EWRAP_CH2 (0x1 << 4) 2479 #define ESR_PAD_LOOPBACK_CH2 (0x2 << 4) 2480 #define ESR_REVLOOPBACK_CH2 (0x3 << 4) 2481 #define ESR_NO_LOOPBACK_CH1 (0x0 << 2) 2482 #define ESR_EWRAP_CH1 (0x1 << 2) 2483 #define ESR_PAD_LOOPBACK_CH1 (0x2 << 2) 2484 #define ESR_REVLOOPBACK_CH1 (0x3 << 2) 2485 #define ESR_NO_LOOPBACK_CH0 0x0 2486 #define ESR_EWRAP_CH0 0x1 2487 #define ESR_PAD_LOOPBACK_CH0 0x2 2488 #define ESR_REVLOOPBACK_CH0 0x3 2489 2490 /* convert values */ 2491 #define NXGE_BASE(x, y) \ 2492 (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2493 2494 #define NXGE_VAL_GET(fieldname, regval) \ 2495 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT)) 2496 2497 #define NXGE_VAL_SET(fieldname, regval, val) \ 2498 { \ 2499 (regval) &= ~((fieldname) ## _MASK); \ 2500 (regval) |= ((val) << (fieldname ## _SHIFT)); \ 2501 } 2502 2503 2504 #ifdef __cplusplus 2505 } 2506 #endif 2507 2508 #endif /* _SYS_MAC_NXGE_MAC_HW_H */ 2509