1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_MAC_H 27 #define _SYS_NXGE_NXGE_MAC_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_mac_hw.h> 34 #include <npi_mac.h> 35 36 #define NXGE_MTU_DEFAULT_MAX 1522 /* 0x5f2 */ 37 #define NXGE_DEFAULT_MTU 1500 /* 0x5dc */ 38 #define NXGE_MIN_MAC_FRAMESIZE 64 39 #define NXGE_MAX_MAC_FRAMESIZE NXGE_MTU_DEFAULT_MAX 40 /* 41 * Maximum MTU: maximum frame size supported by the 42 * hardware (9216) - (22). 43 * (22 = ether header size (including VLAN) - CRC size (4)). 44 */ 45 #define NXGE_EHEADER_VLAN_CRC (sizeof (struct ether_header) + ETHERFCSL + 4) 46 #define NXGE_MAXIMUM_MTU (TX_JUMBO_MTU - NXGE_EHEADER_VLAN_CRC) 47 48 #define NXGE_XMAC_TX_INTRS (ICFG_XMAC_TX_ALL & \ 49 ~(ICFG_XMAC_TX_FRAME_XMIT |\ 50 ICFG_XMAC_TX_BYTE_CNT_EXP |\ 51 ICFG_XMAC_TX_FRAME_CNT_EXP)) 52 #define NXGE_XMAC_RX_INTRS (ICFG_XMAC_RX_ALL & \ 53 ~(ICFG_XMAC_RX_FRAME_RCVD |\ 54 ICFG_XMAC_RX_OCT_CNT_EXP |\ 55 ICFG_XMAC_RX_HST_CNT1_EXP |\ 56 ICFG_XMAC_RX_HST_CNT2_EXP |\ 57 ICFG_XMAC_RX_HST_CNT3_EXP |\ 58 ICFG_XMAC_RX_HST_CNT4_EXP |\ 59 ICFG_XMAC_RX_HST_CNT5_EXP |\ 60 ICFG_XMAC_RX_HST_CNT6_EXP |\ 61 ICFG_XMAC_RX_BCAST_CNT_EXP |\ 62 ICFG_XMAC_RX_MCAST_CNT_EXP |\ 63 ICFG_XMAC_RX_HST_CNT7_EXP)) 64 #define NXGE_BMAC_TX_INTRS (ICFG_BMAC_TX_ALL & \ 65 ~(ICFG_BMAC_TX_FRAME_SENT |\ 66 ICFG_BMAC_TX_BYTE_CNT_EXP |\ 67 ICFG_BMAC_TX_FRAME_CNT_EXP)) 68 #define NXGE_BMAC_RX_INTRS (ICFG_BMAC_RX_ALL & \ 69 ~(ICFG_BMAC_RX_FRAME_RCVD |\ 70 ICFG_BMAC_RX_FRAME_CNT_EXP |\ 71 ICFG_BMAC_RX_BYTE_CNT_EXP)) 72 73 typedef enum { 74 LINK_NO_CHANGE, 75 LINK_IS_UP, 76 LINK_IS_DOWN 77 } nxge_link_state_t; 78 79 /* Common MAC statistics */ 80 81 typedef struct _nxge_mac_stats { 82 /* 83 * MTU size 84 */ 85 uint32_t mac_mtu; 86 uint16_t rev_id; 87 88 /* 89 * Transciever state informations. 90 */ 91 uint32_t xcvr_inits; 92 xcvr_inuse_t xcvr_inuse; 93 uint32_t xcvr_portn; 94 uint32_t xcvr_id; 95 uint32_t serdes_inits; 96 uint32_t serdes_portn; 97 uint32_t cap_autoneg; 98 uint32_t cap_10gfdx; 99 uint32_t cap_10ghdx; 100 uint32_t cap_1000fdx; 101 uint32_t cap_1000hdx; 102 uint32_t cap_100T4; 103 uint32_t cap_100fdx; 104 uint32_t cap_100hdx; 105 uint32_t cap_10fdx; 106 uint32_t cap_10hdx; 107 uint32_t cap_asmpause; 108 uint32_t cap_pause; 109 110 /* 111 * Advertised capabilities. 112 */ 113 uint32_t adv_cap_autoneg; 114 uint32_t adv_cap_10gfdx; 115 uint32_t adv_cap_10ghdx; 116 uint32_t adv_cap_1000fdx; 117 uint32_t adv_cap_1000hdx; 118 uint32_t adv_cap_100T4; 119 uint32_t adv_cap_100fdx; 120 uint32_t adv_cap_100hdx; 121 uint32_t adv_cap_10fdx; 122 uint32_t adv_cap_10hdx; 123 uint32_t adv_cap_asmpause; 124 uint32_t adv_cap_pause; 125 126 /* 127 * Link partner capabilities. 128 */ 129 uint32_t lp_cap_autoneg; 130 uint32_t lp_cap_10gfdx; 131 uint32_t lp_cap_10ghdx; 132 uint32_t lp_cap_1000fdx; 133 uint32_t lp_cap_1000hdx; 134 uint32_t lp_cap_100T4; 135 uint32_t lp_cap_100fdx; 136 uint32_t lp_cap_100hdx; 137 uint32_t lp_cap_10fdx; 138 uint32_t lp_cap_10hdx; 139 uint32_t lp_cap_asmpause; 140 uint32_t lp_cap_pause; 141 142 /* 143 * Physical link statistics. 144 */ 145 uint32_t link_T4; 146 uint32_t link_speed; 147 uint32_t link_duplex; 148 uint32_t link_asmpause; 149 uint32_t link_pause; 150 uint32_t link_up; 151 152 /* Promiscous mode */ 153 boolean_t promisc; 154 } nxge_mac_stats_t; 155 156 /* XMAC Statistics */ 157 158 typedef struct _nxge_xmac_stats { 159 uint32_t tx_frame_cnt; 160 uint32_t tx_underflow_err; 161 uint32_t tx_maxpktsize_err; 162 uint32_t tx_overflow_err; 163 uint32_t tx_fifo_xfr_err; 164 uint64_t tx_byte_cnt; 165 uint32_t rx_frame_cnt; 166 uint32_t rx_underflow_err; 167 uint32_t rx_overflow_err; 168 uint32_t rx_crc_err_cnt; 169 uint32_t rx_len_err_cnt; 170 uint32_t rx_viol_err_cnt; 171 uint64_t rx_byte_cnt; 172 uint64_t rx_hist1_cnt; 173 uint64_t rx_hist2_cnt; 174 uint64_t rx_hist3_cnt; 175 uint64_t rx_hist4_cnt; 176 uint64_t rx_hist5_cnt; 177 uint64_t rx_hist6_cnt; 178 uint64_t rx_hist7_cnt; 179 uint64_t rx_broadcast_cnt; 180 uint64_t rx_mult_cnt; 181 uint32_t rx_frag_cnt; 182 uint32_t rx_frame_align_err_cnt; 183 uint32_t rx_linkfault_err_cnt; 184 uint32_t rx_remotefault_err; 185 uint32_t rx_localfault_err; 186 uint32_t rx_pause_cnt; 187 uint32_t tx_pause_state; 188 uint32_t tx_nopause_state; 189 uint32_t xpcs_deskew_err_cnt; 190 uint32_t xpcs_ln0_symbol_err_cnt; 191 uint32_t xpcs_ln1_symbol_err_cnt; 192 uint32_t xpcs_ln2_symbol_err_cnt; 193 uint32_t xpcs_ln3_symbol_err_cnt; 194 } nxge_xmac_stats_t, *p_nxge_xmac_stats_t; 195 196 /* BMAC Statistics */ 197 198 typedef struct _nxge_bmac_stats { 199 uint64_t tx_frame_cnt; 200 uint32_t tx_underrun_err; 201 uint32_t tx_max_pkt_err; 202 uint64_t tx_byte_cnt; 203 uint64_t rx_frame_cnt; 204 uint64_t rx_byte_cnt; 205 uint32_t rx_overflow_err; 206 uint32_t rx_align_err_cnt; 207 uint32_t rx_crc_err_cnt; 208 uint32_t rx_len_err_cnt; 209 uint32_t rx_viol_err_cnt; 210 uint32_t rx_pause_cnt; 211 uint32_t tx_pause_state; 212 uint32_t tx_nopause_state; 213 } nxge_bmac_stats_t, *p_nxge_bmac_stats_t; 214 215 typedef struct _hash_filter_t { 216 uint_t hash_ref_cnt; 217 uint16_t hash_filter_regs[NMCFILTER_REGS]; 218 uint32_t hash_bit_ref_cnt[NMCFILTER_BITS]; 219 } hash_filter_t, *p_hash_filter_t; 220 221 typedef struct _nxge_mac { 222 uint8_t portnum; 223 nxge_port_t porttype; 224 nxge_port_mode_t portmode; 225 nxge_linkchk_mode_t linkchkmode; 226 boolean_t is_jumbo; 227 uint32_t tx_config; 228 uint32_t rx_config; 229 uint32_t xif_config; 230 uint32_t tx_iconfig; 231 uint32_t rx_iconfig; 232 uint32_t ctl_iconfig; 233 uint16_t minframesize; 234 uint16_t maxframesize; 235 uint16_t maxburstsize; 236 uint16_t ctrltype; 237 uint16_t pa_size; 238 uint8_t ipg[3]; 239 struct ether_addr mac_addr; 240 struct ether_addr alt_mac_addr[MAC_MAX_ALT_ADDR_ENTRY]; 241 struct ether_addr mac_addr_filter; 242 uint16_t hashtab[MAC_MAX_HASH_ENTRY]; 243 hostinfo_t hostinfo[MAC_MAX_HOST_INFO_ENTRY]; 244 nxge_mac_stats_t *mac_stats; 245 nxge_xmac_stats_t *xmac_stats; 246 nxge_bmac_stats_t *bmac_stats; 247 uint32_t default_mtu; 248 } nxge_mac_t; 249 250 #ifdef __cplusplus 251 } 252 #endif 253 254 #endif /* _SYS_NXGE_NXGE_MAC_H */ 255